MSP430FG439, MSP430FG438, MSP430FG437
SLAS380F – APRIL 2004 – REVISED MARCH 2022
MSP430FG43x Mixed-Signal Microcontrollers
•
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
Low supply-voltage range, 1.8 V to 3.6 V
Ultra-low power consumption
– Active mode: 300 µA at 1 MHz, 2.2 V
– Standby mode: 1.1 µA
– Off mode (RAM retention): 0.1 µA
Five power-saving modes
Wakeup from standby mode in less than 6 µs
16-bit RISC architecture, 125-ns instruction cycle
time
Single-channel internal DMA
12-bit analog-to-digital converter (ADC) with
internal reference, sample-and-hold and autoscan
feature
Three configurable operational amplifiers
Dual 12-bit digital-to-analog converters (DACs)
with synchronization
16-bit Timer_A with three capture/compare
registers
16-bit Timer_B with three capture/compare-withshadow registers
On-chip comparator
•
•
•
•
•
•
•
Serial communication interface (USART), select
asynchronous UART or synchronous SPI by
software
Brownout detector
Supply-voltage supervisor and monitor with
programmable level detection
Bootloader (BSL)
Serial onboard programming, no external
programming voltage needed, programmable code
protection by security fuse
Integrated segment liquid crystal display (LCD)
driver for up to 128 segments
Available in 113-ball BGA (ZCA) and 80-pin QFP
(PN) packages
Device Comparison summarizes the available
family members
2 Applications
•
•
•
•
•
•
Analog and Digital Sensor Systems
Digital Motor Control
Remote Controls
Thermostats
Digital Timers
Hand-Held Meters
3 Description
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active
mode in less than 6 µs.
The MSP430FG43x devices are microcontrollers with two 16-bit timers, a high-performance 12-bit ADC, dual
12-bit DACs, three configurable operational amplifiers, one universal synchronous/asynchronous communication
interface, DMA, 48 I/O pins, and an LCD driver.
For complete module descriptions, see the MSP430x4xx Family User's Guide.
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE(2)
MSP430FG439PN
LQFP (80)
12 mm x 12 mm
MSP430FG439ZCA
BGA (113)
7 mm x 7 mm
(1)
(2)
For the most current device, package, and ordering information, see the Package Option Addendum in Section 11, or see the TI web
site at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 11.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FG439, MSP430FG438, MSP430FG437
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
4 Functional Block Diagram
Figure 4-1 shows the functional block diagram.
XIN
XT2IN
XT2OUT
DV CC1/2 DV SS1/2
XOUT
AV CC
AV SS
P1
P2
P4
P3
8
8
P6
P5
8
8
8
8
ACLK
Oscillator
FLL+
Flash
SMCLK
60KB
48KB
32KB
MCLK
8 MHz
CPU
incl. 16
Registers
ADC12
DAC12
Port 1
Port 2
2KB
1KB
12-Biit
12 Channels
30 V/ms (see Figure 8-13)
2000
SVS on, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V
VLD ≠
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 8-13)
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 8-13)
Vhys(SVS_IT–)
VCC/dt ≤ 3 V/s (see Figure 8-13),
external voltage applied on A7
VCC/dt ≤ 3 V/s (see Figure 8-13)
V(SVS_IT–)
VCC/dt ≤ 3 V/s (see Figure 8-13),
external voltage applied on A7
(2)
(3)
22
VLD = 2 to 14
VLD = 15
70
µs
300
µs
12
µs
1.55
1.7
V
155
mV
120
V(SVS_IT–)
× 0.001
V(SVS_IT–)
× 0.016
4.4
20
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.23
VLD = 3
2.05
2.2
2.35
VLD = 4
2.14
2.3
2.46
VLD = 5
2.24
2.4
2.58
VLD = 6
2.33
2.5
2.69
VLD = 7
2.46
2.65
2.84
VLD = 8
2.58
2.8
2.97
VLD = 9
2.69
2.9
3.10
VLD = 10
2.83
3.05
3.26
VLD = 11
2.94
3.2
3.39
VLD = 12
3.11
3.35
3.58(2)
VLD = 13
3.24
3.5
3.73(2)
VLD = 14
3.43
3.7(2)
3.96(2)
VLD = 15
1.1
1.2
1.3
10
15
VLD ≠ 0, VCC = 2.2 V, 3 V
UNIT
150
0(1)
V(SVSstart)
(1)
MAX
150
dVCC/dt ≤ 30 V/ms
tsettle
ICC(SVS) (3)
TYP
5
mV
V
µA
tsettle is the settling time that the comparator output needs to have a stable level after VLD is switched from VLD ≠ 0 to a different VLD
value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV.
The recommended operating voltage range is limited to 3.6 V.
The current consumption of the SVS module is not included in the ICC current consumption data.
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
VCC
V(SVS_IT-)
V(SVSstart)
Software Sets VLD>0:
SVS is Active
Vhys(SVS_IT-)
Vhys(B_IT-)
V(B_IT-)
VCC(start)
Brown
Out
Region
Brownout
Region
Brownout
1
0
SVSOut
t d(BOR)
t d(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT-)
1
0
td(SVSon)
Set POR
1
td(SVSR)
undefined
0
Figure 8-13. SVS Reset (SVSR) vs Supply Voltage
V CC
tpw
3V
2
Rectangular Drop
V CC(drop)
V C C (drop) - V
1.5
Triangular Drop
1
1 ns
1 ns
0.5
V CC
t pw
3V
0
1
100
10
1000
tpw - Pulse Width - m s
V CC(drop)
tf = tr
tf
tr
t - Pulse Width - ms
Figure 8-14. VCC(drop) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
8.18 DCO
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
f(DCOCLK)
N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2,
DCOPLUS = 0, fCrystal = 32.738 kHz
f(DCO=2)
FN_8=FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1
f(DCO=27)
FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1
f(DCO=2)
FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1
f(DCO=27)
FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1
f(DCO=2)
FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1
f(DCO=27)
FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1
f(DCO=2)
FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1
f(DCO=27)
FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1
f(DCO=2)
FN_8 = 1, FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1
f(DCO=27)
FN_8 = 1, FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1
Sn
Step size between adjacent DCO taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n) (see Figure 8-16 for taps 21 to
27)
Dt
Temperature drift, N(DCO) = 01Eh,
FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0
DV
Drift with VCC variation, N(DCO) = 01Eh,
FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0
MIN
TYP
2.2 V, 3 V
1
0.3
0.65
1.25
3V
0.3
0.7
1.3
2.2 V
2.5
5.6
10.5
3V
2.7
6.1
11.3
2.2 V
0.7
1.3
2.3
3V
0.8
1.5
2.5
2.2 V
5.7
10.8
18
3V
6.5
12.1
20
2.2 V
1.2
2
3
3V
1.3
2.2
3.5
9
15.5
25
3V
10.3
17.9
28.5
2.2 V
1.8
2.8
4.2
3V
2.1
3.4
5.2
2.2 V
13.5
21.5
33
3V
16
26.6
41
2.2 V
2.8
4.2
6.2
3V
4.2
6.3
9.2
2.2 V
21
32
46
3V
30
46
70
1 < TAP ≤ 20
1.06
1.11
TAP = 27
1.07
1.17
2.2 V
–0.2
–0.3
–0.4
3V
–0.2
–0.3
–0.4
0
5
15
2.2 V, 3 V
f(DCO)
f(DCO3V)
f(DCO20°C)
1.0
UNIT
MHz
2.2 V
2.2 V
f(DCO)
MAX
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%/°C
%/V
1.0
0
1.8
2.4
3.0
3.6
-40
-20
0
20
40
60
85
TA - ° C
VCC - V
Figure 8-15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
24
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S n - S tepsize R atio betw een D C O Taps
SLAS380F – APRIL 2004 – REVISED MARCH 2022
1.17
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 8-16. DCO Tap Step Size
Legend
f(DCO)
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
9
5
2 to 2 in SCFI1 {N{DCO}}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 8-17. Five Overlapping DCO Ranges Controlled by FN_x Bits
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
8.19 Crystal Oscillator, XT1 Oscillator
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
Integrated input capacitance(3)
CXIN
CXOUT
VIL
(2)
Integrated output capacitance(3)
MIN
TYP
OSCCAPx = 0h, VCC = 2.2 V, 3 V
0
OSCCAPx = 1h, VCC = 2.2 V, 3 V
10
OSCCAPx = 2h, VCC = 2.2 V, 3 V
14
OSCCAPx = 3h, VCC = 2.2 V, 3 V
18
OSCCAPx = 0h, VCC = 2.2 V, 3 V
0
OSCCAPx = 1h, VCC = 2.2 V, 3 V
10
OSCCAPx = 2h, VCC = 2.2 V, 3 V
14
OSCCAPx = 3h, VCC = 2.2 V, 3 V
18
VCC = 2.2 V, 3 V(4)
Input levels at XIN
VIH
(1)
TEST CONDITIONS(2)
MAX
UNIT
pF
pF
VSS
0.2 × VCC
0.8 × VCC
VCC
V
The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is (CXIN
× CXOUT) / (CXIN+ CXOUT). This is independent of XTS_FLL.
To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
•
•
•
•
•
•
•
(3)
(4)
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
External capacitance is recommended for precision real-time clock applications, OSCCAPx = 0h.
Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
8.20 Crystal Oscillator, XT2 Oscillator
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
CXT2IN
TEST CONDITIONS
Integrated input capacitance
CXT2OUT Integrated output capacitance
VIL
VIH
(1)
(2)
Input levels at XT2IN
MIN
TYP
MAX
UNIT
VCC = 2.2 V, 3 V
2
pF
VCC = 2.2 V, 3 V
2
pF
VCC = 2.2 V, 3 V(2)
VSS
0.2 × VCC
V
0.8 × VCC
VCC
V
The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
8.21 USART0
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
t(τ)
(1)
26
USART0 deglitch time
MIN
TYP
MAX
VCC = 2.2 V, SYNC = 0, UART mode
TEST CONDITIONS
200
430
800
VCC = 3 V, SYNC = 0, UART mode
150
280
500
UNIT
ns
The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t(τ) to ensure that the
URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum timing condition of t(τ). The operating
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0 line.
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
8.22 12-Bit ADC, Power Supply and Input Range Conditions
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
MIN
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(P6.x/Ax)
Analog input voltage range(2)
All external Ax terminals, Analog inputs selected in
ADC12MCTLx register and P6Sel.x = 1,
V(AVSS) ≤ VAx ≤ V(AVCC)
IADC12
Operating supply current into the
AVCC terminal(3)
fADC12CLK = 5.0 MHz,
ADC12ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC12DIV = 0
Operating supply current into the
AVCC terminal(4)
IREF+
fADC12CLK = 5.0 MHz,
ADC12ON = 0,
REFON = 1, REF2_5V = 1
fADC12CLK = 5.0 MHz,
ADC12ON = 0
REFON = 1, REF2_5V = 0
MAX
3.6
V
0
VAVCC
V
0.65
1.3
VCC = 3 V
0.8
1.6
VCC = 3 V
0.5
0.8
VCC = 2.2 V
0.5
0.8
VCC = 3 V
0.5
0.8
Input capacitance
Only one terminal can be selected at one
VCC = 2.2 V
time, Ax
RI
Input MUX ON resistance
0 V ≤ VAx ≤ VAVCC
UNIT
2.2
VCC = 2.2 V
CI
(1)
(2)
(3)
(4)
TYP
VCC = 3 V
mA
mA
mA
40
pF
2000
Ω
The leakage current is defined in the leakage current table with Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC12.
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
8.23 12-Bit ADC, External Reference
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX UNIT
VeREF+
Positive external reference
voltage input
VeREF+ > VREF–/VeREF– (2)
1.4
VAVCC
V
VREF–/VeREF–
Negative external reference
voltage input
VeREF+ > VREF–/VeREF– (3)
0
1.2
V
(VeREF+ –
VREF–/VeREF–)
Differential external reference
voltage input
VeREF+ > VREF–/VeREF– (4)
1.4
VAVCC
V
IVeREF+
Static input current
0 V ≤ VeREF+ ≤ VAVCC
VCC = 2.2 V, 3 V
±1
µA
IVREF–/VeREF–
Static input current
0 V ≤ VeREF– ≤ VAVCC
VCC = 2.2 V, 3 V
±1
µA
(1)
(2)
(3)
(4)
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
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8.24 12-Bit ADC, Built-In Reference
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Positive built in reference
voltage output
VREF+
TEST CONDITIONS
VCC
MIN
TYP
MAX
REF2_5V = 1 for 2.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min
3V
2.4
2.5
2.6
REF2_5V = 0 for 1.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min
2.2 V, 3 V
1.44
1.5
1.56
V
REF2_5V = 0,
IVREF+max ≤ IVREF+ ≤ IVREF+min
AVCC(min)
2.2
AVCC minimum voltage, Positive REF2_5V = 1,
built in reference active
IVREF+min ≥ IVREF+ ≥ –0.5 mA
2.9
Load current out of VREF+
terminal
IL(VREF)+
Load-current regulation, VREF+
terminal
IVREF+ = 500 µA ± 100 µA,
Analog input voltage ≈ 0.75 V,
REF2_5V = 0
0.01
–0.5
3V
0.01
–1
mA
±2
3V
±2
IVREF+ = 500 µA ± 100 µA,
Analog input voltage ≈ 1.25 V,
REF2_5V = 1
3V
±2
LSB
3V
20
ns
Load current regulation, VREF+
terminal
IVREF+ = 100 µA → 900 µA,
CVREF+ = 5 µF, ax ≈ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB
CVREF+
Capacitance at pin VREF+ (1)
REFON =1,
0 mA ≤ IVREF+ ≤ IVREF+max
TREF+
Temperature coefficient of built- IVREF+ is a constant in the range of
in reference
0 mA ≤ IVREF+ ≤ 1 mA
tREFON
Settle time of internal reference IVREF+ = 0.5 mA, CVREF+ = 10 µF,
voltage (see Figure 8-18 ) (2)
VREF+ = 1.5 V, VAVCC = 2.2 V
(2)
2.2 V
2.2 V
IDL(VREF)+
(1)
V
2.8
REF2_5V = 1,
IVREF+min ≥ IVREF+ ≥ – 1 mA
IVREF+
UNIT
2.2 V, 3 V
5
10
2.2 V, 3 V
LSB
µF
±100 ppm/°C
17
ms
The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two
capacitors between pins VREF+ and AVSS and VREF-–/VeREF– and AVSS: 10 µF tantalum and 100 nF ceramic.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
100 mF
tREFON » .66 x CVREF+ [ms] with CVREF+ in mF
10 mF
1 mF
0
1 ms
10 ms
100 ms
tREFON
Figure 8-18. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
DV CC1/2
+
-
From Power Supply
DV SS1/2
10µF
100 nF
AVCC
+
-
MSP430FG43x
AVSS
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
10µF
100 nF
VREF+ or V eREF+
+
10µF
100 nF
Apply External Reference
VREF -/V eREF-
+
10µF
100 nF
Figure 8-19. Supply Voltage and Reference Voltage Design VREF–/VeREF– External Supply
DV CC1/2
From Power Supply
+
DV SS1/2
10µF
100 nF
AVCC
+
-
MSP430FG43x
AVSS
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
Reference Is Internally
Switched to AVSS
10µ F
100 nF
VREF+ or VeREF+
+
10µF
100 nF
VREF- /VeREF-
Figure 8-20. Supply Voltage and Reference Voltage Design VREF–/VeREF– = AVSS, Internally Connected
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
8.25 12-Bit ADC, Timing Parameters
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fADC12CLK
ADC12 clock frequency
For specified performance of ADC12
linearity parameters
2.2 V, 3 V
0.45
5
7
MHz
fADC12OSC
Internal ADC12 oscillator
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V, 3 V
3.7
5
7
MHz
CVREF+ ≥ 5 µF, Internal oscillator,
fADC12OSC = 3.7 MHz to 7 MHz
2.2 V, 3 V
1.86
tCONVERT
Conversion time
External fADC12CLK from ACLK, MCLK, or
SMCLK, ADC12SSEL ≠ 0
tADC12ON
Turn on settling time of
the ADC
See (1)
tSample
Sampling time
RS = 400 Ω,RI = 1000 Ω,
CI = 30 pF, τ = [RS +RI] × CI (2)
(1)
(2)
3.51
13 ×
1/fADC12CLK
µs
100
3V
1220
2.2 V
1400
µs
ns
ns
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) × (RS + RI) x CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance.
8.26 12-Bit ADC, Linearity Parameters
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.4 V ≤ (VeREF+ – VREF–/VeREF–) min ≤ 1.6 V
VCC
EI
Integral linearity error
ED
Differential linearity error
(VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
EO
Offset error
(VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
EG
Gain error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ =10 µF (tantalum) and 100 nF (ceramic)
ET
Total unadjusted error
(VeREF+ – VREF–/VeREF– )min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
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MIN
TYP
MAX UNIT
±2
2.2 V, 3 V
±1.7
LSB
±1
LSB
±2
±4
LSB
2.2 V, 3 V
±1.1
±2
LSB
2.2 V, 3 V
±2
±5
LSB
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
8.27 12-Bit ADC, Temperature Sensor and Built-In VMID
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
2.2 V
40
120
3V
60
160
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2.2 V,
3V
986
ADC12ON = 1, INCH = 0Ah
2.2 V,
3V
3.55 ± 3%
ISENSOR
Operating supply current into REFON = 0, INCH = 0Ah,
AVCC terminal(1)
ADC12ON = NA, TA = 25°C
VSENSOR
See
(2)
TCSENSOR
VCC
MIN
2.2 V
30
3V
30
mV/°C
Sample time required if
channel 10 is selected(3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at
channel 11(4)
ADC12ON = 1, INCH = 0Bh
VMID
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID ≈ 0.5 × VAVCC
2.2 V
1.1 1.10 ± 0.04
3V
1.5 1.50 ± 0.04
tVMID(sample)
Sample time required if
channel 11 is selected(5)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
(2)
(3)
(4)
(5)
µA
mV
tSENSOR(sample)
(1)
UNIT
µs
2.2 V
NA
3V
NA
µA
V
ns
The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1), or (ADC12ON = 1 AND INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is already included in IREF+.
The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset
error of the built-in temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
No additional current is needed. The VMID is used during sampling.
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
8.28 12-Bit DAC, Supply Specifications
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
AVCC
TEST CONDITIONS
Analog supply voltage
VCC
AVCC = DVCC, AVSS = DVSS = 0 V
IDD
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h , VeREF+ = VREF+ = AVCC
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h, VeREF+ = VREF+ = AVCC
2.2 V,
3V
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h, VeREF+ = VREF+ = AVCC
PSRR Power-supply rejection
(1)
(2)
(3)
(4)
ratio(3) (4)
DAC12_xDAT = 0800h, VREF = 1.5 V,
ΔAVCC = 100 mV
DAC12_xDAT = 0800h, VREF = 1.5 V or 2.5 V,
ΔAVCC = 100 mV
TYP
MAX
2.2
DAC12AMPx = 2, DAC12IR = 0,
DAC12_xDAT = 0800h
Supply current, single DAC
channel(1) (2)
MIN
3.6
50
110
50
110
200
440
700
1500
UNIT
V
µA
2.2 V
70
dB
3V
No load at the output pin, DAC0 or DAC1, assuming that the control bits for the shared pins are set properly.
Current into reference terminals not included. If DAC12IR = 1, current flows through the input divider (see Reference Input
specifications).
PSRR = 20 × log(ΔAVCC / ΔVDAC12_xOUT).
VREF is applied externally. The internal reference is not used.
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
8.29 12-Bit DAC, Linearity Specifications
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 8-21)
PARAMETER
TEST CONDITIONS
Resolution
DNL
Differential
MIN
12-bit monotonic
Integral nonlinearity(1)
INL
VCC
nonlinearity(1)
Offset voltage without
calibration(1) (2)
EO
Offset voltage with calibration(1) (2)
dE(O)/dT
Offset error temperature coefficient(1)
EG
Gain error(1)
dE(G)/dT
Gain temperature coefficient(1)
tOffset Cal
Time for offset calibration(3)
TYP
12
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
±2.0
±8.0
LSB
±0.4
±1.0
LSB
±21
mV
±2.5
2.2 V, 3 V
VREF = 1.5 V
2.2 V
VREF = 2.5 V
3V
±30
µV/°C
±3.5
2.2 V, 3 V
%FSR
ppm of
FSR/°C
10
100
DAC12AMPx = 3, 5
2.2 V, 3 V
32
DAC12AMPx = 4, 6, 7
(2)
(3)
UNIT
bits
DAC12AMPx = 2
(1)
MAX
ms
6
Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b"
of the first-order equation: y = a + b × x. VDAC12_xOUT = EO + (1 + EG) × (VeREF+ / 4095) × DAC12_xDAT, DAC12IR = 1.
The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON.
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx
= {0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may affect
accuracy and is not recommended.
DAC VOUT
DAC Output
V R+
R Load =
Ideal transfer
function
AVCC
2
Offset Error
C Load = 100pF
Gain Error
Positive
Negative
DAC Code
Figure 8-21. Linearity Test Load Conditions and Gain/Offset Definition
32
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
INL - Integral Nonlinearity Error - LSB
4
VCC = 2.2 V, V REF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
-1
-2
-3
-4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT - Digital Code
Figure 8-22. Typical INL Error vs Digital Input Data
DNL - Differential Nonlinearity Error - LSB
2.0
VCC = 2.2 V, V REF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT - Digital Code
Figure 8-23. Typical DNL Error vs Digital Input Data
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
8.30 12-Bit DAC, Output Specifications
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
Output voltage range(1) (see DAC12AMPx = 7
Figure 8-24)
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
VO
2.2 V,
3V
TYP
MAX UNIT
0
0.005
AVCC –
0.05
AVCC
V
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
0
0.1
AVCC –
0.13
AVCC
CL(DAC12)
Maximum DAC12 load
capacitance
2.2 V,
3V
IL(DAC12)
Maximum DAC12 load
current
2.2 V
–0.5
+0.5
3V
–1.0
+1.0
100
RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 7, DAC12_xDAT = 0h
RO/P(DAC12)
Output resistance (see
Figure 8-24)
RLoad = 3 kΩ,
VO/P(DAC12) > AVCC – 0.3 V,
DAC12AMPx = 7, DAC12_xDAT = 0FFFh
2.2 V,
3V
RLoad = 3 kΩ,
0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V
DAC12AMPx = 7
(1)
150
250
150
250
1
4
pF
mA
Ω
Data is valid after the offset calibration of the output amplifier.
R O/P(DAC12_x)
I Load
Max
R Load
AVCC
DAC12
2
O/P(DAC12_x)
C Load = 100pF
Min
0.3
AVCC -0.3V
V OUT
AVCC
Figure 8-24. DAC12_x Output Resistance Tests
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
8.31 12-Bit DAC, Reference Input Specifications
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0(1) (2)
Reference input voltage DAC12IR =
range
DAC12IR = 1(3) (4)
VeREF+
Ri(VREF+),
Ri(VeREF+)
Reference input
resistance
MIN
2.2 V, 3 V
MAX
AVCC / 3
AVCC + 0.2
AVCC
AVCC + 0.2
DAC12_0 IR = DAC12_1 IR = 0
20
DAC12_0 IR = 1, DAC12_1 IR = 0
40
48
150
40
48
150
20
24
75
2.2 V, 3 V
DAC12_0 IR = 0, DAC12_1 IR = 1
DAC12_0 IR = DAC12_1 IR =1,
DAC12_0 SREFx = DAC12_1 SREFx(5)
(1)
(2)
(3)
(4)
(5)
TYP
UNIT
V
MΩ
kΩ
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel,
reducing the reference input resistance.
8.32 12-Bit DAC, Dynamic Specifications
Vref = VCC, DAC12IR = 1, over recommended operating free-air temperature range (unless otherwise noted) (see Figure 8-25
and Figure 8-26)
PARAMETER
tON
TEST CONDITIONS
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB(1)
(see Figure 8-25)
DAC12 on time
VCC
MIN
DAC12AMPx = 0 → {2, 3, 4}
DAC12AMPx = 0 → {5, 6}
2.2 V, 3 V
DAC12AMPx = 0 → 7
DAC12AMPx = 2
Settling time,
full scale
tS(FS)
DAC12_xDAT =
80h→F7Fh→80h
DAC12AMPx = 3, 5
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
tS(C–C)
DAC12AMPx = 2
DAC12_xDAT =
3F8h→408h→3F8h
BF8h→C08h→BF8h
Settling time,
code to code
DAC12AMPx = 3, 5
DAC12AMPx = 3, 5
DAC12AMPx = 3, 5
12
200
40
80
15
30
2.2 V, 3 V
0.12
0.35
0.7
1.5
2.7
µs
µs
µs
V/µs
10
10
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
(1)
(2)
6
100
0.05
DAC12AMPx = 2
DAC12_xDAT =
80h→ F7Fh→ 80h
30
1
DAC12AMPx = 4, 6, 7
Glitch energy,
full scale
120
15
2
DAC12AMPx = 4, 6, 7
DAC12_xDAT =
80h→ F7Fh→ 80h(2)
Slew rate
60
5
2.2 V, 3 V
DAC12AMPx = 2
SR
TYP MAX UNIT
nV-s
10
RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 8-25.
Slew rate applies to output voltage steps ≥ 200 mV.
Conversion 1
V OUT
DAC Output
I Load
R Load = 3 k W
Glitch
Energy
Conversion 2
Conversion 3
+/- 1/2 LSB
AVCC
2
R O/P(DAC12.x)
+/- 1/2 LSB
C Load = 100pF
t settleLH
t settleHL
Figure 8-25. Settling Time and Glitch Energy Testing
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
Conversion 1
Conversion 2
Conversion 3
V OUT
90%
90%
10%
10%
t SRLH
t SRHL
Figure 8-26. Slew Rate Testing
8.33 12-Bit DAC, Dynamic Specifications (Continued)
TA = 25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
VCC
MIN
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
BW–3dB
3-dB bandwidth,
VDC = 1.5 V, VAC = 0.1 VPP
(see Figure 8-27)
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
MAX
UNIT
40
2.2 V, 3 V
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
kHz
180
550
DAC12_0DAT = 800h, No Load,
DAC12_1DAT = 80h↔F7Fh, RLoad = 3 kΩ
fDAC12_1OUT = 10 kHz with 50/50 duty cycle
–80
Channel-to-channel crosstalk(1)
(see Figure 8-28)
DAC12_0DAT = 80h↔F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No Load,
fDAC12_0OUT = 10 kHz with 50/50 duty cycle
(1)
TYP
2.2 V, 3 V
dB
–80
RLOAD = 3 kΩ, CLOAD = 100 pF
I Load
VeREF+
R Load = 3 k W
AVCC
DAC12_x
2
DACx
AC
C Load = 100pF
DC
Figure 8-27. Test Conditions for 3-dB Bandwidth Specification
I Load
R Load
AVCC
2
DAC12_0
DAC0
DAC12_xDAT
080h
080h
F7Fh
F7Fh
080h
V OUT
C Load = 100 pF
VREF+
I Load
V DAC12_yOUT
R Load
AVCC
2
DAC12_1
DAC1
V DAC12_xOUT
1/fToggle
C Load = 100 pF
Figure 8-28. Crosstalk Test Conditions
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
8.34 Operational Amplifier (OA), Supply Specifications
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
MIN
Supply voltage
2.2
290
Medium Mode, RRIP OFF
110
190
50
80
300
490
190
350
90
190
2.2 V, 3 V
Fast Mode, RRIP ON
Slow Mode, RRIP ON
(1)
Power supply rejection ratio
3.6
180
Medium Mode, RRIP ON
PSRR
MAX UNIT
Fast Mode, RRIP OFF
Slow Mode, RRIP OFF
Supply current(1)
ICC
TYP
Non-inverting
2.2 V, 3 V
70
V
µA
dB
P6SEL.x = 1 for each corresponding pin when used in OA input or OA output mode.
8.35 Operational Amplifier (OA), Input/Output Specifications
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI/P
Voltage supply, I/P
IIkg
Input leakage current, I/
P(1) (2)
VCC
MIN
–0.1
VCC – 1.2
RRIP ON
–0.1
VCC + 0.1
TA = –40°C to +55°C
–5
±0.5
5
TA = +55°C to +85°C
–20
±5
20
Medium Mode
Voltage noise density, I/P
140
Fast Mode
30
fV(I/P) = 10 kHz
Offset voltage, I/P
50
65
2.2 V, 3 V
±10
See (3)
2.2 V, 3 V
Offset voltage drift with
supply, I/P
0.3 V ≤ VIN ≤ VCC – 0.3 V
ΔVCC ≤ ±10%, TA = 25°C
2.2 V, 3 V
VOH
High-level output voltage,
O/P
Fast Mode, ISOURCE ≤ –500 µA
2.2 V
VCC – 0.2
VCC
Slow Mode, ISOURCE ≤ –150 µA
3V
VCC – 0.1
VCC
VOL
Low-level output voltage,
O/P
Fast Mode, ISOURCE ≤ +500 µA
2.2 V
VSS
0.2
Slow Mode, ISOURCE ≤ +150 µA
3V
VSS
0.1
±10
RLoad = 3 kΩ,CLoad = 50 pF, RRIP ON,
VO/P(OAx) > AVCC – 0.2 V
2.2 V, 3 V
RLoad = 3 kΩ,CLoad = 50 pF, RRIP ON,
0.2 V ≤ VO/P(OAx) ≤ AVCC – 0.2 V
(1)
(2)
(3)
(4)
Common-mode rejection
ratio
Non-inverting
2.2 V, 3 V
150
250
150
250
0.1
4
70
mV
µV/°C
±1.5
RLoad = 3 kΩ,CLoad = 50 pF, RRIP ON,
VO/P(OAx) < 0.2 V
CMRR
nA
nV/√ Hz
Offset temperature drift,
I/P
Output resistance(4) (see
Figure 8-29)
V
80
Slow Mode
RO/P (OAx)
UNIT
50
fV(I/P) = 1 kHz
Slow Mode
Medium Mode
VIO
MAX
RRIP OFF
Fast Mode
Vn
TYP
mV/V
V
V
Ω
dB
ESD damage can degrade input current leakage.
The input bias current is overridden by the input leakage current.
Calculated using the box method.
Specification valid for voltage-follower OAx configuration.
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R O/P(OAx)
I Load
Max
R Load
AVCC
2
OAx
C Load
O/P(OAx)
Min
0.2V
AVCC -0.2V AV
V OUT
CC
Figure 8-29. OAx Output Resistance Tests
8.36 Operational Amplifier (OA), Dynamic Specifications
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
SR
TEST CONDITIONS
Slew rate
VCC
MIN
Fast Mode
1.2
Medium Mode
0.8
Slow Mode
GBW
MAX
UNIT
V/µs
0.3
Open-loop voltage gain
φm
TYP
100
dB
Phase margin
CL = 50 pF
60
deg
Gain margin
CL = 50 pF
20
dB
Non-inverting, Fast Mode,
RL = 47 kΩ,CL = 50 pF
2.2
1.4
Non-inverting, Medium Mode,
RL = 300 kΩ, CL = 50 pF
Gain-bandwidth product
(see Figure 8-30 and Figure 8-31)
2.2 V, 3 V
MHz
0.5
Non-inverting, Slow Mode,
RL = 300 kΩ, CL = 50 pF
ten(on)
Enable time on
ten(off)
Enable time off
ton, non-inverting, Gain = 1
2.2 V, 3 V
10
2.2 V, 3 V
20
µs
1
µs
8.37 OA Dynamic Specifications Typical Characteristics
0
140
120
Fast Mode
100
-50
80
Phase - degrees
Medium Mode
Gain = dB
60
40
20
0
Fast Mode
-100
Medium Mode
-150
Slow Mode
Slow Mode
-20
-200
-40
-60
-80
0.001
0.01
0.1
1
10
100
1000 10000
Input Frequency - kHz
Figure 8-30. Typical Open-Loop Gain vs Frequency
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-250
1
10
100
1000
10000
Input Frequency - kHz
Figure 8-31. Typical Phase vs Frequency
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8.38 Flash Memory
over recommended operating free-air temperature range (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX UNIT
VCC(PGM/ ERASE)
Program and erase supply voltage
2.7
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from DVCC during program
2.7 V, 3.6 V
3
5
mA
IERASE
Supply current from DVCC during erase
2.7 V, 3.6 V
3
7
mA
10
ms
tCPT
Cumulative program time
See
(1)
tCMErase
Cumulative mass erase time
See
(2)
2.7 V, 3.6 V
2.7 V, 3.6 V
200
104
Program and erase endurance
tRetention
Data retention duration
tWord
Word or byte program time
35
tBlock, 0
Block program time for first byte or word
30
tBlock, 1-63
Block program time for each additional byte or
word
tBlock, End
Block program end-sequence wait time
tMass Erase
Mass erase time
5297
tSeg Erase
Segment erase time
4819
(1)
(2)
(3)
TJ = 25°C
ms
105
cycles
100
years
21
See (3)
tFTG
6
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297 × 1/fFTG,max = 5297 × 1 / 476 kHz). To
achieve the required cumulative mass erase time the Flash Controller's mass erase operation can be repeated until this time is met. (A
worst case minimum of 19 cycles are required).
These values are hard-wired into the flash controller's state machine (tFTG = 1 / fFTG).
8.39 JTAG Interface
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTCK
TCK input frequency
See (1)
RInternal
Internal pullup resistance on TMS, TCK, TDI/TCLK
See (2)
(1)
(2)
VCC
MIN
2.2 V
0
3V
0
2.2 V, 3 V
25
TYP
60
MAX UNIT
5
MHz
10
MHz
90
kΩ
fTCK may be restricted to meet the timing requirements of the module selected.
TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions.
8.40 JTAG Fuse
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TDI/TCLK for fuse-blow
IFB
Supply current into TDI/TCLK during fuse blow
tFB
Time to blow fuse
(1)
TEST CONDITIONS
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
After the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to
bypass mode.
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9 Detailed Description
9.1 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant
generator respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
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SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
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9.2 Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Table 9-1 shows examples of the three types of instruction formats; Table 9-2 lists the address modes.
Table 9-1. Instruction Word Formats
INSTRUCTION FORMAT
EXAMPLE
OPERATION
Dual operands, source-destination
ADD R4,R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC→(TOS), R8 →PC
Relative jump, un/conditional
JNE
Jump-on-equal bit = 0
Table 9-2. Address Mode Descriptions
(1)
ADDRESS MODE
S(1)
D(1)
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5)→ M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) → M(TONI)
Absolute
✓
✓
MOV & MEM, & TCDAT
M(MEM) → M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2→ R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
SYNTAX
EXAMPLE
OPERATION
S = source D = destination
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9.3 Operating Modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
•
•
•
•
•
•
42
Active mode (AM)
– All clocks are active
Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active. MCLK is disabled
– FLL+ loop control remains active
Low-power mode 1 (LPM1)
– CPU is disabled
– FLL+ loop control is disabled
– ACLK and SMCLK remain active. MCLK is disabled
Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL+ loop control and DCOCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL+ loop control, and DCOCLK are disabled
– DCO's dc-generator is disabled
– ACLK remains active
Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL+ loop control, and DCOCLK are disabled
– DCO's dc-generator is disabled
– Crystal oscillator is stopped
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9.4 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFC0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 9-3. Interrupt Sources, Flags, and Vectors of MSP430FG43x Configurations
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV (1)
Reset
0FFFEh
15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (1)
OFIFG(1)
ACCVIFG(1)
(Non)maskable(2)
(Non)maskable
(Non)maskable
0FFFCh
14
Timer_B3
TBCCR0 CCIFG0(3)
Maskable
0FFFAh
13
Timer_B3
TBCCR1 CCIFG1 and TBCCR2 CCIFG2,
TBIFG(1) (3)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
USART0 Receive
URXIFG0
Maskable
0FFF2h
9
USART0 Transmit
UTXIFG0
Maskable
0FFF0h
8
ADC12
ADC12IFG (1) (3)
Maskable
0FFEEh
7
Maskable
0FFECh
6
(3)
Maskable
0FFEAh
5
I/O Port P1 (Eight Flags)
P1IFG.0 to P1IFG.7(1) (3)
Maskable
0FFE8h
4
DAC12 DMA
DAC12.0IFG, DAC12.1IFG, DMA0IFG(1) (3)
Maskable
0FFE6h
3
0FFE4h
2
I/O Port P2 (Eight Flags)
P2IFG.0 to P2IFG.7 (1) (3)
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h
0, lowest
Timer_A3
Timer_A3
(1)
(2)
(3)
TACCR0
CCIFG0(3)
TACCR1 CCIFG1 and TACCR2 CCIFG2, TAIFG(1)
Multiple source flags
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
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9.5 Special Function Registers (SFRs)
The MSP430 SFRs are located in the lowest address space and are organized as byte-mode registers. SFRs
should be accessed with byte instructions.
Legend
rw
Bit can be read and written.
rw-0, rw-1
Bit can be read and written. It is Reset or Set by PUC.
rw-(0), rw-1
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
9.5.1 Interrupt Enable Registers 1 and 2
Figure 9-1. Interrupt Enable Register 1 (Address = 0h)
7
6
5
4
UTXIE0
URXIE0
ACCVIE
rw–0
rw–0
rw–0
3
2
1
0
NMIIE
OFIE
WDTIE
rw–0
rw–0
rw–0
Table 9-4. Interrupt Enable Register 1 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
UTXIE0
RW
0h
USART0: UART and SPI transmit-interrupt enable
6
URXIE0
RW
0h
USART0: UART and SPI receive-interrupt enable
5
ACCVIE
RW
0h
Flash access violation interrupt enable
4
NMIIE
RW
0h
Nonmaskable-interrupt enable
1
OFIE
RW
0h
Oscillator-fault-interrupt enable
0
WDTIE
RW
0h
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
Figure 9-2. Interrupt Enable Register 2 (Address = 1h)
7
6
5
4
3
2
1
0
BTIE
rw–0
Table 9-5. Interrupt Enable Register 2 Field Descriptions
BIT
7
44
FIELD
TYPE
RESET
DESCRIPTION
BTIE
RW
0h
Basic timer interrupt enable
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9.5.2 Interrupt Flag Registers 1 and 2
Figure 9-3. Interrupt Flag Register 1 (Address = 2h)
7
6
5
UTXIFG0
URXIFG0
rw–1
rw–0
4
3
2
1
0
NMIIFG
OFIFG
WDTIFG
rw–0
rw–1
rw–(0)
Table 9-6. Interrupt Flag Register 1 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
UTXIFG0
RW
1h
USART0: UART and SPI transmit flag
6
URXIFG0
RW
0h
USART0: UART and SPI receive flag
4
NMIIFG
RW
0h
Set by RST/NMI pin
1
OFIFG
RW
1h
Flag set on oscillator fault
0
WDTIFG
RW
0h
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
Figure 9-4. Interrupt Flag Register 2 (Address = 3h)
7
6
5
4
3
2
1
0
1
0
1
0
BTIFG
rw–0
Table 9-7. Interrupt Flag Register 2 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
BTIFG
RW
0h
Basic timer flag
9.5.3 Module Enable Registers 1 and 2
Figure 9-5. Module Enable Register 1 (Address = 4h)
7
6
UTXE0
URXE0
USPIE0
5
rw–0
rw–0
4
3
2
Table 9-8. Module Enable Register 1 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
UTXE0
RW
0h
USART0: UART mode transmit enable
URXE0
RW
0h
USART0: UART mode receive enable
USPIE0
RW
0h
USART0: SPI mode transmit and receive enable
6
Figure 9-6. Module Enable Register 2 (Address = 5h)
7
6
5
4
3
2
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9.6 Memory Organization
Table 9-9 shows the memory organization for all device variants.
Table 9-9. Memory Organization
MSP430FG437
MSP430FG438
MSP430FG439
Size
32KB
48KB
60KB
Main: interrupt vector
Flash
0FFFFh-0FFE0h
0FFFFh-0FFE0h
0FFFFh-0FFE0h
Main: code memory
Flash
0FFFFh-08000h
0FFFFh-04000h
0FFFFh-01100h
Memory
Information memory
Boot memory
RAM
Peripherals
Size
256 Byte
256 Byte
256 Byte
Flash
010FFh-01000h
010FFh-01000h
010FFh-01000h
Size
1KB
1KB
1KB
ROM
0FFFh-0C00h
0FFFh-0C00h
0FFFh-0C00h
Size
1KB
2KB
2KB
05FFh-0200h
09FFh-0200h
09FFh-0200h
16-bit
01FFh-0100h
01FFh-0100h
01FFh-0100h
8-bit
0FFh-010h
0FFh-010h
0FFh-010h
0Fh-00h
0Fh-00h
0Fh-00h
8-bit SFR
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9.7 Bootstrap Loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see MSP430 Programming Via the Bootstrap
Loader (BSL) (SLAU319).
BSL FUNCTION
PN PACKAGE PINS
ZCA PACKAGE PINS
Data Transmit
67 – P1.0
D8 – P1.0
Data Receiver
66 – P1.1
D9 – P1.1
9.8 Flash Memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
•
•
•
•
Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A and B can be erased individually, or as a group with segments 0 to n. Segments A and B are
also called information memory.
New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
32KB
48KB
60KB
0FFFFh
0FFFFh
0FFFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
Segment 0
with Interrupt Vectors
Segment 1
Segment 2
Main
Memory
08400h
083FFh
04400h
043FFh
01400h
013FFh
08200h
081FFh
04200h
041FFh
01200h
011FFh
08000h
010FFh
04000h
010FFh
01100h
010FFh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
Segment n-1
Segment n
(see Note A)
Segment A
Information
Memory
Segment B
A.
MSP430FG43x flash segment n = 256 bytes.
Figure 9-7. Flash Memory Segments
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9.9 Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User's Guide (SLAU056).
9.9.1 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or
from a peripheral.
9.9.2 Oscillator and System Clock
The clock system in the MSP430FG43x family of devices is supported by the FLL+ module, which includes
support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high
frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system
cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in
conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch
crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The
FLL+ module provides the following clock signals:
•
•
•
•
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
Main clock (MCLK), the system clock used by the CPU
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
9.9.3 Brownout, Supply Voltage Supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must make sure that the default FLL+ settings are not changed
until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
9.9.4 Digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read and write access to port-control registers is supported by all instructions
9.9.5 Basic Timer1
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
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9.9.6 LCD Drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
9.9.7 OA
The MSP430FG43x has three configurable low-current general-purpose operational amplifiers. Each OA input
and output terminal is software-selectable and offers a flexible choice of connections for various applications.
The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
9.9.8 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
9.9.9 USART0
The MSP430FG43x has one hardware universal synchronous/asynchronous receive transmit (USART)
peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or
4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
9.9.10 Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/
compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 9-10. Timer_A3 Signal Connections
INPUT PIN NUMBER
ZCA
PN
DEVICE INPUT
SIGNAL
MODULE
INPUT NAME
B10 - P1.5
62 - P1.5
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
B10 - P1.5
62 - P1.5
TACLK
INCLK
D8 - P1.0
67 - P1.0
TA0
CCI0A
D9 - P1.1
66 - P1.1
TA0
CCI0B
B9 - P1.2
C11 - P2.0
65 - P1.2
59 - P2.0
DVSS
GND
DVCC
VCC
TA1
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
OUTPUT PIN NUMBER
PN
ZCA
67 - P1.0
D8 - P1.0
B9 - P1.2
TA0
CCI1A
65 - P1.2
CAOUT
(internal)
CCI1B
ADC12
(internal)
DVSS
GND
DVCC
VCC
TA2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
CCR1
TA1
59 - P2.0
CCR2
C11 - P2.0
TA2
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9.9.11 Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/
compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 9-11. Timer_B3 Signal Connections
INPUT PIN NUMBER
ZCA
PN
DEVICE INPUT
SIGNAL
MODULE
INPUT NAME
E9 - P1.4
63 - P1.4
TBCLK
TBCLK
ACLK
ACLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
PN
ZCA
D11 - P2.1
SMCLK
SMCLK
E9 - P1.4
63 - P1.4
TBCLK
INCLK
D11 - P2.1
58 - P2.1
TB0
CCI0A
58 - P2.1
TB0
CCI0B
ADC12
(internal)
DVSS
GND
D11 - P2.1
58 - P2.1
CCR0
TB0
DVCC
VCC
E11 - P2.2
57 - P2.2
TB1
CCI1A
57 - P2.2
E11 - P2.2
57 - P2.2
TB1
CCI1B
ADC12
(internal)
DVSS
GND
DVCC
VCC
F11 - P2.3
56 - P2.3
TB2
CCI2A
F11 - P2.3
56 - P2.3
TB2
CCI2B
DVSS
GND
DVCC
VCC
CCR1
TB1
56 - P2.3
CCR2
E11 - P2.2
F11 - P2.3
TB2
9.9.12 Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
9.9.13 ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversionand-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU
intervention.
9.9.14 DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode,
and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may
be grouped together for synchronous operation.
50
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.9.15 Peripheral File Map
Table 9-12 shows peripherals with word-access registers, and Table 9-13 shows peripherals with byte-access
registers.
Table 9-12. Peripherals With Word Access
PERIPHERAL
REGISTER NAME
ACRONYM
OFFSET
Watchdog
Watchdog timer control
WDTCTL
0120h
Timer_B3
Capture/compare register 2
TBCCR2
0196h
Capture/compare register 1
TBCCR1
0194h
Capture/compare register 0
TBCCR0
0192h
Timer_B register
TBR
0190h
Capture/compare control 2
TBCCTL2
0186h
Capture/compare control 1
TBCCTL1
0184h
Capture/compare control 0
TBCCTL0
0182h
Timer_B control
TBCTL
0180h
Timer_B interrupt vector
TBIV
011Eh
Capture/compare register 2
TACCR2
0176h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 0
TACCR0
0172h
Timer_A register
TAR
0170h
Capture/compare control 2
TACCTL2
0166h
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 0
TACCTL0
0162h
Timer_A control
TACTL
0160h
Timer_A interrupt vector
TAIV
012Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
DMA module control 0
DMACTL0
0122h
DMA module control 1
DMACTL1
0124h
DMA channel 0 control
DMA0CTL
01E0h
DMA channel 0 source address
DMA0SA
01E2h
DMA channel 0 destination address
DMA0DA
01E4h
DMA channel 0 transfer size
DMA0SZ
01E6h
Timer_A3
Flash
DMA
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
Table 9-12. Peripherals With Word Access (continued)
PERIPHERAL
ADC12
(See also Table 9-13)
DAC12
REGISTER NAME
ACRONYM
OFFSET
Conversion memory 15
ADC12MEM15
015Eh
Conversion memory 14
ADC12MEM14
015Ch
Conversion memory 13
ADC12MEM13
015Ah
Conversion memory 12
ADC12MEM12
0158h
Conversion memory 11
ADC12MEM11
0156h
Conversion memory 10
ADC12MEM10
0154h
Conversion memory 9
ADC12MEM9
0152h
Conversion memory 8
ADC12MEM8
0150h
Conversion memory 7
ADC12MEM7
014Eh
Conversion memory 6
ADC12MEM6
014Ch
Conversion memory 5
ADC12MEM5
014Ah
Conversion memory 4
ADC12MEM4
0148h
Conversion memory 3
ADC12MEM3
0146h
Conversion memory 2
ADC12MEM2
0144h
Conversion memory 1
ADC12MEM1
0142h
Conversion memory 0
ADC12MEM0
0140h
Interrupt-vector-word register
ADC12IV
01A8h
Interrupt-enable register
ADC12IE
01A6h
Interrupt-flag register
ADC12IFG
01A4h
Control register 1
ADC12CTL1
01A2h
Control register 0
ADC12CTL0
01A0h
DAC12_1 data
DAC12_1DAT
01CAh
DAC12_1 control
DAC12_1CTL
01C2h
DAC12_0 data
DAC12_0DAT
01C8h
DAC12_0 control
DAC12_0CTL
01C0h
Table 9-13. Peripherals With Byte Access
PERIPHERAL
OA2
OA1
OA0
LCD
REGISTER NAME
OFFSET
OA2CTL1
0C5h
Operational Amplifier 2 control register 0
OA2CTL0
0C4h
Operational Amplifier 1 control register 1
OA1CTL1
0C3h
Operational Amplifier 1 control register 0
OA1CTL0
0C2h
Operational Amplifier 0 control register 1
OA0CTL1
0C1h
Operational Amplifier 0 control register 0
OA0CTL0
0C0h
LCD memory 20
LCDM20
0A4h
⋮
⋮
⋮
LCD memory 16
LCDM16
0A0h
LCD memory 15
LCDM15
09Fh
⋮
52
ACRONYM
Operational Amplifier 2 control register 1
⋮
⋮
LCD memory 1
LCDM1
091h
LCD control and mode
LCDCTL
090h
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
Table 9-13. Peripherals With Byte Access (continued)
PERIPHERAL
ADC12
(Memory control
registers require byte
access)
REGISTER NAME
ACRONYM
OFFSET
ADC memory-control register 15
ADC12MCTL15
08Fh
ADC memory-control register 14
ADC12MCTL14
08Eh
ADC memory-control register 13
ADC12MCTL13
08Dh
ADC memory-control register 12
ADC12MCTL12
08Ch
ADC memory-control register 11
ADC12MCTL11
08Bh
ADC memory-control register 10
ADC12MCTL10
08Ah
ADC memory-control register 9
ADC12MCTL9
089h
ADC memory-control register 8
ADC12MCTL8
088h
ADC memory-control register 7
ADC12MCTL7
087h
ADC memory-control register 6
ADC12MCTL6
086h
ADC memory-control register 5
ADC12MCTL5
085h
ADC memory-control register 4
ADC12MCTL4
084h
ADC memory-control register 3
ADC12MCTL3
083h
ADC memory-control register 2
ADC12MCTL2
082h
ADC memory-control register 1
ADC12MCTL1
081h
ADC memory-control register 0
ADC12MCTL0
080h
Transmit buffer
U0TXBUF
077h
Receive buffer
U0RXBUF
076h
Baud rate
U0BR1
075h
Baud rate
U0BR0
074h
Modulation control
U0MCTL
073h
Receive control
U0RCTL
072h
Transmit control
U0TCTL
071h
USART control
U0CTL
070h
Comparator_A port disable
CAPD
05Bh
Comparator_A control 2
CACTL2
05Ah
Comparator_A control 1
CACTL1
059h
BrownOUT, SVS
SVS control register (Reset by brownout signal)
SVSCTL
056h
FLL+ Clock
FLL+ Control 1
FLL_CTL1
054h
FLL+ Control 0
FLL_CTL0
053h
System clock frequency control
SCFQCTL
052h
System clock frequency integrator
SCFI1
051h
System clock frequency integrator
SCFI0
050h
BT counter 2
BTCNT2
047h
BT counter 1
BTCNT1
046h
BT control
BTCTL
040h
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
USART0
(UART or SPI mode)
Comparator_A
Basic Timer1
Port P6
Port P5
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
Table 9-13. Peripherals With Byte Access (continued)
PERIPHERAL
Port P4
Port P3
Port P2
Port P1
Special functions
54
REGISTER NAME
ACRONYM
OFFSET
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
P4IN
01Ch
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P3 input
P3IN
018h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR module enable 2
ME2
005h
SFR module enable 1
ME1
004h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10 Input/Output Schematics
9.10.1 Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
Pad Logic
DVSS
DVSS
CAPD.x
P1SEL.x
0: Input
1: Output
0
P1DIR.x
Direction Control
From Module
1
0
1
P1OUT.x
Module X OUT
Bus
Keeper
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1IN.x
EN
D
Module X IN
P1IE.x
P1IRQ.x
P1IFG.x
EN
Q
Set
Interrupt
Edge
Select
P1IES.x
P1SEL.x
Note: 0 ≤ x ≤ 5
Note: Port function is active if CAPD.x = 0
(1)
(2)
PnSEL.x
PnDIR.x
Direction
Control From
Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P1SEL.0
P1DIR.0
P1DIR.0
P1OUT0
Out0 sig.(1)
P1IN.0
CCI0A(1)
P1IE.0
P1IFG.0
P1IES.0
P1SEL.1
P1DIR.1
P1DIR.1
P1OUT.1
MCLK
P1IN.1
CCI0B(1)
P1IE.1
P1IFG.1
P1IES.1
P1SEL.2
P1DIR.2
P1DIR.2
P1OUT.2
Out1 sig.(1)
P1IN.2
CCI1A(1)
P1IE.2
P1IFG.2
P1IES.2
P1SEL.3
P1DIR.3
P1DIR.3
P1OUT.3
SVSOUT
P1IN.3
TBOUTH(2)
P1IE.3
P1IFG.3
P1IES.3
P1SEL.4
P1DIR.4
P1DIR.4
P1OUT.4
SMCLK
P1IN.4
TBCLK(2)
P1IE.4
P1IFG.4
P1IES.4
P1SEL.5
P1DIR.5
P1DIR5
P1OUT.5
ACLK
P1IN.5
TACLK(1)
P1IE.5
P1IFG.5
P1IES.5
Timer_A
Timer_B
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.2 Port P1, P1.6 and P1.7, Input/Output With Schmitt Trigger
Pad Logic
Note: Port function is active if CAPD.6 = 0
CAPD.6
P1SEL.6
0: Input
1: Output
0
P1DIR.6
P1.6/
CA0
1
P1DIR.6
0
P1OUT.6
1
DV SS
Bus
Keeper
P1IN.6
EN
unused
D
P1IE.7
P1IRQ.07
EN
Interrupt
Edge
Select
Q
P1IFG.7
Set
P1IES.x
P1SEL.x
Comparator_A
P2CA
AVcc
CAREF
CAEX
CA0
CAF
CCI1B
+
to Timer_Ax
-
CA1
2
CAREF
Reference Block
Pad Logic
CAPD.7
Note: Port function is active if CAPD.7 = 0
P1SEL.7
0: input
1: output
0
P1DIR.7
P1.7/
CA1
1
P1DIR.7
0
P1OUT.7
1
DV SS
Bus
keeper
P1IN.7
EN
unused
D
P1IE.7
P1IRQ.07
P1IFG.7
EN
Q
Set
Interrupt
Edge
Select
P1IES.7
56
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P1SEL.7
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.3 Port P2, P2.0 and P2.4 to P2.5, Input/Output With Schmitt Trigger
Pad Logic
DVSS
DVSS
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
1
P2OUT.x
Module X OUT
Bus
Keeper
P2.0/TA2
P2.4/UTXD0
P2IN.x
P2.5/URXD0
EN
D
Module X IN
P2IE.x
P2IRQ.x
P2IFG.x
EN
Q
Set
Interrupt
Edge
Select
P2IES.x
Note:
(1)
(2)
P2SEL.x
x {0,4,5}
PnSel.x
PnDIR.x
Direction
Control From
Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
Out2 sig.(1)
P2IN.0
CCI2A(1)
P2IE.0
P2IFG.0
P2IES.0
P2IN.4
unused
P2IE.4
P2IFG.4
P2IES.4
P2IN.5
URXD0(2)
P2IE.5
P2IFG.5
P2IES.5
P2Sel.4
P2DIR.4
DVCC
P2OUT.4
UTXD0(2)
P2Sel.5
P2DIR.5
DVSS
P2OUT.5
DVSS
Timer_A
USART0
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.4 Port P2, P2.1 to P2.3, Input/Output With Schmitt Trigger
Pad Logic
DVSS
DVSS
Module IN of pin
P1.3/TBOUTH/SVSOUT
P1DIR.3
P1SEL.3
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
P2OUT.x
1
0
1
Module X OUT
Bus
Keeper
P2.1/TB0
P2.2/TB1
P2IN.x
P2.3/TB2
EN
Module X IN
D
P2IE.x
P2IRQ.x
Q
P2IFG.x
EN
Set
Interrupt
Edge
Select
P2IES.x
P2SEL.x
Note: 1 ≤ x ≤ 3
(1)
58
PnSel.x
PnDIR.x
Direction
Control From
Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.1
P2DIR.1
P2DIR.1
P2OUT.1
Out0 sig.(1)
P2IN.1
CCI0A(1)
CCI0B
P2IE.1
P2IFG.1
P2IES.1
P2Sel.2
P2DIR.2
P2DIR.2
P2OUT.2
Out1 sig.(1)
P2IN.2
CCI1A(1)
CCI1B
P2IE.2
P2IFG.2
P2IES.2
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
Out2 sig.(1)
P2IN.3
CCI2A(1)
CCI2B
P2IE.3
P2IFG.3
P2IES.3
Timer_B
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.5 Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD
Segment xx
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
P2OUT.x
1
Module X OUT
Bus
Keeper
P2.6/CAOUT/S19
P2.7/ADC12CLK/S18
P2IN.x
EN
Module X IN
P2IRQ.x
D
P2IE.x
P2IFG.x
EN
Interrupt
Edge
Select
Q
Set
P2IES.x
P2SEL.x
Note: 6 ≤ x ≤ 7
PnSel.x
PnDIR.x
Direction
Control
From
Module
PnOUT.x
Module X
OUT
PnIN.x
Module X
IN
PnIE.x
PnIFG.x
PnIES.x
Port/LCD
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
CAOUT(1)
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
0: LCDPx < 02h
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
0: LCDPx < 02h
P2Sel.7
(1)
(2)
P2DIR.7
P2DIR.7
P2OUT.7
ADC12CLK
(2)
Comparator_A
ADC12
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.6 Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
MSP430x43xIPN (80-Pin) Only
0: Port active
1: Segment xx function active
LCDPx[0]
LCDPx[1]
LCDPx[2]
Pad Logic
Segment xx
x43xIPZ and x44xIPZ have not segment
Function on Port P3: Both lines are low.
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
1
0
1
P3OUT.x
Module X OUT
Bus
Keeper
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
P3.3/UCLK0/S28
P3IN.x
EN
Module X IN
D
Note: 0 ≤ x ≤ 3
Direction Control
From Module
PnOUT.x
P3DIR.0
DVSS
P3DIR.1
DCM_SIMO0
P3DIR.2
P3DIR.3
PnSel.x
PnDIR.x
P3Sel.0
P3Sel.1
P3Sel.2
P3Sel.3
Module X OUT
PnIN.x
P3OUT.0
DVSS
P3IN.0
STE0(in)
P3OUT.1
SIMO0(out)
P3IN.1
SIMO0(in)
DCM_SOMI0
P3OUT.2
SOMIO(out)
P3IN.2
SOMI0(in)
DCM_UCLK0
P3OUT.3
UCLK0(out)
P3IN.3
UCLK0(in)
Direction Control for SIMO0 and UCLK0
SYNC
MM
60
DCM_SIMO0
DCM_UCLK0
Direction Control for SOMI0
SYNC
MM
STC
STC
STE
STE
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Module X IN
DCM_SOMI0
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.7 Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
0: Port active
1: Segment xx function active
Pad Logic
LCDPx[2]
Segment xx
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
1
0
P3OUT.x
1
Module X OUT
Bus
Keeper
P3.4/S27
P3.5/S26
P3.6/S25/DMAE0
P3.7/S24
P3IN.x
EN
Module X IN
D
Note: 4 ≤ x ≤ 7
PnSel.x
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P3SEL.4
P3DIR.4
P3DIR.4
P3OUT.4
DVSS
P3IN.4
unused
P3SEL.5
P3DIR.5
P3DIR.5
P3OUT.5
DVSS
P3IN.5
unused
P3SEL.6
P3DIR.6
P3DIR.6
P3OUT.6
DVSS
P3IN.6
DMAE0
P3SEL.7
P3DIR.7
P3DIR.7
P3OUT.7
DVSS
P3IN.7
unused
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.8 Port P4, P4.0 to P4.5, Input/Output With Schmitt Trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD
Segment xx
P4SEL.x
0: Input
1: Output
0
P4DIR.x
Direction Control
From Module
1
0
1
P4OUT.x
Module X OUT
Bus
Keeper
P4.0/S9
P4.1/S8
P4.2/S7
P4.3/S6
P4.4/S5
P4.5/S4
P4IN.x
EN
Module X IN
D
Note: 0 ≤ x ≤ 5
62
PnSEL.x
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P4SEL.0
P4DIR.0
P4DIR.0
P4OUT.0
DVSS
P4IN.0
unused
P4SEL.1
P4DIR.1
P4DIR.1
P4OUT.1
DVSS
P4IN.1
unused
P4SEL.2
P4DIR.2
P4DIR.2
P4OUT.2
DVSS
P4IN.2
unused
P4SEL.3
P4DIR.3
P4DIR.3
P4OUT.3
DVSS
P4IN.3
unused
P4SEL.4
P4DIR.4
P4DIR.4
P4OUT.4
DVSS
P4IN.4
unused
P4SEL.5
P4DIR.5
P4DIR.5
P4OUT.5
DVSS
P4IN.5
unused
DEVICE
PORT BITS
PORT FUNCTION
LCD SEGMENT FUNCTION
MSP430FG43x
P4.0 to P4.5
LCDPx < 01h
LCDPx ≥ 01h
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.9 Port P4, P4.6, Input/Output With Schmitt Trigger
INCH=15(1)
a15 (1)
0: Segment S3 disabled
1: Segment S3 enabled
Pad Logic
1, If LCDPx ≥ 01h
Segment S3
P4SEL.6
0: input
1: output
0
P4DIR.6
Direction Control
From Module
1
0
P4OUT.6
1
Module XOUT
Bus
keeper
P4.6/S3/A15
P4IN.6
EN
D
Module X IN
(1)
Signal from or to ADC12
PnSEL.x
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P4SEL.6
P4DIR.6
P4DIR.6
P4OUT.6
DVSS
P4IN.6
unused
DEVICE
PORT BITS
PORT FUNCTION
LCD SEGMENT FUNCTION
MSP430FG43x
P4.6
LCDPx < 01h
LCDPx ≥ 01h
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.10 Port P4, P4.7, Input/Output With Schmitt Trigger
INCH=14
(1)
a14
(1)
OAADC0
0: Segment S2 disabled
1: Segment S2 enabled
Pad Logic
1, If LCDPx ≥ 01h
Segment S2
P4SEL.7
0: input
1: output
0
P4DIR.7
Direction Control
From Module
1
0
P4OUT.7
1
Module XOUT
Bus
keeper
P4.7/S2/A14
P4IN.7
EN
D
Module X IN
(1)
64
Signal from or to ADC12
PnSel.x
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P4Sel.7
P4DIR.7
P4DIR.7
P4OUT.7
DVSS
P4IN.7
Unused
DEVICE
PORT BITS
PORT FUNCTION
LCD SEGMENT FUNCTION
MSP430FG43x
P4.7
LCDPx < 01h
LCDPx ≥ 01h
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.11 Port P5, P5.0, Input/Output With Schmitt Trigger
OAADC0
INCH=13(1)
a13 (1)
0: Segment S1 disabled
1: Segment S1 enabled
Pad Logic
1, If LCDPx ≥ 01h
Segment S1
P5SEL.0
0: input
1: output
0
P5DIR.0
Direction Control
From Module
1
0
P5OUT.0
1
Module XOUT
Bus
keeper
P5.0/S1/A13
P5IN.0
EN
D
Module X IN
(1)
Signal from or to ADC12
PnSEL.x
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P5SEL.0
P5DIR.0
P5DIR.0
P5OUT.0
DVSS
P5IN.0
unused
DEVICE
PORT BITS
PORT FUNCTION
LCD SEGMENT FUNCTION
MSP430FG43x
P5.0
LCDPx < 01h
LCDPx ≥ 01h
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.12 Port P5, P5.1, Input/Output With Schmitt Trigger
INCH=12(1)
OAADC0
a12(1)
0: Segment S0 disabled
1: Segment S0 enabled
1, If LCDPx ≥ 01h
Pad Logic
DAC12.1OPS
Segment S0
P5SEL.1
0: input
1: output
0
P5DIR.1
Direction Control
From Module
1
0
P5OUT.1
1
Module XOUT
Bus
keeper
P5.1/S0/
A12/DAC1
P5IN.1
EN
D
Module X IN
’0’, if DAC12.1CALON=0 AND
DAC12.1AMPx>1 AND DAC12.1OPS=1
+
1
0
-
’1’, if DAC12.1AMPx>1
’1’, if DAC12.1AMPx=1
DAC12.1OPS
DAC12.1OPS
1
P6.7/A7/
DAC1/SVSIN
DAC1_2_OA
(1)
0
Signal from or to ADC12
Function
P5SEL.1
LCDPx
DAC12.1OPS
DAC12.1AMPx
3-State
X
X
1
0
0V
X
X
1
1
DAC1 output
(the output voltage can be converted with ADC12, channel A12)
X
X
1
>1
ADC12
Channel 12, A12
1
X
0
X
LCD
Segment S0, initial state
0
≥ 01h
0
X
Port
P5.1
0
< 01h
0
X
DAC12
66
Description
PnSEL.x
PnDIR.x
Direction
Control From
Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
Segment
Port/LCD
P5SEL.1
P5DIR.1
P5DIR.1
P5OUT.1
DVSS
P5IN.1
Unused
S0
0: LCDPx < 01h
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.13 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger
0: Port active
1: LCD function active
Port/LCD
LCD signal
Pad Logic
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
Keeper
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5IN.x
EN
Module X IN
D
Note: 2 ≤ x ≤ 4
PnSel.x
PnDIR.x
Direction
Control From
Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
LCD signal
Port/LCD
P5Sel.2
P5DIR.2
P5DIR.2
P5OUT.2
DVSS
P5IN.2
Unused
COM1
P5SEL.2
P5Sel.3
P5DIR.3
P5DIR.3
P5OUT.3
DVSS
P5IN.3
Unused
COM2
P5SEL.3
P5Sel.4
P5DIR.4
P5DIR.4
P5OUT.4
DVSS
P5IN.4
Unused
COM3
P5SEL.4
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.14 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger
0: Port active
1: LCD function active
Port/LCD
LCD signal
Pad Logic
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
Keeper
P5.5/R13
P5.6/R23
P5.7/R33
P5IN.x
EN
D
Module X IN
Note: 5 ≤ x ≤ 7
68
PnSel.x
PnDIR.x
Direction
Control From
Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
LCD signal
Port/LCD
P5Sel.5
P5DIR.5
P5DIR.5
P5OUT.5
DVSS
P5IN.5
Unused
R13
P5SEL.5
P5Sel.6
P5DIR.6
P5DIR.6
P5OUT.6
DVSS
P5IN.6
Unused
R23
P5SEL.6
P5Sel.7
P5DIR.7
P5DIR.7
P5OUT.7
DVSS
P5IN.7
Unused
R33
P5SEL.7
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.15 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger
(1)(2)
INCH=x
(1)(2)
ax
(1)
P6SEL.x
(1)
0
P6DIR.x
Direction Control
From Module
P6OUT.x
Pad Logic
0: input
1: output
1
(1)
0
1
Module XOUT
Bus
keeper
P6.0/A0/OA0I0
P6.2/A2/OA0I1
P6.4/A4/OA1I0
(1)
P6IN.x
EN
(1)
D
Module X IN
+
-
(1)
(1)
x = {0, 2, 4}
(2)
Signal from or to ADC12
OA0 / OA1
PnSel.x(1)
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.0
P6DIR.0
P6DIR.0
P6OUT.0
DVSS
P6IN.0
unused
P6Sel.2
P6DIR.2
P6DIR.2
P6OUT.2
DVSS
P6IN.2
unused
P6Sel.4
P6DIR.4
P6DIR.4
P6OUT.4
DVSS
P6IN.4
unused
The signal at pin P6.x/Ax is used by the 12-bit ADC module.
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.16 Port P6, P6.1, Input/Output With Schmitt Trigger
INCH=1(1)
a1 (1)
P6SEL.1
0
P6DIR.1
Direction Control
From Module
P6OUT.1
Pad Logic
0: input
1: output
1
0
1
Module XOUT
Bus
keeper
P6.1/A1/OA0O
P6IN.1
EN
D
Module X IN
’1’, if OAADC1 = 1 OR OAFCx = 0
+
0
OA0
-
(1)
(1)
70
1
OA0
Signal from or to ADC12
PnSel.x(1)
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.1
P6DIR.1
P6DIR.1
P6OUT.1
DVSS
P6IN.1
unused
The signal at pin P6.x/Ax is used by the 12-bit ADC module.
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.17 Port P6, P6.3, Input/Output With Schmitt Trigger
INCH=3(1)
a3 (1)
P6SEL.3
Pad Logic
0: input
1: output
0
P6DIR.3
Direction Control
From Module
P6OUT.3
1
0
1
Module XOUT
Bus
keeper
P6.3/A3/OA1I1/OA1O
P6IN.3
EN
D
Module X IN
’1’, if OAADC1 = 1 OR OAFCx = 0
+
0
OA1
-
(1)
(1)
1
OA1
Signal from or to ADC12
PnSel.x(1)
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.3
P6DIR.3
P6DIR.3
P6OUT.3
DVSS
P6IN.3
unused
The signal at pin P6.x/Ax is used by the 12-bit ADC module.
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.18 Port P6, P6.5, Input/Output With Schmitt Trigger
INCH=5(1)
a5 (1)
P6SEL.5
Pad Logic
0: input
1: output
0
P6DIR.5
Direction Control
From Module
P6OUT.5
1
0
1
Module XOUT
Bus
keeper
P6.5/A5/OA2I1/OA2O
P6IN.5
EN
D
Module X IN
’1’, if OAADC1 = 1 OR OAFCx = 0
0
+
OA2
-
(1)
(1)
72
1
OA2
Signal from or to ADC12
PnSel.x(1)
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.5
P6DIR.5
P6DIR.5
P6OUT.5
DVSS
P6IN.5
unused
The signal at pins P6.x/Ax is used by the 12-bit ADC module.
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.19 Port P6, P6.6, Input/Output With Schmitt Trigger
0: Port active, T- Switch off
1: T- Switch is on, Port disabled
INCH=6(1)
a6 (1)
’1’, if DAC12.0AMP>0
P6SEL.6
P6DIR.6
0
P6DIR.6
1
P6OUT.6
0
0: input
1: output
Pad Logic
1
DVSS
Bus
keeper
P6.6/A6/DAC0/OA2I0
P6IN.6
EN
D
’0’, if DAC12CALON = 0 AND
DAC12AMPx>1 AND DAC12OPS = 0
+
-
1
0
’1’, if DAC12AMPx>1
(1)
’1’, if DAC12AMPx=1
DAC12OPS
Signal from or to ADC12
DAC12OPS
0
Ve REF+/DAC0
DAC0_2_OA
1
(1)
PnSel.x(1)
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.6
P6DIR.6
P6DIR.6
P6OUT.6
DVSS
P6IN.6
unused
The signal at pins P6.x/Ax is used by the 12-bit ADC module.
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.20 Port P6, P6.7, Input/Output With Schmitt Trigger
To SVS Mux (15) (2)
0: Port active, T−Switch off
1: T−Switch is on, Port disabled
INCH=7(1)
a7 (1)
’1’, if DAC12.1AMP>0
DAC12.1OPS
’1’, if VLD=15 (3)
P6SEL.7
P6DIR.7
0: input
1: output
0
Pad Logic
1
P6DIR.7
0
P6OUT.7
1
DVSS
Bus
keeper
P6.7/A7/
DAC1/SVSIN
P6IN.7
EN
D
’0’, if DAC12CALON = 0 AND
DAC12AMPx>1 AND DAC12OPS = 0
+
−
1
0
’1’, if DAC12AMPx>1
’1’, if DAC12AMPx=1
DAC12OPS
DAC12OPS
0
P5.1/S0/
A12/DAC1
DAC1_2_OA
1
(1)
74
(1)
Signal from or to ADC12
(2)
Signal to SVS block, selected if VLD=15
(3)
VLD control bits are located in SVS
PnSel.x(1)
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.7
P6DIR.7
P6DIR.7
P6OUT.7
DVSS
P6IN.7
unused
The signal at pins P6.x/Ax is used by the 12-bit ADC module. The signal at pin P6.7/A7/SVSIN is also connected to the input
multiplexer in the module brownout/supply voltage supervisor.
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.21 VeREF+/DAC0
DAC12.0OPS
0
DAC0_2_OA
P6.6/A6/DAC0/OA2I0
1
Reference Voltage to DAC1
Reference Voltage to ADC12
(1)
Reference Voltage to DAC0
Ve REF+ /DAC0
’0’, if DAC12CALON = 0
DAC12AMPx>1 AND DAC12OPS=1
+
-
1
0
’1’, if DAC12AMPx>1
’1’, if DAC12AMPx=1
DAC12OPS
(1) If the reference of DAC0 is taken from pin Ve
/DAC0, unpredictable voltage levels will be on pin.
REF+
In this situation, the DAC0 output is fed back to its own reference input.
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.22 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
by JTAG
DV CC
TDI
Burn and Test
Fuse
TDI/TCLK
Test
and
Emulation
DV CC
TMS
Module
TMS
DV CC
TCK
TCK
RST/NMI
Tau ~ 50 ns
Brownout
TCK
76
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G
D
U
S
G
D
U
S
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
9.10.23 JTAG Fuse Check Mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I(TF)) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state
(see Figure 9-8). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I(TF)
ITDI/TCLK
Figure 9-8. Fuse Check Mode Current
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
10 Device and Documentation Support
10.1 Device Support
10.1.1 Development Support
TI offers an extensive line of development tools, including tools to evaluate the performance of the processors,
generate code, develop algorithm implementations, and fully integrate and debug software and hardware
modules. The tool's support documentation is electronically available within the Code Composer Studio™
Integrated Development Environment (IDE).
The following products support development of the MSP430FG43x device applications:
Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE): including
Editor C/C++/Assembly Code Generation, and Debug plus additional development tools.
For a complete listing of development-support tools for the MSP430FG43x platform, visit the Texas Instruments
website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office or
authorized distributor.
10.1.1.1 Development Kit
The MSP-FET430U80 is a powerful flash emulation tool that includes the hardware and software required to
quickly begin application development on the MSP430 MCU. It includes a ZIF socket target board and a USB
debugging interface (MSP-FET) used to program and debug the MSP430 in-system through the JTAG interface
or the pin saving Spy Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased and programmed in
seconds with only a few keystrokes, and because the MSP430 flash is ultra-low power, no external power supply
is required.
The debugging tool interfaces the MSP430 to the included integrated software environment and includes code to
start your design immediately.
10.1.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format. Figure 10-1 provides a legend for reading the complete device
name.
78
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
MSP 430 F 5 438 A I PM T -EP
Processor Family
Optional: Additional Features
MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
Optional: Temperature Range
Optional: Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform
MCU Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash
L = No nonvolatile memory
Specialized Application
AFE = Analog front end
BQ = Contactless power
CG = ROM medical
FE = Flash energy meter
FG = Flash medical
FW = Flash electronic flow meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD driver
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD driver
0 = Low-voltage series
Feature Set
Various levels of integration within a series
Optional: Revision
Updated version of the base part number
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced product (–40°C to 105°C)
-HT = Extreme temperature parts (–55°C to 150°C)
-Q1 = Automotive Q100 qualified
Figure 10-1. Device Nomenclature
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Product Folder Links: MSP430FG439 MSP430FG438 MSP430FG437
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MSP430FG439, MSP430FG438, MSP430FG437
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SLAS380F – APRIL 2004 – REVISED MARCH 2022
10.2 Documentation Support
The following documents describe the MSP430FG43x microcontrollers. Copies of these documents are available
on the Internet at www.ti.com.
MSP430x4xx Family User's Guide
Detailed description of all modules and peripherals available in this device family.
MSP430FG439 Microcontroller Errata
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430FG438 Microcontroller Errata
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430FG437 Microcontroller Errata
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
MSP Academy is a starting point for all developers to learn about the MSP430 MCU Platform, which provides
affordable solutions for many applications. MSP Academy delivers easy-to-use training modules that span a
wide range of topics and LaunchPad development kits in the MSP430 MCU portfolio.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
MSP430™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
80
This glossary lists and explains terms, acronyms, and definitions.
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Product Folder Links: MSP430FG439 MSP430FG438 MSP430FG437
MSP430FG439, MSP430FG438, MSP430FG437
www.ti.com
SLAS380F – APRIL 2004 – REVISED MARCH 2022
11 Mechanical Packaging and Orderable Information
11.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430FG437IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG437
MSP430FG437IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG437
MSP430FG437IZCAR
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG437
MSP430FG437IZCAT
ACTIVE
NFBGA
ZCA
113
250
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG437
MSP430FG438IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG438
MSP430FG438IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG438
MSP430FG438IZCAR
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG438
MSP430FG438IZCAT
ACTIVE
NFBGA
ZCA
113
250
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG438
MSP430FG439IPN
ACTIVE
LQFP
PN
80
119
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG439
MSP430FG439IPNR
ACTIVE
LQFP
PN
80
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG439
MSP430FG439IZCAR
ACTIVE
NFBGA
ZCA
113
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG439
MSP430FG439IZCAT
ACTIVE
NFBGA
ZCA
113
250
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG439
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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