MSP430FG6626, MSP430FG6625
MSP430FG6626, MSP430FG6425
MSP430FG6625
MSP430FG6426,
MSP430FG6426,
MSP430FG6425
SLAS874B –
MAY 2015 – REVISED
SEPTEMBER 2020
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
MSP430FG662x, MSP430FG642x Mixed-Signal Microcontrollers
•
1 Features
•
•
•
•
•
•
•
•
Low supply voltage range:
3.6 V down to 1.8 V
High-performance integrated signal chain
– Continuous-time sigma-delta 16-bit analog-todigital converter (ADC) with internal reference
with 10 external analog inputs, 6 single-ended
and 4 selectable as differential or single-ended
– Dual operational amplifiers
– Quad low-impedance ground switches
– Voltage comparator
Dual 12-bit digital-to-analog converters (DACs)
with synchronization
Integrated LCD driver with contrast control for up
to 160 segments
MSP430FG662x: Full-speed universal serial bus
(USB)
– Integrated USB-PHY
– Integrated 3.3-V and 1.8-V USB power system
– Integrated USB-PLL
– Eight input and eight output endpoints
Ultra-low power consumption
– Active mode (AM),
all system clocks active:
250 µA/MHz at 8 MHz, 3.0 V, flash program
execution (typical)
– Standby mode (LPM3):
watchdog with crystal, and supply supervisor
operational, full RAM retention, fast wakeup:
3.2 µA at 2.2 V, 3.4 µA at 3.0 V (typical)
– Shutdown RTC mode (LPM3.5):
shutdown mode, active RTC with crystal:
0.9 µA at 3.0 V (typical)
– Shutdown mode (LPM4.5):
0.2 µA at 3.0 V (typical)
Intelligent digital peripherals
– Two 16-bit timers with three capture/compare
registers each
– One 16-bit timer with five capture/compare
registers
– One 16-bit timer with seven capture/compare
registers
– 6-channel internal DMA
– Hardware multiplier supports 32-bit operations
Four universal serial communication interfaces
(USCIs)
– USCI_A0 and USCI_A1
•
•
•
•
•
•
•
•
•
•
Enhanced UART with automatic baud-rate
detection
• IrDA encoder and decoder
• Synchronous SPI
– USCI_B0 and USCI_B1
• I2C
• Synchronous SPI
RTC with calibration logic for time offset correction,
operation in LPM 3.5
16-bit RISC architecture, extended memory, up to
20-MHz system clock
Flexible power-management system
– Fully integrated LDO with programmable
regulated core supply voltage
– Supply voltage supervision, monitoring, and
brownout
Unified clock system
– FLL control loop for frequency stabilization
– Low-power low-frequency internal clock source
(VLO)
– Low-frequency trimmed internal reference
source (REFO)
– 32-kHz crystals (XT1)
– High-frequency crystals up to 32 MHz (XT2)
Separate voltage supply for backup subsystem
– 32-kHz low-frequency oscillator (XT1)
– RTC
– Backup memory (8 bytes)
Development tools and software (also see Tools
and Software)
– MSP-TS430PZ100AUSB 100-pin target
development board
– MSP430Ware™ code examples
Wake up from standby mode in 3 µs (typical)
Serial onboard programming, no external
programming voltage needed
Available in 100-pin LQFP and 113-pin Microstar
Junior™ BGA packages
Device Comparison summarizes the available
family members
2 Applications
•
•
•
•
•
•
Analog sensor systems
Digital sensor systems
Hand-held meters
Medical diagnostic meters
Hand-held industrial testers
Measurement equipment
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Copyright
© 2020 Texas
Instruments
Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
3 Description
The Texas Instruments MSP430FG662x and MSP430FG642x microcontrollers (MCUs) are part of the
MSP430TM Metrology and Monitoring portfolio. The architecture and integrated peripherals, combined with five
extensive low-power modes, are optimized to achieve extended battery life in portable and battery-powered
measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant
generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the
devices to wake up from low-power modes to active mode in less than 5 µs.
The MSP430FG662x MCUs are targeted at small signal-monitoring applications and include a 16-bit sigma-delta
ADC, dual low-power operational amplifiers, dual 12-bit DACs, voltage comparator, four USCIs (two USCI_A
modules and two USCI_B modules), four 16-bit timers, a hardware multiplier, a DMA module, an RTC module,
an LCD driver with integrated contrast control for up to 160 segments, integrated full-speed USB, an auxiliary
supply system, up to 128KB flash, 10KB SRAM and 73 I/O pins in 100‑pin devices and 113‑pin devices.
The MSP430FG642x MCUs are targeted at small-signal monitoring applications and include a 16-bit sigma-delta
ADC, dual low-power operational amplifiers, dual 12-bit DACs, voltage comparator, four USCIs (two USCI_A
modules and two USCI_B modules), four 16-bit timers, a hardware multiplier, a DMA module, an RTC module,
an LCD driver with integrated contrast control for up to 160 segments, an auxiliary supply system, up to 128KB
of flash, 10KB of SRAM, and 73 I/O pins in 100‑pin devices and 113‑pin devices.
Typical applications for these microcontrollers include small signal-monitoring applications such as handheld test
and measurement equipment, field transmitters, and blood glucose meters. These microcontrollers can reduce
overall system cost through high analog integration and enable long battery life by low-power operation.
The MSP430FG662x and MSP430FG642x MCUs are supported by an extensive hardware and software
ecosystem with reference designs and code examples to get your design started quickly. Development kits
include the MSP-TS430PZ100AUSB 100-pin target development board. TI also provides free MSP430Ware™
software, which is available as a component of Code Composer Studio™ IDE desktop and cloud versions within
TI Resource Explorer. The MSP430 MCUs are also supported by extensive online collateral, training, and online
support through the TI E2E™ support forums.
For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.
Device Information
PART
NUMBER(1)
MSP430FG6626IPZ
MSP430FG6626IZCA
MSP430FG6626IZQW(3)
(1)
(2)
(3)
2
PACKAGE
BODY SIZE(2)
PZ (100)
14 mm × 14 mm
nFBGA (113)
7 mm × 7 mm
MicroStar Junior™ BGA (113)
7 mm × 7 mm
For the most current part, package, and ordering information for all available devices, see the
Package Option Addendum in Section 12, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 12.
All orderable part numbers in the ZQW (MicroStar Junior BGA) package have been changed to a
status of Last Time Buy. Visit the Product life cycle page for details on this status.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
4 Functional Block Diagrams
Figure 4-1 shows the functional block diagram for the MSP430FG6626 and MSP430FG6625 devices.
XIN XOUT
DVCC
DVSS
AVCC
AVSS
RST/NMI
VCORE
NR
P1.x
XT2IN
XT2OUT
Unified
Clock
System
8KB
RAM
ACLK
128KB
64KB
SMCLK
MCLK
Watchdog
+2KB RAM
USB Buffer
Flash
SYS
Power
Management
LDO
SVM, SVS
Brownout
+8B Backup
RAM
P2 Port
Mapping
Controller
PA
P2.x
P3.x
PB
P4.x
P5.x
PC
P6.x
P7.x
PD
P8.x
I/O Ports
P1, P2
2×8 I/Os
Interrupt
Capability
I/O Ports
P3, P4
2×8 I/Os
Interrupt
Capability
I/O Ports
P5, P6
1×7 I/Os
1×8 I/Os
I/O Ports
P7, P8
1×6 I/Os
1×8 I/Os
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×15 I/Os
PD
1×14 I/Os
P9.x
DP, DM, PUR
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
USCI0,1
USB
Ax: UART,
IrDA, SPI
Full-Speed
2
Bx: SPI, I C
CPUXV2
and
Working
Registers
DMA
6 Channel
EEM
(L: 8+2)
TA1 and
TA2
TA0
JTAG,
SBW
Interface
MPY32
Port PJ
Timer_A
5 CC
Registers
PJ.x
2 Timer_A
each with
3 CC
Registers
TB0
Timer_B
7 CC
Registers
CTSD16
Sigma-Delta
ADC
RTC_B
CRC16
Comp_B
Battery
Backup
System
DAC12_A
14 inputs
(6 SE ext,
4 SE/diff ext,
4 int)
12 bit
2 channels
voltage out
Reference
1.5 V,
2.0 V,
2.5 V
LCD_B
160
Segments
Operational
Amplifiers
OA0, OA1
Quad
Ground
Switches
1.16 V
VREFBG
Figure 4-1. Functional Block Diagram – MSP430FG6626, MSP430FG6625
Figure 4-2 shows the functional block diagram for the MSP430FG6426 and MSP430FG6425 devices.
XIN XOUT
DVCC
DVSS
AVCC
AVSS
RST/NMI
VCORE
NR
P1.x
XT2IN
XT2OUT
Unified
Clock
System
MCLK
ACLK
SMCLK
Power
Management
128KB
64KB
10KB
RAM
Flash
+8B Backup
RAM
SYS
Watchdog
LDO
SVM, SVS
Brownout
P2 Port
Mapping
Controller
PA
P2.x
I/O Ports
P1, P2
2×8 I/Os
Interrupt
Capability
PA
1×16 I/Os
P3.x
PB
P4.x
I/O Ports
P3, P4
2×8 I/Os
Interrupt
Capability
PB
1×16 I/Os
P5.x
PC
P6.x
I/O Ports
P5, P6
1×7 I/Os
1×8 I/Os
PC
1×15 I/Os
P7.x
PD
P8.x
I/O Ports
P7, P8
1×6 I/Os
1×8 I/Os
PD
1×14 I/Os
PU.0,
PU.1 LDOO LDOI
P9.x
I/O Ports
P9
1×8 I/Os
PE
1×8 I/Os
USCI0,1
PU Port
Ax: UART,
IrDA, SPI
LDO
2
Bx: SPI, I C
CPUXV2
and
Working
Registers
DMA
6 Channel
EEM
(L: 8+2)
JTAG,
SBW
Interface
Port PJ
PJ.x
TA1 and
TA2
TA0
MPY32
Timer_A
5 CC
Registers
2 Timer_A
each with
3 CC
Registers
CTSD16
Sigma-Delta
ADC
RTC_B
TB0
Timer_B
7 CC
Registers
CRC16
Battery
Backup
System
Comp_B
14 inputs
(6 SE ext,
4 SE/dif ext,
4 int)
Reference
DAC12_A
12 bit
2 channels
voltage out
1.5 V,
2.0 V,
2.5 V
LCD_B
160
Segments
Operational
Amplifiers
OA0, OA1
Quad
Ground
Switches
1.16 V
VREFBG
Figure 4-2. Functional Block Diagram – MSP430FG6426, MSP430FG6425
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................2
4 Functional Block Diagrams............................................ 3
5 Revision History.............................................................. 5
6 Device Comparison......................................................... 6
6.1 Related Products........................................................ 7
7 Terminal Configuration and Functions..........................8
7.1 Pin Diagrams.............................................................. 8
7.2 Pin Attributes.............................................................11
7.3 Signal Descriptions................................................... 18
7.4 Pin Multiplexing.........................................................25
7.5 Buffer Type................................................................25
7.6 Connection of Unused Pins...................................... 26
8 Specifications................................................................ 27
8.1 Absolute Maximum Ratings ..................................... 27
8.2 ESD Ratings............................................................. 27
8.3 Recommended Operating Conditions.......................27
8.4 Active Mode Supply Current Into VCC Excluding
External Current.......................................................... 29
8.5 Low-Power Mode Supply Currents (Into VCC)
Excluding External Current..........................................30
8.6 Low-Power Mode With LCD Supply Currents
(Into VCC) Excluding External Current......................... 31
8.7 Thermal Resistance Characteristics ........................ 32
8.8 Timing and Switching Characteristics....................... 32
9 Detailed Description......................................................76
9.1 Overview................................................................... 76
9.2 CPU.......................................................................... 76
9.3 Instruction Set........................................................... 77
9.4 Operating Modes...................................................... 78
4
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9.5 Interrupt Vector Addresses....................................... 79
9.6 USB BSL...................................................................80
9.7 UART BSL................................................................ 80
9.8 JTAG Operation........................................................ 81
9.9 Flash Memory........................................................... 81
9.10 RAM........................................................................ 81
9.11 Backup RAM........................................................... 82
9.12 Peripherals..............................................................82
9.13 Input/Output Diagrams............................................96
9.14 Device Descriptors................................................136
9.15 Memory................................................................. 136
9.16 Identification..........................................................152
10 Applications, Implementation, and Layout............. 153
10.1 Device Connection and Layout Fundamentals..... 153
10.2 Peripheral- and Interface-Specific Design
Information................................................................ 157
11 Device and Documentation Support........................168
11.1 Getting Started...................................................... 168
11.2 Device Nomenclature............................................168
11.3 Tools and Software................................................170
11.4 Documentation Support........................................ 172
11.5 Related Links........................................................ 173
11.6 Support Resources............................................... 173
11.7 Trademarks........................................................... 173
11.8 Electrostatic Discharge Caution............................ 173
11.9 Export Control Notice............................................ 173
11.10 Glossary.............................................................. 174
12 Mechanical, Packaging, and Orderable
Information.................................................................. 175
12.1 Packaging Information.......................................... 175
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from revision A to revision B
Changes from September 27, 2018 to September 11, 2020
Page
• Updated the numbering for sections, tables, figures, and cross-references throughout the document..............1
• Updated Section 1, Features ............................................................................................................................. 1
• Added nFBGA package (ZCA) information throughout document......................................................................2
• Added note about status change for all orderable part numbers in the ZQW package in Device Information .. 2
• Updated Section 3, Description ......................................................................................................................... 2
• Corrected the signal name and description (changed DVCC to AVCC) on pin 16 (or H1, G2) in Table 7-2,
Signal Descriptions .......................................................................................................................................... 18
• Changed the MAX value of the IERASE and IMERASE, IBANK parameters in Section 8.8.19.1, Flash Memory ... 75
Changes from initial release to revision A
Changes from May 22, 2015 to September 26, 2018
Page
• Added Section 6.1, Related Products ................................................................................................................7
• Added typical conditions statements at the beginning of Section 8, Specifications .........................................27
• Updated notes (1) and (2) and added note (3) in Section 8.8.4.1, Wake-up Times From Low-Power Modes
and Reset ........................................................................................................................................................ 37
• Removed duplicate symbol and removed note (5) on Ri(VREFBG), Ri(VeREF+) parameter in Section 8.8.13.4, 12Bit DAC, Reference Input Specifications ......................................................................................................... 64
• Added "CBPWRMD = 00 or 01" to Test Conditions of the first row of the tEN_CMP parameter; Added second
row for tEN_CMP with Test Conditions of "CBPWRMD = 10" and MAX value of 100 µs in Section 8.8.16.1,
Comparator_B ................................................................................................................................................. 70
• Added Section 8.8.18, LDO-PWR (LDO Power System) ................................................................................ 74
• Throughout document, changed all instances of "bootstrap loader" to "bootloader"........................................ 85
• Changed decoupling capacitor recommendation from "one 10 µF and one 100 nF" to "one 1 µF and one
100 nF" for consistency with Section 10.1.1 .................................................................................................. 157
• Changed decoupling capacitor recommendation from "one 10 µF and one 100 nF" to "one 1 µF and one
100 nF" for consistency with Section 10.1.1 .................................................................................................. 158
• Changed decoupling capacitor recommendation from "one 10 µF and one 100 nF" to "one 1 µF and one
100 nF" for consistency with Section 10.1.1 .................................................................................................. 161
• Added Section 10.2.5, DAC12 Peripheral ..................................................................................................... 165
• Added Section 10.2.6, USB Module .............................................................................................................. 166
• Added Section 10.2.7, LDO Module .............................................................................................................. 167
• Replaced former section Development Tools Support with Section 11.3, Tools and Software ......................170
• Changed format and added content to Section 11.4, Documentation Support ..............................................172
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
6 Device Comparison
Table 6-1 summarizes the available family members.
Table 6-1. Device Comparison
DEVICE(1) (2)
FLASH
(KB)
SRAM
(KB)(3)
Timer_A(4)
Timer_B(5)
USCI_A:
UART, IrDA,
SPI
MSP430FG6626
128
8+2
5, 3, 3
7
2
2
10 ext,
5 int
2
2
12
1
73
100 PZ,
113 ZCA
113 ZQW
MSP430FG6625
64
8+2
5, 3, 3
7
2
2
10 ext,
5 int
2
2
12
1
73
100 PZ,
113 ZCA
113 ZQW
MSP430FG6426
128
10
5, 3, 3
7
2
2
10 ext,
5 int
2
2
12
0
73
100 PZ,
113 ZCA
113 ZQW
MSP430FG6425
64
10
5, 3, 3
7
2
2
10 ext,
5 int
2
2
12
0
73
100 PZ,
113 ZCA
113 ZQW
(1)
(2)
(3)
(4)
(5)
(6)
6
USCI_B:
SPI, I2C
CTSD16
(Ch)(6)
DAC12_A
(Ch)
OA
Comp_B
(channels)
USB
I/Os
PACKAGE
For the most current package and ordering information, see the Package Option Addendum in Section 12, or see the TI website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
The additional 2KB of USB SRAM that is listed can be used as general-purpose SRAM when USB is not in use.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
ADC inputs consist of a mix of single ended and differential. See the pinning for available input pairs and types.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI microcontrollers
TI's low-power and high-performance MCUs, with wired and wireless connectivity options, are optimized for a
broad range of applications.
Products for MSP430 ultra-low-power microcontrollers
One platform. One ecosystem. Endless possibilities. Enabling the connected world with innovations in ultra-lowpower microcontrollers with advanced peripherals for precise sensing and measurement.
Companion products for MSP430FG6626
Review products that are frequently purchased or used with this product.
Reference designs for MSP430FG6626
Find reference designs that leverage the best in TI technology to solve your system-level challenges.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
7 Terminal Configuration and Functions
7.1 Pin Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MSP430FG6626
MSP430FG6625
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P9.7/S0
P9.6/S1
P9.5/S2
P9.4/S3
P9.3/S4
P9.2/S5
P9.1/S6
P9.0/S7
P8.7/S8
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
DVSS2
P8.4/UCB1CLK/UCA1STE/S11
P8.3/UCA1RXD/UCA1SOMI/S12
P8.2/UCA1TXD/UCA1SIMO/S13
P8.1/UCB1STE/UCA1CLK/S14
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.2/TB0.2/S21
P4.1/TB0.1/S22
DVCC1
DVSS1
VCORE
LCDCAP/R33
COM0
P5.3/COM1/S42
P5.4/COM2/S41
P5.5/COM3/S40
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P6.4/CB4/AD0+/OA0O
P6.5/CB5/AD0-/OA0IN0
P6.6/CB6/AD1+/G0SW0
P6.7/CB7/AD1-/G0SW1
P7.4/CB8/AD2+/OA1O
P7.5/CB9/AD2-/OA1IN0
P7.6/CB10/AD3+/G1SW0
P7.7/CB11/AD3-/G1SW1
P5.0/VREFBG/VeREF+
P5.1/A4/DAC0
P5.6/A5/DAC1
NR
AVSS1
XOUT
XIN
AVCC
CPCAP
P2.0/P2MAP0/DAC0
P2.1/P2MAP1/DAC1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4/R03
P2.5/P2MAP5
P2.6/P2MAP6/LCDREF/R13
P2.7/P2MAP7/R23
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P6.3/CB3/A3/OA1IP0
P6.2/CB2/A2/OA0IP0
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
DVSS3
DVCC3
P5.7/DMAE0/RTCCLK
VBAT
VBAK
P7.3/XT2OUT
P7.2/XT2IN
AVSS2
V18
VUSB
VBUS
PU.1/DM
PUR
PU.0/DP
VSSU
Figure 7-1 shows the pinout for the MSP430FG6626 and MSP430FG6625 devices in the 100-pin PZ package.
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
Figure 7-1. 100-Pin PZ Package (Top View), MSP430FG6626IPZ, MSP430FG6625IPZ
8
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MSP430FG6426
MSP430FG6425
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P9.7/S0
P9.6/S1
P9.5/S2
P9.4/S3
P9.3/S4
P9.2/S5
P9.1/S6
P9.0/S7
P8.7/S8
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
DVSS2
P8.4/UCB1CLK/UCA1STE/S11
P8.3/UCA1RXD/UCA1SOMI/S12
P8.2/UCA1TXD/UCA1SIMO/S13
P8.1/UCB1STE/UCA1CLK/S14
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.2/TB0.2/S21
P4.1/TB0.1/S22
DVCC1
DVSS1
VCORE
LCDCAP/R33
COM0
P5.3/COM1/S42
P5.4/COM2/S41
P5.5/COM3/S40
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P4.0/TB0.0/S23
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P6.4/CB4/AD0+/OA0O
P6.5/CB5/AD0-/OA0IN0
P6.6/CB6/AD1+/G0SW0
P6.7/CB7/AD1-/G0SW1
P7.4/CB8/AD2+/OA1O
P7.5/CB9/AD2-/OA1IN0
P7.6/CB10/AD3+/G1SW0
P7.7/CB11/AD3-/G1SW1
P5.0/VREFBG/VeREF+
P5.1/A4/DAC0
P5.6/A5/DAC1
NR
AVSS1
XOUT
XIN
AVCC
CPCAP
P2.0/P2MAP0/DAC0
P2.1/P2MAP1/DAC1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4/R03
P2.5/P2MAP5
P2.6/P2MAP6/LCDREF/R13
P2.7/P2MAP7/R23
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P6.3/CB3/A3/OA1IP0
P6.2/CB2/A2/OA0IP0
P6.1/CB1/A1
P6.0/CB0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
DVSS3
DVCC3
P5.7/DMAE0/RTCCLK
VBAT
VBAK
P7.3/XT2OUT
P7.2/XT2IN
AVSS2
NC
LDOO
LDOI
PU.1
NC
PU.0
VSSU
Figure 7-2 shows the pinout for the MSP430FG6426 and MSP430FG6425 devices in the 100-pin PZ package.
A. CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
Figure 7-2. 100-Pin PZ Package (Top View), MSP430FG6426IPZ, MSP430FG6425IPZ
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Figure 7-3 shows the pinout for the 113-pin ZCA or ZQW package.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C11
C12
D1
D2
D4
D5
D6
D7
D8
D9
D11
D12
E1
E2
E4
E5
E6
E7
E8
E9
E11
E12
F1
F2
F4
F5
F8
F9
F11
F12
G1
G2
G4
G5
G8
G9
G11
G12
H1
H2
H4
H5
H6
H7
H8
H9
H11
H12
J1
J2
J4
J5
J6
J7
J8
J9
J11
J12
K1
K2
K11
K12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
NOTE: For terminal assignments, see Section 7.3.
Figure 7-3. 113-Pin ZCA or ZQW Package (Top View), MSP430FG6626IZCA, MSP430FG6625IZCA,
MSP430FG6426IZCA, MSP430FG6425IZCA, MSP430FG6626IZQW, MSP430FG6625IZQW,
MSP430FG6426IZQW, MSP430FG6425IZQW
10
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
7.2 Pin Attributes
Table 7-1 describes the attributes of the pins.
Table 7-1. Pin Attributes
PIN NO.
PZ
1
2
3
SIGNAL NAME (1) (2)
ZCA, ZQW
A1
B2
B1
C3
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
AD0+
I
Analog
DVCC
N/A
OA0O
O
Analog
DVCC
N/A
P6.5
I/O
LVCMOS
DVCC
OFF
CB5
I
Analog
DVCC
N/A
AD0-
I
Analog
DVCC
N/A
OA0IN0
I
Analog
DVCC
N/A
P6.6
I/O
LVCMOS
DVCC
OFF
CB6
I
Analog
DVCC
N/A
AD1+
I
Analog
DVCC
N/A
I
Analog
DVCC
N/A
P6.7
I/O
LVCMOS
DVCC
OFF
CB7
I
Analog
DVCC
N/A
AD1-
I
Analog
DVCC
N/A
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
G0SW1
6
C2
C1
CB8
I
Analog
DVCC
N/A
AD2+
I
Analog
DVCC
N/A
OA1O
O
Analog
DVCC
N/A
P7.5
I/O
LVCMOS
DVCC
OFF
CB9
I
Analog
DVCC
N/A
AD2-
I
Analog
DVCC
N/A
OA1IN0
7
D4
I
Analog
DVCC
N/A
P7.6
I/O
LVCMOS
DVCC
OFF
CB10
I
Analog
DVCC
N/A
AD3+
I
Analog
DVCC
N/A
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
G1SW0
P7.7
8
D2
CB11
I
Analog
DVCC
N/A
AD3-
I
Analog
DVCC
N/A
G1SW1
9
D1
I
Analog
DVCC
N/A
P5.0
I/O
LVCMOS
DVCC
OFF
VREFBG
O
Analog
DVCC
N/A
VeREF+
I
Analog
N/A
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
P5.1
10
11
E4
E2
RESET STATE
AFTER BOR (6) (7)
CB4
P7.4
5
POWER
SOURCE(5)
P6.4
G0SW0
4
SIGNAL TYPE (3) BUFFER TYPE (4)
A4
DAC0
O
Analog
DVCC
N/A
P5.6
I/O
LVCMOS
DVCC
OFF
A5
I
Analog
DVCC
N/A
DAC1
O
Analog
DVCC
N/A
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 7-1. Pin Attributes (continued)
PIN NO.
POWER
SOURCE(5)
RESET STATE
AFTER BOR (6) (7)
Analog
N/A
N/A
Power
N/A
N/A
O
Analog
N/A
N/A
I
Analog
N/A
N/A
N/A
SIGNAL TYPE (3) BUFFER TYPE (4)
ZCA, ZQW
12
E1
NR
I
13
F2
AVSS1
P
14
F1
XOUT
15
G1
XIN
16
H1, G2
17
G4
18
19
20
21
22
23
24
H2
J1
H4
J2
K1
K2
L2
AVCC
P
Power
N/A
CPCAP
I/O
Analog
DVCC
N/A
P2.0
I/O
LVCMOS
DVCC
OFF
P2MAP0
I/O
LVCMOS
DVCC
N/A
DAC0
O
Analog
DVCC
N/A
P2.1
I/O
LVCMOS
DVCC
OFF
P2MAP1
I/O
LVCMOS
DVCC
N/A
DAC1
O
Analog
DVCC
N/A
P2.2
I/O
LVCMOS
DVCC
OFF
P2MAP2
I/O
LVCMOS
DVCC
N/A
P2.3
I/O
LVCMOS
DVCC
OFF
P2MAP3
I/O
LVCMOS
DVCC
N/A
P2.4
I/O
LVCMOS
DVCC
OFF
P2MAP4
I/O
LVCMOS
DVCC
N/A
R03
I/O
Analog
DVCC
N/A
P2.5
I/O
LVCMOS
DVCC
OFF
P2MAP5
I/O
LVCMOS
DVCC
N/A
P2.6
I/O
LVCMOS
DVCC
OFF
P2MAP6
I/O
LVCMOS
DVCC
N/A
I
Analog
N/A
N/A
R13
LCDREF
I/O
Analog
DVCC
N/A
P2.7
I/O
LVCMOS
DVCC
OFF
25
L3
P2MAP7
I/O
LVCMOS
DVCC
N/A
R23
I/O
Analog
DVCC
N/A
26
L1
DVCC1
P
Power
N/A
N/A
27
M1
DVSS1
P
Power
N/A
N/A
28
M2
VCORE
P
Power
DVCC
N/A
29
M3
LCDCAP
I/O
Analog
DVCC
N/A
R33
I/O
Analog
DVCC
N/A
30
J4
31
32
33
34
12
SIGNAL NAME (1) (2)
PZ
L4
M4
J5
L5
COM0
O
Analog
DVCC
N/A
P5.3
I/O
LVCMOS
DVCC
OFF
COM1
O
Analog
DVCC
N/A
S42
O
Analog
DVCC
N/A
P5.4
I/O
LVCMOS
DVCC
OFF
COM2
O
LVCMOS
DVCC
N/A
S41
O
Analog
DVCC
N/A
P5.5
I/O
LVCMOS
DVCC
OFF
COM3
I/O
LVCMOS
DVCC
N/A
S40
O
Analog
DVCC
N/A
P1.0
I/O
LVCMOS
DVCC
OFF
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 7-1. Pin Attributes (continued)
PIN NO.
PZ
35
36
37
38
39
40
41
42
43
44
45
46
47
ZCA, ZQW
M5
J6
H6
M6
L6
J7
M7
L7
H7
M8
L8
J8
M9
SIGNAL NAME (1) (2)
SIGNAL TYPE (3) BUFFER TYPE (4)
POWER
SOURCE(5)
RESET STATE
AFTER BOR (6) (7)
TA0CLK
I
LVCMOS
DVCC
N/A
ACLK
O
LVCMOS
DVCC
N/A
S39
O
Analog
DVCC
N/A
P1.1
I/O
LVCMOS
DVCC
OFF
TA0.0
I/O
LVCMOS
DVCC
N/A
BSLTX
O
LVCMOS
DVCC
N/A
S38
O
Analog
DVCC
N/A
P1.2
I/O
LVCMOS
DVCC
OFF
TA0.1
I/O
LVCMOS
DVCC
N/A
BSLRX
I
LVCMOS
DVCC
N/A
S37
O
Analog
DVCC
N/A
P1.3
I/O
LVCMOS
DVCC
OFF
TA0.2
I/O
LVCMOS
DVCC
N/A
S36
O
Analog
DVCC
N/A
P1.4
I/O
LVCMOS
DVCC
OFF
TA0.3
I/O
LVCMOS
DVCC
N/A
S35
O
Analog
DVCC
N/A
P1.5
I/O
LVCMOS
DVCC
OFF
TA0.4
I/O
LVCMOS
DVCC
N/A
S34
O
Analog
DVCC
N/A
P1.6
I/O
LVCMOS
DVCC
OFF
TA0.1
I/O
LVCMOS
DVCC
N/A
S33
O
Analog
DVCC
N/A
P1.7
I/O
LVCMOS
DVCC
OFF
TA0.2
I/O
LVCMOS
DVCC
N/A
S32
O
Analog
DVCC
N/A
P3.0
I/O
LVCMOS
DVCC
OFF
TA1CLK
I
LVCMOS
DVCC
N/A
CBOUT
O
LVCMOS
DVCC
N/A
S31
O
Analog
DVCC
N/A
P3.1
I/O
LVCMOS
DVCC
OFF
TA1.0
I/O
LVCMOS
DVCC
N/A
S30
O
Analog
DVCC
N/A
P3.2
I/O
LVCMOS
DVCC
OFF
TA1.1
I/O
LVCMOS
DVCC
N/A
S29
O
Analog
DVCC
N/A
P3.3
I/O
LVCMOS
DVCC
OFF
TA1.2
I/O
LVCMOS
DVCC
N/A
S28
O
Analog
DVCC
N/A
P3.4
I/O
LVCMOS
DVCC
OFF
TA2CLK
I
LVCMOS
DVCC
N/A
SMCLK
O
LVCMOS
DVCC
N/A
S27
O
Analog
DVCC
N/A
P3.5
I/O
LVCMOS
DVCC
OFF
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 7-1. Pin Attributes (continued)
PIN NO.
PZ
48
49
50
51
52
53
54
55
56
57
58
59
60
14
ZCA, ZQW
L9
M10
J9
M11
L10
M12
L12
L11
K11
K12
J11
J12
H11
SIGNAL NAME (1) (2)
SIGNAL TYPE (3) BUFFER TYPE (4)
POWER
SOURCE(5)
RESET STATE
AFTER BOR (6) (7)
TA2.0
I/O
LVCMOS
DVCC
N/A
S26
O
Analog
DVCC
N/A
P3.6
I/O
LVCMOS
DVCC
OFF
TA2.1
I/O
LVCMOS
DVCC
N/A
S25
O
Analog
DVCC
N/A
P3.7
I/O
LVCMOS
DVCC
OFF
TA2.2
I/O
LVCMOS
DVCC
N/A
S24
O
Analog
DVCC
N/A
P4.0
I/O
LVCMOS
DVCC
OFF
TB0.0
I/O
LVCMOS
DVCC
N/A
S23
O
Analog
DVCC
N/A
P4.1
I/O
LVCMOS
DVCC
OFF
TB0.1
I/O
LVCMOS
DVCC
N/A
S22
O
Analog
DVCC
N/A
P4.2
I/O
LVCMOS
DVCC
OFF
TB0.2
I/O
LVCMOS
DVCC
N/A
S21
O
Analog
DVCC
N/A
P4.3
I/O
LVCMOS
DVCC
OFF
TB0.3
I/O
LVCMOS
DVCC
N/A
S20
O
Analog
DVCC
N/A
P4.4
I/O
LVCMOS
DVCC
OFF
TB0.4
I/O
LVCMOS
DVCC
N/A
S19
O
Analog
DVCC
N/A
P4.5
I/O
LVCMOS
DVCC
OFF
TB0.5
I/O
LVCMOS
DVCC
N/A
S18
O
Analog
DVCC
N/A
P4.6
I/O
LVCMOS
DVCC
OFF
TB0.6
I/O
LVCMOS
DVCC
N/A
S17
O
Analog
DVCC
N/A
P4.7
I/O
LVCMOS
DVCC
OFF
TB0OUTH
I
LVCMOS
DVCC
N/A
SVMOUT
O
LVCMOS
DVCC
N/A
S16
O
Analog
DVCC
N/A
P8.0
I/O
LVCMOS
DVCC
OFF
I
LVCMOS
DVCC
N/A
TB0CLK
S15
O
Analog
DVCC
N/A
P8.1
I/O
LVCMOS
DVCC
OFF
UCB1STE
I/O
LVCMOS
DVCC
N/A
UCA1CLK
I/O
LVCMOS
DVCC
N/A
S14
O
Analog
DVCC
N/A
P8.2
I/O
LVCMOS
DVCC
OFF
UCA1TXD
O
LVCMOS
DVCC
N/A
UCA1SIMO
I/O
LVCMOS
DVCC
N/A
S13
O
Analog
DVCC
N/A
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 7-1. Pin Attributes (continued)
PIN NO.
PZ
SIGNAL NAME (1) (2)
ZCA, ZQW
P8.3
61
H12
SIGNAL TYPE (3) BUFFER TYPE (4)
POWER
SOURCE(5)
RESET STATE
AFTER BOR (6) (7)
I/O
LVCMOS
DVCC
OFF
UCA1RXD
I
LVCMOS
DVCC
N/A
UCA1SOMI
I/O
LVCMOS
DVCC
N/A
S12
O
Analog
DVCC
N/A
P8.4
I/O
LVCMOS
DVCC
OFF
UCB1CLK
I/O
LVCMOS
DVCC
N/A
UCA1STE
I/O
LVCMOS
DVCC
N/A
62
G11
S11
O
Analog
DVCC
N/A
63
G12
DVSS2
P
Power
N/A
N/A
64
F12
DVCC2
65
66
67
68
69
70
71
72
73
74
F11
G9
E12
E11
F9
D12
D11
E9
C12
C11
75
D9
76
B11, B12
77
A12
78
B10
79
A11
P
Power
N/A
N/A
P8.5
I/O
LVCMOS
DVCC
OFF
UCB1SIMO
I/O
LVCMOS
DVCC
N/A
UCB1SDA
I/O
LVCMOS
DVCC
N/A
S10
O
Analog
DVCC
N/A
P8.6
I/O
LVCMOS
DVCC
OFF
UCB1SOMI
I/O
LVCMOS
DVCC
N/A
UCB1SCL
I/O
LVCMOS
DVCC
N/A
S9
O
Analog
DVCC
N/A
P8.7
I/O
LVCMOS
DVCC
OFF
S8
O
Analog
DVCC
N/A
P9.0
I/O
LVCMOS
DVCC
OFF
S7
O
Analog
DVCC
N/A
P9.1
I/O
LVCMOS
DVCC
OFF
S6
O
Analog
DVCC
N/A
P9.2
I/O
LVCMOS
DVCC
OFF
S5
O
Analog
DVCC
N/A
P9.3
I/O
LVCMOS
DVCC
OFF
S4
O
Analog
DVCC
N/A
P9.4
I/O
LVCMOS
DVCC
OFF
S3
O
Analog
DVCC
N/A
P9.5
I/O
LVCMOS
DVCC
OFF
S2
O
Analog
DVCC
N/A
P9.6
I/O
LVCMOS
DVCC
OFF
S1
O
Analog
DVCC
N/A
P9.7
I/O
LVCMOS
DVCC
OFF
S0
O
Analog
DVCC
N/A
VSSU
P
Power
N/A
N/A
PU.0
I/O
HVCMOS
VBUS
HiZ
DP
I/O
HVCMOS
VBUS
N/A
PUR (FG662x only)
I/O
HVCMOS/opendrain
VBUS
HiZ
NC (FG642x only)
I/O
N/A
N/A
N/A
PU.1
I/O
HVCMOS
VBUS
HiZ
DM
I/O
HVCMOS
VBUS
N/A
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 7-1. Pin Attributes (continued)
PIN NO.
PZ
ZCA, ZQW
80
A10
81
A9
82
B9
83
A8
84
B8
85
B7
SIGNAL NAME (1) (2)
POWER
SOURCE(5)
RESET STATE
AFTER BOR (6) (7)
VBUS
I
Power
N/A
N/A
LDOI
I
Analog
External
N/A
VUSB
O
Power
N/A
N/A
LDOO
O
Analog
VBUS
N/A
V18 (FG662x only)
O
Power
N/A
N/A
NC (FG642x only)
–
N/A
N/A
N/A
AVSS2
P
Power
N/A
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
P7.3
I/O
LVCMOS
DVCC
OFF
XT2OUT
O
Analog
DVCC
N/A
P7.2
XT2IN
86
A7
VBAK
I/O
Analog
N/A
N/A
87
D8
VBAT
P
Power
N/A
N/A
P5.7
I/O
LVCMOS
DVCC
OFF
88
D7
DMAE0
I
LVCMOS
DVCC
N/A
RTCCLK
O
LVCMOS
DVCC
N/A
89
A6
DVCC3
P
Power
N/A
N/A
90
A5
DVSS3
P
Power
N/A
N/A
91
B6
TEST
I
LVCMOS
DVCC
No Emu: PD
Emu: PD
SBWTCK
I
LVCMOS
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
PJ.0
92
93
B5
A4
94
E7
95
D6
96
97
A3
B4
TDO
O
LVCMOS
DVCC
No Emu: OFF
Emu: DRIVE0
PJ.1
I/O
LVCMOS
DVCC
OFF
TDI
I
LVCMOS
DVCC
No Emu: OFF
Emu: PU
TCLK
I
LVCMOS
DVCC
No Emu: OFF
Emu: OFF
PJ.2
I/O
LVCMOS
DVCC
OFF
TMS
I
LVCMOS
DVCC
No Emu: OFF
Emu: PU
PJ.3
I/O
LVCMOS
DVCC
OFF
TCK
I
LVCMOS
DVCC
No Emu: OFF
Emu: PU
RST
I/O
LVCMOS
DVCC
PU
NMI
I
LVCMOS
DVCC
N/A
SBWTDIO
I/O
LVCMOS
DVCC
PU
P6.0
I/O
LVCMOS
DVCC
OFF
CB0
I
Analog
DVCC
N/A
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
N/A
A0
P6.1
98
99
16
SIGNAL TYPE (3) BUFFER TYPE (4)
B3
A2
CB1
I
Analog
DVCC
A1
I
Analog
DVCC
N/A
P6.2
I/O
LVCMOS
DVCC
OFF
CB2
I
Analog
DVCC
N/A
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 7-1. Pin Attributes (continued)
PIN NO.
PZ
100
N/A
(1)
(2)
(3)
(4)
(5)
(6)
(7)
SIGNAL NAME (1) (2)
ZCA, ZQW
D5
SIGNAL TYPE (3) BUFFER TYPE (4)
POWER
SOURCE(5)
RESET STATE
AFTER BOR (6) (7)
A2
I
Analog
DVCC
N/A
OA0IP0
I
Analog
DVCC
N/A
P6.3
I/O
LVCMOS
DVCC
OFF
CB3
I
Analog
DVCC
N/A
A3
I
Analog
DVCC
N/A
OA1IP0
I
Analog
DVCC
N/A
-
–
–
–
E5, E6, E8,
F4, F5, F8,
Reserved
G5, G8, H5,
H8, H9
For each multiplexed pin, the signal that is listed first in this table is the reset default.
To determine the pin mux encodings for each pin, refer to Section 9.13.
Signal Types: I = Input, O = Output, I/O = Input or Output, P = power
Buffer Types: LVCMOS, HVCMOS, Analog, or Power (see Table 7-3 for details).
The power source shown in this table is the I/O power source, which may differ from the module power source.
Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
HiZ = High-impedance (neither input nor output)
PD = High-impedance input with pulldown enabled
PU = High-impedance input with pullup enabled
DRIVE0 = Drive output low
DRIVE1 = Drive output high
N/A = Not applicable
For Debug pins: Emu = with emulator attached at reset, No Emu = without emulator attached at reset
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
7.3 Signal Descriptions
Table 7-2 describes the signals for all device variants and package options.
Table 7-2. Signal Descriptions
SIGNAL
NAME
FUNCTION
ADC
BSL
PIN NO.
PIN
TYPE(1)
ZCA,
ZQW
A0
97
B4
I
ADC analog single ended input A0
A1
98
B3
I
ADC analog single ended input A1
A2
99
A2
I
ADC analog single ended input A2
A3
100
D5
I
ADC analog single ended input A3
A4
10
E4
I
ADC analog single ended input A4
A5
11
E2
I
ADC analog single ended input A5
AD0+
1
A1
I
ADC positive analog differential input AD0+
AD0-
2
B2
I
ADC negative analog differential input AD0-
AD1+
3
B1
I
ADC positive analog differential input AD1+
AD1-
4
C3
I
ADC negative analog differential input AD1-
AD2+
5
C2
I
ADC positive analog differential input AD2+
AD2-
6
C1
I
ADC negative analog differential input AD2-
AD3+
7
D4
I
ADC positive analog differential input AD3+
AD3-
8
D2
I
ADC negative analog differential input AD3-
VeREF+
9
D1
I
Input for an external reference voltage to the ADC and DAC
BSLRX
36
J6
I
BSL receive input
BSLTX
35
M5
O
BSL transmit output
VBAK
86
A7
I/O
Capacitor for backup subsystem. Do not load this pin externally. For
capacitor values, see CBAK in Section 8.3.
VBAT
87
D8
P
CPCAP
17
G4
I/O
ACLK
34
L5
O
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
RTCCLK
88
D7
O
RTCCLK output
SMCLK
46
J8
O
SMCLK output
XIN
15
G1
I
Input terminal for crystal oscillator XT1
XOUT
14
F1
O
Output terminal of crystal oscillator XT1
XT2IN
84
B8
I
Input terminal for crystal oscillator XT2
XT2OUT
85
B7
O
Output terminal of crystal oscillator XT2
CB0
97
B4
I
Comparator_B input CB0
CB1
98
B3
I
Comparator_B input CB1
Backup
Charge Pump
Clock
Comparator
18
DESCRIPTION
PZ
Backup or secondary supply voltage. If backup voltage is not supplied,
connect to DVCC externally.
Capacitor for op amp and CTSD16 rail-to-rail charge pump
CB2
99
A2
I
Comparator_B input CB2
CB3
100
D5
I
Comparator_B input CB3
CB4
1
A1
I
Comparator_B input CB4
CB5
2
B2
I
Comparator_B input CB5
CB6
3
B1
I
Comparator_B input CB6
CB7
4
C3
I
Comparator_B input CB7
CB8
5
C2
I
Comparator_B input CB8
CB9
6
C1
I
Comparator_B input CB9
CB10
7
D4
I
Comparator_B input CB10
CB11
8
D2
I
Comparator_B input CB11
CBOUT
42
L7
O
Comparator_B output
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 7-2. Signal Descriptions (continued)
FUNCTION
SIGNAL
NAME
Debug
PIN
TYPE(1)
ZCA,
ZQW
DAC0
10
18
E4
H2
O
DAC output channel 0
DAC1
11
19
E2
J1
O
DAC output channel 1
DMAE0
88
D7
I
DMA external trigger input
SBWTCK
91
B6
I
Spy-Bi-Wire input clock
TCK
95
D6
I
Test clock
TCLK
93
A4
I
Test clock input
TDI
93
A4
I
Test data input
TDO
92
B5
O
Test data output
TEST
91
B6
I
Test mode pin; selects digital I/O on JTAG pins
TMS
94
E7
I
Test mode select
SBWTDIO
96
A3
I/O
Spy-Bi-Wire data input/output
P1.0
34
L5
I/O
General-purpose digital I/O with port interrupt
P1.1
35
M5
I/O
General-purpose digital I/O with port interrupt
P1.2
36
J6
I/O
General-purpose digital I/O with port interrupt
P1.3
37
H6
I/O
General-purpose digital I/O with port interrupt
P1.4
38
M6
I/O
General-purpose digital I/O with port interrupt
P1.5
39
L6
I/O
General-purpose digital I/O with port interrupt
P1.6
40
J7
I/O
General-purpose digital I/O with port interrupt
P1.7
41
M7
I/O
General-purpose digital I/O with port interrupt
P2.0
18
H2
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.1
19
J1
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.2
20
H4
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.3
21
J2
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.4
22
K1
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.5
23
K2
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.6
24
L2
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.7
25
L3
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
P3.0
42
L7
I/O
General-purpose digital I/O with port interrupt
P3.1
43
H7
I/O
General-purpose digital I/O with port interrupt
P3.2
44
M8
I/O
General-purpose digital I/O with port interrupt
P3.3
45
L8
I/O
General-purpose digital I/O with port interrupt
P3.4
46
J8
I/O
General-purpose digital I/O with port interrupt
P3.5
47
M9
I/O
General-purpose digital I/O with port interrupt
P3.6
48
L9
I/O
General-purpose digital I/O with port interrupt
P3.7
49
M10
I/O
General-purpose digital I/O with port interrupt
P4.0
50
J9
I/O
General-purpose digital I/O with port interrupt
GPIO
GPIO
DESCRIPTION
PZ
DAC
DMA
PIN NO.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 7-2. Signal Descriptions (continued)
FUNCTION
GPIO
20
SIGNAL
NAME
PIN NO.
PIN
TYPE(1)
DESCRIPTION
PZ
ZCA,
ZQW
P4.1
51
M11
I/O
General-purpose digital I/O with port interrupt
P4.2
52
L10
I/O
General-purpose digital I/O with port interrupt
P4.3
53
M12
I/O
General-purpose digital I/O with port interrupt
P4.4
54
L12
I/O
General-purpose digital I/O with port interrupt
P4.5
55
L11
I/O
General-purpose digital I/O with port interrupt
P4.6
56
K11
I/O
General-purpose digital I/O with port interrupt
P4.7
57
K12
I/O
General-purpose digital I/O with port interrupt
P5.0
9
D1
I/O
General-purpose digital I/O
P5.1
10
E4
I/O
General-purpose digital I/O
P5.3
31
L4
I/O
General-purpose digital I/O
P5.4
32
M4
I/O
General-purpose digital I/O
P5.5
33
J5
I/O
General-purpose digital I/O
P5.6
11
E2
I/O
General-purpose digital I/O
P5.7
88
D7
I/O
General-purpose digital I/O
P6.0
97
B4
I/O
General-purpose digital I/O
P6.1
98
B3
I/O
General-purpose digital I/O
P6.2
99
A2
I/O
General-purpose digital I/O
P6.3
100
D5
I/O
General-purpose digital I/O
P6.4
1
A1
I/O
General-purpose digital I/O
P6.5
2
B2
I/O
General-purpose digital I/O
P6.6
3
B1
I/O
General-purpose digital I/O
P6.7
4
C3
I/O
General-purpose digital I/O
P7.2
84
B8
I/O
General-purpose digital I/O
P7.3
85
B7
I/O
General-purpose digital I/O
P7.4
5
C2
I/O
General-purpose digital I/O
P7.5
6
C1
I/O
General-purpose digital I/O
P7.6
7
D4
I/O
General-purpose digital I/O
P7.7
8
D2
I/O
General-purpose digital I/O
P8.0
58
J11
I/O
General-purpose digital I/O
P8.1
59
J12
I/O
General-purpose digital I/O
P8.2
60
H11
I/O
General-purpose digital I/O
P8.3
61
H12
I/O
General-purpose digital I/O
P8.4
62
G11
I/O
General-purpose digital I/O
P8.5
65
F11
I/O
General-purpose digital I/O
P8.6
66
G9
I/O
General-purpose digital I/O
P8.7
67
E12
I/O
General-purpose digital I/O
P9.0
68
E11
I/O
General-purpose digital I/O
P9.1
69
F9
I/O
General-purpose digital I/O
P9.2
70
D12
I/O
General-purpose digital I/O
P9.3
71
D11
I/O
General-purpose digital I/O
P9.4
72
E9
I/O
General-purpose digital I/O
P9.5
73
C12
I/O
General-purpose digital I/O
P9.6
74
C11
I/O
General-purpose digital I/O
P9.7
75
D9
I/O
General-purpose digital I/O
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 7-2. Signal Descriptions (continued)
SIGNAL
NAME
FUNCTION
PIN NO.
PIN
TYPE(1)
ZCA,
ZQW
PJ.0
92
B5
I/O
General-purpose digital I/O
PJ.1
93
A4
I/O
General-purpose digital I/O
PJ.2
94
E7
I/O
General-purpose digital I/O
PJ.3
95
D6
I/O
General-purpose digital I/O
PU.0
77
A12
I/O
General-purpose digital I/O - controlled by USB control register (FG662x
devices) or PU control register
PU.1
79
A11
I/O
General-purpose digital I/O - controlled by USB control register (FG662x
devices) or PU control register
G0SW0
3
B1
I
Analog switch to AVSS. Internally connected to ADC positive analog
differential input AD1+.
G0SW1
4
C3
I
Analog switch to AVSS. Internally connected to ADC negative analog
differential input AD1-.
G1SW0
7
D4
I
Analog switch to AVSS. Internally connected to ADC positive analog
differential input AD3+.
G1SW1
8
D2
I
Analog switch to AVSS. Internally connected to ADC negative analog
differential input AD3-.
UCB1SCL
66
G9
I/O
USCI_B1 I2C clock
UCB1SDA
65
F11
I/O
USCI_B1 I2C data
COM0
30
J4
O
LCD common output COM0 for LCD backplane
COM1
31
L4
O
LCD common output COM1 for LCD backplane
COM2
32
M4
O
LCD common output COM2 for LCD backplane
COM3
33
J5
I/O
LCD common output COM3 for LCD backplane
LCDCAP
29
M3
I/O
LCD capacitor connection
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
LCDREF
24
L2
I
R03
22
K1
I/O
Input/output port of lowest analog LCD voltage (V5)
R13
24
L2
I/O
Input/output port of third most positive analog LCD voltage (V3 or V4)
R23
25
L3
I/O
Input/output port of second most positive analog LCD voltage (V2)
R33
29
M3
I/O
Input/output port of most positive analog LCD voltage (V1)
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
S0
75
D9
O
LCD segment output S0
S1
74
C11
O
LCD segment output S1
S2
73
C12
O
LCD segment output S2
S3
72
E9
O
LCD segment output S3
S4
71
D11
O
LCD segment output S4
S5
70
D12
O
LCD segment output S5
S6
69
F9
O
LCD segment output S6
S7
68
E11
O
LCD segment output S7
S8
67
E12
O
LCD segment output S8
S9
66
G9
O
LCD segment output S9
S10
65
F11
O
LCD segment output S10
S11
62
G11
O
LCD segment output S11
S12
61
H12
O
LCD segment output S12
S13
60
H11
O
LCD segment output S13
S14
59
J12
O
LCD segment output S14
S15
58
J11
O
LCD segment output S15
Ground Switch
I2C
LCD
LCD
DESCRIPTION
PZ
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External reference voltage input for regulated LCD voltage
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 7-2. Signal Descriptions (continued)
FUNCTION
SIGNAL
NAME
PIN NO.
PIN
TYPE(1)
ZCA,
ZQW
S16
57
K12
O
LCD segment output S16
S17
56
K11
O
LCD segment output S17
S18
55
L11
O
LCD segment output S18
S19
54
L12
O
LCD segment output S19
S20
53
M12
O
LCD segment output S20
S21
52
L10
O
LCD segment output S21
S22
51
M11
O
LCD segment output S22
S23
50
J9
O
LCD segment output S23
S24
49
M10
O
LCD segment output S24
S25
48
L9
O
LCD segment output S25
S26
47
M9
O
LCD segment output S26
S27
46
J8
O
LCD segment output S27
S28
45
L8
O
LCD segment output S28
S29
44
M8
O
LCD segment output S29
S30
43
H7
O
LCD segment output S30
S31
42
L7
O
LCD segment output S31
S32
41
M7
O
LCD segment output S32
S33
40
J7
O
LCD segment output S33
S34
39
L6
O
LCD segment output S34
S35
38
M6
O
LCD segment output S35
S36
37
H6
O
LCD segment output S36
S37
36
J6
O
LCD segment output S37
S38
35
M5
O
LCD segment output S38
S39
34
L5
O
LCD segment output S39
S40
33
J5
O
LCD segment output S40
S41
32
M4
O
LCD segment output S41
S42
31
L4
O
LCD segment output S42
P2MAP0
18
H2
I/O
Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock
input/output
Mapping Options: See Table 9-8
P2MAP1
19
J1
I/O
Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data
Mapping Options: See Table 9-8
P2MAP2
20
H4
I/O
Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock
Mapping Options: See Table 9-8
P2MAP3
21
J2
I/O
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave
transmit enable
Mapping Options: See Table 9-8
P2MAP4
22
K1
I/O
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/
master out
Mapping Options: See Table 9-8
P2MAP5
23
K2
I/O
Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/
master in
Mapping Options: See Table 9-8
P2MAP6
24
L2
I/O
Default mapping: no secondary function
Mapping Options: See Table 9-8
P2MAP7
25
L3
I/O
Default mapping: no secondary function
Mapping Options: See Table 9-8
Mappable
22
DESCRIPTION
PZ
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Table 7-2. Signal Descriptions (continued)
FUNCTION
Noise
Reduction
Op Amp
SIGNAL
NAME
REF
System
Timer_A
DESCRIPTION
ZCA,
ZQW
NR
12
E1
I
Noise reduction. Connect pin to analog ground.
OA1IN0
6
C1
I
OA1 negative input internally connected to ADC negative analog
differential input AD2-
OA0IN0
2
B2
I
OA0 negative input internally connected to ADC negative analog
differential input AD0-
OA0IP0
99
A2
I
OA0 positive input internally connected to ADC analog input A2
OA0O
1
A1
O
OA0 output internally connected to ADC positive analog differential input
AD0+
100
D5
I
OA1 positive input internally connected to ADC analog input A3
OA1O
5
C2
O
OA1 output internally connected to ADC positive analog differential input
AD2+
AVSS1
13
F2
P
Analog ground supply
AVSS2
83
A8
P
Analog ground supply
AVCC
16
H1, G2
P
Analog power supply
DVCC1
26
L1
P
Digital power supply
DVCC2
64
F12
P
Digital power supply
DVCC3
89
A6
P
Digital power supply
DVSS1
27
M1
P
Digital ground supply
DVSS2
63
G12
P
Digital ground supply
DVSS3
90
A5
P
Digital ground supply
LDOI
80
A10
I
LDO input (not available on FG662x devices)
LDOO
81
A9
O
LDO output (not available on FG662x devices)
VCORE(2)
28
M2
O
Regulated core power supply (internal use only, no external current
loading)
VREFBG
9
D1
O
Output of reference voltage to the ADC and DAC
NC
78
82
B10
B9
I/O
Not connected (not available on FG662x devices)
Reserved
–
E5, E6,
E8, F4,
F5, F8,
G5, G8,
H5, H8,
H9
–
UCA1CLK
59
J12
I/O
USCI_A1 clock input/output
UCA1SIMO
60
H11
I/O
USCI_A1 SPI slave in/master out
UCA1SOMI
61
H12
I/O
USCI_A1 SPI slave out/master in
UCA1STE
62
G11
I/O
USCI_A1 SPI slave transmit enable
UCB1CLK
62
G11
I/O
USCI_B1 clock input/output
UCB1SIMO
65
F11
I/O
USCI_B1 SPI slave in/master out
UCB1SOMI
66
G9
I/O
USCI_B1 SPI slave out/master in
UCB1STE
59
J12
I/O
USCI_B1 SPI slave transmit enable
NMI
96
A3
I
RST
96
A3
I/O
Reset input (active low)(3)
SVMOUT
57
K12
O
SVM output
TA0.0
35
M5
I/O
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
TA0.1
36
J6
I/O
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
Reserved
SPI
PIN
TYPE(1)
PZ
OA1IP0
Power
PIN NO.
Copyright © 2020 Texas Instruments Incorporated
Reserved. Internally connected to DVSS. TI recommends external
connection to ground (DVSS).
Nonmaskable interrupt input
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Table 7-2. Signal Descriptions (continued)
SIGNAL
NAME
FUNCTION
TA0.2
Timer_B
UART
PIN NO.
PZ
ZCA,
ZQW
PIN
TYPE(1)
DESCRIPTION
40
J7
I/O
Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output
37
H6
I/O
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output
41
M7
I/O
Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output
TA0.3
38
M6
I/O
Timer TA0 CCR3 capture: CCI3A input compare: Out3 output
TA0.4
39
L6
I/O
Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output
TA0CLK
34
L5
I
Timer TA0 clock signal TACLK input
TA1.0
43
H7
I/O
Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
TA1.1
44
M8
I/O
Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
TA1.2
45
L8
I/O
Timer TA1 capture CCR2: CCI2A input, compare: Out2 output
TA1CLK
42
L7
I
TA2.0
47
M9
I/O
Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
TA2.1
48
L9
I/O
Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
TA2.2
49
M10
I/O
TA2CLK
46
J8
I
TB0.0
50
J9
I/O
Timer TB0 capture CCR0: CCI0A input, compare: Out0 output
TB0.1
51
M11
I/O
Timer TB0 capture CCR1: CCI1A input, compare: Out1 output
TB0.2
52
L10
I/O
Timer TB0 capture CCR2: CCI2A input, compare: Out2 output
TB0.3
53
M12
I/O
Timer TB0 capture CCR3: CCI3A input, compare: Out3 output
TB0.4
54
L12
I/O
Timer TB0 capture CCR4: CCI4A input, compare: Out4 output
TB0.5
55
L11
I/O
Timer TB0 capture CCR5: CCI5A input, compare: Out5 output
TB0.6
56
K11
I/O
Timer TB0 capture CCR6: CCI6A input, compare: Out6 output
TB0CLK
58
J11
I
TB0OUTH
57
K12
I
UCA1CLK
59
J12
I/O
UCA1RXD
61
H12
I
USCI_A1 UART receive data
UCA1TXD
60
H11
O
USCI_A1 UART transmit data
DM
79
A11
I/O
USB data terminal DM (not available on FG6426 and FG6425 devices)
DP
77
A12
I/O
USB data terminal DP (not available on FG6426 and FG6425 devices)
Timer TA1 clock input
Timer TA2 capture CCR2: CCI2A input, compare: Out2 output
Timer TA2 clock input
Timer TB0 clock input
Timer TB0: switch all PWM outputs to high impedance
USCI_A1 clock input/output
USB pullup resistor pin (open drain). The voltage level at the PUR pin is
used to invoke the default USB BSL.
PUR
78
B10
I/O
Not available on FG6426 and FG6425 devices.
USB
(FG662x only)
(1)
(2)
(3)
24
Recommended 1-MΩ resistor to ground. See Section 9.6 for more
information.
V18
82
B9
O
USB regulated power (internal use only, no external current loading) (not
available on FG6426 and FG6425 devices)
VBUS
80
A10
I
USB LDO input (connect to USB power source) (not available on FG6426
and FG6425 devices)
VSSU
76
B11
B12
P
USB PHY ground supply
VUSB
81
A9
O
USB LDO output (not available on FG6426 and FG6425 devices)
I = input, O = output, I/O = input or output, P = power
VCORE is for internal use only. No external current loading is possible. VCORE must be connected to the recommended capacitor
value, CVCORE.
When this pin is configured as reset, the internal pullup resistor is enabled by default.
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7.4 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the
device is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see
Section 9.13.
7.5 Buffer Type
Table 7-3 describes the buffer types that are referenced in Table 7-1.
Table 7-3. Buffer Type
BUFFER TYPE
(STANDARD)
Analog(2)
NOMINAL
VOLTAGE
HYSTERESIS
3.0 V
N
PU OR PD
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT DRIVE
STRENGTH
(mA)
OTHER
CHARACTERISTICS
N/A
N/A
N/A
See analog modules in
Section 8, Specifications for
details
HVCMOS
5.0 V
Y
N/A
N/A
See Section
8.8.5.7, Typical
Characteristics –
Outputs
LVCMOS
3.0 V
Y(1)
Programmable
See Section
8.8.5, GeneralPurpose I/Os
See Section
8.8.5.7, Typical
Characteristics –
Outputs
Power (DVCC)(3)
3.0 V
N
N/A
N/A
N/A
Power (AVCC)(3)
3.0 V
N
N/A
N/A
N/A
0V
N
N/A
N/A
N/A
Power (DVSS
and AVSS)(3)
(1)
(2)
(3)
SVS enables hysteresis on
DVCC
Only for input pins
This is a switch, not a buffer.
This is supply input, not a buffer.
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7.6 Connection of Unused Pins
Table 7-4 lists the correct termination of all unused pins.
Table 7-4. Connection of Unused Pins
(1)PIN
AVCC
POTENTIAL
COMMENT
DVCC
AVSS
DVSS
CPCAP
Open
LCDCAP
DVSS
LDOI
DVSS
For devices with LDO-PWR module when not being used in the application.
LDOO
Open
For devices with LDO-PWR module when not being used in the application.
NC
Open
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
Open
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used, these must
be switched to port function, output direction (PJDIR.n = 1). When used as JTAG pins, these pins
must remain open.
PU.0/DP
PU.1/DM
Open
For USB devices only when USB module is not being used in the application
PUR(3)
DVSS
For USB devices only when USB module is not being used in the application
Px.y
Open
Switched to port function, output direction (PxDIR.n = 1). Px.y represents port x and bit y of port x
(for example, P1.0, P1.1, P2.2, PJ.0, PJ.1)
RST/NMI
DVCC or VCC
47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF) pulldown(2)
For devices where the charge pump is not used (no rail-to-rail OA and no rail-to-rail CTSD16).
Reserved
DVSS
TEST
Open
This pin always has an internal pulldown enabled.
V18
Open
For USB devices only when USB module is not being used in the application
VBAK
Open
For devices where no separate battery backup supply is used in the system. Set bit BAKDIS = 1.
VBAT
DVCC
For devices where no separate battery backup supply is used in the system. Set bit BAKDIS = 1.
VBUS, VSSU
DVSS
For USB devices only when USB module is not being used in the application
VUSB
Open
For USB devices only when USB module is not being used in the application
XIN
DVSS
For dedicated XIN pins only. XIN pins with shared GPIO functions must be programmed to GPIO
and follow Px.y recommendations.
XOUT
Open
For dedicated XOUT pins only. XOUT pins with shared GPIO functions must be programmed to
GPIO and follow Px.y recommendations.
XT2IN
DVSS
For dedicated XT2IN pins only. XT2IN pins with shared GPIO functions must be programmed to
GPIO and follow Px.y recommendations.
XT2OUT
Open
For dedicated XT2OUT pins only. XT2OUT pins with shared GPIO functions must be programmed
to GPIO and follow Px.y recommendations.
(1)
(2)
(3)
26
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.y unused pin connection
guidelines.
The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire
JTAG mode with TI tools such as FET interfaces or GANG programmers.
The default USB BSL evaluates the state of the PUR pin after a BOR reset. If it is pulled high externally, then the BSL is invoked.
Therefore, unless invoking the BSL, it is important to keep PUR pulled low after a BOR reset, even if BSL or USB is never used. TI
recommends a 1-MΩ resistor to ground.
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8 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Voltage applied at VCC to VSS
–0.3
4.1
V
Voltage applied to any pin (excluding VCORE, VBUS, V18, LDOI) (2)
–0.3
VCC + 0.3
V
±2
mA
–55
150
°C
95
°C
Diode current at any device pin
Storage temperature, Tstg (3)
Maximum junction temperature, TJ
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±250 V may actually have higher performance.
8.3 Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
VCC
VCC,USB (2)
Supply voltage during program execution and flash
programming (AVCC = DVCC1 = DVCC2 = DVCC3 =
DVCC = VCC) (1) (2) (3)
Supply voltage during USB operation, USB PLL disabled
(USB_EN = 1, UPLLEN = 0)
Supply voltage during USB operation, USB PLL enabled
(USB_EN = 1, UPLLEN = 1)
(4)
NOM
MAX
PMMCOREV = 0
1.8
PMMCOREV = 0, 1
2.0
3.6
PMMCOREV = 0, 1, 2
2.2
3.6
PMMCOREV = 0, 1, 2, 3
2.4
3.6
PMMCOREV = 0
1.8
3.6
PMMCOREV = 0, 1
2.0
3.6
PMMCOREV = 0, 1, 2
2.2
3.6
PMMCOREV = 0, 1, 2, 3
2.4
3.6
PMMCOREV = 2
2.2
3.6
PMMCOREV = 2, 3
2.4
VSS
Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 = DVSS2 = DVSS3 = VSS)
VBAT,RTC
Backup-supply voltage with RTC operational
UNIT
3.6
V
V
3.6
0
V
TA = 0°C to 85°C
1.55
3.6
TA = –40°C to 85°C
1.70
3.6
V
VBAT,MEM
Backup-supply voltage with backup memory retained
TA = –40°C to 85°C
1.20
3.6
V
TA
Operating free-air temperature
I version
–40
85
°C
TJ
Operating junction temperature
I version
–40
CBAK
Capacitance at pin VBAK
Copyright © 2020 Texas Instruments Incorporated
1
4.7
85
°C
10
nF
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8.3 Recommended Operating Conditions (continued)
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
CVCORE
Capacitor at VCORE(5)
CDVCC/
CVCORE
Capacitor ratio of DVCC to VCORE
fSYSTEM
Processor frequency (maximum MCLK frequency) (6) (7)
(see Figure 8-1)
USB_wait
Wait state cycles during USB operation
(4)
(5)
(6)
(7)
UNIT
nF
10
Minimum processor frequency for USB operation
(2)
(3)
MAX
470
fSYSTEM_USB
(1)
NOM
PMMCOREV = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
0
8.0
PMMCOREV = 1,
2 V ≤ VCC ≤ 3.6 V
0
12.0
PMMCOREV = 2,
2.2 V ≤ VCC ≤ 3.6 V
0
16.0
PMMCOREV = 3,
2.4 V ≤ VCC ≤ 3.6 V
0
20.0
1.5
MHz
MHz
16
cycles
TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
Some modules may have reduced recommended ranges of operation.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Section
8.8.6.2 for the exact values and further details.
USB operation with USB PLL enabled requires PMMCOREV ≥ 2 for proper operation.
A capacitor tolerance of ±20% is required.
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
25
System Frequency - MHz
20
3
16
2
2, 3
1
1, 2
1, 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
12
8
0
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
NOTE: The numbers within the fields denote the supported PMMCOREVx settings.
Figure 8-1. Frequency vs Supply Voltage
28
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8.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1) (2) (3)
PARAMETER
IAM, Flash
IAM, RAM
(1)
(2)
(3)
EXECUTION
MEMORY
Flash
RAM
FREQUENCY (fDCO = fMCLK = fSMCLK)
VCC
3V
3V
PMMCOREV
1 MHz
8 MHz
12 MHz
TYP
MAX
TYP
MAX
0
0.31
0.36
2.0
2.4
1
0.35
2
3
20 MHz
TYP
MAX
2.3
3.4
4.0
0.37
2.5
3.8
0.4
2.7
4.0
0
0.2
1
0.22
0.23
1.1
1.3
1.9
2
0.24
1.5
2.2
3
0.26
1.6
2.4
TYP
UNIT
MAX
mA
6.6
1.2
2.1
mA
3.9
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external
load capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing. FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0).
FG6426 and FG6425 LDO disabled (LDOEN = 0).
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
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8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREV
–40°C
TYP
ILPM0,1MHz
Low-power mode 0(3) (9)
ILPM2
Low-power mode 2(4) (9)
ILPM3,XT1LF
ILPM3,
Low-power mode 4(7) (9)
ILPM4
ILPM3.5,
RTC,VCC
ILPM3.5,
RTC,VBAT
ILPM3.5,
RTC,TOT
ILPM4.5
(1)
(2)
(3)
(4)
(5)
(6)
30
60°C
MAX
TYP
85°C
MAX
TYP
UNIT
MAX
0
72
77
87
81
87
98
3V
3
86
92
105
97
104
117
2.2 V
0
6.9
7.5
9.9
8.5
12
17
3V
3
7.9
8.5
11
9.7
14
20
0
2.8
3.2
3.7
4.2
7.6
13.5
2.2 V
1
3.1
3.6
4.6
8.2
2
3.5
4.0
5.1
8.8
0
3.0
3.4
4.4
7.9
1
3.3
3.8
4.9
8.5
2
3.7
4.2
5.3
9.0
3
3.7
4.2
4.8
5.3
9.1
16
2.1
12.5
3V
VLO,WDT
25°C
TYP
2.2 V
Low-power mode 3,
crystal mode(5) (9)
Low-power mode 3,
VLO mode, Watchdog
enabled(6) (9)
MAX
3V
3V
4.0
14
0
1.2
1.5
2.4
5.8
1
1.4
1.6
2.6
6.1
2
1.6
1.8
2.8
6.5
3
1.6
1.8
2.6
2.9
6.5
14
1.8
11.5
µA
µA
µA
0
0.6
0.9
1.9
5.4
1
0.7
1.0
2.0
5.6
2
0.8
1.1
2.2
5.9
3
0.8
1.1
2.2
6.0
13
2.1
µA
µA
Low-power mode 3.5
(LPM3.5) current with
active RTC into primary
supply pin DVCC (10)
3V
0.2
0.7
1.7
µA
Low-power mode 3.5
(LPM3.5) current with
active RTC into backup
supply pin VBAT(11)
3V
0.7
0.9
1.2
µA
Total low-power mode 3.5
(LPM3.5) current with
active RTC(12)
3V
0.8
0.9
1.0
1.6
2.9
µA
Low-power mode 4.5
(LPM4.5)(8)
3V
0.12
0.2
0.32
0.8
1.9
µA
0.6
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO
setting = 1 MHz operation, DCO bias generator enabled.
FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
Current for watchdog timer clocked by VLO included.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fMCLK = fSMCLK = fDCO = 0 MHz
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FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
(8) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) Current for brownout included. Low-side supervisor and monitors disabled (SVSL, SVML). High-side supervisor and monitor disabled
(SVSH, SVMH). RAM retention enabled.
(10) VVBAT = VCC – 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active
(11) VVBAT = VCC – 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no
current drawn on VBAK
(12) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK
(7)
8.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREV
–40°C
TYP
Low-power mode 3
ILPM3, LCD, (LPM3) current, LCD 4ext. bias
mux mode, external
biasing(1) (2)
Low-power mode 3
(LPM3) current, LCD 4ILPM3, LCD,
mux mode, internal
int. bias
biasing, charge pump
disabled(1) (3)
ILPM3
LCD,CP
(1)
(2)
(3)
(4)
Low-power mode 3
(LPM3) current, LCD 4mux mode, internal
biasing, charge pump
enabled(1) (4)
3V
3V
2.2 V
3V
MAX
25°C
60°C
85°C
TYP
MAX
TYP
0
3.7
4.3
4.9
5.5
1
4.1
4.7
5.9
9.6
2
4.5
5.1
6.3
10.2
3
4.5
5.2
5.8
6.5
10.4
18.0
0
4.2
4.8
5.4
6.0
9.6
17.0
1
4.7
5.4
6.6
10.4
2
5.1
5.8
7.1
11.0
3
5.0
5.7
7.0
11.0
0
6.4
1
6.77
2
7.13
0
6.53
1
7.0
2
7.43
3
7.6
6.4
MAX
UNIT
TYP
MAX
9.0
15.0
µA
µA
19.0
µA
µA
Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout included. Low-side supervisor (SVSL) and low-side monitor (SVML) disabled. High-side supervisor (SVSH) and
high-side monitor (SVMH) disabled. RAM retention enabled.
LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
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8.7 Thermal Resistance Characteristics
PARAMETER
θJA
Junction-to-ambient thermal resistance, still air (1)
θJC(TOP)
Junction-to-case (top) thermal resistance (2)
θJB
Junction-to-board thermal resistance (3)
(1)
(2)
(3)
VALUE
QFP (PZ)
122
BGA (ZQW)
108
QFP (PZ)
83
BGA (ZQW)
72
QFP (PZ)
98
BGA (ZQW)
76
UNIT
°C/W
°C/W
°C/W
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board,
as specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
8.8 Timing and Switching Characteristics
8.8.1 Power Supply Sequencing
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power
down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits
specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device
including erroneous writes to RAM and flash.
Section 8.8.1.1 lists the device reset requirements.
8.8.1.1 Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(DVCC_BOR_IT–)
BORH on voltage, DVCC falling level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_IT+)
BORH off voltage, DVCC rising level
| dDVCC/dt | < 3 V/s
V(DVCC_BOR_hys)
BORH hysteresis
MIN
TYP
0.80
1.30
60
MAX
UNIT
1.47
V
1.55
V
250
mV
8.8.2 Reset Timing
Section 8.8.2.1 lists the reset input timing.
8.8.2.1 Reset Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
tRESET
32
PARAMETER
TYP
Pulse duration required at RST/NMI pin to accept a reset
2
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UNIT
µs
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8.8.3 Clock Specifications
Section 8.8.3.1 lists the characteristics of XT1 in low-frequency mode.
8.8.3.1 Crystal Oscillator, XT1, Low-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1
ΔIDVCC,LF
Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2
fXT1,LF,SW
XT1 oscillator logic-level squarewave input frequency, LF mode
XTS = 0, XT1BYPASS = 1(2) (3)
OALF
0.170
32768
XTS = 0, XT1BYPASS = 0
Oscillation allowance for
LF crystals(4)
3V
0.290
XT1 oscillator crystal frequency,
LF mode
10
32.768
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
210
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
Integrated effective load
capacitance, LF mode(5)
fFault,LF
tSTART,LF
(1)
(2)
(3)
(4)
(5)
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
12.0
Duty cycle, LF mode
Oscillator fault frequency,
LF mode(7)
XTS = 0(8)
Start-up time, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
CL,eff = 12 pF
Hz
50
kHz
1
XTS = 0, XCAPx = 1
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
µA
kΩ
XTS = 0, XCAPx = 0(6)
CL,eff
UNIT
0.075
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3
fXT1,LF0
MAX
pF
30%
70%
10
10000
Hz
1000
3V
ms
500
To improve EMI on the XT1 oscillator, observe the following guidelines.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For XT1DRIVEx = 0, CL,eff ≤ 6 pF
• For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF
• For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF
• For XT1DRIVEx = 3, CL,ef f ≥ 6 pF
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, verify
the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the
specification of the used crystal.
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(6)
(7)
(8)
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Section 8.8.3.2 lists the characteristics of XT2.
8.8.3.2 Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 4 MHz, XT2OFF = 0, TA = 25°C,
XT2BYPASS = 0, XT2DRIVEx = 0
IDVCC,XT2
XT2 oscillator crystal current
consumption
fOSC = 12 MHz, XT2OFF = 0, TA = 25°C,
XT2BYPASS = 0, XT2DRIVEx = 1
fOSC = 20 MHz, XT2OFF = 0, TA = 25°C,
XT2BYPASS = 0, XT2DRIVEx = 2
TYP
MAX
UNIT
200
260
3V
µA
325
fOSC = 32 MHz, XT2OFF = 0, TA = 25°C,
XT2BYPASS = 0, XT2DRIVEx = 3
450
fXT2,HF0
XT2 oscillator crystal frequency,
mode 0
XT2DRIVEx = 0, XT2BYPASS = 0(3)
4
8
MHz
fXT2,HF1
XT2 oscillator crystal frequency,
mode 1
XT2DRIVEx = 1, XT2BYPASS = 0(3)
8
16
MHz
fXT2,HF2
XT2 oscillator crystal frequency,
mode 2
XT2DRIVEx = 2, XT2BYPASS = 0(3)
16
24
MHz
fXT2,HF3
XT2 oscillator crystal frequency,
mode 3
XT2DRIVEx = 3, XT2BYPASS = 0(3)
24
32
MHz
fXT2,HF,SW
XT2 oscillator logic-level squarewave input frequency
XT2BYPASS = 1(3) (4)
0.7
32
MHz
Oscillation allowance for
HF crystals(5)
OAHF
tSTART,HF
Start-up time
fFault,HF
34
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
320
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
200
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
200
fOSC = 6 MHz,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
0.5
fOSC = 20 MHz,
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C, CL,eff = 15 pF
Duty cycle
(3)
(4)
(5)
450
Ω
3V
ms
0.3
Integrated effective load
capacitance, HF mode(6) (1)
CL,eff
(1)
(2)
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
1
Measured at ACLK, fXT2,HF2 = 20 MHz
Oscillator fault
frequency(7)
XT2BYPASS =
1(8)
40%
30
50%
pF
60%
300
kHz
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
To improve EMI on the XT2 oscillator, observe the following guidelines.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
• Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
Maximum frequency of operation of the entire device cannot be exceeded.
When XT2BYPASS is set, the XT2 circuit is automatically powered down.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
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(7)
(8)
SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, verify
the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the
specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Section 8.8.3.3 lists the characteristics of the VLO.
8.8.3.3 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
(1)
(2)
TEST CONDITIONS
Measured at ACLK
VCC
1.8 V to 3.6 V
MIN
TYP
MAX
6
9.4
14
UNIT
kHz
ACLK(1)
1.8 V to 3.6 V
0.5
%/°C
Measured at ACLK(2)
1.8 V to 3.6 V
4
%/V
Measured at ACLK
1.8 V to 3.6 V
Measured at
40%
50%
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Section 8.8.3.4 lists the characteristics of the REFO.
8.8.3.4 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
fREFO
TEST CONDITIONS
VCC
MAX
UNIT
1.8 V to 3.6 V
3
µA
REFO frequency calibrated
Measured at ACLK
1.8 V to 3.6 V
32768
Hz
REFO absolute tolerance
calibrated
Full temperature range
1.8 V to 3.6 V
±3.5%
TA = 25°C
3V
±1.5%
ACLK(1)
1.8 V to 3.6 V
0.01
%/°C
1.0
%/V
REFO frequency temperature drift Measured at
dfREFO/dVCC
REFO frequency supply voltage
drift
Measured at ACLK(2)
1.8 V to 3.6 V
Duty cycle
Measured at ACLK
1.8 V to 3.6 V
REFO start-up time
40%/60% duty cycle
1.8 V to 3.6 V
(1)
(2)
TYP
TA = 25°C
dfREFO/dT
tSTART
MIN
REFO oscillator current
consumption
40%
50%
25
60%
µs
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
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Section 8.8.3.5 lists the characteristics of the DCO frequency.
8.8.3.5 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fDCO(0,0)
TEST CONDITIONS
DCO frequency (0, 0)(1)
31)(1)
fDCO(0,31)
DCO frequency (0,
fDCO(1,0)
DCO frequency (1, 0)(1)
31)(1)
fDCO(1,31)
DCO frequency (1,
fDCO(2,0)
DCO frequency (2, 0)(1)
31)(1)
MAX
UNIT
DCORSELx = 0, DCOx = 0, MODx = 0
0.07
MIN
TYP
0.20
MHz
DCORSELx = 0, DCOx = 31, MODx = 0
0.70
1.70
MHz
DCORSELx = 1, DCOx = 0, MODx = 0
0.15
0.36
MHz
DCORSELx = 1, DCOx = 31, MODx = 0
1.47
3.45
MHz
DCORSELx = 2, DCOx = 0, MODx = 0
0.32
0.75
MHz
fDCO(2,31)
DCO frequency (2,
DCORSELx = 2, DCOx = 31, MODx = 0
3.17
7.38
MHz
fDCO(3,0)
DCO frequency (3, 0)(1)
DCORSELx = 3, DCOx = 0, MODx = 0
0.64
1.51
MHz
fDCO(3,31)
DCO frequency (3, 31)(1)
DCORSELx = 3, DCOx = 31, MODx = 0
6.07
14.0
MHz
0)(1)
fDCO(4,0)
DCO frequency (4,
fDCO(4,31)
DCO frequency (4, 31)(1)
0)(1)
fDCO(5,0)
DCO frequency (5,
fDCO(5,31)
DCO frequency (5, 31)(1)
0)(1)
fDCO(6,0)
DCO frequency (6,
fDCO(6,31)
DCO frequency (6, 31)(1)
0)(1)
DCORSELx = 4, DCOx = 0, MODx = 0
1.3
3.2
MHz
DCORSELx = 4, DCOx = 31, MODx = 0
12.3
28.2
MHz
DCORSELx = 5, DCOx = 0, MODx = 0
2.5
6.0
MHz
DCORSELx = 5, DCOx = 31, MODx = 0
23.7
54.1
MHz
DCORSELx = 6, DCOx = 0, MODx = 0
4.6
10.7
MHz
DCORSELx = 6, DCOx = 31, MODx = 0
39.0
88.0
MHz
fDCO(7,0)
DCO frequency (7,
DCORSELx = 7, DCOx = 0, MODx = 0
8.5
19.6
MHz
fDCO(7,31)
DCO frequency (7, 31)(1)
DCORSELx = 7, DCOx = 31, MODx = 0
60
135
MHz
SDCORSEL
Frequency step between range
DCORSEL and DCORSEL + 1
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3
ratio
SDCO
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.02
1.12
ratio
Duty cycle
Measured at SMCLK
40%
dfDCO/dT
DCO frequency temperature drift
fDCO = 1 MHz,
0.1
%/°C
dfDCO/dVCC
DCO frequency voltage drift
fDCO = 1 MHz
1.9
%/V
(1)
50%
60%
When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
100
VCC = 3.0 V
TA = 25°C
fDCO – MHz
10
DCOx = 31
1
0.1
DCOx = 0
0
1
2
3
4
5
6
7
DCORSEL
Figure 8-2. Typical DCO Frequency
36
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8.8.4 Wake-up Characteristics
Section 8.8.4.1 lists the characteristics of the wake-up times.
8.8.4.1 Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
fMCLK ≥ 4 MHz
MIN
3
6.5
UNIT
1 MHz < fMCLK <
4 MHz
4
8.0
150
165
µs
tWAKE-UP-FAST
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode(1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
tWAKE-UP-SLOW
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode(2) (3)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
tWAKE-UP-LPM5
Wake-up time from LPM3.5
or LPM4.5 to active mode(4)
2
3
ms
tWAKE-UP-RESET
Wake-up time from RST or
BOR event to active mode(4)
2
3
ms
(1)
(2)
(3)
(4)
µs
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the
performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in
full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx
Family User's Guide.
This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the
performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in
normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx
Family User's Guide.
The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by
the performance mode settings as for LPM2, LPM3, and LPM4.
This value represents the time from the wake-up event to the reset vector execution.
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8.8.5 General-Purpose I/Os
Section 8.8.5.1 lists the characteristics of the Schmitt-trigger inputs.
8.8.5.1 Schmitt-Trigger Inputs – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
(1)
VCC
MIN
1.8 V
0.80
1.40
3V
1.50
2.10
1.8 V
0.45
1.00
3V
0.75
1.65
1.8 V
0.3
0.8
3V
0.4
1.0
20
TYP
35
MAX
50
5
UNIT
V
V
V
kΩ
pF
The same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
Section 8.8.5.2 lists the characteristics of P1, P2, P3, and P4 .
8.8.5.2 Inputs – Ports P1, P2, P3, and P4
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
External interrupt timing(2)
t(int)
(1)
(2)
TEST CONDITIONS
Port P1, P2, P3, P4: P1.x to P4.x,
External trigger pulse duration to set interrupt flag
VCC
2.2 V, 3 V
MIN
MAX
20
UNIT
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Section 8.8.5.3 lists the leakage current of the GPIOs.
8.8.5.3 Leakage Current – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.x)
(1)
(2)
38
High-impedance leakage current
TEST CONDITIONS
See (1) (2)
VCC
1.8 V, 3 V
MIN
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
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Section 8.8.5.4 lists the output characteristics of the GPIOs.
8.8.5.4 Outputs – General-Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
VOH
High-level output voltage
I(OHmax) = –10 mA(2)
I(OHmax) = –5 mA(1)
I(OHmax) = –15 mA(2)
I(OLmax) = 3 mA(1)
VOL
Low-level output voltage
I(OLmax) = 10 mA(2)
I(OLmax) = 5 mA(1)
I(OLmax) = 15 mA(2)
(1)
(2)
VCC
1.8 V
3V
1.8 V
3V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
UNIT
V
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
Section 8.8.5.5 lists the output characteristics of the GPIOs.
8.8.5.5 Outputs – General-Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(3)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(1)
VOH
High-level output voltage
I(OHmax) = –3 mA(2)
I(OHmax) = –2 mA(1)
I(OHmax) = –6 mA(2)
I(OLmax) = 1 mA(1)
VOL
Low-level output voltage
I(OLmax) = 3 mA(2)
I(OLmax) = 2 mA(1)
I(OLmax) = 6 mA(2)
(1)
(2)
(3)
VCC
1.8 V
3V
1.8 V
3V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
UNIT
V
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Selecting reduced drive strength may reduce EMI.
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Section 8.8.5.6 lists the frequency characteristics of the GPIOs.
8.8.5.6 Output Frequency – Ports P1, P2 and P3
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fPx.y
fPort_CLK
(1)
(2)
(3)
40
TEST CONDITIONS
Port output frequency
(with load)
P3.4/TA2CLK/SMCLK/S27
CL = 20 pF, RL = 1 kΩ(1) or 3.2 kΩ(2) (3)
Clock output frequency
P1.0/TA0CLK/ACLK/S39
P3.4/TA2CLK/SMCLK/S27
P2.0/P2MAP0 (P2MAP0 = PM_MCLK )
CL = 20 pF(3)
MIN
MAX
VCC = 1.8 V
PMMCOREVx = 0
8
VCC = 3 V
PMMCOREVx = 3
20
VCC = 1.8 V
PMMCOREVx = 0
8
VCC = 3 V
PMMCOREVx = 3
20
UNIT
MHz
MHz
Full drive strength of port: A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the
center tap of the divider.
Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩ between VCC and VSS is used as load. The output is connected to
the center tap of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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8.8.5.7 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
8.0
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
25.0
TA = 25°C
20.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
TA = 25°C
7.0
6.0
TA = 85°C
5.0
4.0
3.0
2.0
1.0
0.0
0.0
3.5
0.5
VCC = 3.0 V
VCC = 1.8 V
P3.2
Figure 8-3. Typical Low-Level Output Current vs
Low-Level Output Voltage
IOH – Typical High-Level Output Current – mA
IOH – Typical High-Level Output Current – mA
−10.0
−25.0
0.0
2.0
P3.2
0.0
−5.0
−20.0
1.5
Figure 8-4. Typical Low-Level Output Current vs
Low-Level Output Voltage
0.0
−15.0
1.0
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
−1.0
−2.0
−3.0
−4.0
−5.0
TA = 85°C
−6.0
TA = 25°C
−7.0
−8.0
0.0
VOH – High-Level Output Voltage – V
VCC = 3.0 V
P3.2
Figure 8-5. Typical High-Level Output Current Vs
High-Level Output Voltage
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VCC = 1.8 V
0.5
1.0
1.5
VOH – High-Level Output Voltage – V
2.0
P3.2
Figure 8-6. Typical High-Level Output Current Vs
High-Level Output Voltage
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8.8.5.8 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
24
TA = 25°C
55.0
IOL – Typical Low-Level Output Current – mA
IOL – Typical Low-Level Output Current – mA
60.0
50.0
TA = 85°C
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
TA = 25°C
20
16
TA = 85°C
12
8
4
5.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.0
3.5
0.5
VCC = 3.0 V
VCC = 1.8 V
P3.2
Figure 8-7. Typical Low-Level Output Current vs
Low-Level Output Voltage
IOH – Typical High-Level Output Current – mA
IOH – Typical High-Level Output Current – mA
−15.0
P3.2
−20.0
−25.0
−30.0
−35.0
−40.0
−45.0
TA = 85°C
−55.0
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
−4
−8
−12
TA = 85°C
−16
TA = 25°C
−20
0.0
VOH – High-Level Output Voltage – V
VCC = 3.0 V
P3.2
Figure 8-9. Typical High-Level Output Current vs
High-level Output Voltage
42
2.0
0
−10.0
−60.0
0.0
1.5
Figure 8-8. Typical Low-Level Output Current vs
Low-Level Output Voltage
0.0
−5.0
−50.0
1.0
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
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0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
VCC = 1.8 V
P3.2
Figure 8-10. Typical High-Level Output Current vs
High-level Output Voltage
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8.8.6 PMM
Section 8.8.6.1 lists the characteristics of the PMM core voltage.
8.8.6.1 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE3(AM)
Core voltage, active mode,
PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA
1.90
V
VCORE2(AM)
Core voltage, active mode,
PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA
1.80
V
VCORE1(AM)
Core voltage, active mode,
PMMCOREV = 1
2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 17 mA
1.60
V
VCORE0(AM)
Core voltage, active mode,
PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 13 mA
1.40
V
VCORE3(LPM)
Core voltage, low-current mode,
PMMCOREV = 3
2.4 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
1.94
V
VCORE2(LPM)
Core voltage, low-current mode,
PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
1.84
V
VCORE1(LPM)
Core voltage, low-current mode,
PMMCOREV = 1
2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
1.64
V
VCORE0(LPM)
Core voltage, low-current mode,
PMMCOREV = 0
1.8 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
1.44
V
Section 8.8.6.2 lists the characteristics of the SVS high side.
8.8.6.2 PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSHE = 0, DVCC = 3.6 V
I(SVSH)
SVS current consumption
V(SVSH_IT+)
SVSH on voltage level(1)
SVSH off voltage level(1)
tpd(SVSH)
SVSH propagation delay
t(SVSH)
SVSH on or off delay time
dVDVCC/dt
DVCC rise time
(1)
MAX
0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
2.0
µA
SVSHE = 1, SVSHRVL = 0
1.59
1.64
1.69
SVSHE = 1, SVSHRVL = 1
1.79
1.84
1.91
SVSHE = 1, SVSHRVL = 2
1.98
2.04
2.11
SVSHE = 1, SVSHRVL = 3
2.10
2.16
2.23
SVSHE = 1, SVSMHRRL = 0
1.62
1.74
1.81
SVSHE = 1, SVSMHRRL = 1
1.88
1.94
2.01
SVSHE = 1, SVSMHRRL = 2
2.07
2.14
2.21
SVSHE = 1, SVSMHRRL = 3
2.20
2.26
2.33
SVSHE = 1, SVSMHRRL = 4
2.32
2.40
2.48
SVSHE = 1, SVSMHRRL = 5
2.56
2.70
2.84
SVSHE = 1, SVSMHRRL = 6
2.85
3.00
3.15
SVSHE = 1, SVSMHRRL = 7
2.85
3.00
3.15
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
2.5
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
20
SVSHE = 0→1, SVSHFP = 1
12.5
SVSHE = 0→1, SVSHFP = 0
100
0
UNIT
nA
200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
V(SVSH_IT–)
TYP
V
V
µs
µs
1000
V/s
The SVSH settings available depend on the VCORE (PMMCOREV) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use.
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Section 8.8.6.3 lists the characteristics of the SVM high side.
8.8.6.3 PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVMHE = 0, DVCC = 3.6 V
I(SVMH)
V(SVMH)
SVMH current consumption
SVMH on or off voltage level(1)
SVMH propagation delay
t(SVMH)
SVMH on or off delay time
(1)
MAX
0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
200
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
2.0
UNIT
nA
µA
SVMHE = 1, SVSMHRRL = 0
1.65
1.74
1.86
SVMHE = 1, SVSMHRRL = 1
1.85
1.94
2.02
SVMHE = 1, SVSMHRRL = 2
2.02
2.14
2.22
SVMHE = 1, SVSMHRRL = 3
2.18
2.26
2.35
SVMHE = 1, SVSMHRRL = 4
2.32
2.40
2.48
SVMHE = 1, SVSMHRRL = 5
2.56
2.70
2.84
SVMHE = 1, SVSMHRRL = 6
2.85
3.00
3.15
SVMHE = 1, SVSMHRRL = 7
2.85
3.00
3.15
SVMHE = 1, SVMHOVPE = 1
tpd(SVMH)
TYP
V
3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
2.5
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
20
SVMHE = 0→1, SVSMFP = 1
12.5
SVMHE = 0→1, SVMHFP = 0
100
µs
µs
The SVMH settings available depend on the VCORE (PMMCOREV) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use.
Section 8.8.6.4 lists the characteristics of the SVS low side.
8.8.6.4 PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SVSLE = 0, PMMCOREV = 2
I(SVSL)
SVSL current consumption
tpd(SVSL)
SVSL propagation delay
t(SVSL)
SVSL on or off delay time
44
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TYP
0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
2.0
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
2.5
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
20
SVSLE = 0→1, SVSLFP = 1
12.5
SVSLE = 0→1, SVSLFP = 0
100
MAX
UNIT
nA
µA
µs
µs
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Section 8.8.6.5 lists the characteristics of the SVM low side.
8.8.6.5 PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
SVMLE = 0, PMMCOREV = 2
I(SVML)
SVML current consumption
tpd(SVML)
SVML propagation delay
t(SVML)
SVML on or off delay time
MAX
0
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
200
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
2.0
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
2.5
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
20
SVMLE = 0→1, SVMLFP = 1
12.5
SVMLE = 0→1, SVMLFP = 0
100
UNIT
nA
µA
µs
µs
8.8.7 Timers
Section 8.8.7.1 lists the characteristics of Timer_A.
8.8.7.1 Timer_A, Timers TA0, TA1, and TA2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fTA
Timer_A input clock frequency
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
1.8 V, 3 V
tTA,cap
Timer_A capture timing
All capture inputs, minimum pulse
duration required for capture
1.8 V, 3 V
MAX
UNIT
20
MHz
20
ns
Section 8.8.7.2 lists the characteristics of Timer_B.
8.8.7.2 Timer_B, Timer TB0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fTB
Timer_B input clock frequency
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
1.8 V, 3 V
tTB,cap
Timer_B capture timing
All capture inputs, minimum pulse
duration required for capture
1.8 V, 3 V
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20
MAX
UNIT
20
MHz
ns
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8.8.8 Battery Backup
Section 8.8.8.1 lists the characteristics of the battery backup.
8.8.8.1 Battery Backup
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VBAT = 1.7 V,
DVCC not connected,
RTC running
Current into VBAT terminal in VBAT = 2.2 V,
DVCC not connected,
case no primary battery is
RTC running
connected.
IVBAT
VBAT = 3 V,
DVCC not connected,
RTC running
VCC
MIN
TYP
TA = –40°C
0.43
TA = 25°C
0.52
TA = 60°C
0.58
TA = 85°C
0.66
TA = –40°C
0.50
TA = 25°C
0.59
TA = 60°C
0.64
TA = 85°C
0.72
TA = –40°C
0.68
TA = 25°C
0.75
TA = 60°C
0.79
TA = 85°C
Switch-over level (VCC to
VBAT)
RON_VBAT
ON-resistance of switch
between VBAT and VBAK
VBAT3
VBAT to ADC:
VBAT divided,
VBAT3 = VBAT /3
VCHVx
RCHARGE
46
Charger end voltage
Charge limiting resistor
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CVCC = 4.7 µF
µA
VSVSH_IT-
SVSHRL = 0
1.59
1.69
SVSHRL = 1
1.79
1.91
SVSHRL = 2
1.98
2.11
SVSHRL = 3
2.10
2.23
VBAT = 1.8 V
CHVx = 2
UNIT
0.86
General
VSWITCH
MAX
0V
0.35
1
1.8 V
0.6
±5%
3V
1.0
±5%
3.6 V
1.2
±5%
2.7
2.9
2.65
CHCx = 1
5.2
CHCx = 2
10.2
CHCx = 3
20
V
kΩ
V
V
kΩ
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8.8.9 USCI
Section 8.8.9.1 lists the characteristics of the USCI in UART mode.
8.8.9.1 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency (equals baud rate in MBaud)
UART receive deglitch time(1)
tτ
(1)
VCC
MIN
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
MAX
UNIT
fSYSTEM
MHz
1
MHz
2.2 V
50
600
3V
50
600
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Section 8.8.9.2 lists the characteristics of the USCI in SPI master mode.
8.8.9.2 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-11 and Figure 8-12)
PARAMETER
fUSCI
TEST CONDITIONS
USCI input clock frequency
PMMCOREV = 0
tSU,MI
SOMI input data setup time
PMMCOREV = 3
PMMCOREV = 0
tHD,MI
SOMI input data hold time
PMMCOREV = 3
tVALID,MO
SIMO output data valid time(2)
SIMO output data hold
(2)
(3)
1.8 V
55
3V
38
2.4 V
30
3V
25
1.8 V
0
3V
0
2.4 V
0
3V
0
MAX
UNIT
fSYSTEM
MHz
ns
ns
1.8 V
20
3V
18
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
2.4 V
16
time(3)
CL = 20 pF, PMMCOREV = 3
(1)
MIN
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 0
tHD,MO
VCC
SMCLK, ACLK, duty cycle = 50% ±10%
3V
ns
15
1.8 V
–10
3V
–8
2.4 V
–10
3V
–8
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8-11 and Figure 8-12.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure
8-11 and Figure 8-12.
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 8-11. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 8-12. SPI Master Mode, CKPH = 1
48
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Section 8.8.9.3 lists the characteristics of the USCI in SPI slave mode.
8.8.9.3 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-13 and Figure 8-14)
PARAMETER
TEST CONDITIONS
PMMCOREV = 0
tSTE,LEAD
STE lead time, STE low to clock
PMMCOREV = 3
PMMCOREV = 0
tSTE,LAG
STE lag time, Last clock to STE high
PMMCOREV = 3
PMMCOREV = 0
tSTE,ACC
STE access time, STE low to SOMI data out
PMMCOREV = 3
PMMCOREV = 0
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
PMMCOREV = 3
PMMCOREV = 0
tSU,SI
SIMO input data setup time
PMMCOREV = 3
PMMCOREV = 0
tHD,SI
SIMO input data hold time
PMMCOREV = 3
tVALID,SO
SOMI output data valid time(2)
(2)
(3)
11
3V
8
2.4 V
7
3V
6
1.8 V
3
3V
3
2.4 V
3
3V
3
MAX
ns
1.8 V
66
3V
50
2.4 V
36
3V
30
1.8 V
30
3V
30
2.4 V
30
3V
30
1.8 V
5
3V
5
2.4 V
2
3V
2
1.8 V
5
3V
5
2.4 V
5
3V
5
60
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 3
2.4 V
44
3V
40
SOMI output data hold time(3)
12
12
2.4 V
12
3V
12
ns
ns
76
3V
ns
ns
3V
1.8 V
UNIT
ns
1.8 V
CL = 20 pF, PMMCOREV = 3
(1)
MIN
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 0
tHD,SO
VCC
1.8 V
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8-13 and Figure 8-14.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure
8-13 and Figure 8-14.
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,SI
tLO/HI
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 8-13. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tHD,MO
tVALID,SO
tSTE,DIS
SOMI
Figure 8-14. SPI Slave Mode, CKPH = 1
50
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Section 8.8.9.4 lists the characteristics of the USCI in I2C mode.
8.8.9.4 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 8-15)
PARAMETER
TEST CONDITIONS
fUSCI
USCI input clock frequency
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
VCC
MIN
2.2 V, 3 V
fSCL ≤ 100 kHz
0
fSCL ≤ 100 kHz
fSYSTEM
MHz
400
kHz
µs
0.6
4.7
2.2 V, 3 V
fSCL > 100 kHz
UNIT
4.0
2.2 V, 3 V
fSCL > 100 kHz
MAX
µs
0.6
tHD,DAT
Data hold time
2.2 V, 3 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3 V
250
ns
tSU,STO
Setup time for STOP
tSP
Pulse duration of spikes suppressed by input filter
fSCL ≤ 100 kHz
tSU,STA
tHD,STA
4.0
2.2 V, 3 V
fSCL > 100 kHz
µs
0.6
2.2 V
50
600
3V
50
600
tHD,STA
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 8-15. I2C Mode Timing
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8.8.10 LCD Controller
Section 8.8.10.1 lists the operating conditions of the LCD controller.
8.8.10.1 LCD_B Operating Conditions
PARAMETER
VCC,LCD_B,
CONDITIONS
MIN
NOM
MAX
UNIT
Supply voltage range, charge
pump enabled, VLCD ≤ 3.6 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1111
(charge pump enabled, VLCD ≤ 3.6 V)
2.2
3.6
V
Supply voltage range, charge
pump enabled, VLCD ≤ 3.3 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1100
(charge pump enabled, VLCD ≤ 3.3 V)
2.0
3.6
V
VCC,LCD_B, int. bias
Supply voltage range, internal
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_B, ext. bias
Supply voltage range, external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
Supply voltage range, external
LCD voltage, internal or external
biasing, charge pump disabled
LCDCPEN = 0, VLCDEXT = 1
2.0
3.6
V
VLCDCAP/R33
External LCD voltage at LCDCAP/
R33, internal or external biasing,
charge pump disabled
LCDCPEN = 0, VLCDEXT = 1
2.4
3.6
V
CLCDCAP
Capacitor on LCDCAP when
charge pump enabled
LCDCPEN = 1, VLCDx > 0000
(charge pump enabled)
10
µF
fFrame
LCD frame frequency range
fLCD = 2 × mux × fFRAME
(mux = 1 (static), 2, 3, 4)
100
Hz
fACLK,in
ACLK input frequency range
40
kHz
CPanel
Panel capacitance
100-Hz frame frequency
10000
pF
VCC +
0.2
V
CP en,3.6
VCC,LCD_B,
CP en,3.3
VCC,LCD_B,
VLCDEXT
4.7
0
30
32
VR33
Analog input voltage at R33
LCDCPEN = 0, VLCDEXT = 1
VR23,1/3bias
Analog input voltage at R23
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR13
VR03 + 2/3 ×
(VR33 – VR03)
VR33
V
VR13,1/3bias
Analog input voltage at R13 with
1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR03
VR03 + 1/3 ×
(VR33 – VR03)
VR23
V
VR13,1/2bias
Analog input voltage at R13 with
1/2 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1
VR03
VR03 + 1/2 ×
(VR33 – VR03)
VR33
V
VR03
Analog input voltage at R03
R0EXT = 1
VLCD-VR03
Voltage difference between VLCD
and R03
LCDCPEN = 0, R0EXT = 1
2.4
VLCDREF/R13
External LCD reference voltage
applied at LCDREF/R13
VLCDREFx = 01
0.8
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2.4
VSS
V
1.2
VCC
+ 0.2
V
1.5
V
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Section 8.8.10.2 lists the characteristics of the LCD controller.
8.8.10.2 LCD_B, Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VLCD
LCD voltage
TEST CONDITIONS
VCC
MIN
TYP
VLCDx = 0000, VLCDEXT = 0
2.4 V to 3.6 V
VCC
LCDCPEN = 1, VLCDx = 0001
2 V to 3.6 V
2.60
LCDCPEN = 1, VLCDx = 0010
2 V to 3.6 V
2.66
LCDCPEN = 1, VLCDx = 0011
2 V to 3.6 V
2.72
LCDCPEN = 1, VLCDx = 0100
2 V to 3.6 V
2.79
LCDCPEN = 1, VLCDx = 0101
2 V to 3.6 V
2.85
LCDCPEN = 1, VLCDx = 0110
2 V to 3.6 V
2.92
LCDCPEN = 1, VLCDx = 0111
2 V to 3.6 V
2.98
LCDCPEN = 1, VLCDx = 1000
2 V to 3.6 V
3.05
LCDCPEN = 1, VLCDx = 1001
2 V to 3.6 V
3.10
LCDCPEN = 1, VLCDx = 1010
2 V to 3.6 V
3.17
LCDCPEN = 1, VLCDx = 1011
2 V to 3.6 V
3.24
LCDCPEN = 1, VLCDx = 1100
2 V to 3.6 V
3.30
LCDCPEN = 1, VLCDx = 1101
2.2 V to 3.6 V
3.36
LCDCPEN = 1, VLCDx = 1110
2.2 V to 3.6 V
3.42
LCDCPEN = 1, VLCDx = 1111
2.2 V to 3.6 V
3.48
MAX
UNIT
V
3.6
ICC,Peak,CP
Peak supply currents due to
charge pump activities
LCDCPEN = 1, VLCDx = 1111
2.2 V
400
tLCD,CP,on
Time to charge CLCD when
discharged
CLCD = 4.7 µF,
LCDCPEN = 0→1,
VLCDx = 1111
2.2 V
100
ICP,Load
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111
2.2 V
RLCD,Seg
LCD driver output impedance,
segment lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
2.2 V
10
kΩ
RLCD,COM
LCD driver output impedance,
common lines
LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA
2.2 V
10
kΩ
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µA
500
50
ms
µA
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8.8.11 CTSD16
Note
The delta-sigma analog-to-digital converter uses the CTSD16. The CTSD16 is proceeded by a unitygain buffer stage following the channel muxing as shown in Figure 9-2. See Section 8.8.14.1 for the
electrical characteristics of the PGA buffer stages.
Section 8.8.11.1 lists the operating conditions of the CTSD16.
8.8.11.1 CTSD16, Power Supply and Operating Conditions
PARAMETER
TEST CONDITIONS
VCC
VCC
Supply voltage range
ICTSD16
Analog plus digital supply
current per converter
(reference current not
included)
CTSD16OSRx = 256,
CTSD16RRI = 0
CTSD16 clock current
consumption
This is requested when CTSD16 is converting, or
CTSD16RRIBURST = 0, or when OA is in rail-torail input mode (OARRI = 1), or when OA charge
pump is on. The current should only be counted
once even if both OA and CTSD16 are requesting
the clock.
ICTSD16CLK
(1)
AVSS = DVSS = 0 V
MIN
TYP
2.2
GAIN: 1, 2, 4, 8, 16
3V
GAIN: 1, 16
3V
MAX
UNIT
3.6
V
190(1)
µA
300(1)
3V
205
240
µA
See Table 8-1 to calculate total current from CTSD16 for different use cases.
Table 8-1 explains how to compute the total current, ITOTAL, when the CTSD, along with associated modules, are
used. See Section 8.8.14.2 for a similar table for the OA. A "yes" means it must be included in computing ITOTAL.
Here is an example current calculation for CTS16D in rail-to-rail input mode (CTSD16RRI = 1) using the internal
reference (CTSD16REFS = 1) and OA0 and OA1 enabled in rail-to-rail input modes, OARRI = 1.
As an example, assume that the application uses the CTS16D in rail-to-rail input mode (CTSD16RRI = 1) with
the internal reference (CTSD16REFS = 1) and OA0 and OA1 are enabled in rail-to-rail input modes, OARRI = 1.
The total current, ITOTAL, would be computed as follows:
ITOTAL = ICTSD16 + ICTSD16CLK+ ICP + IREFBG + 2 × IOA
(1)
Table 8-1. CTSD16, Current Calculation
USE CASE
DETAILS
USE CASE NAME
CTSD16
CTSD16 rail-to-rail inputs
(1)
(2)
(3)
(4)
CTSD16RRI = 1
ICTSD16
ICTSD16CLK (1)
ICP (2)
IREFBG (3)
IREF (4)
yes
yes
no
yes if CTSD16REFS = 1
no if CTSD16REFS = 0
yes
yes
yes
yes
yes if CTSD16REFS = 1
no if CTSD16REFS = 0
yes
Count this only once no matter how many modules use it. OA can also use this when rail-to-rail input is selected.
Count this only once no matter how many modules use it. OA also uses this. This current is listed in Section 8.8.14.1.
Count this only once no matter how many modules use it. DAC can use this as well as internal reference when it is available externally,
REFOUT = 1. This current is listed in Section 8.8.12.1.
Count this only once no matter how many modules use it. This current is listed in Section 8.8.14.1. If IREFBG is used that includes IREF
current.
Section 8.8.11.2 lists the characteristics of the CTSD16 external voltage reference.
8.8.11.2 CTSD16, External Voltage Reference
VCC
MIN
TYP
MAX
VVeREF+
Input voltage range
PARAMETER
CTSD16REFS = 0
3V
1.0
1.2
1.5
V
IVeREF+
Input current
CTSD16REFS = 0
3V
50
nA
54
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TEST CONDITIONS
UNIT
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Section 8.8.11.3 lists the characteristics of the CTSD16 input range.
8.8.11.3 CTSD16, Input Range
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VID,FSR
Differential full-scale input
voltage range
VID = VI,A+ – VI,A–
VI,FSR
Single-ended full-scale input
voltage range
VID = VI,A+ – VR
negative input is tied to VR
VID
Differential input voltage range
for specified performance(2)
CTSD16REFS = 1
VCC
MIN
TYP
MAX
UNIT
–VR/Gain
+VR/Gain
V
VR – VR/
Gain
VR + VR/
Gain
V
CTSD16GAINx = 1
±928
CTSD16GAINx = 2
±464
CTSD16GAINx = 4
±232
CTSD16GAINx = 8
±116
CTSD16GAINx = 16
mV
±58
VR –
(0.8 × VR/
Gain)
VR +
(0.8 × VR/
Gain)
VI
Single-ended input voltage
range for specified performance
ZI
Input impedance
(pin Ax or ADx+ or ADx- to
AVSS)
CTSD16GAINx = 1, 16
3V
20
MΩ
ZID
Differential input impedance
(pin ADx+ to pin ADx-)
CTSD16GAINx = 1, 16
3V
35
MΩ
VI
Absolute input voltage range
AVSS
VCC
V
VIC
Common-mode input voltage
range
AVSS
VCC
V
(1)
(2)
V
All parameters pertain to each CTSD16 input.
The full-scale range is defined by VFSR+ = +VR/GAIN and VFSR- = -VR/GAIN; FSR = VFSR+ - VFSR- = 2xVR/GAIN. If VR is sourced
externally, the analog input range should not exceed 80% of VFSR+ or VFSR-; that is, VID = 0.8 VFSR- to 0.8 VFSR+. If VR is sourced
internally, the given VID ranges apply.
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Section 8.8.11.4 lists the performance characteristics of the CTSD16.
8.8.11.4 CTSD16, Performance
CTSD16OSRx = 256, CTSD164REFS = 1 (see Figure 8-16, Figure 8-17, and Figure 8-18)
PARAMETER
fM
TEST CONDITIONS
VCC
MIN
Modulator clock
CTSD16GAINx = 1, input ADx+ and
ADx- (differential)
84
CTSD16GAINx = 2, input ADx+ and
ADx- (differential)
SINAD
SINAD
Signal-to-noise +
distortion ratio for
differential inputs
Signal-to-noise +
distortion ratio for
single-ended input
CTSD16GAINx = 4, input ADx+ and
ADx- (differential)
fIN = 50 Hz(1)
87
CTSD16GAINx = 8, input ADx+ and
ADx- (differential)
82
CTSD16GAINx = 16, input ADx+ and
ADx- (differential)
77
CTSD16GAINx = 1, input Ax (singleended)
83
CTSD16GAINx = 2, input Ax (singleended)
82
CTSD16GAINx = 4, input Ax (singleended)
UNIT
MHz
85
3V
fIN = 50 Hz(1)
3V
CTSD16GAINx = 8, input Ax (singleended)
72
CTSD16GAINx = 16, input Ax (singleended)
66
CTSD16GAINx = 4
dB
78
dB
1
CTSD16GAINx = 2
Nominal gain
MAX
86
CTSD16GAINx = 1
G
TYP
1.024
2
3V
4
CTSD16GAINx = 8
8
CTSD16GAINx = 16
16
EG
Gain error
CTSD16GAINx: 1, 8, or 16 with external reference (1.2
V)
3V
ΔEG/ΔT
Gain error
temperature
coefficient, internal
reference
CTSD16GAINx: 1, 8, or 16
3V
3
50
ppm/
°C
ΔEG/ΔT
Gain error
temperature
coefficient, external
reference
CTSD16GAIN: 1, 8, or 16 with external reference
(1.2 V)
3V
4
15
ppm/
°C
ΔEG/ ΔVCC Gain error vs VCC
–1%
CTSD16GAINx: 1, 8, or 16
CTSD16GAINx = 1
+1%
0.02
±4.1
EOS
Offset error
ΔEOS/ΔT
Offset error
temperature
coefficient
CTSD16GAINx = 1, 16
3V
±1
ΔEOS/
ΔVCC
Offset error vs VCC
CTSD16GAINx = 1, 16
3V
11
CMRR,
50Hz
CTSD16GAINx = 1, VID = 928 mV, fIN = 50 Hz
Common-mode
rejection ratio at 50 Hz CTSD16GAINx = 16, VID = 58 mV, fIN = 50 Hz
3V
56
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CTSD16GAINx = 16
%/V
3V
±3.4
78
80
±10
mV
ppm
FSR/
°C
µV/V
dB
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8.8.11.4 CTSD16, Performance (continued)
CTSD16OSRx = 256, CTSD164REFS = 1 (see Figure 8-16, Figure 8-17, and Figure 8-18)
PARAMETER
AC PSRR
DC PSRR
(1)
AC power supply
rejection ratio
DC power supply
rejection ratio
TEST CONDITIONS
VCC
MIN
TYP
CTSD16GAINx: 1, VCC = 3 V ±50 mV × sin(2π × fVcc ×
t), fVcc = 50 Hz,
Inputs grounded (no analog signal applied)
95
CTSD16GAINx: 8, VCC = 3 V ±50 mV × sin(2π × fVcc ×
t), fVcc = 50 Hz,
Inputs grounded (no analog signal applied)
105
CTSD16GAINx: 16, VCC = 3 V ±50 mV × sin(2π × fVcc ×
t), fVcc = 50 Hz,
Inputs grounded (no analog signal applied)
105
CTSD16GAINx: (1, 8, 16), VCC = 2.2 V to 3.6 V, (PSRR
[dB] = –20 log(dVout/dVcc) with dVout observed as
change in the digital conversion result; assumed to be
dominated by reference)
90
MAX
UNIT
dB
dB
The following voltages were applied to the CTSD16 inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t)
VI,A–(t) = 0 V – VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VIN,A+(t) – VIN,A-(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to CTSD16 input range).
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0
3
-0.2
2.5
Offset Voltage (mV)
Offset (mV)
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-40
A.
1.5
1
0.5
Gain = 1
Gain = 16
-20
2
0
20
40
Temperature (°C)
60
80
0
0.25
100
A.
Average of four typical devices
0.55
Gain = 1
0.85
1.5
1.8
1.2
2.1
Common-Mode Voltage (V)
OSR = 256
2.4
2.7
DIfferential Signal = 300
Figure 8-17. CTSD16 Typical Offset Voltage vs
Common-Mode Voltage
Figure 8-16. CTSD16 Offset Voltage vs
Temperature
90
85
SINAD (dB)
80
75
70
65
60
55
50
10
CTSD16REFS = 1
100
OSR
1000
CTSD16GAINx = 1
Figure 8-18. SINAD Performance vs OSR
58
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Section 8.8.11.5 lists the characteristics of the built-in Vcc sense.
8.8.11.5 Built-in Vcc Sense
PARAMETER
VCC,sense
TEST CONDITIONS
AVCC divider
MIN
0.95 ×
(AVCC / 2)
CTSD16ON = 1, CTSD16INCH = 0111
TYP
MAX
AVCC / 2
1.05 ×
(AVCC / 2)
UNIT
V
Section 8.8.11.6 lists the characteristics of the temperature sensor.
8.8.11.6 Temperature Sensor
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Vsensor
Temperature sensor output voltage(1) (2)
CTSD16ON = 1, CTSD16INCH = 110,
VCC = 3 V, TA = 30°C
Isensor
Temperature sensor quiescent current consumption
CTSD16ON = 1, CTSD16INCH = 110,
TA = 85°C
(1)
(2)
MIN
TYP
MAX
UNIT
800
mV
2
uA
The temperature sensor offset can be as much as ±30°C. TI recommends a single-point calibration to minimize the offset error of the
built-in temperature sensor.
The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage
levels. The sensor voltage can be computed as VSENSE = TCSENSOR * (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR
can be computed from the calibration values for higher accuracy.
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8.8.12 REF
Section 8.8.12.1 lists the characteristics of the REF and REFBG built-in reference.
8.8.12.1 REF and REFBG, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IREFBG
Operating supply current into AVCC
VCC = 3.0 V, REFON = 1 and REFOUT = 1
terminal(1)
VREFBG
Bandgap output voltage calibrated
IREF
Operating supply current into AVCC
VCC = 3.0 V, REFON = 1
terminal(1)
VREF
Positive built-in reference voltage
output
VCC = 3.0 V,
VeREF+ ≤ 1.5 V if used
MIN
1.146
TYP
MAX
UNIT
110
130
µA
1.16
1.174
V
15
20
µA
REFVSEL = {2} for 2.5 V, REFON = 1
2.5
±1%
REFVSEL = {1} for 2.0 V, REFON = 1
2.0
±1%
1.5
±1%
REFVSEL = {0} for 1.5 V, REFON = 1
AVCC(min)
AVCC minimum voltage, Positive
built-in reference active
DAC12SREFx = 0, REFVSEL = {0} for 1.5 V
2.2
DAC12SREFx = 0, REFVSEL = {1} for 2 V
2.3
DAC12SREFx = 0, REFVSEL = {2} for 2.5 V
2.8
V
V
PSRR_DC Power supply rejection ratio (DC)
VCC = 2.2 V to 3.6 V, TA = 25°C
50
µV/V
PSRR_AC Power supply rejection ratio (AC)
VCC = 2.2 V to 3.6 V, TA = 25°C,
f = 1 kHz, ΔVpp = 100 mV
1.5
mV/V
15
TCREF+
Bandgap reference temperature
coefficient(2)
IVREF+ = 0 A
tSETTLE
Settling time of VREFBG reference
voltage(3)
AVCC = AVCC (min) through AVCC(max),
REFON = 0 → 1
CVREFBG
Capacitance at VREFBG terminal
ILOAD
IL(VREFBG)
(1)
(2)
(3)
(4)
(5)
60
50 ppm/°C
120
µs
See (4)
1
nF
VREFBG maximum load current
REFOUT = REFON = 1
1
mA
Load-current regulation, VREFBG
terminal(5)
I(VREF+) = +1 mA or –1 mA,
AVCC = AVCC (min),
REFON = REFOUT = 1
3.5 mV/mA
The internal reference current is supplied from terminal AVCC. Consumption is independent of the CTSD16ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
There is no capacitance required on VREFBG if the reference voltage is not used externally. However, TI recommends a capacitance
close to the maximum value to reduce any reference voltage noise.
Contribution only due to the reference and buffer including package. This does not include resistance due to PCB traces or other
external factors.
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8.8.13 DAC
Section 8.8.13.1 lists the supply specifications of the DAC.
8.8.13.1 12-Bit DAC, Supply Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
AVCC
TEST CONDITIONS
Analog supply voltage
VCC
Supply current, single DAC channel(1) (2)
3V
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = AVCC
2.2 V to
3.6 V
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = AVCC
PSRR
(1)
(2)
(3)
(4)
Power supply rejection
MAX
3.6
65
110
125
165
UNIT
V
µA
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = AVCC
ratio(3) (4)
TYP
2.2
DAC12AMPx = 2, DAC12IR = 0,
DAC12OG = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREFBG = 1.16 V
IDD
MIN
AVCC = DVCC, AVSS = DVSS = 0 V
DAC12_xDAT = 800h,
VeREF+ = 1.16 V or 1.5 V,
ΔAVCC = 100 mV
2.2 V to
3.6 V
DAC12_xDAT = 800h,
VeREF+ = 1.16 V or 2.5 V
ΔAVCC = 100 mV
3V
250
350
750
1100
70
dB
70
No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications Section 8.8.13.4.
PSRR = 20 log (ΔAVCC / ΔVDAC12_xOUT)
The internal reference is not used.
DAC VOUT
DAC Output
VR+
RLoad = ¥
Ideal transfer
function
AVCC
2
Offset Error
CLoad = 100 pF
Gain Error
Positive
Negative
DAC Code
Figure 8-19. Linearity Test Load Conditions, Gain and Offset Definition
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Section 8.8.13.2 lists the linearity specifications of the DAC.
8.8.13.2 12-Bit DAC, Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 8-19)
PARAMETER
Resolution
TEST CONDITIONS
INL
Integral nonlinearity(1)
DNL
Differential
nonlinearity(1)
MIN
TYP
MAX
12
VeREF+ = 1.16 V, DAC12AMPx = 7, DAC12IR = 1
2.2 V, 3 V
±2
±4
2.2 V, 3 V
±2
±4
VeREF+ = 1.16 V, DAC12AMPx = 7, DAC12IR = 1
2.2 V, 3 V
±0.4
±1
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1
2.2 V, 3 V
±0.4
±1
calibration(1) (2)
Offset voltage
With calibration(1) (2)
VeREF+ = 1.16 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V, 3 V
±21
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V, 3 V
±21
VeREF+ = 1.16 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V, 3 V
±1.5
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V, 3 V
±1.5
Offset error temperature
With calibration
coefficient(1)
2.2 V, 3 V
EG
Gain error
VeREF+ = 1.16 V
2.2 V, 3 V
±2.5
VeREF+ = 2.5 V
2.2 V, 3 V
±2.5
dE(G)/dT
Gain temperature
coefficient(1)
tOffset_Cal
Time for offset
calibration(3)
2.2 V, 3 V
DAC12AMPx = 2
(2)
(3)
62
LSB
±10
µV/°C
%FSR
ppm of
FSR/
°C
10
165
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
(1)
LSB
mV
dE(O)/dT
DAC12AMPx = 3, 5
UNIT
bits
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1
Without
EO
VCC
12-bit monotonic
66
ms
16.5
Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b"
of the first-order equation: y = a + bx. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with
DAC12AMPx = {0, 1}. TI recommends configuring the DAC12 module before initiating calibration. Port activity during calibration may
affect accuracy and is not recommended.
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Section 8.8.13.3 lists the output specifications of the DAC.
8.8.13.3 12-Bit DAC, Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
No load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
Output voltage
range(1) (see Figure
8-20)
VO
No load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
Maximum DAC12
load capacitance
IL(DAC12)
Maximum DAC12
load current
0
0.005
AVCC –
0.05
AVCC
0
0.1
AVCC –
0.13
AVCC
2.2 V, 3.6 V
DAC12AMPx = 2, DAC12_xDAT = 0FFFh,
VO/P(DAC12) > AVCC – 0.3
DAC12AMPx = 2, DAC12_xDAT = 0h,
VO/P(DAC12) < 0.3 V
Output resistance
(see Figure 8-20)
RLoad = 3 kΩ, VO/P(DAC12) > AVCC – 0.3 V,
DAC12_xDAT = 0FFFh
100
pF
–1
2.2 V, 3.6 V
mA
1
2.2 V, 3.6 V
150
250
150
250
RLoad = 3 kΩ,
0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V
(1)
UNIT
V
RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h
RO/P(DAC12)
MAX
2.2 V, 3.6 V
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
CL(DAC12)
TYP
Ω
6
Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
Max
RLoad
ILoad
AVCC
DAC12
2
O/P(DAC12_x)
CLoad = 100 pF
Min
0.3
AVCC – 0.3 V
VOUT
AVCC
Figure 8-20. DAC12_x Output Resistance Tests
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Section 8.8.13.4 lists the reference input specificaitons of the DAC.
8.8.13.4 12-Bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VeREF+
TEST CONDITIONS
Reference input voltage
range
DAC12IR = 0(1) (2)
VCC
MIN
2.2 V to 3.6 V
DAC12IR = 1(3) (4)
DAC12_0 DAC12IR =
DAC12_1 DAC12IR = 0
TYP
MAX
AVCC / 3
AVCC + 0.2
AVCC
AVCC + 0.2
20
DAC12_0 DAC12IR = 0,
DAC12_1 DAC12IR = 1
52
2.2 V, 3 V
52
kΩ
DAC12_0 DAC12IR =
DAC12_1 DAC12IR = 1,
DAC12_0 DAC12SREFx =
DAC12_1 DAC12SREFx(5)
(1)
(2)
(3)
(4)
(5)
V
MΩ
DAC12_0 DAC12IR = 1,
DAC12_1 DAC12IR = 0
Ri(VREFBG), Reference input
Ri(VeREF+) resistance
UNIT
26
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
and reduce the reference input resistance.
Section 8.8.13.5 and Section 8.8.13.6 list the dynamic specifications of the DAC.
8.8.13.5 12-Bit DAC, Dynamic Specifications
VREF = VCC, DAC12IR = 1 (see Figure 8-21 and Figure 8-22), over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted)
PARAMETER
tON
TEST CONDITIONS
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB(1)
(see Figure 8-21)
DAC12 on time
VCC
MIN
DAC12AMPx = 0 → {2, 3, 4}
DAC12AMPx = 0 → {5, 6}
2.2 V, 3 V
DAC12AMPx = 0 → 7
DAC12AMPx = 2
tS(FS)
Settling time, full scale
DAC12_xDAT =
80h → F7Fh → 80h
DAC12AMPx = 3, 5
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
tS(C-C)
Settling time, code to
code
DAC12_xDAT =
3F8h → 408h → 3F8h,
BF8h → C08h → BF8h
DAC12AMPx = 2
DAC12AMPx = 3, 5
Slew rate
DAC12_xDAT =
80h → F7Fh → 80h(2)
Glitch energy
DAC12_xDAT =
800h → 7FFh → 800h
(1)
(2)
64
120
30
6
12
100
200
40
80
15
30
UNIT
µs
µs
µs
1
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
DAC12AMPx = 7
60
15
2
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
DAC12AMPx = 3, 5
MAX
5
DAC12AMPx = 2
SR
TYP
0.05
0.35
0.35
1.10
1.50
5.20
2.2 V, 3 V
35
V/µs
nV-s
RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 8-21.
Slew rate applies to output voltage steps ≥ 200 mV.
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Conversion 1
VOUT
DAC Output
Conversion 2
±1/2 LSB
Glitch
Energy
RLoad = 3 kW
Conversion 3
ILoad
AVCC
2
±1/2 LSB
CLoad = 100 pF
RO/P(DAC12.x)
tsettleLH
tsettleHL
Figure 8-21. Settling Time and Glitch Energy Testing
Conversion 1
Conversion 2
Conversion 3
VOUT
90%
90%
10%
10%
tSRLH
tSRHL
Figure 8-22. Slew Rate Testing
8.8.13.6 12-Bit DAC, Dynamic Specifications (Continued)
over recommended ranges of supply voltage and TA = 25°C (unless otherwise noted)
PARAMETER
BW–3dB
TEST CONDITIONS
3-dB bandwidth,
VDC = 1.5 V,
VAC = 0.1 VPP
(see Figure 8-23)
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
MIN
TYP
MAX
UNIT
40
2.2 V, 3 V
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
Channel-to-channel crosstalk(1)
(see Figure 8-24)
(1)
VCC
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
kHz
180
550
DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
fDAC12_1OUT = 10 kHz at 50/50 duty cycle
DAC12_0DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No load,
fDAC12_0OUT = 10 kHz at 50/50 duty cycle
–80
2.2 V, 3 V
dB
–80
RLoad = 3 kΩ, CLoad = 100 pF
RLoad = 3 kW
ILoad
VeREF+
AVCC
DAC12_x
2
DACx
AC
CLoad = 100 pF
DC
Figure 8-23. Test Conditions for 3-dB Bandwidth Specification
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RLoad
ILoad
AVCC
DAC12_0
DAC12_xDA T
2
DAC0
080h
080h
F7Fh
F7Fh
080h
VOUT
CLoad = 100 pF
VREF+
VDAC12_yOUT
RLoad
ILoad
AVCC
DAC12_1
VDAC12_xOUT
2
DAC1
1/fToggle
CLoad = 100 pF
Figure 8-24. Crosstalk Test Conditions
8.8.14 Operational Amplifier
Section 8.8.14.1 lists the characteristics of the OA.
8.8.14.1 Operational Amplifier, OA0, OA1, PGA Buffers
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC
Analog supply voltage
AVCC = DVCC, AVSS = DVSS = 0 V
2.2
CCPCAP
External charge pump
capacitor to AVSS.
Required when charge pump is enabled
20
ICP_PEAK
Charge pump peak
current
OARRI = 0h to 1h, ICP_LOAD = 0 μA
ICP
Charge pump average
OARRI = 1h, ICP_LOAD = 100 μA
current
tCP_EN_fast
Charge pump enable
time fast
tCP_EN_slow
Charge pump enable
time slow
IOA
Supply current, per
opamp
IO = 0 mA,
OARRI = 0h (charge pump disabled)
VOS
Input offset voltage
Noninverting, unity gain
±2
mV
dVOS/dT
Input offset voltage
temperature drift
Noninverting, unity gain
±1
μV/°C
dVOS/dV
Input offset voltage
voltage drift
Noninverting, unity gain
±3
μV/V
Cin
Input capacitance
Differential
4
pF
Common mode
6
pF
PSRR_DC
Power supply rejection Noninverting, unity gain,
ratio, DC
VINP = positive input of OA = 1 V
50
μV/V
VCM
Common mode
voltage range(2)
CMRR_DC
Common mode
rejection ratio, DC
en
Input voltage noise
density
AOL
Open-loop voltage
gain, DC
66
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22
3.6
V
24
nF
1.6
570(1)
OARRI = 0h to 1h, ICP_LOAD = 0 μA,
AFE biases previously enabled and settled
which can be done with REFON=1 or other
modules requesting REFON.
OARRI = 0h to 1h, ICP_LOAD = 0 μA,
Includes AFE bias settling
mA
710(1)
μA
50
μs
75
μs
105(1)
130(1)
μA
OARRI = 0h,
Noninverting, unity gain
0.1
VCC - 1.0
V
OARRI = 1h,
Noninverting, unity gain
0.1
VCC - 0.1
V
Over common-mode voltage range
110
f = 100 Hz, OARRI = 0h or 1h
3.0 V
90
f = 50 kHz, OARRI = 0h or 1h
3.0 V
25
95
dB
nV/√Hz
dB
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
GBW
Gain-bandwidth
product
CL = 100 pF, OAM = 1h
800
kHz
SR
Slew rate
Noninverting, unity gain,
CL = 100 pF, OAM = 1h
0.4
V/μs
tSETTLE
Settling time
Noninverting, unity gain,
2.0-V step, 0.1%, OAM = 1h
5.3
μs
VO
Voltage output swing
from rail
–250 μA ≤ IO ≤ 250 μA,
Noninverting, unity gain (OAM = 1h)
5
55
mV
Enable time fast
Noninverting, unity gain,
OAM = 0h transition to 1h,
AFE biases previously enabled and settled
which can be done with REFON = 1 or other
modules requesting REFON(3)
3
7
μs
tEN_SLOW
Enable time slow
Noninverting,unity gain,
OARRI = 0h transition to 1h,
OAM = 0h transition to 1h,
Includes AFE bias and charge pump
settling(3)
190
225
μs
tDIS
Disable time
tEN_FAST
(1)
(2)
3.0 V
0.4
μs
See Section 8.8.14.2 to calculate total current from OA for different use cases.
The common-mode input range is measured with the OA in a unity-gain source-follower configuration. The input signal is swept from 0
V to VCC, and the output of the OA is monitored. The minimum and maximum values represent when the input and output differ more
than 10 mV, not including the offset, VOS.
The AFE bias is used by several modules including the OA charge pump, OA, and CTSD16. Any of these modules will request the
AFE bias when enabled. The AFE bias is generated by the REF module, so enabling the REF module also enables the AFE bias.
(3)
Section 8.8.14.2 explains how to compute the total current, ITOTAL, when the OA and associated modules are
used. See Table 8-1 for a similar table for the CTSD16. A "yes" means it must be included in computing ITOTAL.
As an example, assume that the application uses the CTS16D in rail-to-rail input mode (CTSD16RRI = 1) with
the internal reference (CTSD16REFS = 1) and OA0 and OA1 are enabled in rail-to-rail input modes, OARRI = 1.
The total current, ITOTAL, would be computed as follows:
ITOTAL = ICTSD16 + ICTSD16CLK+ ICP + IREFBG + 2 × IOA
700
160
650
140
600
550
120
Number of Units
Number of Units
500
450
400
350
300
250
200
100
80
60
40
150
100
20
50
0
0
0.4
0.6
0.8
1
1.2
1.5
1.6
1.8
Offset Voltage (mV)
2
2.2
2.4
2.6
Figure 8-25. OA Offset Voltage Sample Production
Distribution
Copyright © 2020 Texas Instruments Incorporated
0
0.5
1
1.5
2
2.5
3
Offset Voltage Drift (µV/°C)
3.5
4
4.5
Figure 8-26. OA Offset Voltage Drift Sample
Production Distribution
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8.8.14.2 OA, Current Calculation
USE CASE NAME
USE CASE DETAILS
IOA
ICTSD16CLK (1)
ICP (2)
IREF (3)
OA
OARRI = 0
yes
no
no
yes
OA with rail-to-rail input
OARRI = 1
yes
yes
yes
yes
Rail-to-rail input up, module off
(CTSD16SC = 0) AND
(CTSD16RRI = 1) AND
(CTSD16RRIBURST = 0) OR
((OARRI = 1 (for any OA))
AND (OAM = 0))
no
yes
yes
yes
(1)
(2)
(3)
Count this current only once no matter how many modules use it. CTSD16 and the charge pump also use this. This current is listed in
Section 8.8.11.1.
Count this current only once no matter how many modules use it. CTSD16 also uses this when rail-to-rail inputs are selected.
Count this current only once no matter how many modules use it. This current is listed in Section 8.8.14.1. If IREFBG is used, that
includes the IREF current.
8.8.15 Switches
Section 8.8.15.1 lists the characteristics of the ground switches.
8.8.15.1 Ground Switches (GSW0A, GSW0B, GSW1A, GSW1B)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
Supply voltage
TYP
2.2
TA = 0°C to 60°C
ILKG
Input leakage(1)
IIN
Input current switch to AVSS
RON
Switch ON resistance with switch closed
IIN = 100 µA,
TA = –40°C to 85°C
ROFF
Switch OFF resistance with switch open
TA = –40°C to 85°C,
Input signal frequency < 100 Hz
tON/OFF
Enable or disable time
TA = –40°C to 85°C
(1)
MIN
MAX
3.6
±0.25
TA = –40°C to 85°C
±50
0
9.5
100
UNIT
V
nA
100
µA
18.5
Ω
MΩ
0.25
µs
Ground switches are shared with general-purpose I/Os. This leakage includes all leakage seen at the device pin, not only leakage
caused by the switch itself.
4
DVCC = 2.2 V
DVCC = 3 V
DVCC = 3.6 V
Input Leakage Current (nA)
3.5
3
2.5
2
1.5
1
0.5
0
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
Temperature (°C)
Average of three typical devices
Figure 8-27. Ground Switch Input Leakage Current vs Temperature
68
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Section 8.8.15.2 lists the characteristics of the OA switches.
8.8.15.2 Operational Amplifier Switches
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
Supply voltage
ILKG
Input leakage(1)
IIN
Input current through switch
TEST CONDITIONS
TYP
2.2
TA = 0°C to 60°C
MAX
±0.25
±50
0
RON
Switch ON resistance with switch closed(2)
ROFF
Switch OFF resistance with switch open
TA = –40°C to 85°C,
Input signal frequency < 100 Hz
tON/OFF
Enable or disable time
TA = –40°C to 85°C
UNIT
3.6
TA = –40°C to 85°C
IIN = 100 µA,
TA = –40°C to 85°C
(1)
MIN
100
1
V
nA
µA
kΩ
100
MΩ
0.45
µs
This leakage includes all leakage seen at the device pin, not only leakage caused by the switch itself. It assumes a total of five
switches present and a shared digital I/O.
The resistance varies with input voltage range. This resistance represents the peak resistance at the worst case input range (see
Figure 8-29).
(2)
1400
0.30
Input Leakage Current (nA)
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Temperature (°C)
Average of three typical devices
Figure 8-28. OA Switch Input Leakage Current vs
Temperature
Copyright © 2020 Texas Instruments Incorporated
1200
Switch ON-Resistance – RON (W)
DVCC = 2.2 V
DVCC = 2.3 V
DVCC = 3 V
DVCC = 3.6 V
1000
800
600
400
200
0
0.2
TA = –40°C
TA = 25°C
TA = 85°C
0.6
1.0
1.4
1.8
2.2
Common-Mode Voltage (V)
2.6
3.0
Average of three typical devices
Figure 8-29. OA Switch RON vs Common-Mode
Voltage
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8.8.16 Comparator
Section 8.8.16.1 lists the characteristics of the comparator.
8.8.16.1 Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
Supply voltage
MIN
TYP
1.8
3.6
1.8 V
CBPWRMD = 00, CBON = 1,
CBRSx = 00
IAVCC_COMP
Comparator operating supply
current into AVCC, Excludes
reference resistor ladder
IAVCC_REF
Quiescent current of resistor
ladder into AVCC, Includes
REF module current
VIC
Common mode input range
VOFFSET
Input offset voltage
CIN
Input capacitance
RSIN
Series input resistance
Propagation delay, response
time
tPD
tPD,filter
tEN_CMP
Propagation delay with filter
active
Comparator enable time
V
40
2.2 V
30
50
3V
40
65
2.2 V, 3 V
10
30
CBPWRMD = 10, CBON = 1,
CBRSx = 00
2.2 V, 3 V
0.5
1.3
CBREFACC = 1, CBREFLx = 01,
CBRSx = 10, REFON = 0, CBON = 0
2.2 V, 3 V
10
22
µA
0
VCC – 1
V
CBPWRMD = 00
–20
20
CBPWRMD = 01 or 10
–10
10
µA
5
On (switch closed)
Off (switch open)
3
50
CBPWRMD = 01, CBF = 0
600
CBPWRMD = 10, CBF = 0
50
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 00
0.35
0.6
1.5
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 01
0.6
1.0
1.8
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 10
1.0
1.8
3.4
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 11
1.8
3.4
6.5
1
2
Reference voltage for a given
tap
VIN = reference into resistor ladder,
n = 0 to 31
µs
µs
CBON = 0 → 1,
CBPWRMD = 10
VCB_REF
ns
µs
CBON = 0 → 1,
CBPWRMD = 00 or 01
Temperature coefficient of
VCB_REF
kΩ
MΩ
450
TCCB_REF
mV
pF
4
CBPWRMD = 00, CBF = 0
Resistor reference enable time CBON = 0 → 1
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UNIT
CBPWRMD = 01, CBON = 1,
CBRSx = 00
tEN_REF
70
MAX
100
1.0
1.5
µs
50
ppm/
°C
VIN ×
VIN ×
VIN ×
(n + 0.5) / (n + 1) / (n + 1.5) /
32
32
32
V
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8.8.17 USB
Section 8.8.17.1 lists the characteristics of PU.0 and PU.1.
8.8.17.1 Ports PU.0 and PU.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
High-level output voltage (see Figure 8-31)
MIN
VUSB = 3.3 V ±10%, IOH = –25 mA
VOL
Low-level output voltage (see Figure 8-30)
VUSB = 3.3 V ±10%, IOL = 25 mA
VIH
High-level input voltage (see Figure 8-32)
VUSB = 3.3 V ±10%
VIL
Low-level input voltage (see Figure 8-32)
VUSB = 3.3 V ±10%
MAX
2.4
UNIT
V
0.4
2.0
V
V
0.8
V
IOL - Typical Low-Level Output Current - mA
90
VCC = 3.0 V
TA = 25ºC
80
VCC = 3.0 V
TA = 85ºC
VCC = 1.8 V
TA = 25ºC
70
60
50
VCC = 1.8 V
TA = 85ºC
40
30
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
VOL - Low-Level Output Voltage - V
Figure 8-30. Ports PU.0, PU.1 Typical Low-Level Output Characteristics
IOH - Typical High-Level Output Current - mA
0
-10
-20
-30
VCC = 1.8 V
TA = 85ºC
-40
-50
VCC = 3.0 V
TA = 85ºC
-60
VCC = 1.8 V
TA = 25ºC
-70
VCC = 3.0 V
TA = 25ºC
-80
-90
0.5
1
1.5
2
VOH - High-Level Output Voltage - V
2.5
3
Figure 8-31. Ports PU.0, PU.1 Typical High-Level Output Characteristics
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2.0
TA = 25°C, 85°C
1.8
VIT+, postive-going input threshold
1.6
Input Threshold - V
1.4
1.2
VIT–, negative-going input threshold
1.0
0.8
0.6
0.4
0.2
0.0
1.8
2.2
2.6
VUSB Supply Voltage, VUSB - V
3
3.4
Figure 8-32. Ports PU.0, PU.1 Typical Input Threshold Characteristics
Section 8.8.17.2 and Section 8.8.17.3 list the characteristics of the DP and DM ports.
8.8.17.2 USB Output Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
D+, D– single ended
USB 2.0 load conditions
MIN
MAX
2.8
3.6
UNIT
0
0.3
V
28
44
Ω
V
VOL
D+, D– single ended
USB 2.0 load conditions
Z(DRV)
D+, D– impedance
Including external series resistor of 27 Ω
tRISE
Rise time
Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+
4
20
ns
tFALL
Fall time
Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+
4
20
ns
8.8.17.3 USB Input Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
MAX
2.5
V(CM)
Differential input common mode range
0.8
Z(IN)
Input impedance
300
UNIT
V
kΩ
VCRS
Crossover voltage
1.3
VIL
Static SE input logic low level
0.8
VIH
Static SE input logic high level
2.0
V
VDI
Differential input voltage
0.2
V
72
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2.0
V
V
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Section 8.8.17.4 lists the characteristics of the USB power system.
8.8.17.4 USB-PWR (USB Power System)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLAUNCH
VBUS detection threshold
VBUS
USB bus voltage
VUSB
USB LDO output voltage
TEST CONDITIONS
Normal operation
MIN
TYP
3.76
3.3
voltage(1)
MAX
UNIT
3.75
V
5.5
V
±9%
V
V18
Internal USB
IUSB_EXT
Maximum external current from VUSB terminal(2)
IDET
USB LDO current overload detection(3)
ISUSPEND
Operating supply current into VBUS terminal(4)
CBUS
VBUS terminal recommended capacitance
4.7
µF
CUSB
VUSB terminal recommended capacitance
220
nF
C18
V18 terminal recommended capacitance
220
nF
tENABLE
Settling time VUSB and V18
RPUR
Pullup resistance of PUR terminal
(1)
(2)
(3)
(4)
1.8
USB LDO is on
60
USB LDO is on, USB PLL disabled
Within 2%,
recommended capacitances
70
110
V
12
mA
100
mA
250
µA
2
ms
150
Ω
This voltage is for internal use only. No external DC loading should be applied.
This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB
operation.
A current overload is detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value.
Does not include current contribution of Rpu and Rpd as outlined in the USB specification.
Section 8.8.17.5 lists the characteristics of the USB PLL.
8.8.17.5 USB-PLL (USB Phase-Locked Loop)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IPLL
Operating supply current
fPLL
PLL frequency
MIN
TYP
MAX
7
48
fUPD
PLL reference frequency
tLOCK
PLL lock time
tJitter
PLL jitter
1.5
1000
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UNIT
mA
MHz
3
MHz
2
ms
ps
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8.8.18 LDO-PWR (LDO Power System)
Section 8.8.18.1 lists the characteristics of the LDP power system.
8.8.18.1 LDO-PWR (LDO Power System)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VLAUNCH
LDO input detection threshold
VLDOI
LDO input voltage
VLDO
LDO output voltage
VLDO_EXT
LDOO terminal input voltage with LDO
disabled
LDO disabled
ILDOO
Maximum external current from LDOO
terminal
LDO is on
IDET
LDO current overload detection (1)
CLDOI
LDOI terminal recommended capacitance
CLDOO
LDOO terminal recommended capacitance
tENABLE
Settling time VLDO
(1)
74
MIN
TYP
3.76
3.3
1.8
60
MAX
UNIT
3.75
V
5.5
V
±9%
V
3.6
V
20
mA
100
mA
4.7
µF
220
Within 2%, recommended capacitances
nF
2
ms
A current overload will be detected when the total current supplied from the LDO exceeds this value.
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8.8.19 Flash
Section 8.8.19.1 lists the characteristics of the flash memory.
8.8.19.1 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
DVCC(PGM/ERASE) Program and erase supply voltage
MIN
TYP
1.8
MAX
3.6
UNIT
V
IPGM
Average supply current from DVCC during program
3
5
mA
IERASE
Average supply current from DVCC during erase
6
15
mA
IMERASE, IBANK
Average supply current from DVCC during mass erase or bank erase
6
15
mA
tCPT
Cumulative program time(1)
16
ms
104
Program and erase endurance
tRetention
Data retention duration
25°C
time(2)
105
cycles
100
years
tWord
Word or byte program
64
85
µs
tBlock, 0
Block program time for first byte or word(2)
49
65
µs
tBlock, 1–(N–1)
Block program time for each additional byte or word, except for last byte or
word(2)
37
49
µs
tBlock, N
Block program time for last byte or word(2)
55
73
µs
tSeg Erase
Erase time for segment, mass erase, and bank erase when available(2)
23
32
ms
fMCLK,MGR
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1)
0
1
MHz
(1)
(2)
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
These values are hardwired into the state machine of the flash controller.
8.8.20 Debug and Emulation
Section 8.8.20.1 lists the characteristics of the JTAG and SBW interface.
8.8.20.1 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
µs
1
µs
15
100
µs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
tSBW,Rst
Spy-Bi-Wire return to normal operation time
fTCK
TCK input frequency (4-wire JTAG)(2)
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
edge)(1)
2.2 V, 3 V
2.2 V
0
5
MHz
3V
0
10
MHz
2.2 V, 3 V
45
80
kΩ
60
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
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9 Detailed Description
9.1 Overview
The MSP430FG6626 and MSP430FG6625 are microcontroller configurations with a high-performance 16-bit
ADC, dual 12-bit DACs, dual low-power operational amplifiers, a comparator (COMPB), two USCIs, USB 2.0, a
hardware multiplier (MPY32), DMA, four 16-bit timers, an RTC module with alarm capabilities, an LCD driver,
and up to 73 I/O pins.
The MSP430FG6426 and MSP430FG6425 are microcontroller configurations with a high-performance 16-bit
ADC, dual 12-bit DACs, dual low-power operational amplifiers, a comparator (COMPB), two USCIs, a 3.3-V
LDO, a hardware multiplier (MPY32), DMA, four 16-bit timers, an RTC module with alarm capabilities, an LCD
driver, and up to 73 I/O pins.
9.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are
general-purpose registers (see Figure 9-1).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be managed with
all instructions.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Figure 9-1. Integrated CPU Registers
76
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9.3 Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Table 9-1 lists examples of the three types of instruction formats, and Table 9-2 lists the address modes.
Table 9-1. Instruction Word Formats
INSTRUCTION WORD FORMAT
Dual operands, source and destination
Single operands, destination only
EXAMPLE
OPERATION
ADD R4,R5
R4 + R5 → R5
CALL R8
PC → (TOS), R8 → PC
JNE
Jump-on-equal bit = 0
Relative jump, unconditional or conditional
Table 9-2. Address Mode Descriptions
S(1)
D(1)
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) → M(TONI)
Absolute
✓
✓
MOV &MEM, &TCDAT
M(MEM) → M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect auto-increment
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
ADDRESS MODE
(1)
SYNTAX
EXAMPLE
OPERATION
S = source, D = destination
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9.4 Operating Modes
The devices have one active mode and seven software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
Software can configure the following operating modes:
•
•
•
•
•
•
•
•
78
Active mode (AM)
– All clocks are active
Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
Low-power mode 3.5 (LPM3.5)
– Internal regulator disabled
– No data retention
– RTC enabled and clocked by low-frequency oscillator
– Wake-up input from RST/NMI, RTC_B, P1, P2, P3, and P4
Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wake-up input from RST/NMI, P1, P2, P3, and P4
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9.5 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table
9-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 9-3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power-up, External reset
Watchdog time-out, key violation
Flash memory key violation
WDTIFG, KEYV (SYSRSTIV)(1) (3)
Reset
0FFFEh
63, highest
System NMI
PMM
Vacant memory access
JTAG mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV)(1)
(Non)maskable
0FFFCh
62
(Non)maskable
0FFFAh
61
User NMI
NMI
Oscillator fault
Flash memory access violation
NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)
(1) (3)
Comp_B
Comparator B interrupt flags (CBIV)(1) (2)
Maskable
0FFF8h
60
Timer TB0
TB0CCR0 CCIFG0(2)
Maskable
0FFF6h
59
Timer TB0
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TBIV)(1) (2)
Maskable
0FFF4h
58
Watchdog interval timer mode
WDTIFG
Maskable
0FFF2h
57
USCI_A0 receive or transmit
UCA0RXIFG, UCA0TXIFG
(UCA0IV)(1) (2)
Maskable
0FFF0h
56
USCI_B0 receive or transmit
UCB0RXIFG, UCB0TXIFG (UCB0IV)(1) (2)
Maskable
0FFEEh
55
CTSD16
CTSD16IFG0,
CTSD16OVIFG0(1) (2)
Maskable
0FFECh
54
Timer TA0
TA0CCR0 CCIFG0(2)
Maskable
0FFEAh
53
Timer TA0
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1) (2)
Maskable
0FFE8h
52
USB_UBM(5)
USB interrupts (USBIV)(1) (2)
LDO-PWR (6)
LDOOFFIG, LDOONIFG, LDOOVLIFG
Maskable
0FFE6h
51
DMA
DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,
DMA4IFG, DMA5IFG (DMAIV)(1) (2)
Maskable
0FFE4h
50
Timer TA1
TA1CCR0 CCIFG0(2)
Maskable
0FFE2h
49
Timer TA1
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1) (2)
Maskable
0FFE0h
48
I/O Port P1
P1IFG.0 to P1IFG.7 (P1IV)(1) (2)
Maskable
0FFDEh
47
USCI_A1 receive or transmit
UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (2)
Maskable
0FFDCh
46
USCI_B1 receive or transmit
(UCB1IV)(1) (2)
UCB1RXIFG, UCB1TXIFG
P2IFG.0 to P2IFG.7 (P2IV)(1) (2)
I/O port P2
LCD_B
LCD_B Interrupt Flags
(LCDBIV)(1)
Maskable
0FFDAh
45
Maskable
0FFD8h
44
Maskable
0FFD6h
43
RTC_B
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)(1) (2)
Maskable
0FFD4h
42
DAC12_A
DAC12_0IFG, DAC12_1IFG(1) (2)
Maskable
0FFD2h
41
Timer TA2
TA2CCR0
CCIFG0(2)
Maskable
0FFD0h
40
Timer TA2
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV)(1) (2)
Maskable
0FFCEh
39
I/O port P3
P3IFG.0 to P3IFG.7 (P3IV)(1) (2)
Maskable
0FFCCh
38
I/O port P4
(P4IV)(1) (2)
Maskable
0FFCAh
37
0FFC8h
36
⋮
⋮
P4IFG.0 to P4IFG.7
Reserved(4)
Reserved
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Table 9-3. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
(1)
(2)
(3)
(4)
(5)
(6)
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
0FF80h
0, lowest
Multiple source flags
Interrupt flags are in the module.
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To
maintain compatibility with other devices, TI recommends reserving these locations.
Only on devices with peripheral module USB (MSP430FG6626 and MSP430FG6625)
Only on devices with peripheral module LDO-PWR (MSP430FG6426 and MSP430FG6425)
9.6 USB BSL
The devices MSP430FG6626 and MSP430FG6625 are preprogrammed with the USB BSL. Use of the USB BSL
requires external access to six pins (see Table 9-4). In addition to these pins, the application must support
external components necessary for normal USB operation; for example, the proper crystal on XT2IN and
XT2OUT, proper decoupling, and so on. For additional information, see the MSP430™ Flash Device Bootloader
(BSL) User's Guide.
Table 9-4. USB BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
PU.0/DP
USB data terminal DP
PU.1/DM
USB data terminal DM
PUR
USB pullup resistor terminal
VBUS
USB bus power supply
VSSU
USB ground supply
Note
The default USB BSL evaluates the logic level of the PUR pin after a BOR reset. If it is pulled high
externally, then the BSL is invoked. Therefore, unless the application is invoking the BSL, it is
important to keep PUR pulled low after a BOR reset, even if BSL or USB is never used. TI
recommends applying a 1-MΩ resistor to ground.
9.7 UART BSL
Devices without a USB module (MSP430FG642x) come preprogrammed with the UART BSL. A UART BSL is
also available for devices with the USB module (MSP430FG662x), and it can be programmed by the user into
the BSL memory by replacing the preprogrammed factory-supplied USB BSL. Use of the UART BSL requires
external access to six pins (see Table 9-5). For additional information, see the MSP430™ Flash Device
Bootloader (BSL) User's Guide.
Table 9-5. UART BSL Pin Requirements and Functions
80
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.1
Data transmit
P1.2
Data receive
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VCC
Power supply
VSS
Ground supply
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9.8 JTAG Operation
9.8.1 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/Os. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. Table 9-6 lists the JTAG pin requirements. For further details on
interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a
complete description of the features of the JTAG interface and its implementation, see MSP430 Programming
With the JTAG Interface.
Table 9-6. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
9.8.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two-wire Spy-Bi-Wire interface. SpyBi-Wire can be used to interface with MSP430 development tools and device programmers. Table 9-7 lists the
Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the
JTAG interface and its implementation, see MSP430 Programming With the JTAG interface.
Table 9-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
VSS
Ground supply
9.9 Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
•
•
•
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
Segment A can be locked separately.
9.10 RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all
data is lost. Features of the RAM include:
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•
•
•
•
RAM has n sectors. The size of a sector can be found in Section 9.15.
Each sector 0 to n can be complete disabled; however, data retention is lost.
Each sector 0 to n automatically enters low-power retention mode when possible.
For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
9.11 Backup RAM
The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during
operation from a backup supply if the Battery Backup System module is implemented.
There are 8 bytes of backup RAM. It can be word-wise accessed through the control registers BAKMEM0,
BAKMEM1, BAKMEM2, and BAKMEM3.
9.12 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx
Family User's Guide.
9.12.1 Digital I/O
Up to nine 8-bit I/O ports are implemented: P1 through P9 are complete except P5.2, and port PJ contains four
individual I/O ports.
•
•
•
•
•
•
•
82
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Programmable drive strength on all ports.
Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P9) or word-wise (P1 through P8) in pairs (PA through PD).
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9.12.2 Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2 (see
Table 9-8).
Table 9-8. Port Mapping Mnemonics and Functions
VALUE
0
1
2
3
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
PM_NONE
None
DVSS
PM_CBOUT
–
Comparator_B output
PM_TB0CLK
Timer TB0 clock input
–
Reserved
–
Reserved
PM_DMAE0
DMAE0 Input
–
PM_SVMOUT
–
SVM output
PM_TB0OUTH
Timer TB0 high impedance input TB0OUTH
–
4
PM_TB0CCR0B
Timer TB0 CCR0 capture input CCI0B
Timer TB0: TB0.0 compare output Out0
5
PM_TB0CCR1B
Timer TB0 CCR1 capture input CCI1B
Timer TB0: TB0.1 compare output Out1
6
PM_TB0CCR2B
Timer TB0 CCR2 capture input CCI2B
Timer TB0: TB0.2 compare output Out2
7
PM_TB0CCR3B
Timer TB0 CCR3 capture input CCI3B
Timer TB0: TB0.3 compare output Out3
8
PM_TB0CCR4B
Timer TB0 CCR4 capture input CCI4B
Timer TB0: TB0.4 compare output Out4
9
PM_TB0CCR5B
Timer TB0 CCR5 capture input CCI5B
Timer TB0: TB0.5 compare output Out5
10
PM_TB0CCR6B
Timer TB0 CCR6 capture input CCI6B
Timer TB0: TB0.6 compare output Out6
11
12
13
14
15
16
PM_UCA0RXD
USCI_A0 UART RXD (Direction controlled by USCI – input)
PM_UCA0SOMI
USCI_A0 SPI slave out master in (direction controlled by USCI)
PM_UCA0TXD
USCI_A0 UART TXD (Direction controlled by USCI – output)
PM_UCA0SIMO
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0CLK
USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE
USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
PM_UCB0SOMI
USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0SIMO
USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK
USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE
USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
17
PM_MCLK
18-30
Reserved
31 (0FFh)(1)
(1)
PxMAPy MNEMONIC
PM_ANALOG
–
MCLK
None
DVSS
Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when
applying analog signals.
The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are 5 bits wide, and the upper bits are ignored,
which results in a read value of 31.
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Table 9-9 lists the default settings for all pins that support port mapping.
Table 9-9. Default Mapping
PIN
PxMAPy
MNEMONIC
P2.0/P2MAP0
PM_UCB0STE,
PM_UCA0CLK
USCI_B0 SPI slave transmit enable (direction controlled by USCI – input),
USCI_A0 clock input/output (direction controlled by USCI)
P2.1/P2MAP1
PM_UCB0SIMO,
PM_UCB0SDA
USCI_B0 SPI slave in master out (direction controlled by USCI),
USCI_B0 I2C data (open drain and direction controlled by USCI)
P2.2/P2MAP2
PM_UCB0SOMI,
PM_UCB0SCL
USCI_B0 SPI slave out master in (direction controlled by USCI),
USCI_B0 I2C clock (open drain and direction controlled by USCI)
P2.3/P2MAP3
PM_UCB0CLK,
PM_UCA0STE
USCI_B0 clock input/output (direction controlled by USCI),
USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
P2.4/P2MAP4
PM_UCA0TXD,
PM_UCA0SIMO
USCI_A0 UART TXD (direction controlled by USCI – output),
USCI_A0 SPI slave in master out (direction controlled by USCI)
P2.5/P2MAP5/R23
PM_UCA0RXD,
PM_UCA0SOMI
USCI_A0 UART RXD (direction controlled by USCI – input),
USCI_A0 SPI slave out master in (direction controlled by USCI)
P2.6/P2MAP6/R03
PM_NONE
-
DVSS
P2.7/P2MAP7/LCDREF/R13
PM_NONE
-
DVSS
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
9.12.3 Oscillator and System Clock
The clock system in the MSP430FG662x and MSP430FG642x devices are supported by the Unified Clock
System (UCS) module that includes support for a 32-kHz watch crystal oscillator (in XT1 LF mode; XT1 HF
mode is not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed lowfrequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency
crystal oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low
power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction
with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turnon clock source and stabilizes in 3 µs (typical). The UCS module provides
the following clock signals:
•
•
•
•
Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitallycontrolled oscillator (DCO).
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources available to
ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
9.12.4 Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit
provides the proper internal reset signal to the device during power on and power off. The SVS and SVM
circuitry detect if the supply voltage drops below a user-selectable level and supports both supply voltage
supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically
reset). SVS and SVM circuitry is available on the primary supply and the core supply.
9.12.5 Hardware Multiplier (MPY32)
The multiplication operation is supported by a dedicated peripheral module. The module performs operations
with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed
and unsigned multiply-and-accumulate operations.
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9.12.6 Real-Time Clock (RTC_B)
The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds, minutes,
hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which
compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports
flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in
LPM3.5 mode and operation from a backup supply.
9.12.7 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
9.12.8 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset and
power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootloader
entry mechanisms, and configuration management (device descriptors). SYS also includes a data exchange
mechanism through JTAG called a JTAG mailbox that can be used in the application. Table 9-10 lists the SYS
module interrupt vector registers.
Table 9-10. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
SYSRSTIV, System Reset
SYSSNIV, System NMI
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INTERRUPT EVENT
WORD ADDRESS
OFFSET
No interrupt pending
00h
Brownout (BOR)
02h
RST/NMI (BOR)
04h
PMMSWBOR (BOR)
06h
LPM3.5 or LPM4.5 wake up (BOR)
08h
Security violation (BOR)
0Ah
SVSL (POR)
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SVMH_OVP (POR)
Highest
10h
019Eh
12h
PMMSWPOR (POR)
14h
WDT time-out (PUC)
16h
WDT key violation (PUC)
18h
KEYV flash key violation (PUC)
1Ah
Reserved
1Ch
Peripheral area fetch (PUC)
1Eh
PMM key violation (PUC)
20h
Reserved
22h to 3Eh
No interrupt pending
00h
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
DLYHIFG
PRIORITY
Lowest
Highest
08h
019Ch
VMAIFG
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
SVMLVLRIFG
10h
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Table 9-10. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR REGISTER
SYSUNIV, User NMI
INTERRUPT EVENT
WORD ADDRESS
OFFSET
SVMHVLRIFG
12h
Reserved
14h to 1Eh
No interrupt pending
00h
NMIFG
02h
OFIFG
04h
ACCVIFG
019Ah
08h
Reserved
0Ah to 1Eh
USB wait state time-out
Reserved
86
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Lowest
Highest
06h
BUSIFG
No interrupt pending
SYSBERRIV, Bus Error
PRIORITY
Lowest
00h
0198h
02h
Highest
04h to 1Eh
Lowest
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9.12.9 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or
from a peripheral.
The USB timestamp generator also uses the channel 0, 1, and 2 DMA trigger assignments (see Table 9-11). The
USB timestamp generator is available only on devices with the USB module (MSP430FG662x).
Table 9-11. DMA Trigger Assignments
TRIGGER(1)
CHANNEL
0
1
2
3
0
DMAREQ
1
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
5
TA2CCR0 CCIFG
6
TA2CCR2 CCIFG
7
TBCCR0 CCIFG
8
TBCCR2 CCIFG
9
Reserved
10
Reserved
11
Reserved
12
Reserved
13
Reserved
14
Reserved
15
Reserved
16
UCA0RXIFG
17
UCA0TXIFG
18
UCB0RXIFG
19
UCB0TXIFG
20
UCA1RXIFG
21
UCA1TXIFG
22
UCB1RXIFG
23
UCB1TXIFG
24
CTSD16IFG0
25
DAC12_0IFG
26
DAC12_1IFG
27
USB FNRXD(2)
28
USB ready(2)
29
30
(2)
5
DMA3IFG
DMA4IFG
MPY ready
DMA5IFG
DMA0IFG
31
(1)
4
DMA1IFG
DMA2IFG
DMAE0
Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not cause any DMA trigger event when
selected.
Only on devices with peripheral module USB (MSP430FG662x), otherwise reserved (MSP430FG642x).
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9.12.10 Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,
A and B.
The USCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3- or 4-pin) or I2C.
The MSP430FG662x and MSP430FG642x include two complete USCI modules (n = 0 to 1).
9.12.11 Timer TA0
Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 supports multiple
capture/compares, PWM outputs, and interval timing (see Table 9-12). It also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 9-12. Timer TA0 Signal Connections
INPUT PIN NUMBER
PZ
ZCA, ZQW
DEVICE
INPUT
SIGNAL
34-P1.0
L5-P1.0
TA0CLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
34-P1.0
L5-P1.0
TA0CLK
TACLK
35-P1.1
M5-P1.1
TA0.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
36-P1.2
J6-P1.2
TA0.1
CCI1A
40-P1.6
J7-P1.6
TA0.1
CCI1B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
CCR1
TA0
TA1
OUTPUT PIN NUMBER
PZ
ZCA, ZQW
35-P1.1
M5-P1.1
36-P1.2
J6-P1.2
40-P1.6
J7-P1.6
TA0.0
TA0.1
37-P1.3
H6-P1.3
TA0.2
CCI2A
37-P1.3
H6-P1.3
41-P1.7
M7-P1.7
TA0.2
CCI2B
41-P1.7
M7-P1.7
DVSS
GND
DVCC
VCC
TA0.3
CCI3A
38-P1.4
M6-P1.4
DVSS
CCI3B
DVSS
GND
DVCC
VCC
TA0.4
CCI4A
39-P1.5
L6-P1.5
DVSS
CCI4B
DVSS
GND
DVCC
VCC
38-P1.4
39-P1.5
88
MODULE
INPUT
SIGNAL
M6-P1.4
L6-P1.5
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CCR2
CCR3
CCR4
TA2
TA3
TA4
TA0.2
TA0.3
TA0.4
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9.12.12 Timer TA1
Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 supports multiple
capture/compares, PWM outputs, and interval timing (see Table 9-13). It also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 9-13. Timer TA1 Signal Connections
INPUT PIN NUMBER
PZ
ZCA, ZQW
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
42-P3.0
L7-P3.0
TA1CLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
42-P3.0
L7-P3.0
TA1CLK
TACLK
43-P3.1
H7-P3.1
TA1.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
TA1.1
CCI1A
44-P3.2
45-P3.3
M8-P3.2
L8-P3.3
CBOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
TA1.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
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MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
CCR1
TA0
TA1
OUTPUT PIN NUMBER
PZ
ZCA, ZQW
43-P3.1
H7-P3.1
44-P3.2
M8-P3.2
TA1.0
TA1.1
DAC12_A
DAC12_0, DAC12_1
(internal)
45-P3.3
CCR2
TA2
L8-P3.3
TA1.2
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9.12.13 Timer TA2
Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA2 supports multiple
capture/compares, PWM outputs, and interval timing (see Table 9-14). It also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 9-14. Timer TA2 Signal Connections
INPUT PIN NUMBER
PZ
ZCA, ZQW
DEVICE
INPUT
SIGNAL
46-P3.4
J8-P3.4
TA2CLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
46-P3.4
J8-P3.4
TA2CLK
TACLK
47-P3.5
M9-P3.5
TA2.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
48-P3.6
49-P3.7
90
MODULE
INPUT
SIGNAL
L9-P3.6
TA2.1
CCI1A
CBOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
M10-P3.7
TA2.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
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MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
CCR0
CCR1
CCR2
TA0
TA1
TA2
OUTPUT PIN NUMBER
PZ
ZCA, ZQW
47-P3.5
M9-P3.5
48-P3.6
L9-P3.6
49-P3.7
M10-P3.7
TA2.0
TA2.1
TA2.2
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9.12.14 Timer TB0
Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 supports multiple
capture/compares, PWM outputs, and interval timing (see Table 9-15). It also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 9-15. Timer TB0 Signal Connections
INPUT PIN NUMBER
PZ
ZCA, ZQW
58-P8.0
P2MAPx(1)
J11-P8.0
P2MAPx(1)
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
TB0CLK
TB0CLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
NA
NA
OUTPUT PIN NUMBER
PZ
ZCA, ZQW
58-P8.0
P2MAPx(1)
J11-P8.0
P2MAPx(1)
TB0CLK
TB0CLK
50-P4.0
J9-P4.0
TB0.0
CCI0A
50-P4.0
J9-P4.0
P2MAPx(1)
P2MAPx(1)
TB0.0
CCI0B
P2MAPx(1)
P2MAPx(1)
DVSS
GND
51-P4.1
M11-P4.1
P2MAPx(1)
P2MAPx(1)
52-P4.2
L10-P4.2
P2MAPx(1)
P2MAPx(1)
53-P4.3
M12-P4.3
P2MAPx(1)
P2MAPx(1)
CCR0
TB0
TB0.0
DVCC
VCC
TB0.1
CCI1A
51-P4.1
M11-P4.1
TB0.1
CCI1B
P2MAPx(1)
P2MAPx(1)
DVSS
GND
CCR1
TB1
TB0.1
DVCC
VCC
TB0.2
CCI2A
52-P4.2
L10-P4.2
TB0.2
CCI2B
P2MAPx(1)
P2MAPx(1)
DVSS
GND
CCR2
TB2
TB0.2
DAC12_A
DAC12_0, DAC12_1
(internal)
DVCC
VCC
TB0.3
CCI3A
53-P4.3
M12-P4.3
TB0.3
CCI3B
P2MAPx(1)
P2MAPx(1)
DVSS
GND
DVCC
VCC
CCR3
TB3
TB0.3
54-P4.4
L12-P4.4
TB0.4
CCI4A
54-P4.4
L12-P4.4
P2MAPx(1)
P2MAPx(1)
TB0.4
CCI4B
P2MAPx(1)
P2MAPx(1)
DVSS
GND
DVCC
VCC
CCR4
TB4
TB0.4
55-P4.5
L11-P4.5
TB0.5
CCI5A
55-P4.5
L11-P4.5
P2MAPx(1)
P2MAPx(1)
TB0.5
CCI5B
P2MAPx(1)
P2MAPx(1)
DVSS
GND
DVCC
VCC
CCR5
TB5
TB0.5
56-P4.6
K11-P4.6
TB0.6
CCI6A
56-P4.6
K11-P4.6
P2MAPx(1)
P2MAPx(1)
TB0.6
CCI6B
P2MAPx(1)
P2MAPx(1)
DVSS
GND
DVCC
VCC
(1)
CCR6
TB6
TB0.6
Timer functions are selectable by the port mapping controller.
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9.12.15 Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
9.12.16 Signal Chain
All devices include all the building blocks to construct a complete signal chain. These blocks include two digitalto-analog converter (DAC) channels, two integrated operational amplifiers (OAs), a sigma-delta analog-to-digital
converter (CTSD16), and low-ohmic switches (GSW). Figure 9-2 shows the various signal chain blocks and their
interconnections in the overall system.
92
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NR
Device Boundary
P5.0/VREFBG/VeREF+
CTSD16
P6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2/OA0IP0
P6.3/CB3/A3/OA1IP0
P5.1/A4/DAC0
P5.6/A5/DAC1
A0
A1
A2
A3
A4
A5
Temp
Sense
REFON
A6
AVCC
Sense
+
A7
CTSD16REFS AND CTD16SC
BUF
VBAT
Sense
A8
+
AD0+
AD0-
+
PGA
BUF
-
AD1+
AD1-
OR
Request to
shared reference
+
Delta
Sigma
Bandgap voltage
from shared reference
~1.16 V nominal
-
-
AD2+
AD2AD3+
AD3VREFBG/VeREF+
AD4+
AD4-
DAC0
AD4+
AD4-
VREFBG/VeREF+
OA0
P6.2/CB2/A2/OA0IP0
PSW
4
PSW0
PSW1
PSW2
DAC12_A
DAC12_0
12 bit
DAC12AMP>0 & !DAC12OPS
OAM
PSW3
+
P6.4/CB4/AD0+/OA0O
DAC12AMP>0 & DAC12OPS
NSW
5
NSW0
-
P2.0/P2MAP0/DAC0
NSW1
NSW2
NSW3
P5.1/A4/DAC0
NSW4
P5.6/A5/DAC1
P6.5/CB5/AD0-/OA0IN0
GSW0
P6.6/CB6/AD1+/G0SW0
GSW1
P6.7/CB7/AD1-/G0SW1
PSW
OA1
4
PSW0
PSW1
PSW2
OAM
PSW3
+
P7.4/CB8/AD2+/OA1O
-
DAC12_1
12 bit
DAC12AMP>0 & !DAC12OPS
DAC12AMP>0 & DAC12OPS
NSW
5
NSW0
P2.1/P2MAP1/DAC1
NSW1
P6.3/CB3/A3/OA1IP0
NSW2
NSW3
NSW4
P7.5/CB9/AD2-/OA1IN0
GSW0
P7.6/CB10/AD3+/G1SW0
GSW1
P7.7/CB11/AD3-/G1SW1
Device Boundary
A. See the MSP430F5xx and MSP430F6xx Family User's Guide for additional module details.
Figure 9-2. Signal Chain
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9.12.16.1 CTSD16
The CTSD16 module integrates a single sigma-delta ADC with ten external inputs and four internal inputs. The
converter is designed with a fully differential analog input pair and a programmable gain amplifier input stage.
The converter is based on second-order over-sampling sigma-delta modulators and digital decimation filters. The
decimation filters are comb type filters with selectable oversampling ratios of up to 256.
The CTSD16 is proceeded by an analog multiplexer which is used for channel selection, followed by a unity gain
buffer stage useful when sampling high impedance sensors.
The CTSD16 can use as its reference the internal bandgap voltage from the REF module or an external
reference at the VeREF+ pin.
9.12.16.2 DAC12_A
The DAC12_A module is a 12-bit R-ladder voltage-output DAC. The DAC12_A can be used in 8-bit or 12-bit
mode, and can be used in conjunction with the DMA controller. When multiple DAC12_A modules are present,
they may be grouped together for synchronous operation. Two complete channels are available, DAC12_0 and
DAC12_1.
9.12.16.3 Operational Amplifiers (OA)
The device integrates two low-power operational amplifiers. The operational amplifiers can perform signal
conditioning of low-level analog signals before conversion by the ADC. Each operational amplifier can be
individually controlled by software.
9.12.16.4 Ground Switches (GSW)
The device integrates four low-ohmic switches to ground that are individually controllable in software. These can
switch in and out various components in the measurement system.
9.12.17 REF Voltage Reference
The reference module (REF) generates all of the critical reference voltages that can be used by the various
analog peripherals in the device.
9.12.18 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
9.12.19 LCD_B
The LCD_B driver generates the segment and common signals that are required to drive a liquid crystal display
(LCD). The LCD_B controller has dedicated data memories to hold segment drive information. Common and
segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux LCDs are supported.
The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is
possible to control the level of the LCD voltage, and thus contrast, by software. The module also provides an
automatic blinking capability for individual segments.
9.12.20 USB Universal Serial Bus
The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module
supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO,
PHY, and PLL. The PLL is highly flexible and can support a wide range of input clock frequencies. USB RAM,
when not used for USB communication, can be used by the system.
The USB module is only available on the MSP430FG662x devices.
9.12.21 LDO and PU Port
The integrated 3.3-V power system incorporates an integrated 3.3-V LDO regulator that allows the entire
MSP430 microcontroller to be powered from nominal 5-V LDOI when it is made available for the system.
Alternatively, the power system can supply power only to other components within the system, or it can be
unused altogether.
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The Port U pins (PU.0 and PU.1) function as general-purpose high-current I/O pins. These pins must be
configured together as either both inputs or both outputs. Port U is supplied by the LDOO rail. If the 3.3-V LDO is
not used in the system (disabled), the LDOO pin can be supplied externally.
The LDO-PWR module (LDO and PU port) is available only on the MSP430FG6426 and MSP430FG6425
devices.
9.12.22 Embedded Emulation Module (EEM) (L Version)
The EEM supports real-time in-system debugging. The L version of the EEM has the following features:
•
•
•
•
•
•
•
Eight hardware triggers or breakpoints on memory access.
Two hardware triggers or breakpoints on CPU register write access.
Up to ten hardware triggers can be combined to form complex triggers or breakpoints.
Two cycle counters
Sequencer
State storage
Clock control on module level
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9.13 Input/Output Diagrams
9.13.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
Figure 9-3 shows the port diagram. Table 9-16 summarizes the selection of the port function.
Pad Logic
S32...S39
LCDS32...LCDS39
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
D
Module X IN
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Figure 9-3. Port P1 (P1.0 to P1.7) Diagram
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Table 9-16. Port P1 (P1.0 to P1.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
P1.0 (I/O)
P1.0/TA0CLK/ACLK/S39
0
Timer TA0.TA0CLK
1
2
3
5
0
1
I: 0; O: 1
0
0
Timer TA0.CCI0A capture input
0
1
0
Timer TA0.0 output
1
1
0
S38
X
X
1
I: 0; O: 1
0
0
Timer TA0.CCI1A capture input
0
1
0
Timer TA0.1 output
1
1
0
S37
X
X
1
I: 0; O: 1
0
0
Timer TA0.CCI2A capture input
0
1
0
Timer TA0.2 output
1
1
0
X
X
1
I: 0; O: 1
0
0
Timer TA0.CCI3A capture input
0
1
0
Timer TA0.3 output
1
1
0
S35
X
X
1
I: 0; O: 1
0
0
Timer TA0.CCI4A capture input
0
1
0
Timer TA0.4 output
1
1
0
S34
X
X
1
I: 0; O: 1
0
0
Timer TA0.CCI1B capture input
0
1
0
Timer TA0.1 output
1
1
0
S33
X
X
1
I: 0; O: 1
0
0
Timer TA0.CCI2B capture input
0
1
0
Timer TA0.2 output
1
1
0
S32
X
X
1
P1.6 (I/O)
P1.6/TA0.1/S33
6
P1.7 (I/O)
P1.7/TA0.2/S32
(1)
7
0
1
P1.5 (I/O)
P1.5/TA0.4/S34
0
1
X
P1.4 (I/O)
4
0
0
1
S36
P1.4/TA0.3/S35
I: 0; O: 1
X
P1.3 (I/O)
P1.3/TA0.2/S36
LCDS32 to
LCDS39
S39
P1.2 (I/O)
P1.2/TA0.1/S37
P1SEL.x
ACLK
P1.1 (I/O)
P1.1/TA0.0/S38
P1DIR.x
X= don't care
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9.13.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
Figure 9-4 shows the port diagram. Table 9-17 summarizes the selection of the port function.
0
Dvss
1
From DAC12_A
2
Pad Logic
0 if DAC12AMPx=0
1 if DAC12AMPx=1
2 if DAC12AMPx>1
to LCD_B
from LCD_B
P2REN.x
P2DIR.x
0
P2OUT.x
0
1
1
Direction
0: Input
1: Output
1
From Port Mapping
DAC12AMPx>0
DVSS
DVCC
0
1
DAC12OPS
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
From Port Mapping
P2.0/P2MAP0/DAC0
P2.1/P2MAP1/DAC1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4/R03
P2.5/P2MAP5
P2.6/P2MAP6/LCDREF/R13
P2.7/P2MAP7/R23
EN
To Port Mapping
D
P2IE.x
EN
P2IRQ.x
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Figure 9-4. Port P2 (P2.0 to P2.7) Diagram
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Table 9-17. Port P2 (P2.0 to P2.7) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.0 (I/O)
P2.0/P2MAP0/DAC0
0
Mapped secondary digital
function
DAC0
P2.1 (I/O)
P2.1/P2MAP1/DAC1
1
Mapped secondary digital
function
DAC1
P2.2 (I/O)
P2.2/P2MAP2
2
P2.3/P2MAP3
3
Mapped secondary digital
function
P2.3 (I/O)
Mapped secondary digital
function
P2.4 (I/O)
P2.4/P2MAP4/R03
4
5
6
(1)
P2MAPx
X
1
≤ 19
= 31
X
X
I: 0; O: 1
0
X
1
≤ 19
= 31
X
X
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
DAC12OPS
DAC12AMPx
X
0
X
0
≤ 19
≤ 19
1
>1
X
0
X
0
1
>1
X
0
X
0
X
0
X
0
X
0
X
1
≤ 19
X
0
R03
X
1
= 31
X
0
I: 0; O: 1
0
X
0
X
1
X
0
I: 0; O: 1
0
X
0
X
1
≤ 19
X
0
= 31
X
0
X
0
Mapped secondary digital
function
Mapped secondary digital
function
≤ 19
X
1
I: 0; O: 1
0
Mapped secondary digital
function
X
1
≤ 19
X
0
R23
X
1
= 31
X
0
P2.7 (I/O)
7
0
0
LCDREF/R13
P2.7/P2MAP7/R23
P2SEL.x
I: 0; O: 1
P2.6 (I/O)
P2.6/P2MAP6/LCDREF/R13
P2DIR.x
I: 0; O: 1
Mapped secondary digital
function
P2.5 (I/O
P2.5/P2MAP5
CONTROL BITS OR SIGNALS(1)
X= Don't care
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9.13.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
Figure 9-5 shows the port diagram. Table 9-18 summarizes the selection of the port function.
Pad Logic
S24...S31
LCDS24...LCDS31
P3REN.x
P3DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3OUT.x
DVSS
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
P3.7/TA2.2/S24
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
Bus
Keeper
EN
D
Module X IN
P3IE.x
EN
P3IRQ.x
Q
P3IFG.x
P3SEL.x
P3IES.x
Set
Interrupt
Edge
Select
Figure 9-5. Port P3 (P3.0 to P3.7) Diagram
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Table 9-18. Port P3 (P3.0 to P3.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
P3.0 (I/O)
P3.0/TA1CLK/CBOUT/S31
0
1
2
0
0
0
1
0
CBOUT
1
1
0
S31
X
X
1
I: 0; O: 1
0
0
Timer TA1.CCI0A capture input
0
1
0
Timer TA1.0 output
1
1
0
S30
X
X
1
I: 0; O: 1
0
0
Timer TA1.CCI1A capture input
0
1
0
Timer TA1.1 output
1
1
0
S29
X
X
1
I: 0; O: 1
0
0
Timer TA1.CCI2A capture input
0
1
0
Timer TA1.2 output
1
1
0
P3.3 (I/O)
P3.3/TA1.2/S28
3
S28
X
X
1
I: 0; O: 1
0
0
Timer TA2.TA2CLK
0
1
0
SMCLK
1
1
0
S27
X
X
1
P3.4 (I/O)
P3.4/TA2CLK/SMCLK/S27
4
P3.5 (I/O)
P3.5/TA2.0/S26
5
I: 0; O: 1
0
0
Timer TA2.CCI0A capture input
0
1
0
Timer TA2.0 output
1
1
0
S26
X
X
1
I: 0; O: 1
0
0
Timer TA2.CCI1A capture input
0
1
0
Timer TA2.1 output
1
1
1
S25
X
X
1
I: 0; O: 1
0
0
Timer TA2.CCI2A capture input
0
1
0
Timer TA2.2 output
1
1
0
S24
X
X
1
P3.6 (I/O)
P3.6/TA2.1/S25
6
P3.7 (I/O)
P3.7/TA2.2/S24
(1)
7
LCDS24 to
LCDS31
I: 0; O: 1
P3.2 (I/O)
P3.2/TA1.1/S29
P3SEL.x
Timer TA1.TA1CLK
P3.1 (I/O)
P3.1/TA1.0/S30
P3DIR.x
X= don't care
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9.13.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
Figure 9-6 shows the port diagram. Table 9-19 summarizes the selection of the port function.
Pad Logic
S16...S23
LCDS16...LCDS23
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
Bus
Keeper
EN
Module X IN
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4.0/TB0.0/S23
P4.1/TB0.1/S22
P4.2/TB0.2/S21
P4.3/TB0.3/S20
P4.4/TB0.4/S19
P4.5/TB0.5/S18
P4.6/TB0.6/S17
P4.7/TB0OUTH/SVMOUT/S16
D
P4IE.x
EN
P4IRQ.x
Q
P4IFG.x
P4SEL.x
P4IES.x
Set
Interrupt
Edge
Select
Figure 9-6. Port P4 (P4.0 to P4.7) Diagram
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Table 9-19. Port P4 (P4.0 to P4.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P4.x)
x
FUNCTION
P4.0 (I/O)
P4.0/TB0.0/S23
0
1
0
0
0
1
0
Timer TB0.0 output(2)
1
1
0
S23
X
X
1
0
I: 0; O: 1
0
Timer TB0.CCI1A capture input
0
1
0
Timer TB0.1 output(2)
1
1
0
X
X
1
I: 0; O: 1
0
0
P4.2 (I/O)
2
Timer TB0.CCI2A capture input
0
1
0
Timer TB0.2 output(2)
1
1
0
S21
X
X
1
I: 0; O: 1
0
0
Timer TB0.CCI3A capture input
0
1
0
Timer TB0.3 output(2)
1
1
0
P4.3 (I/O)
P4.3/TB0.3/S20
3
S20
X
X
1
I: 0; O: 1
0
0
Timer TB0.CCI4A capture input
0
1
0
Timer TB0.4 output(2)
1
1
0
S19
X
X
1
0
P4.4 (I/O)
P4.4/TB0.4/S19
4
P4.5 (I/O)
P4.5/TB0.5/S18
5
I: 0; O: 1
0
Timer TB0.CCI5A capture input
0
1
0
Timer TB0.5 output(2)
1
1
0
X
X
1
I: 0; O: 1
0
0
S18
P4.6 (I/O)
P4.6/TB0.6/S17
6
Timer TB0.CCI6A capture input
0
1
0
Timer TB0.6 output(2)
1
1
0
S17
X
X
1
I: 0; O: 1
0
0
Timer TB0.TB0OUTH
0
1
0
SVMOUT
1
1
0
S16
X
X
1
P4.7 (I/O)
P4.7/TB0OUTH/ SVMOUT/S16
(1)
(2)
7
LCDS16 to
LCDS23
I: 0; O: 1
S22
P4.2/TB0.2/S21
P4SEL.x
Timer TB0.CCI0A capture input
P4.1 (I/O)
P4.1/TB0.1/S22
P4DIR.x
X= don't care
Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance.
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9.13.5 Port P5 (P5.0) Input/Output With Schmitt Trigger
Figure 9-7 shows the port diagram. Table 9-20 summarizes the selection of the port function.
Pad Logic
To/From
Reference
P5REN.x
P5DIR.x
DVSS
0
DVCC
1
1
0
1
P5OUT.x
0
Module X OUT
1
P5.0/VREFBG/VeREF+
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
Module X IN
D
Figure 9-7. Port P5 (P5.0) Diagram
Table 9-20. Port P5 (P5.0) Pin Functions
PIN NAME (P5.x)
x
FUNCTION
P5.0
P5.0/VREFBG/VeREF+
(1)
(2)
(3)
(4)
(5)
(6)
104
0
(I/O)(2)
CONTROL BITS OR SIGNALS(1)
P5DIR.x
P5SEL.x
REFOUT
REFON(5)
CTSD16REFS(6)
I: 0; O: 1
0
X
X
X
VeREF+(3)
X
1
0
X
0
VREFBG(4)
X
1
1
1
1
X = Don't care
Default condition
Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the CTSD16 or DAC.
Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The internal reference voltage signal, VREFBG, is available at the pin.
If a module is requesting a reference then REFON need not be set to 1 for VREFBG to be selected on P5.0.
If CTSD16 is active, this bit must be set as shown in the table. Otherwise if set to 1, it will force VREFBG to be selected regardless of
REFOUT setting and if P5SEL.x is set to 0 it will cause possible contention on the I/O.
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9.13.6 Port P5 (P5.1 and P5.6) Input/Output With Schmitt Trigger
Figure 9-8 shows the port diagram. Table 9-21 summarizes the selection of the port function.
0
Dvss
1
From DAC12_A
2
Pad Logic
0 if DAC12AMPx=0
1 if DAC12AMPx=1
2 if DAC12AMPx>1
To ADC
INCHx = y
DAC12AMPx>0
DAC12OPS
P5REN.x
DVSS
0
DVCC
1
1
P5DIR.x
P5OUT.x
P5.1/A4/DAC0
P5.6/A5/DAC1
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
Figure 9-8. Port P5 (P5.1 and P5.6) Diagram
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 9-21. Port P5 (P5.1 and P5.6) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P5DIR.x
P5SEL.x
DAC12OPS
DAC12AMPx
I: 0; O: 1
0
X
0
A4(2) (3)
X
1
X
0
DAC0
X
X
0
>1
P5.1(I/O)
P5.1/A4/DAC0
1
P5.6(I/O)
P5.6/A5/DAC1
(1)
(2)
(3)
106
1
CONTROL BITS OR SIGNALS(1)
I: 0; O: 1
0
X
0
A5(2) (3)
X
1
X
0
DAC1
X
X
0
>1
X = Don't care
Setting the P5SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
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9.13.7 Port P5 (P5.3 to P5.5, P5.7) Input/Output With Schmitt Trigger
Figure 9-9 shows the port diagram. Table 9-22 summarizes the selection of the port function.
Pad Logic
S40...S42
LCDS40...LCDS42
P5REN.x
P5DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P5OUT.x
DVSS
P5.3/COM1/S42
P5.4/COM2/S41
P5.5/COM3/S40
P5.7/DMAE0/RTCCLK
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
Module X IN
D
Figure 9-9. Port P5 (P5.3 to P5.5 and P5.7) Diagram
Table 9-22. Port P5 (P5.3 to P5.5, P5.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5.3 (I/O)
P5.3/COM1/S42
3
COM1
S42
P5.4 (I/O)
P5.4/COM2/S41
4
COM2
S41
P5.5 (I/O)
P5.5/COM3/S40
5
COM3
S40
7
P5SEL.x
I: 0; O: 1
0
0
X
1
X
1
X
0
I: 0; O: 1
0
0
X
1
X
1
X
0
I: 0; O: 1
0
0
X
1
X
X
0
1
I: 0; O: 1
0
na
DMAE0
0
1
na
RTCCLK
1
1
na
P5.7 (I/O)
P5.7/DMAE0/RTCCLK
LCDS40 to
LCDS42
P5DIR.x
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9.13.8 Port P6 (P6.0 to P6.1) Input/Output With Schmitt Trigger
Figure 9-10 shows the port diagram. Table 9-23 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
P6REN.x
DVSS
0
DVCC
1
1
P6DIR.x
P6OUT.x
P6.0/CB0/A0
P6.1/CB1/A1
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
Figure 9-10. Port P6 (P6.0 to P6.1) Diagram
Table 9-23. Port P6 (P6.0 to P6.1) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL.x
CBPD.x
I: 0; O: 1
0
0
CB0
X
X
1
A0(2) (3)
X
1
X
I: 0; O: 1
0
0
CB1
X
X
1
A1(2) (3)
X
1
X
P6.0 (I/O)
P6.0/CB0/A0
0
P6.1 (I/O)
P6.1/CB1/A1
(1)
(2)
(3)
108
1
CONTROL BITS OR SIGNALS(1)
X= Don't care
Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
9.13.9 Port P6 (P6.2 and P6.3) Input/Output With Schmitt Trigger
Figure 9-11 shows the port diagram. Table 9-24 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
P6REN.x
DVSS
0
DVCC
1
1
P6DIR.x
P6.2/CB2/A2/OA0IP0
P6.3/CB3/A3/OA1IP1
P6OUT.x
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OAx
-
Figure 9-11. Port P6 (P6.2 and P6.3) Diagram
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Table 9-24. Port P6 (P6.2 and P6.3) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6.2 (I/O)
P6.2/CB2/A2/OA0IP0
P6.3/CB3/A3/OA1IP0
(1)
(2)
(3)
110
2
3
CONTROL BITS OR SIGNALS(1)
P6DIR.x
P6SEL.x(3)
CBPD.x(3)
0
I: 0; O: 1
0
CB2
X
X
1
A2 (2)
X
1
X
OA0IP0(3)
X
1
X
P6.2 (I/O)
I: 0; O: 1
0
0
CB3
X
X
1
A3 (3)
X
1
X
OA1IP0(3)
X
1
X
X = Don't care
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting the P6SEL.x bit or CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
9.13.10 Port P6 (P6.4) Input/Output With Schmitt Trigger
Figure 9-12 shows the port diagram. Table 9-25 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
OAMx
P6REN.x
DVSS
0
DVCC
1
1
P6DIR.x
P6.4/CB4/AD0+/OA0O
P6OUT.x
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OA0
-
Figure 9-12. Port P6 (P6.4) Diagram
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Table 9-25. Port P6 (P6.4) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL.x(3)
CBPD.x(3)
OAMx
I: 0; O: 1
0
0
0(4)
CB4
X
X
1
0(4)
AD0+ (2)
X
1
X
0(4)
OA0O
X
X
X
= 1(4)
P6.4 (I/O)
P6.4/CB4/AD0+/OA0O
(1)
(2)
(3)
(4)
112
4
CONTROL BITS OR SIGNALS(1)
X = Don't care
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting the P6SEL.x bit, the CBPD.x bit, or the OAMx bit disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals.
Setting OAMx = 0 disables the operational amplifier and its output is high impedance. Setting OAMx = 1 enables the operational
amplifier output. Because the operational amplifier output is shared with the ADC channel, selection of the respective ADC channel
allows for direct measurement of the output voltage of the amplifier.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
9.13.11 Port P6 (P6.5) Input/Output With Schmitt Trigger
Figure 9-13 shows the port diagram. Table 9-26 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
P6REN.x
DVSS
0
DVCC
1
1
P6DIR.x
P6.5/CB5/AD0-/OA0IN0
P6OUT.x
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OA0
-
Figure 9-13. Port P6 (P6.5) Diagram
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Table 9-26. Port P6 (P6.5) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6.5 (I/O)
P6.5/CB5/AD0-/OA0IN0
(1)
(2)
(3)
114
5
CONTROL BITS OR SIGNALS(1)
P6DIR.x
P6SEL.x(3)
CBPD.x(3)
0
I: 0; O: 1
0
CB5
X
X
1
AD0- (2)
X
1
X
OA0IN0(3)
X
1
X
X = Don't care
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting the P6SEL.x bit or CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
9.13.12 Port P6 (P6.6) Input/Output With Schmitt Trigger
Figure 9-14 shows the port diagram. Table 9-27 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
GSW0
P6REN.x
DVSS
0
DVCC
1
1
P6DIR.x
P6.6/CB6/AD1+/G0SW0
P6OUT.x
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OA0
-
GSW0
GSW1
to P6.7
Figure 9-14. Port P6 (P6.6) Diagram
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Table 9-27. Port P6 (P6.6) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6.6 (I/O)
P6.6/CB6/AD1+/G0SW0
(1)
(2)
(3)
(4)
116
6
CONTROL BITS OR SIGNALS(1)
P6DIR.x
P6SEL.x(3)
CBPD.x(3)
GSW0(3)
I: 0; O: 1
0
0
0
CB6
X
X
1
0
AD1+ (2)
X
1
X
0
G0SW0(4)
X
X
X
1
X = Don't care
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting the P6SEL.x bit, the CBPD.x bit, or the GSW0 bit disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals.
Setting GSW0 = 1 closes the switch and forces the pin to be switched to ground. All switches are independent of each other, so
different settings can impose different voltages on the pin. Application must ensure there are no conflicts.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
9.13.13 Port P6 (P6.7) Input/Output With Schmitt Trigger
Figure 9-15 shows the port diagram. Table 9-28 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
GSW1
P6REN.x
DVSS
0
DVCC
1
1
P6DIR.x
P6.7/CB7/AD1-/G0SW1
P6OUT.x
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OA0
-
GSW0
to P6.6
GSW1
Figure 9-15. Port P6 (P6.7) Diagram
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Table 9-28. Port P6 (P6.7) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6.7 (I/O)
P6.7/CB7/AD1-/G0SW1
(1)
(2)
(3)
118
7
CONTROL BITS OR SIGNALS(1)
P6DIR.x
P6SEL.x(3)
CBPD.x(3)
GSW1(3)
I: 0; O: 1
0
0
0
CB7
X
X
1
0
AD1- (2)
X
1
X
0
G0SW1(3)
X
X
X
1
X = Don't care
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting GSW1 = 1 closes the switch and forces the pin to be switched to ground. All switches are independent of each other, so
different settings can impose different voltages on the pin. Application must ensure there are no conflicts.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
9.13.14 Port P7 (P7.2 and P7.3) Input/Output With Schmitt Trigger
Figure 9-16 and Figure 9-17 show the port diagrams. Table 9-29 summarizes the selection of the port function.
Pad Logic
To XT2
P7REN.2
P7DIR.2
DVSS
0
DVCC
1
1
0
1
P7OUT.2
P7.2/XT2IN
P7DS.2
0: Low drive
1: High drive
P7SEL.2
P7IN.2
Bus
Keeper
Figure 9-16. Port P7 (P7.2) Diagram
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Pad Logic
To XT2
P7REN.3
P7DIR.3
DVSS
0
DVCC
1
1
0
1
P7OUT.3
P7SEL.2
P7.3/XT2OUT
P7DS.3
0: Low drive
1: High drive
XT2BYPASS
P7SEL.3
P7IN.3
Bus
Keeper
Figure 9-17. Port P7 (P7.3) Diagram
Table 9-29. Port P7 (P7.2 and P7.3) Pin Functions
PIN NAME (P7.x)
x
FUNCTION
P7.2 (I/O)
P7.2/XT2IN
2
3
(3)
120
P7SEL.3
XT2BYPASS
I: 0; O: 1
0
X
X
X
1
X
0
XT2IN bypass mode(2)
X
1
X
1
I: 0; O: 1
0
X
X
X
1
X
0
X
1
X
1
XT2OUT crystal mode(3)
P7.3
(1)
(2)
P7SEL.2
XT2IN crystal mode(2)
P7.3 (I/O)
P7.3/XT2OUT
CONTROL BITS OR SIGNALS(1)
P7DIR.x
(I/O)(3)
X= Don't care
Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal
mode or bypass mode.
Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as
general-purpose I/O.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
9.13.15 Port P7 (P7.4) Input/Output With Schmitt Trigger
Figure 9-18 shows the port diagram. Table 9-30 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
OAMx
P7REN.x
DVSS
0
DVCC
1
1
P7DIR.x
P7.4/CB8/AD2+/OA1O
P7OUT.x
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
+
OA1
-
Figure 9-18. Port P7 (P7.4) Diagram
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Table 9-30. Port P7 (P7.4) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P7SEL.x(3)
CBPD.x(3)
OAMx(3)
I: 0; O: 1
0
0
0(3)
CB8
X
X
1
0(3)
AD2+ (2)
X
1
X
0(3)
OA1O
X
X
X
1(3)
P7.4 (I/O)
P7.4/CB8/AD2+/OA1O
(1)
(2)
(3)
122
4
CONTROL BITS OR SIGNALS(1)
X = Don't care
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting OAMx = 0 disables the operational amplifier and its output is high impedance. Setting OAMx = 1 enables the operational
amplifier output. Because the operational amplifier output is shared with the ADC channel, selection of the respective ADC channel
allows for direct measurement of the output voltage of the amplifier.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
9.13.16 Port P7 (P7.5) Input/Output With Schmitt Trigger
Figure 9-19 shows the port diagram. Table 9-31 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
P7REN.x
DVSS
0
DVCC
1
1
P7DIR.x
P7.5/CB9/AD2-/OA1IN0
P7OUT.x
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
+
OA1
-
Figure 9-19. Port P7 (P7.5) Diagram
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Table 9-31. Port P7 (P7.5) Pin Functions
PIN NAME (P7.x)
x
FUNCTION
P7.5 (I/O)
P7.5/CB9/AD2-/OAIN0
(1)
(2)
(3)
124
5
CONTROL BITS OR SIGNALS(1)
P7DIR.x
P7SEL.x(3)
CBPD.x(3)
0
I: 0; O: 1
0
CB9
X
X
1
AD2- (2)
X
1
X
OAIN0(3)
X
1
X
X = Don't care
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting the P7SEL.x bit or the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
9.13.17 Port P7 (P7.6) Input/Output With Schmitt Trigger
Figure 9-20 shows the port diagram. Table 9-32 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
GSW0
P7REN.x
DVSS
0
DVCC
1
1
P7DIR.x
P7.6/CB10/AD3+/G1SW0
P7OUT.x
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
+
OA1
-
GSW0
GSW1
to P7.7
Figure 9-20. Port P7 (P7.6) Diagram
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 9-32. Port P7 (P7.6) Pin Functions
PIN NAME (P7.x)
x
FUNCTION
P7.6 (I/O)
P7.6/CB10/AD3+/G1SW0
(1)
(2)
(3)
(4)
126
6
CONTROL BITS OR SIGNALS(1)
P6DIR.x
P7SEL.x(3)
CBPD.x(3)
GSW0(3)
0
I: 0; O: 1
0
0
CB10
X
X
1
0
AD3+ (2)
X
1
X
0
G1SW0(4)
X
X
X
1
X = Don't care
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting the P7SEL.x bit, the CBPD.x bit, or the GSW0 disables the output driver and the input Schmitt trigger to prevent parasitic cross
currents when applying analog signals.
Setting GSW0 = 1 closes the switch and forces the pin to be switched to ground. All switches are independent of each other, so
different settings can impose different voltages on the pin. Application must ensure there are no conflicts.
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9.13.18 Port P7 (P7.7) Input/Output With Schmitt Trigger
Figure 9-21 shows the port diagram. Table 9-33 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
GSW1
P7REN.x
DVSS
0
DVCC
1
1
P7DIR.x
P7.7/CB11/AD3-/G1SW1
P7OUT.x
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
+
OA1
-
GSW0
to P7.6
GSW1
Figure 9-21. Port P7 (P7.7) Diagram
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Table 9-33. Port P7 (P7.7) Pin Functions
PIN NAME (P7.x)
x
FUNCTION
P7.7 (I/O)
P7.7/CB11/AD3-/G1SW1
(1)
(2)
(3)
(4)
128
7
CONTROL BITS OR SIGNALS(1)
P6DIR.x
P7SEL.x(3)
CBPD.x(3)
GSW1(3)
I: 0; O: 1
0
0
0
CB11
X
X
1
0
AD3- (2)
X
1
X
0
G1SW1(4)
X
X
X
1
X = Don't care
The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
Setting the P7SEL.x bit, the CBPD.x bit, or the GSW1 bit disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals.
Setting GSW1 = 1 closes the switch and forces the pin to be switched to ground. All switches are independent of each other, so
different settings can impose different voltages on the pin. Application must ensure there are no conflicts.
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9.13.19 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
Figure 9-22 shows the port diagram. Table 9-34 summarizes the selection of the port function.
Pad Logic
S8...S15
LCDS8...LCDS15
P8REN.x
P8DIR.x
0
From module
1
P8OUT.x
0
Module X OUT
1
DVSS
0
DVCC
1
Direction
0: Input
1: Output
P8DS.x
0: Low drive
1: High drive
P8SEL.x
P8IN.x
Bus
Keeper
EN
Module X IN
1
P8.0/TB0CLK/S15
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
P8.4/UCB1CLK/UCA1STE/S11
P8.5/UCB1SIMO//UCB1SDA/S10
P8.6/UCB1SOMI/UCB1SCL/S9
P8.7/S8
D
Figure 9-22. Port P8 (P8.0 to P8.7) Diagram
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Table 9-34. Port P8 (P8.0 to P8.7) Pin Functions
PIN NAME (P9.x)
x
FUNCTION
P8DIR.x
P8SEL.x
LCDS8 to 16
I: 0; O: 1
0
0
Timer TB0.TB0CLK clock input
0
1
0
S15
X
X
1
I: 0; O: 1
0
0
X
1
0
P8.0 (I/O)
P8.0/TB0CLK/S15
0
P8.1 (I/O)
P8.1/UCB1STE/UCA1CLK/S14
1
UCB1STE/UCA1CLK
S14
X
X
1
I: 0; O: 1
0
0
UCA1TXD/UCA1SIMO
X
1
0
S13
X
X
1
I: 0; O: 1
0
0
P8.2 (I/O)
P8.2/UCA1TXD/UCA1SIMO/S13
2
P8.3 (I/O)
P8.3/UCA1RXD/UCA1SOMI/S12
3
UCA1RXD/UCA1SOMI
X
1
0
S12
X
X
1
I: 0; O: 1
0
0
UCB1CLK/UCA1STE
X
1
0
S11
X
X
1
P8.4 (I/O)
P8.4/UCB1CLK/UCA1STE/S11
4
P8.5 (I/O)
P8.5/UCB1SIMO/UCB1SDA/S10
5
I: 0; O: 1
0
0
UCB1SIMO/UCB1SDA
X
1
0
S10
X
X
1
I: 0; O: 1
0
0
UCB1SOMI/UCB1SCL
X
1
0
S9
X
X
1
I: 0; O: 1
0
0
X
X
1
P8.6 (I/O)
P8.6/UCB1SOMI/UCB1SCL/S9
P8.7/S8
(1)
130
6
7
CONTROL BITS OR SIGNALS(1)
P8.7 (I/O)
S8
X= don't care
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9.13.20 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
Figure 9-23 shows the port diagram. Table 9-35 summarizes the selection of the port function.
Pad Logic
S0...S7
LCDS0...LCDS7
P9REN.x
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
P9DIR.x
P9OUT.x
P9.0/S7
P9.1/S6
P9.2/S5
P9.3/S4
P9.4/S3
P9.5/S2
P9.6/S1
P9.7/S0
P9DS.x
0: Low drive
1: High drive
P9IN.x
Bus
Keeper
Figure 9-23. Port P9 (P9.0 to P9.7) Diagram
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Table 9-35. Port P9 (P9.0 to P9.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P9.x)
P9.0/S7
x
0
P9.1/S6
1
P9.2/S5
2
P9.3/S4
P9.4/S3
P9.5/S2
P9.6/S1
P9.7/S0
(1)
132
3
4
5
6
7
FUNCTION
P9.0 (I/O)
S7
P9.1 (I/O)
S6
P9.2 (I/O)
S5
P9.3 (I/O)
S4
P9.4 (I/O)
S3
P9.5 (I/O)
S2
P9.6 (I/O)
S1
P9.7 (I/O)
S0
P9SEL.x
LCDS0 to
LCDS7
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
P9DIR.x
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X= don't care
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
9.13.21 Port U (PU.0/DP, PU.1/DM, PUR) USB Ports for MSP430FG662x
Figure 9-24 shows the port diagram. Table 9-36 and Table 9-37 summarize the port function selection.
PUSEL
PUOPE
0
USB output enable
1
PUOUT0
0
USB DP output
1
VUSB
VSSU
Pad Logic
PU.0/DP
PUIN0
USB DP input
PUIPE
PUIN1
USB DM input
PUOUT1
0
USB DM output
1
PU.1/DM
VUSB
VSSU
Pad Logic
PUREN
PUR
“1 ”
PUSEL
PURIN
Figure 9-24. Port U (PU.0 and PU.1) Diagram
Table 9-36. Port U (PU.0/DP, PU.1/DM) Output Functions for MSP430FG662x
CONTROL BITS
PIN NAME
FUNCTION
PUSEL
PUDIR
PUOUT1
PUOUT0
PU.1/DM
PU.0/DP
0
0
X
X
Hi-Z
Hi-Z
Outputs off
0
1
0
0
0
0
Outputs enabled
0
1
0
1
0
1
Outputs enabled
0
1
1
0
1
0
Outputs enabled
0
1
1
1
1
1
Outputs enabled
1
X
X
X
DM
DP
Direction set by USB module
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Table 9-37. Port U (PUR) Input Functions
CONTROL BITS
FUNCTION
PUSEL
PUREN
0
0
Input disabled
Pullup disabled
0
1
Input disabled
Pullup enabled
1
0
Input enabled
Pullup disabled
1
1
Input enabled
Pullup enabled
9.13.22 Port J (J.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 9-25 shows the port diagram. Table 9-38 summarizes the selection of the port function.
Pad Logic
PJREN.0
PJDIR.0
0
DVCC
1
PJOUT.0
0
From JTAG
1
DVSS
0
DVCC
1
1
PJDS.0
0: Low drive
1: High drive
From JTAG
PJ.0/TDO
PJIN.0
EN
D
Figure 9-25. Port PJ (PJ.0) Diagram
134
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9.13.23 Port J (J.1 to J.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Figure 9-26 shows the port diagram. Table 9-38 summarizes the selection of the port function.
Pad Logic
PJREN.x
PJDIR.x
0
DVSS
1
PJOUT.x
0
From JTAG
1
DVSS
0
DVCC
1
1
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJDS.x
0: Low drive
1: High drive
From JTAG
PJIN.x
EN
To JTAG
D
Figure 9-26. Port PJ (PJ.1 to PJ.3) Diagram
Table 9-38. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
x
CONTROL BITS
OR SIGNALS(1)
FUNCTION
PJDIR.x
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
(1)
(2)
(3)
(4)
0
1
2
3
PJ.0
(I/O)(2)
I: 0; O: 1
TDO(3)
PJ.1
X
(I/O)(2)
I: 0; O: 1
TDI/TCLK(3) (4)
PJ.2
X
(I/O)(2)
I: 0; O: 1
TMS(3) (4)
PJ.3
X
(I/O)(2)
I: 0; O: 1
TCK(3) (4)
X
X= don't care
Default condition
The pin direction is controlled by the JTAG module.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
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9.14 Device Descriptors
Table 9-39 summarizes the contents of the device descriptor tag-length-value (TLV) structure.
Table 9-39. Device Descriptor Table
DESCRIPTION
Info Block
Die Record
CTSD16 Calibration
VALUE
ADDRESS
SIZE
(bytes)
FG6626
FG6625
FG6426
FG6425
Info length
01A00h
1
06h
06h
06h
06h
CRC length
01A01h
1
06h
06h
06h
06h
CRC value
01A02h
2
Per unit
Per unit
Per unit
Per unit
Device ID
01A04h
2
8234h
8235h
8236h
8237h
Hardware revision
01A06h
1
Per unit
Per unit
Per unit
Per unit
Firmware revision
01A07h
1
Per unit
Per unit
Per unit
Per unit
Die record tag
01A08h
1
08h
08h
08h
08h
Die record length
01A09h
1
0Ah
0Ah
0Ah
0Ah
Lot/wafer ID
01A0Ah
4
Per unit
Per unit
Per unit
Per unit
Die X position
01A0Eh
2
Per unit
Per unit
Per unit
Per unit
Die Y position
01A10h
2
Per unit
Per unit
Per unit
Per unit
Test results
01A12h
2
Per unit
Per unit
Per unit
Per unit
CTSD16 calibration tag
01A14h
1
1Dh
1Dh
1Dh
1Dh
CTSD16 calibration length
01A15h
1
0Ch
0Ch
0Ch
0Ch
CTSD16 gain factor gain = 1
01A16h
2
Per unit
Per unit
Per unit
Per unit
CTSD16 gain factor gain = 16
01A18h
2
Per unit
Per unit
Per unit
Per unit
CTSD16 offset gain = 1
01A1Ah
2
Per unit
Per unit
Per unit
Per unit
CTSD16 offset gain = 16
01A1Ch
2
Per unit
Per unit
Per unit
Per unit
CTSD16 internal reference
temperature sensor 30°C
01A1Eh
2
Per unit
Per unit
Per unit
Per unit
CTSD16 internal reference
temperature sensor 85°C
01A20h
2
Per unit
Per unit
Per unit
Per unit
9.15 Memory
Table 9-40 summarizes the memory organization for all devices.
Table 9-40. Memory Organization
VALUE(1) (2)
Memory (flash)
Main: interrupt vector
MSP430FG6626
MSP430FG6625
MSP430FG6426
MSP430FG6425
Total Size
128KB
00FFFFh to 00FF80h
64KB
00FFFFh to 00FF80h
128KB
00FFFFh to 00FF80h
64KB
00FFFFh to 00FF80h
Bank 3
32KB
0243FFh to 01C400h
NA
32KB
0243FFh to 01C400h
NA
Bank 2
32KB
01C3FFh to 014400h
NA
32KB
01C3FFh to 014400h
NA
Bank 1
32KB
0143FFh to 00C400h
32KB
0143FFh to 00C400h
32KB
0143FFh to 00C400h
32KB
0143FFh to 00C400h
Bank 0
32KB
00C3FFh to 004400h
32KB
00C3FFh to 004400h
32KB
00C3FFh to 004400h
32KB
00C3FFh to 004400h
Sector 3
2KB
0043FFh to 003C00h
2KB
0043FFh to 003C00h
2KB
0043FFh to 003C00h
2KB
0043FFh to 003C00h
Sector 2
2KB
003BFFh to 003400h
2KB
003BFFh to 003400h
2KB
003BFFh to 003400h
2KB
003BFFh to 003400h
Sector 1
2KB
0033FFh to 002C00h
2KB
0033FFh to 002C00h
2KB
0033FFh to 002C00h
2KB
0033FFh to 002C00h
Main: code memory
RAM
136
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Table 9-40. Memory Organization (continued)
VALUE(1) (2)
MSP430FG6626
MSP430FG6625
MSP430FG6426
MSP430FG6425
Sector 0
2KB
002BFFh to 002400h
2KB
002BFFh to 002400h
2KB
002BFFh to 002400h
2KB
002BFFh to 002400h
RAM(3)
Sector 7
NA
NA
2KB
0023FFh to 001C00h
2KB
0023FFh to 001C00h
USB RAM(4)
Sector 7
2KB
0023FFh to 001C00h
2KB
0023FFh to 001C00h
NA
NA
A
128 bytes
001BFFh to 001B80h
128 bytes
001BFFh to 001B80h
128 bytes
001BFFh to 001B80h
128 bytes
001BFFh to 001B80h
B
128 bytes
001B7Fh to 001B00h
128 bytes
001B7Fh to 001B00h
128 bytes
001B7Fh to 001B00h
128 bytes
001B7Fh to 001B00h
C
128 bytes
001AFFh to 001A80h
128 bytes
001AFFh to 001A80h
128 bytes
001AFFh to 001A80h
128 bytes
001AFFh to 001A80h
D
128 bytes
001A7Fh to 001A00h
128 bytes
001A7Fh to 001A00h
128 bytes
001A7Fh to 001A00h
128 bytes
001A7Fh to 001A00h
Info A
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
Info B
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
Info C
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
Info D
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
BSL 3
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
BSL 2
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
BSL 1
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
BSL 0
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
Size
4KB
000FFFh to 000000h
4KB
000FFFh to 000000h
4KB
000FFFh to 000000h
4KB
000FFFh to 000000h
TI factory memory
(ROM)
Information memory
(flash)
Bootloader (BSL)
memory (flash)
Peripherals
(1)
(2)
(3)
(4)
N/A = Not available.
Backup RAM is accessed through the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
Only available on FG642x.
Only available on FG662x. USB RAM can be used as general-purpose RAM when not used for USB operation.
9.15.1 Peripheral File Map
Table 9-41 lists all of the the available peripherals and their base addresses. Table 9-42 through Table 9-78 list
the registers and their offset addresses for each peripheral.
Table 9-41. Peripherals
BASE ADDRESS
OFFSET ADDRESS RANGE(1)
Special Functions (see Table 9-42)
0100h
000h to 01Fh
PMM (see Table 9-43)
0120h
000h to 010h
Flash Control (see Table 9-44)
0140h
000h to 00Fh
CRC16 (see Table 9-45)
0150h
000h to 007h
RAM Control (see Table 9-46)
0158h
000h to 001h
Watchdog (see Table 9-47)
015Ch
000h to 001h
UCS (see Table 9-48)
0160h
000h to 01Fh
MODULE NAME
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Table 9-41. Peripherals (continued)
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS RANGE(1)
SYS (see Table 9-49)
0180h
000h to 01Fh
Shared Reference (see Table 9-50)
01B0h
000h to 001h
Port Mapping Control (see Table 9-51)
01C0h
000h to 003h
Port Mapping Port P2 (see Table 9-51)
01D0h
000h to 007h
Port P1, P2 (see Table 9-52)
0200h
000h to 01Fh
Port P3, P4 (see Table 9-53)
0220h
000h to 01Fh
Port P5, P6 (see Table 9-54)
0240h
000h to 00Bh
Port P7, P8 (see Table 9-55)
0260h
000h to 00Bh
Port P9 (see Table 9-56)
0280h
000h to 00Bh
Port PJ (see Table 9-57)
0320h
000h to 01Fh
Timer TA0 (see Table 9-58)
0340h
000h to 02Eh
Timer TA1 (see Table 9-59)
0380h
000h to 02Eh
Timer TB0 (see Table 9-60)
03C0h
000h to 02Eh
Timer TA2 (see Table 9-61)
0400h
000h to 02Eh
Battery Backup (see Table 9-62)
0480h
000h to 01Fh
RTC_B (see Table 9-63)
04A0h
000h to 01Fh
32-Bit Hardware Multiplier (see Table 9-64)
04C0h
000h to 02Fh
DMA General Control (see Table 9-65)
0500h
000h to 00Fh
DMA Channel 0 (see Table 9-65)
0510h
000h to 00Ah
DMA Channel 1 (see Table 9-65)
0520h
000h to 00Ah
DMA Channel 2 (see Table 9-65)
0530h
000h to 00Ah
DMA Channel 3 (see Table 9-65)
0540h
000h to 00Ah
DMA Channel 4 (see Table 9-65)
0550h
000h to 00Ah
DMA Channel 5 (see Table 9-65)
0560h
000h to 00Ah
USCI_A0 (see Table 9-66)
05C0h
000h to 01Fh
USCI_B0 (see Table 9-67)
05E0h
000h to 01Fh
USCI_A1 (see Table 9-68)
0600h
000h to 01Fh
USCI_B1 (see Table 9-69)
0620h
000h to 01Fh
DAC12_A (see Table 9-70)
0780h
000h to 01Fh
Comparator_B (see Table 9-71)
08C0h
000h to 00Fh
USB configuration (see Table
9-72)(2)
USB control (see Table 9-73)(2)
(1)
(2)
(3)
138
0900h
000h to 014h
0920h
000h to 01Fh
LDO-PWR; LDO and Port U configuration (see Table 9-74) (3)
0900h
000h to 014h
LCD_B control (see Table 9-75)
0A00h
000h to 05Fh
CTSD16 (see Table 9-76)
0A80h
000h to 05Fh
OA0 and GSW0 (see Table 9-77)
0AE0h
000h to 00Fh
OA1 and GSW1 (see Table 9-78)
0AF0h
000h to 00Fh
For a detailed description of the individual control register offset addresses, see the MSP430F5xx and MSP430F6xx Family User's
Guide.
Only on devices with peripheral module USB.
Only on devices with peripheral module LDO-PWR.
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 9-42. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
SFR interrupt enable
SFR interrupt flag
SFR reset pin control
REGISTER
OFFSET
SFRIE1
00h
SFRIFG1
02h
SFRRPCR
04h
Table 9-43. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
PMM control 0
PMM control 1
REGISTER
OFFSET
PMMCTL0
00h
PMMCTL1
02h
SVS high-side control
SVSMHCTL
04h
SVS low-side control
SVSMLCTL
06h
PMM interrupt flags
PMMIFG
0Ch
PMMIE
0Eh
PM5CTL0
10h
PMM interrupt enable
PMM power mode 5 control
Table 9-44. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Flash control 1
FCTL1
00h
Flash control 3
FCTL3
04h
Flash control 4
FCTL4
06h
Table 9-45. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
CRC data input
CRC result
REGISTER
OFFSET
CRC16DI
00h
CRC16INIRES
04h
Table 9-46. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
RAM control 0
REGISTER
OFFSET
RCCTL0
00h
Table 9-47. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
Copyright © 2020 Texas Instruments Incorporated
REGISTER
OFFSET
WDTCTL
00h
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 9-48. UCS Registers (Base Address: 0160h)
REGISTER
OFFSET
UCS control 0
REGISTER DESCRIPTION
UCSCTL0
00h
UCS control 1
UCSCTL1
02h
UCS control 2
UCSCTL2
04h
UCS control 3
UCSCTL3
06h
UCS control 4
UCSCTL4
08h
UCS control 5
UCSCTL5
0Ah
UCS control 6
UCSCTL6
0Ch
UCS control 7
UCSCTL7
0Eh
UCS control 8
UCSCTL8
10h
Table 9-49. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SYSCTL
00h
Bootloader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
SYSSNIV
1Ch
SYSRSTIV
1Eh
System control
System NMI vector generator
Reset vector generator
Table 9-50. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
OFFSET
REFCTL
00h
Table 9-51. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P2: 01D0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port mapping password
PMAPPWD
00h
Port mapping control
PMAPCTL
02h
Port P2.0 mapping
P2MAP0
00h
Port P2.1 mapping
P2MAP1
01h
Port P2.2 mapping
P2MAP2
02h
Port P2.3 mapping
P2MAP3
03h
Port P2.4 mapping
P2MAP4
04h
Port P2.5 mapping
P2MAP5
05h
Port P2.6 mapping
P2MAP6
06h
Port P2.7 mapping
P2MAP7
07h
140
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 9-52. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 resistor enable
P1REN
06h
Port P1 drive strength
P1DS
08h
Port P1 selection
Port P1 input
P1SEL
0Ah
Port P1 interrupt vector word
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1IE
1Ah
P1IFG
1Ch
P2IN
01h
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 resistor enable
P2REN
07h
Port P2 output
Port P2 drive strength
P2DS
09h
Port P2 selection
P2SEL
0Bh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
Port P2 interrupt flag
P2IE
1Bh
P2IFG
1Dh
Table 9-53. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
Port P3 input
REGISTER
OFFSET
P3IN
00h
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 resistor enable
P3REN
06h
Port P3 output
Port P3 drive strength
P3DS
08h
Port P3 selection
P3SEL
0Ah
Port P3 interrupt vector word
P3IV
0Eh
Port P3 interrupt edge select
P3IES
18h
P3IE
1Ah
P3IFG
1Ch
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 resistor enable
P4REN
07h
Port P4 drive strength
P4DS
09h
Port P4 selection
Port P3 interrupt enable
Port P3 interrupt flag
Port P4 input
P4SEL
0Bh
Port P4 interrupt vector word
P4IV
1Eh
Port P4 interrupt edge select
P4IES
19h
P4IE
1Bh
P4IFG
1Dh
Port P4 interrupt enable
Port P4 interrupt flag
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 9-54. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 resistor enable
P5REN
06h
Port P5 drive strength
P5DS
08h
Port P5 selection
P5SEL
0Ah
P6IN
01h
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 resistor enable
P6REN
07h
Port P5 input
Port P6 input
Port P6 output
Port P6 drive strength
P6DS
09h
Port P6 selection
P6SEL
0Bh
Table 9-55. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
Port P7 input
REGISTER
OFFSET
P7IN
00h
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 resistor enable
P7REN
06h
Port P7 output
Port P7 drive strength
P7DS
08h
Port P7 selection
P7SEL
0Ah
Port P8 input
P8IN
01h
P8OUT
03h
Port P8 direction
P8DIR
05h
Port P8 resistor enable
P8REN
07h
Port P8 output
Port P8 drive strength
P8DS
09h
Port P8 selection
P8SEL
0Bh
Table 9-56. Port P9 Register (Base Address: 0280h)
REGISTER DESCRIPTION
Port P9 input
REGISTER
OFFSET
P9IN
00h
Port P9 output
P9OUT
02h
Port P9 direction
P9DIR
04h
Port P9 resistor enable
P9REN
06h
Port P9 drive strength
P9DS
08h
Port P9 selection
P9SEL
0Ah
Table 9-57. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ resistor enable
PJREN
06h
Port PJ drive strength
PJDS
08h
Port PJ input
142
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 9-58. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
Capture/compare control 3
TA0CCTL3
08h
Capture/compare control 4
TA0CCTL4
0Ah
TA0R
10h
Capture/compare 0
TA0CCR0
12h
Capture/compare 1
TA0CCR1
14h
Capture/compare 2
TA0CCR2
16h
Capture/compare 3
TA0CCR3
18h
Capture/compare 4
TA0CCR4
1Ah
TA0 control
TA0 counter
TA0 expansion 0
TA0 interrupt vector
TA0EX0
20h
TA0IV
2Eh
Table 9-59. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
TA1 control
REGISTER
OFFSET
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1 counter
TA1R
10h
Capture/compare 0
TA1CCR0
12h
Capture/compare 1
TA1CCR1
14h
Capture/compare 2
TA1CCR2
16h
TA1 expansion 0
TA1 interrupt vector
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TA1EX0
20h
TA1IV
2Eh
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 9-60. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
Capture/compare control 3
TB0CCTL3
08h
Capture/compare control 4
TB0CCTL4
0Ah
Capture/compare control 5
TB0CCTL5
0Ch
Capture/compare control 6
TB0CCTL6
0Eh
TB0 control
TB0 counter
TB0R
10h
Capture/compare 0
TB0CCR0
12h
Capture/compare 1
TB0CCR1
14h
Capture/compare 2
TB0CCR2
16h
Capture/compare 3
TB0CCR3
18h
Capture/compare 4
TB0CCR4
1Ah
Capture/compare 5
TB0CCR5
1Ch
Capture/compare 6
TB0CCR6
1Eh
TB0 expansion 0
TB0 interrupt vector
TB0EX0
20h
TB0IV
2Eh
Table 9-61. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
TA2 control
REGISTER
OFFSET
TA2CTL
00h
Capture/compare control 0
TA2CCTL0
02h
Capture/compare control 1
TA2CCTL1
04h
Capture/compare control 2
TA2CCTL2
06h
TA2 counter
TA2R
10h
Capture/compare 0
TA2CCR0
12h
Capture/compare 1
TA2CCR1
14h
Capture/compare 2
TA2CCR2
16h
TA2 expansion 0
TA2 interrupt vector
TA2EX0
20h
TA2IV
2Eh
Table 9-62. Battery Backup Registers (Base Address: 0480h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Battery backup memory 0
BAKMEM0
00h
Battery backup memory 1
BAKMEM1
02h
Battery backup memory 2
BAKMEM2
04h
Battery backup memory 3
BAKMEM3
06h
Battery backup control
BAKCTL
1Ch
Battery charger control
BAKCHCTL
1Eh
144
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 9-63. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER
OFFSET
RTC control 0
REGISTER DESCRIPTION
RTCCTL0
00h
RTC control 1
RTCCTL1
01h
RTC control 2
RTCCTL2
02h
RTC control 3
RTCCTL3
03h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTCIV
0Eh
RTCSEC
10h
RTC interrupt vector word
RTC seconds
RTC minutes
RTCMIN
11h
RTC hours
RTCHOUR
12h
RTC day of week
RTCDOW
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year low
RTCYEARL
16h
RTC year high
RTCYEARH
17h
RTCAMIN
18h
RTC alarm minutes
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Binary-to-BCD conversion
BIN2BCD
1Ch
BCD-to-binary conversion
BCD2BIN
1Eh
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 9-64. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
16-bit operand 1 – multiply
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
REGISTER
OFFSET
MPY
00h
MPYS
02h
MAC
04h
MACS
06h
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
16 × 16 sum extension register
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32CTL0
2Ch
MPY32 control 0
146
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SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 9-65. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h)
REGISTER
OFFSET
DMA general control: DMA module control 0
REGISTER DESCRIPTION
DMACTL0
00h
DMA general control: DMA module control 1
DMACTL1
02h
DMA general control: DMA module control 2
DMACTL2
04h
DMA general control: DMA module control 3
DMACTL3
06h
DMA general control: DMA module control 4
DMACTL4
08h
DMA general control: DMA interrupt vector
DMAIV
0Ah
DMA channel 0 control
DMA0CTL
00h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 destination address high
DMA0DAH
08h
DMA0SZ
0Ah
DMA channel 0 transfer size
DMA channel 1 control
DMA1CTL
00h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 destination address high
DMA1DAH
08h
DMA1SZ
0Ah
DMA channel 1 transfer size
DMA channel 2 control
DMA2CTL
00h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 destination address high
DMA2DAH
08h
DMA2SZ
0Ah
DMA channel 2 transfer size
DMA channel 3 control
DMA3CTL
00h
DMA channel 3 source address low
DMA3SAL
02h
DMA channel 3 source address high
DMA3SAH
04h
DMA channel 3 destination address low
DMA3DAL
06h
DMA channel 3 destination address high
DMA3DAH
08h
DMA3SZ
0Ah
DMA channel 3 transfer size
DMA channel 4 control
DMA4CTL
00h
DMA channel 4 source address low
DMA4SAL
02h
DMA channel 4 source address high
DMA4SAH
04h
DMA channel 4 destination address low
DMA4DAL
06h
DMA channel 4 destination address high
DMA4DAH
08h
DMA4SZ
0Ah
DMA channel 4 transfer size
DMA channel 5 control
DMA5CTL
00h
DMA channel 5 source address low
DMA5SAL
02h
DMA channel 5 source address high
DMA5SAH
04h
DMA channel 5 destination address low
DMA5DAL
06h
DMA channel 5 destination address high
DMA5DAH
08h
DMA5SZ
0Ah
DMA channel 5 transfer size
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Table 9-66. USCI_A0 Registers (Base Address: 05C0h)
REGISTER
OFFSET
USCI control 0
REGISTER DESCRIPTION
UCA0CTL0
00h
USCI control 1
UCA0CTL1
01h
USCI baud rate 0
UCA0BR0
06h
UCA0BR1
07h
UCA0MCTL
08h
USCI baud rate 1
USCI modulation control
USCI status
UCA0STAT
0Ah
USCI receive buffer
UCA0RXBUF
0Ch
USCI transmit buffer
UCA0TXBUF
0Eh
USCI LIN control
UCA0ABCTL
10h
USCI IrDA transmit control
UCA0IRTCTL
12h
USCI IrDA receive control
UCA0IRRCTL
13h
UCA0IE
1Ch
UCA0IFG
1Dh
UCA0IV
1Eh
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
Table 9-67. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 0
UCB0CTL0
00h
USCI synchronous control 1
UCB0CTL1
01h
USCI synchronous bit rate 0
UCB0BR0
06h
USCI synchronous bit rate 1
UCB0BR1
07h
UCB0STAT
0Ah
USCI synchronous receive buffer
USCI synchronous status
UCB0RXBUF
0Ch
USCI synchronous transmit buffer
UCB0TXBUF
0Eh
USCI I2C own address
UCB0I2COA
10h
USCI I2C slave address
UCB0I2CSA
12h
UCB0IE
1Ch
UCB0IFG
1Dh
UCB0IV
1Eh
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
Table 9-68. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 0
UCA1CTL0
00h
USCI control 1
UCA1CTL1
01h
USCI baud rate 0
UCA1BR0
06h
USCI baud rate 1
USCI modulation control
USCI status
UCA1BR1
07h
UCA1MCTL
08h
UCA1STAT
0Ah
USCI receive buffer
UCA1RXBUF
0Ch
USCI transmit buffer
UCA1TXBUF
0Eh
USCI LIN control
UCA1ABCTL
10h
USCI IrDA transmit control
UCA1IRTCTL
12h
USCI IrDA receive control
UCA1IRRCTL
13h
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
148
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UCA1IE
1Ch
UCA1IFG
1Dh
UCA1IV
1Eh
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Table 9-69. USCI_B1 Registers (Base Address: 0620h)
REGISTER
OFFSET
USCI synchronous control 0
REGISTER DESCRIPTION
UCB1CTL0
00h
USCI synchronous control 1
UCB1CTL1
01h
USCI synchronous bit rate 0
UCB1BR0
06h
USCI synchronous bit rate 1
UCB1BR1
07h
USCI synchronous status
UCB1STAT
0Ah
USCI synchronous receive buffer
UCB1RXBUF
0Ch
USCI synchronous transmit buffer
UCB1TXBUF
0Eh
USCI I2C own address
UCB1I2COA
10h
USCI I2C slave address
UCB1I2CSA
12h
UCB1IE
1Ch
UCB1IFG
1Dh
UCB1IV
1Eh
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
Table 9-70. DAC12_A Registers (Base Address: 0780h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DAC12_A channel 0 control 0
DAC12_0CTL0
00h
DAC12_A channel 0 control 1
DAC12_0CTL1
02h
DAC12_A channel 0 data
DAC12_0DAT
04h
DAC12_A channel 0 calibration control
DAC12_0CALCTL
06h
DAC12_A channel 0 calibration data
DAC12_0CALDAT
08h
DAC12_A channel 1 control 0
DAC12_1CTL0
10h
DAC12_A channel 1 control 1
DAC12_1CTL1
12h
DAC12_A channel 1 data
DAC12_1DAT
14h
DAC12_A channel 1 calibration control
DAC12_1CALCTL
16h
DAC12_A channel 1 calibration data
DAC12_1CALDAT
18h
DAC12IV
1Eh
DAC12_A interrupt vector word
Table 9-71. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comp_B control 0
CBCTL0
00h
Comp_B control 1
CBCTL1
02h
Comp_B control 2
CBCTL2
04h
Comp_B control 3
CBCTL3
06h
Comp_B interrupt
CBINT
0Ch
CBIV
0Eh
Comp_B interrupt vector word
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Table 9-72. USB Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTION
USB key/ID
USB module configuration
USB PHY control
REGISTER
OFFSET
USBKEYID
00h
USBCNF
02h
USBPHYCTL
04h
USB power control
USBPWRCTL
08h
USB power voltage setting
USBPWRVSR
0Ah
USB PLL control
USBPLLCTL
10h
USB PLL divider
USBPLLDIV
12h
USBPLLIR
14h
USB PLL interrupts
Table 9-73. USB Control Registers (Base Address: 0920h)
REGISTER DESCRIPTION
Input endpoint_0 configuration
Input endpoint_0 byte count
REGISTER
OFFSET
USBIEPCNF_0
00h
USBIEPBCNT_0
01h
Output endpoint_0 configuration
USBOEPCNFG_0
02h
Output endpoint_0 byte count
USBOEPBCNT_0
03h
Input endpoint interrupt enables
USBIEPIE
0Eh
Output endpoint interrupt enables
USBOEPIE
0Fh
Input endpoint interrupt flags
USBIEPIFG
10h
Output endpoint interrupt flags
USBOEPIFG
11h
USB interrupt vector
USBIV
12h
USB maintenance
USBMAINT
16h
Time stamp
USBTSREG
18h
USB frame number
USBFN
1Ah
USB control
USBCTL
1Ch
USBIE
1Dh
USBIFG
1Eh
USBFUNADR
1Fh
USB interrupt enables
USB interrupt flags
Function address
Table 9-74. LDO and Port U Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTION
LDO key and ID
PU port control
LDO power control
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REGISTER
OFFSET
LDOKEYPID
00h
PUCTL
04h
LDOPWRCTL
08h
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Table 9-75. LCD_B Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
LCD_B control 0
LCD_B control 1
REGISTER
OFFSET
LCDBCTL0
000h
LCDBCTL1
002h
LCD_B blinking control
LCDBBLKCTL
004h
LCD_B memory control
LCDBMEMCTL
006h
LCD_B voltage control
LCDBVCTL
008h
LCD_B port control 0
LCDBPCTL0
00Ah
LCD_B port control 1
LCDBPCTL1
00Ch
LCD_B port control 2
LCDBPCTL2
00Eh
LCD_B charge pump control
LCDBCTL0
012h
LCD_B interrupt vector word
LCDBIV
01Eh
LCD_B memory 1
LCDM1
020h
LCD_B memory 2
LCDM2
021h
⋮
⋮
LCD_B memory 22
⋮
LCDM22
035h
LCD_B blinking memory 1
LCDBM1
040h
LCD_B blinking memory 2
LCDBM2
041h
⋮
LCD_B blinking memory 22
⋮
⋮
LCDBM22
055h
Table 9-76. CTSD16 Registers (Base Address: 0A80h)
REGISTER DESCRIPTION
CTSD16 control
REGISTER
OFFSET
CTSD16CTL
00h
CTSD16 channel 0 control
CTSD16CCTL0
02h
CTSD16 channel 0 input control
CTSD16INCTL0
04h
CTSD16PRE0
06h
CTSD16IFG
2Ch
CTSD16IE
2Eh
CTSD16IV
30h
CTSD16MEM0
32h
CTSD16 channel 0 preload
CTSD16 interrupt flag
CTSD16 interrupt enable
CTSD16 interrupt vector
CTSD16 channel 0 conversion memory
Table 9-77. OA0 Registers (Base Address: 0AE0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OA0CTL0
00h
OA0 positive input terminal switches
OA0PSW
02h
OA0 negative input terminal switches
OA0NSW
04h
OA0 ground switches
OA0GSW
0Eh
OA0 control 0
Table 9-78. OA1 Registers (Base Address: 0AF0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OA1CTL0
00h
OA1 positive input terminal switches
OA1PSW
02h
OA1 negative input terminal switches
OA1NSW
04h
OA1 ground switches
OA1GSW
0Eh
OA1 control 0
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9.16 Identification
9.16.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The devicespecific errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see Section 11.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For details on
this value, see the "Hardware Revision" entries in Section 9.14.
9.16.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific errata
sheet describes these markings. For links to all of the errata sheets for the devices in this data sheet, see
Section 11.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For details
on this value, see the "Device ID" entries in Section 9.14.
9.16.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in detail in
the MSP430 Programming With the JTAG Interface.
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10 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430. These guidelines are to
make sure that the device has proper connections for powering, programming, debugging, and optimum analog
performance.
10.1.1 Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling capacitor to
each AVCC and DVCC pin. Higher-value capacitors may be used but can impact supply rail ramp-up time.
Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few
millimeters). Additionally, separated grounds with a single-point connection are recommend for better noise
isolation from digital to analog circuits on the board and are especially recommended to achieve high analog
accuracy.
DVCC
Digital
Power Supply
Decoupling
1 µF
+
100 nF
DVSS
AVCC
Analog
Power Supply
Decoupling
1 µF
+
100 nF
AVSS
Figure 10-1. Power Supply Decoupling
10.1.2 External Oscillator
Depending on the device variant (see Section 6), the device can support a low-frequency crystal (32 kHz) on the
XT1 pins, a high-frequency crystal on the XT2 pins, or both. External bypass capacitors for the crystal oscillator
pins are required.
It is also possible to apply digital clock signals to the XIN and XT2IN input pins that meet the specifications of the
respective oscillator if the appropriate XT1BYPASS or XT2BYPASS mode is selected. In this case, the
associated XOUT and XT2OUT pins can be used for other purposes. If they are left unused, they must be
terminated according to Table 7-4.
Figure 10-2 shows a typical connection diagram.
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XIN
or
XT2IN
CL1
XOUT
or
XT2OUT
CL2
Figure 10-2. Typical Crystal Connection
See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP430 devices.
10.1.3 JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or MSPFET430UIF) can be used to program and debug code on the target board. In addition, the connections also
support the MSP-GANG production programmers, thus providing an easy way to program prototype boards, if
desired. Figure 10-3 shows the connections between the 14-pin JTAG connector and the target device required
to support in-system programming and debugging for 4-wire JTAG communication. Figure 10-4 shows the
connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are identical.
Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-FET430UIF
interface modules and MSP-GANG have a VCC sense feature that, if used, requires an alternate connection (pin
4 instead of pin 2). The VCC-sense feature senses the local VCC present on the target board (that is, a battery
or other local power supply) and adjusts the output signals accordingly. Figure 10-3 and Figure 10-4 show a
jumper block that supports both scenarios of supplying VCC to the target board. If this flexibility is not required,
the desired VCC connections may be hard-wired to eliminate the jumper block. Pins 2 and 4 must not be
connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s Guide.
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VCC
Important to connect
MSP430FGxxxx
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kW
JTAG
VCC TOOL
VCC TARGET
TEST
2
C2
10 µF
C3
0.1 µF
RST/NMI/SBWTDIO
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
TDI
TDO/TDI
TDI
TMS
TMS
TCK
TCK
GND
RST
TEST/SBWTCK
C1
2.2 nF
See Note B
AVSS/DVSS
A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection
J2.
B. The upper limit for C1 is 2.2 nF when using current TI tools.
Figure 10-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430FGxxxx
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kΩ
See Note B
C2
10 µF
C3
0.1 µF
JTAG
VCC TOOL
VCC TARGET
2
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
RST/NMI/SBWTDIO
TCK
GND
TEST/SBWTCK
C1
2.2 nF
See Note B
AVSS/DVSS
A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or
programming adapter.
B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and any
capacitance that is attached to this signal may affect the ability to establish a connection with the device. The upper limit for C1 is 2.2 nF
when using current TI tools.
Figure 10-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
10.1.4 Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is edge
sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the external NMI.
When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either pullup or
pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not. If the RST/NMI
pin is unused, it is required either to select and enable the internal pullup or to connect an external 47-kΩ pullup
resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown capacitor should not exceed 2.2 nF
when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like
FET interfaces or GANG programmers.
See the MSP430F5xx and MSP430F6xx Family User's Guide for more information on the referenced control
registers and bits.
10.1.5 Unused Pins
For details on the connection of unused pins, see Section 7.6.
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10.1.6 General Layout Recommendations
•
•
•
•
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430 32-kHz
Crystal Oscillators for recommended layout guidelines.
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital switching
signals such as PWM or JTAG signals away from the oscillator circuit.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
10.1.7 Do's and Don'ts
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power
down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits
specified in Section 8.1. Exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and flash.
10.2 Peripheral- and Interface-Specific Design Information
10.2.1 CTSD16 Peripheral
For internal connections between signal chain modules such as CTSD16, OA, and DAC12, see Section 9.12.16.
When internal connections are available, they should be chosen over external connections to reduce noise and
save pins.
Solid decoupling on both the digital and analog supplies is also required (best with two capacitors, one 1 µF and
one 100 nF [see Section 10.1.1]).
VREFBG/VeREF+
(see Note A)
1 nF
CPCAP
(see Note B)
22 nF
AVSS
A. The capacitor reduces noise when using internal VREFBG setting. This pin is also used for the external reference input for the CTSD16 or
DAC, and when doing so the capacitor is not needed. Because of the shared signal path and pin, the internal and external references
(VREFBG and VeREF+, respectively) cannot be used at the same time.
B. The capacitor on CPCAP is required when the charge pump is enabled. The charge pump can be enabled by rail-to-rail operation of the
CTSD16 or by the OA module. See the register settings for each module in the MSP430F5xx and MSP430F6xx Family User's Guide for
enabling this operation.
Figure 10-5. CTSD16 Partial Schematic
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10.2.1.1 Example Measurement Schematic – Differential Input
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