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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
MSP430FR572x 混合信号微控制器
1 器件概述
1.1
特性
1
• 嵌入式微控制器
– 高达 8MHz 时钟频率的 16 位精简指令集计算机
(RISC) 架构
– 宽电源电压范围（2V 至 3.6V）
– -40°C 至 85°C 运行
• 经优化超低功率模式
– 激活模式：81.4µA/MHz（典型值）
– 待机（具有 VLO 的 LPM3）：6.3µA（典型值）
– 实时时钟 (RTC)（LPM3.5，采用晶振）：1.5µA
（典型值）
– 关断 (LPM4.5)：0.32µA（典型值）
• 超低功率铁电 RAM (FRAM)
– 高达 16KB 的非易失性存储器
– 超低功率写入
– 125ns 每个字的快速写入（1ms 内写入 16KB）
– 内置纠错编码 (ECC) 和存储器保护单元 (MPU)
– 通用内存 = 程序 + 数据 + 存储
– 1015 写入周期持耐久性
– 抗辐射和非磁性
• 智能数字外设
– 32 位硬件乘法器 (MPY)
– 3 通道内部直接存储器访问 (DMA)
– 具有日历和报警功能的实时时钟 (RTC)
– 5 个具有多达 3 个捕捉/比较寄存器的 16 位定时
器
– 16 位循环冗余校验器 (CRC)
• 高性能模拟
– 支持电压基准和可编程滞后的 16 通道模拟比较
器
– 具有内部基准、采样与保持功能的 12 通道 10 位
模数转换器 (ADC)
– 在流耗为 100µA 时为 200ksps
1.2
•
•
• 增强型串行通信
– eUSCI_A0 和 eUSCI_A1 支持：
– 支持自动波特率侦测的通用异步收发器
(UART)
– IrDA 编码和解码
– 串行外设接口 (SPI)
– eUSCI_B0 支持：
– 支持多从器件寻址的 I2C
– 串行外设接口 (SPI)
– 硬件通用异步收发器 (UART) 引导加载程序
(BSL)
• 电源管理系统
– 完全集成的低压降稳压器 (LDO)
– 具有复位功能的内核与电源电压监控器
– 常开模式的零功率欠压检测
– 串行板上编程，无需外部电压
• 灵活的时钟系统
– 具有 6 个可选出厂校准频率的固定频率数控振荡
器 (DCO)（视器件而定）
– 低功率低频内部时钟源 (VLO)
– 32kHz 晶振 (LFXT)
– 高频晶振 (HFXT)
• 开发工具和软件
– 免费的专业开发环境
(Code Composer Studio™ IDE)
– 低成本全功能套件
()
– 完全开发套件(MSP-FET430U40A)
– 目标板 (MSP-TS430RHA40A)
• 系列产品成员
– 有关可用器件型号和封装的信息，请参见 系列产
品
– 欲了解完整的模块说明，请参见
《MSP430FR57xx 系列产品用户指南》
应用范围
家庭自动化
安全性
•
•
传感器管理
数据采集
注意事项
这些产品采用 FRAM 非易失性存储器技术。FRAM 保持对于极端温度环境敏感，例如那些回流焊接或者手工焊接时产生
的温度。更多信息请参阅 最大绝对额定值。
注意事项
必须采用与器件级 ESD 规范兼容的系统级 ESD 保护以防止电气过载或者数据或代码内存的干扰。有关更多信息，请参
阅《MSP430™ 系统级 ESD 注意事项》。
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASE35
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
1.3
www.ti.com.cn
说明
德州仪器 (TI) MSP430FR572x 系列超低功耗微控制器包含多个器件，该系列器件具有嵌入式 FRAM 非易失
性存储器，超低功率 16 位 MSP430™CPU 以及专用于各种应用的不同 外设。这种架构、FRAM 和外设与
7 种低功耗模式相组合，专为在便携式无线感测应用中延长电池的使用寿命而进行了 优化。FRAM 是全新的
非易失性存储器，其完美结合了 SRAM 的速度、灵活性和耐用性与闪存的稳定性和可靠性，并且总功耗更
低。外设包括一个 10 位模数转换器 (ADC)，一个具有电压基准生成和滞后功能的 16 通道比较器，3 条支持
I2C，SPI，或 UART 协议的增强型串行通道，一个内部 DMA，一个硬件乘法器，一个实时时钟 (RTC)，5
个 16 位定时器和数字 I/O。
器件信息 (1)
器件型号
封装尺寸 (2)
封装
MSP430FR5729RHA
VQFN (40)
6mm x 6mm
MSP430FR5729DA
TSSOP (38)
12.5mm x 6.2mm
MSP430FR5728RGE
VQFN (24)
4mm x 4mm
MSP430FR5728PW
TSSOP (28)
9.7mm x 4.4mm
(1)
(2)
1.4
要获得最新的产品、封装和订购信息，请参见封装选项附录（节 8），或者访问德州仪器 (TI) 网站 www.ti.com.cn。
此处显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（节 8）。
功能方框图
图 1-1 显示采用 RHA 封装的 MSP430FR5721，MSP430FR5725 和 MSP430FR5729 器件的功能方框图。
要获得所有器件变量和封装选项的功能方框图，请见 节 6.1。
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16KB
Clock
System
ACLK
8KB
SMCLK
4KB
(FR5721)
FRAM
MCLK
CPUXV2
and
Working
Registers
1KB
Boot
ROM
Power
Management
SYS
Watchdog
P3.x
I/O Ports
P1/P2
2×8 I/Os
(FR5729)
(FR5725)
PA
P2.x
REF
Interrupt,
Wake up
PA
1×16 I/Os
SVS
RAM
Memory
Protection
Unit
PB
P4.x
I/O Ports
P3/P4
1×8 I/Os
1x 2 I/Os
Interrupt,
Wake up
PB
1×10 I/Os
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
TA0
TA1
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG,
SBW
Interface
TB0
TB1
TB2
RTC_B
MPY32
(2) Timer_A
3 CC
Registers
(3) Timer_B
3 CC
Registers
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
eUSCI_A1:
UART,
IrDA, SPI
ADC10_B
10 bit
200 ksps
Comp_D
16 channels
14 channels
(12 ext/2 int)
Copyright © 2016, Texas Instruments Incorporated
图 1-1. 功能方框图 - RHA 封装 - MSP430FR5721，
，MSP430FR5725，
，MSP430FR5729
2
器件概述
版权 © 2014–2017, Texas Instruments Incorporated
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
内容
器件概述 .................................................... 1
5.17
MODOSC............................................ 26
1.1
特性 ................................................... 1
5.18
PMM, Core Voltage ................................. 27
1.2
应用范围 .............................................. 1
5.19
PMM, SVS, BOR .................................... 27
1.3
说明 ................................................... 2
5.20
Wake-up Times From Low-Power Modes
27
1.4
功能方框图 ............................................ 2
5.21
Timer_A
28
2
3
修订历史记录............................................... 4
Device Comparison ..................................... 5
5.22
Related Products ..................................... 6
5.24
4
Terminal Configuration and Functions .............. 7
5.25
4.1
5.26
1
3.1
4.2
4.3
4.4
4.5
5
Pin Diagram – RHA Package –
MSP430FR5721, MSP430FR5723,
MSP430FR5725, MSP430FR5727,
Pin Diagram – DA Package –
MSP430FR5721, MSP430FR5723,
MSP430FR5725, MSP430FR5727,
Pin Diagram – RGE Package –
MSP430FR5720, MSP430FR5722,
MSP430FR5724, MSP430FR5726,
Pin Diagram – PW Package –
MSP430FR5720, MSP430FR5722,
MSP430FR5724, MSP430FR5726,
5.23
5.27
MSP430FR5729 7
5.28
5.29
MSP430FR5729 8
MSP430FR5728 8
MSP430FR5728 9
Signal Descriptions .................................. 10
Specifications ........................................... 15
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
........................
ESD Ratings ........................................
Recommended Operating Conditions ...............
Absolute Maximum Ratings
15
15
Active Mode Supply Current Into VCC Excluding
External Current ..................................... 16
Low-Power Mode Supply Currents (Into VCC)
Excluding External Current.......................... 17
Thermal Resistance Characteristics ................
Schmitt-Trigger Inputs – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to
P4.1, PJ.0 to PJ.5, RST/NMI) .......................
Inputs – Ports P1 and P2
(P1.0 to P1.7, P2.0 to P2.7) ........................
Leakage Current – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to
P4.1, PJ.0 to PJ.5, RST/NMI) .......................
Outputs – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to
P4.1, PJ.0 to PJ.5) .................................
Output Frequency – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to
P4.1, PJ.0 to PJ.5) .................................
18
19
19
19
7
20
20
5.12
Typical Characteristics – Outputs ................... 21
5.13
5.14
Crystal Oscillator, XT1, Low-Frequency (LF) Mode 23
Crystal Oscillator, XT1, High-Frequency (HF) Mode
...................................................... 24
Internal Very-Low-Power Low-Frequency Oscillator
(VLO) ................................................ 25
5.15
5.16
6
15
DCO Frequencies ................................... 26
版权 © 2014–2017, Texas Instruments Incorporated
8
..........
.............................................
Timer_B .............................................
eUSCI (UART Mode) Clock Frequency .............
eUSCI (UART Mode)................................
eUSCI (SPI Master Mode) Clock Frequency .......
eUSCI (SPI Master Mode) ..........................
eUSCI (SPI Slave Mode) ...........................
eUSCI (I2C Mode) ...................................
28
28
28
29
29
31
33
10-Bit ADC, Power Supply and Input Range
Conditions ........................................... 34
....................
..................
5.32 REF, External Reference ...........................
5.33 REF, Built-In Reference .............................
5.34 REF, Temperature Sensor and Built-In VMID .......
5.35 Comparator_D .......................................
5.36 FRAM................................................
5.37 JTAG and Spy-Bi-Wire Interface ....................
Detailed Description ...................................
6.1
Functional Block Diagrams..........................
6.2
CPU .................................................
6.3
Operating Modes ....................................
6.4
Interrupt Vector Addresses..........................
6.5
Memory Organization ...............................
6.6
Bootloader (BSL) ....................................
6.7
JTAG Operation .....................................
6.8
FRAM ...............................................
6.9
Memory Protection Unit (MPU) .....................
6.10 Peripherals ..........................................
6.11 Input/Output Diagrams .............................
6.12 Device Descriptors (TLV) ...........................
器件和文档支持 ..........................................
7.1
开始使用 .............................................
7.2
Device Nomenclature ...............................
7.3
工具和软件 ..........................................
7.4
文档支持 .............................................
7.5
相关链接 .............................................
7.6
社区资源 .............................................
7.7
商标..................................................
7.8
静电放电警告 ........................................
7.9
出口管制提示 ........................................
7.10 术语表 ...............................................
机械、封装和可订购信息................................
5.30
10-Bit ADC, Timing Parameters
34
5.31
10-Bit ADC, Linearity Parameters
34
内容
35
35
36
37
37
38
39
39
44
44
45
47
48
48
49
49
49
69
90
93
93
93
95
97
99
99
99
99
99
99
99
3
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from October 1, 2016 to December 5, 2017
•
4
Page
Added the note that begins "In LPM3, the VLO frequency varies..." following Section 5.15, Internal Very-LowPower Low-Frequency Oscillator (VLO) .......................................................................................... 25
修订历史记录
Copyright © 2014–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725
MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Family Members (1) (2)
DEVICE
SRAM
(KB)
SYSTEM
CLOCK
(MHz)
ADC10_B
Comp_D
MSP430FR5729
16
1
8
12 ext, 2 int ch.
16 ch.
MSP430FR5728
16
1
8
6 ext, 2 int ch.
10 ch.
8 ext, 2 int ch.
12 ch.
MSP430FR5727
(4)
16
1
8
–
16 ch.
10 ch.
MSP430FR5726
16
1
8
–
MSP430FR5725
8
1
8
12 ext, 2 int ch.
16 ch.
6 ext, 2 int ch.
10 ch.
8 ext, 2 int ch.
12 ch.
–
16 ch.
MSP430FR5724
8
1
8
MSP430FR5723
8
1
8
MSP430FR5722
(1)
(2)
(3)
eUSCI
FRAM
(KB)
8
1
8
MSP430FR5721
4
1
8
MSP430FR5720
4
1
8
–
12 ch.
10 ch.
12 ch.
12 ext, 2 int ch.
16 ch.
6 ext, 2 int ch.
10 ch.
8 ext, 2 int ch.
12 ch.
Timer_A
(3)
Timer_B
(4)
Channel A:
UART, IrDA,
SPI
Channel B:
SPI, I2C
3, 3
3, 3, 3
2
1
3, 3
3
1
1
3, 3
3, 3, 3
2
1
3, 3
3
1
1
3, 3
3, 3, 3
2
1
3, 3
3
1
1
3, 3
3, 3, 3
2
1
3, 3
3
1
1
3, 3
3, 3, 3
2
1
3, 3
3
1
1
I/O
PACKAGE
32
RHA
30
DA
17
RGE
21
PW
32
RHA
30
DA
17
RGE
21
PW
32
RHA
30
DA
17
RGE
21
PW
32
RHA
30
DA
17
RGE
21
PW
32
RHA
30
DA
17
RGE
21
PW
For the most current package and ordering information, see the Package Option Addendum in 节 8, or see the TI website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output
generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output
generators, respectively.
Copyright © 2014–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725
MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
Device Comparison
5
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
3.1
www.ti.com.cn
Related Products
For information about other devices in this family of products or related products, see the following links.
Products for MSP 16-Bit and 32-Bit MCUs Low-power mixed-signal processors with smart analog and
digital peripherals for a wide range of industrial and consumer applications.
Products for Ultra-Low-Power MCUs MSP Ultra-Low-Power microcontrollers (MCUs) from Texas
Instruments (TI) offer the lowest power consumption and the perfect mix of integrated
peripherals for a wide range of low power and portable applications.
Products for MSP430FRxx FRAM MCUs 16-bit microcontrollers for ultra-low-power sensing and system
management in building automation, smart grid, and industrial designs.
Companion Products for MSP430FR5729 Review products that are frequently purchased or used in
conjunction with this product.
Reference Designs for MSP430FR5729 TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
6
Device Comparison
Copyright © 2014–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725
MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
4 Terminal Configuration and Functions
4.1
Pin Diagram – RHA Package –
MSP430FR5721, MSP430FR5723, MSP430FR5725, MSP430FR5727, MSP430FR5729
Figure 4-1 shows the pin diagram for the MSP430FR5721, MSP430FR5723, MSP430FR5725,
MSP430FR5727, and MSP430FR5729 devices in the 40-pin RHA package.
P2.4/TA1.0/UCA1CLK/A7*/CD11
P2.3/TA0.0/UCA1STE/A6*/CD10
P2.7
DVCC
DVSS
31
32
33
35
34
30
29
3
28
4
27
5
26
VCORE
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
P3.7/TB2.2
P3.6/TB2.1/TB1CLK
P3.5/TB1.2/CDOUT
P3.4/TB1.1/TB2CLK/SMCLK
P2.2/TB2.2/UCB0CLK/TB1.0
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
20
19
18
21
17
22
10
16
23
9
15
8
14
24
13
25
7
11
6
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJ.3/TCK/CD9
P4.0/TB2.0
Note:
36
37
39
1
2
12
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2
P3.0/A12*/CD12
P3.1/A13*/CD13
P3.2/A14*/CD14
P3.3/A15*/CD15
P1.3/TA1.2/UCB0STE/A3*/CD3
P1.4/TB0.1/UCA0STE/A4*/CD4
P1.5/TB0.2/UCA0CLK/A5*/CD5
38
40
AVSS
PJ.4/XIN
PJ.5/XOUT
AVSS
AVCC
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.6/TB1.0/UCA1RXD/UCA1SOMI
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P4.1
* Not available on MSP430FR5727, MSP430FR5723
Exposed thermal pad connection to VSS recommended.
Figure 4-1. 40-Pin RHA Package (Top View)
Terminal Configuration and Functions
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MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
Copyright © 2014–2017, Texas Instruments Incorporated
7
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
4.2
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Pin Diagram – DA Package –
MSP430FR5721, MSP430FR5723, MSP430FR5725, MSP430FR5727, MSP430FR5729
Figure 4-2 shows the pin diagram for the MSP430FR5721, MSP430FR5723, MSP430FR5725,
MSP430FR5727, and MSP430FR5729 devices in the 38-pin DA package.
PJ.4/XIN
PJ.5/XOUT
AVSS
AVCC
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2
P3.0/A12*/CD12
P3.1/A13*/CD13
P3.2/A14*/CD14
P3.3/A15*/CD15
P1.3/TA1.2/UCB0STE/A3*/CD3
P1.4/TB0.1/UCA0STE/A4*/CD4
P1.5/TB0.2/UCA0CLK/A5*/CD5
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJ.3/TCK/CD9
P2.5/TB0.0/UCA1TXD/UCA1SIMO
1
38
2
37
3
36
4
35
5
34
6
33
7
32
8
31
9
30
10
29
11
28
12
27
13
26
14
25
15
24
16
23
17
22
18
21
19
20
AVSS
P2.4/TA1.0/UCA1CLK/A7*/CD11
P2.3/TA0.0/UCA1STE/A6*/CD10
P2.7
DVCC
DVSS
VCORE
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
P3.7/TB2.2
P3.6/TB2.1/TB1CLK
P3.5/TB1.2/CDOUT
P3.4/TB1.1/TB2CLK/SMCLK
P2.2/TB2.2/UCB0CLK/TB1.0
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.6/TB1.0/UCA1RXD/UCA1SOMI
* Not available on MSP430FR5727, MSP430FR5723
Figure 4-2. 38-Pin DA Package (Top View)
4.3
Pin Diagram – RGE Package –
MSP430FR5720, MSP430FR5722, MSP430FR5724, MSP430FR5726, MSP430FR5728
Figure 4-3 shows the pin diagram for the MSP430FR5720, MSP430FR5722, MSP430FR5724,
MSP430FR5726, and MSP430FR5728 devices in the 24-pin RGE package.
PJ.4/XIN
DVCC
DVSS
19
20
21
18
17
13
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/MCLK/CD7
PJ.2/TMS/ACLK/CD8
* Not available on MSP430FR5726, MSP430FR5722
Exposed thermal pad connection to VSS recommended.
VCORE
P1.7/UCB0SOMI/UCB0SCL/TA1.0
P1.6/UCB0SIMO/UCB0SDA/TA0.0
P2.2/UCB0CLK
P2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
12
14
11
5
6
10
16
15
9
3
4
7
Note:
23
1
2
8
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2
P1.3/TA1.2/UCB0STE/A3*/CD3
P1.4/TB0.1/UCA0STE/A4*/CD4
P1.5/TB0.2/UCA0CLK/A5*/CD5
22
24
PJ.5/XOUT
AVSS
AVCC
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.3/TCK/CD9
Figure 4-3. 24-Pin RGE Package (Top View)
8
Terminal Configuration and Functions
Copyright © 2014–2017, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725
MSP430FR5724 MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
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4.4
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
Pin Diagram – PW Package –
MSP430FR5720, MSP430FR5722, MSP430FR5724, MSP430FR5726, MSP430FR5728
图 4-4 shows the pin diagram for the MSP430FR5720, MSP430FR5722,
MSP430FR5726, and MSP430FR5728 devices in the 28-pin PW package.
PJ.4/XIN
PJ.5/XOUT
AVSS
AVCC
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2
P1.3/TA1.2/UCB0STE/A3*/CD3
P1.4/TB0.1/UCA0STE/A4*/CD4
P1.5/TB0.2/UCA0CLK/A5*/CD5
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/MCLK/CD7
PJ.2/TMS/ACLK/CD8
PJ.3/TCK/CD9
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
MSP430FR5724,
P2.4/TA1.0/A7*/CD11
P2.3/TA0.0/A6*/CD10
DVCC
DVSS
VCORE
P1.7/UCB0SOMI/UCB0SCL/TA1.0
P1.6/UCB0SIMO/UCB0SDA/TA0.0
P2.2/UCB0CLK
P2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.6
P2.5/TB0.0
* Not available on MSP430FR5726, MSP430FR5722
图 4-4. 28-Pin PW Package (Top View)
Terminal Configuration and Functions
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
9
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
4.5
www.ti.com.cn
Signal Descriptions
表 4-1 describes the signals for all device variants and packages.
表 4-1. Signal Descriptions
TERMINAL
NAME
I/O
NO.
RHA
RGE
DESCRIPTION
(1)
DA
PW
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA0 CCR1 capture: CCI1A input, compare: Out1
External DMA trigger
P1.0/TA0.1/DMAE0/
RTCCLK/A0/CD0/VeREF-
1
1
5
5
I/O
RTC clock calibration output
Analog input A0 – ADC (not available on devices without ADC)
Comparator_D input CD0
External applied reference voltage (not available on devices without ADC)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA0 CCR2 capture: CCI2A input, compare: Out2
TA1 input clock
P1.1/TA0.2/TA1CLK/
CDOUT/A1/CD1/VeREF+
2
2
6
6
I/O
Comparator_D output
Analog input A1 – ADC (not available on devices without ADC)
Comparator_D input CD1
Input for an external reference voltage to the ADC (not available on
devices without ADC)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA1 CCR1 capture: CCI1A input, compare: Out1
P1.2/TA1.1/TA0CLK/
CDOUT/A2/CD2
3
3
7
7
I/O
TA0 input clock
Comparator_D output
Analog input A2 – ADC (not available on devices without ADC)
Comparator_D input CD2
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
P3.0/A12/CD12
4
N/A
8
N/A
I/O
Analog input A12 – ADC (not available on devices without ADC or
package options PW, RGE)
Comparator_D input CD12 (not available on package options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
P3.1/A13/CD13
5
N/A
9
N/A
I/O
Analog input A13 – ADC (not available on devices without ADC or
package options PW, RGE)
Comparator_D input CD13 (not available on package options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
P3.2/A14/CD14
6
N/A
10
N/A
I/O
Analog input A14 – ADC (not available on devices without ADC or
package options PW, RGE)
Comparator_D input CD14 (not available on package options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
P3.3/A15/CD15
7
N/A
11
N/A
I/O
Analog input A15 – ADC (not available on devices without ADC or
package options PW, RGE)
Comparator_D input CD15 (not available on package options PW, RGE)
(1)
I = input, O = output, N/A = not available
10
Terminal Configuration and Functions
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产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
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ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
表 4-1. Signal Descriptions (continued)
TERMINAL
NAME
I/O
NO.
RHA
RGE
DESCRIPTION
(1)
DA
PW
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA1 CCR2 capture: CCI2A input, compare: Out2
P1.3/TA1.2/UCB0STE/
A3/CD3
8
4
12
8
I/O
Slave transmit enable – eUSCI_B0 SPI mode
Analog input A3 – ADC (not available on devices without ADC)
Comparator_D input CD3
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB0 CCR1 capture: CCI1A input, compare: Out1
P1.4/TB0.1/UCA0STE/
A4/CD4
9
5
13
9
I/O
Slave transmit enable – eUSCI_A0 SPI mode
Analog input A4 – ADC (not available on devices without ADC)
Comparator_D input CD4
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB0 CCR2 capture: CCI2A input, compare: Out2
P1.5/TB0.2/UCA0CLK/
A5/CD5
10
6
14
10
I/O
Clock signal input – eUSCI_A0 SPI slave mode,
Clock signal output – eUSCI_A0 SPI master mode
Analog input A5 – ADC (not available on devices without ADC)
Comparator_D input CD5
General-purpose digital I/O
Test data output port
PJ.0/TDO/TB0OUTH/
SMCLK/CD6 (2)
11
7
15
11
I/O
Switch all PWM outputs high impedance input – TB0
SMCLK output
Comparator_D input CD6
General-purpose digital I/O
Test data input or test clock input
PJ.1/TDI/TCLK/TB1OUTH/
MCLK/CD7 (2)
12
8
16
12
I/O
Switch all PWM outputs high impedance input – TB1 (not available on
devices without TB1)
MCLK output
Comparator_D input CD7
General-purpose digital I/O
Test mode select
PJ.2/TMS/TB2OUTH/
ACLK/CD8 (2)
13
9
17
13
I/O
Switch all PWM outputs high impedance input – TB2 (not available on
devices without TB2)
ACLK output
Comparator_D input CD8
General-purpose digital I/O
PJ.3/TCK/CD9
(2)
14
10
18
14
I/O
Test clock
Comparator_D input CD9
P4.0/TB2.0
15
N/A
N/A
N/A
I/O
P4.1
16
N/A
N/A
N/A
I/O
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
TB2 CCR0 capture: CCI0B input, compare: Out0 (not available on
devices without TB2 or package options DA, PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options DA, PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
P2.5/TB0.0/UCA1TXD/
UCA1SIMO
(2)
17
N/A
19
15
I/O
TB0 CCR0 capture: CCI0A input, compare: Out0
Transmit data – eUSCI_A1 UART mode, Slave in, master out –
eUSCI_A1 SPI mode (not available on devices without UCSI_A1)
See 节 6.7 for use with JTAG function.
Terminal Configuration and Functions
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
11
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 4-1. Signal Descriptions (continued)
TERMINAL
I/O
NO.
NAME
RHA
RGE
DESCRIPTION
(1)
DA
PW
General-purpose digital I/O with port interrupt and wake up from LPMx.5
P2.6/TB1.0/UCA1RXD/
UCA1SOMI
18
N/A
20
16
I/O
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on
devices without TB1)
Receive data – eUSCI_A1 UART mode, Slave out, master in – eUSCI_A1
SPI mode (not available on devices without UCSI_A1)
TEST/SBWTCK
(2) (3)
19
11
21
17
I
20
12
22
18
I/O
Test mode pin – enable JTAG pins
Spy-Bi-Wire input clock
Reset input active low
RST/NMI/SBWTDIO
(2) (3)
Non-maskable interrupt input
Spy-Bi-Wire data input/output
General-purpose digital I/O with port interrupt and wake up from LPMx.5
P2.0/TB2.0/UCA0TXD/
UCA0SIMO/TB0CLK/ACLK
(3)
TB2 CCR0 capture: CCI0A input, compare: Out0 (not available on
devices without TB2)
21
13
23
19
I/O
Transmit data – eUSCI_A0 UART mode
Slave in, master out – eUSCI_A0 SPI mode
TB0 clock input
ACLK output
General-purpose digital I/O with port interrupt and wake up from LPMx.5
P2.1/TB2.1/UCA0RXD/
UCA0SOMI/TB0.0 (3)
TB2 CCR1 capture: CCI1A input, compare: Out1 (not available on
devices without TB2)
22
14
24
20
I/O
Receive data – eUSCI_A0 UART mode
Slave out, master in – eUSCI_A0 SPI mode
TB0 CCR0 capture: CCI0A input, compare: Out0
General-purpose digital I/O with port interrupt and wake up from LPMx.5
P2.2/TB2.2/UCB0CLK/
TB1.0
TB2 CCR2 capture: CCI2A input, compare: Out2 (not available on
devices without TB2)
23
15
25
21
I/O
Clock signal input – eUSCI_B0 SPI slave mode,
Clock signal output – eUSCI_B0 SPI master mode
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on
devices without TB1)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
P3.4/TB1.1/TB2CLK/
SMCLK
24
N/A
26
N/A
I/O
TB1 CCR1 capture: CCI1B input, compare: Out1 (not available on
devices without TB1)
TB2 clock input (not available on devices without TB2 or package options
PW, RGE)
SMCLK output (not available on package options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
P3.5/TB1.2/CDOUT
25
N/A
27
N/A
I/O
TB1 CCR2 capture: CCI2B input, compare: Out2 (not available on
devices without TB1)
Comparator_D output (not available on package options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
P3.6/TB2.1/TB1CLK
26
N/A
28
N/A
I/O
TB2 CCR1 capture: CCI1B input, compare: Out1 (not available on
devices without TB2)
TB1 clock input (not available on devices without TB1 or package options
PW, RGE)
(3)
12
See 节 6.6 and 节 6.7 for use with BSL and JTAG functions.
Terminal Configuration and Functions
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
表 4-1. Signal Descriptions (continued)
TERMINAL
NAME
P3.7/TB2.2
I/O
NO.
RHA
27
RGE
N/A
DESCRIPTION
(1)
DA
29
PW
N/A
I/O
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
TB2 CCR2 capture: CCI2B input, compare: Out2 (not available on
devices without TB2 or package options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
P1.6/TB1.1/UCB0SIMO/
UCB0SDA/TA0.0
TB1 CCR1 capture: CCI1A input, compare: Out1 (not available on
devices without TB1)
28
16
30
22
I/O
Slave in, master out – eUSCI_B0 SPI mode
I2C data – eUSCI_B0 I2C mode
TA0 CCR0 capture: CCI0A input, compare: Out0
General-purpose digital I/O with port interrupt and wake up from LPMx.5
P1.7/TB1.2/UCB0SOMI/
UCB0SCL/TA1.0
TB1 CCR2 capture: CCI2A input, compare: Out2 (not available on
devices without TB1)
29
17
31
23
I/O
Slave out, master in – eUSCI_B0 SPI mode
I2C clock – eUSCI_B0 I2C mode
TA1 CCR0 capture: CCI0A input, compare: Out0
30
18
32
24
Regulated core power supply (internal use only, no external current
loading)
DVSS
31
19
33
25
Digital ground supply
DVCC
32
20
34
26
Digital power supply
P2.7
33
N/A
35
N/A
VCORE
(4)
I/O
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options PW, RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options RGE)
P2.3/TA0.0/UCA1STE/
A6/CD10
TA0 CCR0 capture: CCI0B input, compare: Out0 (not available on
package options RGE)
34
N/A
36
27
I/O
Slave transmit enable – eUSCI_A1 SPI mode (not available on devices
without eUSCI_A1)
Analog input A6 – ADC (not available on devices without ADC)
Comparator_D input CD10 (not available on package options RGE)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
(not available on package options RGE)
TA1 CCR0 capture: CCI0B input, compare: Out0 (not available on
package options RGE)
P2.4/TA1.0/UCA1CLK/
A7/CD11
35
N/A
37
28
I/O
Clock signal input – eUSCI_A1 SPI slave mode, Clock signal output –
eUSCI_A1 SPI master mode (not available on devices without
eUSCI_A1)
Analog input A7 – ADC (not available on devices without ADC)
Comparator_D input CD11 (not available on package options RGE)
AVSS
36
N/A
38
N/A
PJ.4/XIN
37
21
1
1
I/O
PJ.5/XOUT
38
22
2
2
I/O
AVSS
39
23
3
3
Analog ground supply
AVCC
40
24
4
4
Analog power supply
Pad
Pad
N/A
N/A
QFN Pad
(4)
Analog ground supply
General-purpose digital I/O
Input terminal for crystal oscillator XT1
General-purpose digital I/O
Output terminal of crystal oscillator XT1
QFN package pad. Connection to VSS recommended.
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
Terminal Configuration and Functions
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
13
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
14
Terminal Configuration and Functions
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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
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ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS
Voltage applied to any pin (excluding VCORE)
(2)
MIN
MAX
–0.3
4.1
–0.3
VCC + 0.3
Diode current at any device pin
(1)
(2)
(3)
(4)
(5)
(4) (5)
–55
95
°C
125
°C
ESD Ratings
VALUE
V(ESD)
(2)
V
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
Data retention on FRAM cannot be ensured when exceeding the specified maximum storage temperature, Tstg.
For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Programming of devices with user application code should only be performed after reflow or hand soldering. Factory programmed
information, such as calibration values, are designed to withstand the temperatures reached in the current JEDEC J-STD-020
specification.
5.2
(1)
V
±2
Maximum junction temperature, TJ
Storage temperatureTstg (3)
UNIT
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3
Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
(1)
NOM
Supply voltage during program execution and FRAM programming (AVCC = DVCC)
VSS
Supply voltage (AVSS = DVSS)
TA
Operating free-air temperature
–40
85
TJ
Operating junction temperature
–40
85
CVCORE
Required capacitor at VCORE (2)
CVCC/
CVCORE
Capacitor ratio of VCC to VCORE
fSYSTEM
(1)
(2)
(3)
(4)
Processor frequency (maximum MCLK frequency) (3)
2.0
MAX
VCC
3.6
0
UNIT
V
V
470
°C
°C
nF
10
No FRAM wait states
2 V ≤ VCC ≤ 3.6 V
(4)
,
0
8.0
MHz
TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
A capacitor tolerance of ±20% or better is required.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
When using manual wait state control, see the MSP430FR57xx Family User's Guide for recommended settings for common system
frequencies.
Specifications
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15
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
5.4
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Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2) (3)
Frequency (fMCLK = fSMCLK)
PARAMETER
EXECUTION MEMORY
VCC
1 MHz
TYP
IAM,
FRAM_UNI
IAM,0%
(4)
(5)
4 MHz
MAX
FRAM
3V
0.27
FRAM
0% cache hit ratio
3V
0.42
TYP
8 MHz
MAX
TYP
0.58
0.73
UNIT
MAX
1.0
1.2
1.6
mA
2.2
2.8
mA
IAM,50% (5)
(6)
FRAM
50% cache hit ratio
3V
0.31
0.73
1.3
mA
IAM,66% (5)
(6)
FRAM
66% cache hit ratio
3V
0.27
0.58
1.0
mA
IAM,75% (5)
(6)
FRAM
75% cache hit ratio
3V
0.25
0.5
0.82
mA
FRAM
100% cache hit ratio
3V
0.2
0.43
0.3
0.55
0.42
0.8
mA
RAM
3V
0.2
0.4
0.35
0.55
0.55
0.75
mA
IAM,100% (5)
IAM,
(1)
(2)
(3)
(4)
(5)
(6)
(7)
RAM
(6)
(6) (7)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
Characterized with program executing typical data processing.
Program and data reside entirely in FRAM. No wait states enabled. DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK.
Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 25% ratio implies one of every
four accesses is from cache, the remaining are FRAM accesses.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK. No wait states enabled.
See 图 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in .
fACLK = 32786 Hz, fMCLK = fSMCLK at specified frequency. No peripherals active.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
All execution is from RAM.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK.
2.50
IAM,0% (mA) = 0.2541 * (f, MHz) + 0.1724
2.00
IAM,50% (mA) = 0.1415 * (f, MHz) + 0.1669
IAM,66%(mA) = 0.1043 * (f, MHz) + 0.1646
IA M, mA
1.50
IAM,75% (mA) = 0.0814 * (f, MHz) + 0.1708
1.00
0.50
IAM,RAM (mA) = 0.05 * (f, MHz) + 0.150
IAM,100% (mA) = 0.0314 * (f, MHz) + 0.1708
0.00
0
1
2
3
4
5
6
7
8
9
fMCLK = f SMCLK , MHz
图 5-1. Typical Active Mode Supply Currents, No Wait States
16
Specifications
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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
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5.5
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
–40°C
TYP
MAX
25°C
TYP
ILPM0,1MHz
Low-power mode 0
(3) (4)
2 V,
3V
166
175
LPM0,8MHz
Low-power mode 0
(5) (4)
2 V,
3V
170
177
LPM0,24MHz
Low-power mode 0
(6) (4)
2 V,
3V
274
ILPM2
Low-power mode 2
(7) (8)
2 V,
3V
ILPM3,XT1LF
Low-power mode 3, crystal
mode (9) (8)
ILPM3,VLO
Low-power mode 3,
VLO mode (10) (8)
ILPM4
Low-power mode 4
ILPM3.5
ILPM4.5
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(1) (2)
60°C
MAX
TYP
MAX
85°C
TYP
MAX
UNIT
190
225
µA
244
195
225
360
µA
285
340
315
340
455
µA
56
61
80
75
110
210
µA
2 V,
3V
3.4
6.4
15
18
48
150
µA
2 V,
3V
3.3
6.3
15
18
48
150
µA
(11) (8)
2 V,
3V
2.9
5.9
15
18
48
150
µA
Low-power mode 3.5
(12)
2 V,
3V
1.3
1.5
2.2
1.9
2.8
5.0
µA
Low-power mode 4.5
(13)
2 V,
3V
0.3
0.32
0.66
0.38
0.57
2.55
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = 1 MHz. DCORSEL = 0,
DCOFSELx = 3 (fDCO = 8 MHz)
Current for brownout, high-side supervisor (SVSH), and low-side supervisor (SVSL) included.
Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = 8 MHz. DCORSEL = 0,
DCOFSELx = 3 (fDCO = 8 MHz)
Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = 24 MHz. DCORSEL = 1,
DCOFSELx = 3 (fDCO = 24 MHz)
Current for watchdog timer (clocked by ACLK) and RTC (clocked by XT1 LF mode) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCORSEL = 0,
DCOFSELx = 3, DCO bias generator enabled.
Current for brownout and high-side supervisor (SVSH) included. Low-side supervisor (SVSL) disabled.
Current for watchdog timer (clocked by ACLK) and RTC (clocked by XT1 LF mode) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for watchdog timer (clocked by ACLK) included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Internal regulator disabled. No data retention. RTC active clocked by XT1 LF mode.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM3.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Specifications
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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
5.6
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Thermal Resistance Characteristics
PARAMETER
PACKAGE
VALUE (1)
UNIT
θJA
Junction-to-ambient thermal resistance, still air (2)
78.8
°C/W
θJC(TOP)
Junction-to-case (top) thermal resistance (3)
19.4
°C/W
θJB
Junction-to-board thermal resistance (4)
36.7
°C/W
ΨJB
Junction-to-board thermal characterization parameter
36.2
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.5
°C/W
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance (5)
N/A
°C/W
θJA
Junction-to-ambient thermal resistance, still air (2)
42.1
°C/W
38.8
°C/W
18.1
°C/W
18.0
°C/W
0.6
°C/W
TSSOP-24 (PW)
(3)
θJC(TOP)
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
QFN-24 (RGE)
(5)
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance
2.8
°C/W
θJA
Junction-to-ambient thermal resistance, still air (2)
74.5
°C/W
θJC(TOP)
Junction-to-case (top) thermal resistance (3)
22.0
°C/W
40.7
°C/W
40.3
°C/W
0.9
°C/W
(4)
θJB
Junction-to-board thermal resistance
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
SOIC-38 (DA)
(5)
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
θJA
Junction-to-ambient thermal resistance, still air (2)
37.8
°C/W
θJC(TOP)
Junction-to-case (top) thermal resistance (3)
27.4
°C/W
θJB
Junction-to-board thermal resistance (4)
12.6
°C/W
ΨJB
Junction-to-board thermal characterization parameter
12.6
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.4
°C/W
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance (5)
3.6
°C/W
(1)
(2)
(3)
(4)
(5)
18
QFN-40 (RHA)
N/A = Not applicable
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Specifications
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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
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5.7
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
Schmitt-Trigger Inputs – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
VCC
MIN
2V
0.80
TYP
1.40
3V
1.50
2.10
2V
0.45
1.10
3V
0.75
1.65
2V
0.25
0.8
3V
0.30
1.0
20
35
MAX
50
5
UNIT
V
V
V
kΩ
pF
Inputs – Ports P1 and P2 (1)
(P1.0 to P1.7, P2.0 to P2.7)
5.8
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
(2)
External interrupt timing
TEST CONDITIONS
(2)
External trigger pulse duration to set interrupt flag
VCC
MIN
2 V, 3 V
MAX
20
UNIT
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
5.9
Leakage Current – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.x)
(1)
(2)
High-impedance leakage current
TEST CONDITIONS
(1) (2)
VCC
MIN
MAX
2 V, 3 V
–50
50
UNIT
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Specifications
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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
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ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
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5.10 Outputs – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
(1)
(2)
TEST CONDITIONS
Low-level output voltage
I(OHmax) = –1 mA
(1)
I(OHmax) = –3 mA
(2)
I(OHmax) = –2 mA
(1)
I(OHmax) = –6 mA
(2)
I(OLmax) = 1 mA
(1)
I(OLmax) = 3 mA
(2)
I(OLmax) = 2 mA
(1)
I(OLmax) = 6 mA
(2)
VCC
2V
3V
2V
3V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
UNIT
V
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
5.11 Output Frequency – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fPx.y
Port output frequency
(with load)
Px.y
fPort_CLK
Clock output frequency
ACLK, SMCLK, or MCLK at configured output port,
CL = 20 pF, no DC loading (2)
(1)
(2)
20
(1) (2)
VCC
MIN
MAX
2V
16
3V
24
2V
16
3V
24
UNIT
MHz
MHz
A resistive divider with 2 × 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
CL = 20 pF is connected from the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Specifications
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MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
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ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
5.12 Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
16
TA = -40 ° C
IOL - Typical Low-Level Output Current - mA
14
TA = 25 ° C
12
TA = 85 ° C
10
8
6
4
2
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
V OL - Low-Level Output Voltage - V
VCC = 2.0 V
Measured at Px.y
图 5-2. Typical Low-Level Output Current vs Low-Level Output Voltage
35
IOL - Typical Low-Level Output Current - mA
TA = -40 ° C
30
TA = 25 ° C
TA = 85 ° C
25
20
15
10
5
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
VOL - Low-Level Output Voltage - V
VCC = 3.0 V
Measured at Px.y
图 5-3. Typical Low-Level Output Current vs Low-Level Output Voltage
Specifications
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
21
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
IOH - Typical High-Level Output Current - mA
0
-2
-4
-6
-8
-10
TA = 85 ° C
-12
TA = 25 ° C
-14
TA = -40 ° C
-16
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
V OH - High-Level Output Voltage - V
VCC = 2.0 V
Measured at Px.y
图 5-4. Typical High-Level Output Current vs High-Level Output Voltage
0
IOH - Typical High-Level Output Current - mA
-5
-10
-15
-20
-25
TA = 85 ° C
-30
TA = 25 ° C
-35
TA = -40 ° C
-40
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
V OH - High-Level Output Voltage - V
VCC = 3.0 V
Measured at Px.y
图 5-5. Typical High-Level Output Current vs High-Level Output Voltage
22
Specifications
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
5.13 Crystal Oscillator, XT1, Low-Frequency (LF) Mode
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ΔIVCC.LF
TEST CONDITIONS
Additional current consumption
XT1 LF mode from lowest drive
setting
60
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {2},
TA = 25°C, CL,eff = 9 pF
3V
90
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 12 pF
3V
140
XTS = 0, XT1BYPASS = 0
fXT1,LF,SW
XT1 oscillator logic-level squarewave input frequency, LF mode
XTS = 0, XT1BYPASS = 1
fFault,LF
tSTART,LF
CL,eff
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Oscillator fault frequency, LF mode
(5)
Start-up time, LF mode
(2) (3)
10
(7)
Integrated effective load
capacitance, LF mode (8)
210
XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
TA = 25°C, CL,eff = 6 pF
XTS = 0
UNIT
nA
Hz
50
kHz
kΩ
(6)
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 12 pF
(9)
32.768
XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
fXT1,LF = 32768 Hz, CL,eff = 6 pF
XTS = 0
MAX
32768
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Duty cycle, LF mode
TYP
3V
XT1 oscillator crystal frequency,
LF mode
OALF
MIN
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {1},
CL,eff = 9 pF, TA = 25°C,
fXT1,LF0
Oscillation allowance for
LF crystals (4)
VCC
30%
70%
10
10000
Hz
1000
3V
ms
1000
1
pF
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVE
settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but
should be evaluated based on the actual crystal selected for the application:
• For XT1DRIVE = {0}, CL,eff ≤ 6 pF.
• For XT1DRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF.
• For XT1DRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF.
• For XT1DRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Includes start-up counter of 4096 clock cycles.
Requires external capacitors at both terminals.
Values are specified by crystal manufacturers. Include parasitic bond and package capacitance (approximately 2 pF per pin).
Recommended values supported are 6 pF, 9 pF, and 12 pF. Maximum shunt capacitance of 1.6 pF.
Specifications
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
23
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
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5.14 Crystal Oscillator, XT1, High-Frequency (HF) Mode
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
XT1 oscillator crystal current HF
mode
IVCC,HF
VCC
MIN
TYP
fOSC = 4 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
TA = 25°C, CL,eff = 16 pF
175
fOSC = 8 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {1},
TA = 25°C, CL,eff = 16 pF
300
MAX
3V
fOSC = 16 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {2},
TA = 25°C, CL,eff = 16 pF
UNIT
µA
350
fOSC = 24 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 16 pF
550
fXT1,HF0
XT1 oscillator crystal frequency,
HF mode 0
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0}
(2)
4
6
MHz
fXT1,HF1
XT1 oscillator crystal frequency,
HF mode 1
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {1}
(2)
6
10
MHz
fXT1,HF2
XT1 oscillator crystal frequency,
HF mode 2
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {2}
(2)
10
16
MHz
fXT1,HF3
XT1 oscillator crystal frequency,
HF mode 3
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {3}
(2)
16
24
MHz
fXT1,HF,SW
XT1 oscillator logic-level squarewave input frequency, HF mode
XTS = 1,
XT1BYPASS = 1
1
24
MHz
Oscillation allowance for
HF crystals (4)
OAHF
tSTART,HF
(1)
(2)
(3)
(4)
(5)
24
Start-up time, HF mode
(5)
(3) (2)
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0},
fXT1,HF = 4 MHz, CL,eff = 16 pF
450
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {1},
fXT1,HF = 8 MHz, CL,eff = 16 pF
320
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {2},
fXT1,HF = 16 MHz, CL,eff = 16 pF
200
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {3},
fXT1,HF = 24 MHz, CL,eff = 16 pF
200
fOSC = 4 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0},
TA = 25°C, CL,eff = 16 pF
8
fOSC = 24 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 16 pF
Ω
3V
ms
2
To improve EMI on the XT1 oscillator the following guidelines should be observed.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
Maximum frequency of operation of the entire device cannot be exceeded.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Includes start-up counter of 4096 clock cycles.
Specifications
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
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ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
Crystal Oscillator, XT1, High-Frequency (HF) Mode
(1)
(continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CL,eff
fFault,HF
(6)
(7)
(8)
(9)
TEST CONDITIONS
Integrated effective load
capacitance (6) (7)
XTS = 1
Duty cycle, HF mode
XTS = 1, Measured at ACLK,
fXT1,HF2 = 24 MHz
Oscillator fault frequency, HF mode
(8)
XTS = 1
VCC
MIN
TYP
MAX
1
40%
(9)
50%
145
UNIT
pF
60%
900
kHz
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are
14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specificiations might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
5.15 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TYP
MAX
5
8.3
13
UNIT
VLO frequency
Measured at ACLK
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK
(1)
2 V to 3.6 V
0.5
%/°C
dfVLO/dVCC VLO frequency supply voltage drift
Measured at ACLK
(2)
2 V to 3.6 V
4
%/V
fVLO,DC
Measured at ACLK
(1)
(2)
Duty cycle
2 V to 3.6 V
MIN
fVLO
2 V to 3.6 V
40%
50%
kHz
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(2.0 V to 3.6 V) – MIN(2.0 V to 3.6 V)) / MIN(2.0 V to 3.6 V) / (3.6 V – 2 V)
NOTE
In LPM3, the VLO frequency varies by up to ±6% (typical), due to bias current sampling. This
frequency variation is not a violation VLO specifications (see Section 5.15).
Specifications
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
25
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
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5.16 DCO Frequencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fDCO,LO
DCO frequency low, trimmed
fDCO,MID
DCO frequency mid, trimmed
fDCO,HI
DCO frequency high, trimmed
fDCO,DC
Duty cycle
5.17
TEST CONDITIONS
Measured at ACLK,
DCORSEL = 0
Measured at ACLK,
DCORSEL = 0
Measured at ACLK,
DCORSEL = 0
Measured at ACLK, divide by 1,
No external divide, all DCO
settings
VCC
TA
MIN
TYP
MAX
2 V to 3.6 V
–40°C to 85°C
5.37
±3.5%
2 V to 3.6 V
0°C to 50°C
5.37
±2.0%
2 V to 3.6 V
–40°C to 85°C
6.67
±3.5%
2 V to 3.6 V
0°C to 50°C
6.67
±2.0%
2 V to 3.6 V
–40°C to 85°C
8
±3.5%
2 V to 3.6 V
0°C to 50°C
8
±2.0%
UNIT
MHz
MHz
MHz
2 V to 3.6 V
–40°C to 85°C
40%
50%
60%
VCC
MIN
TYP
MAX
44
80
µA
MHz
MODOSC
over operating free-air temperature range (unless otherwise noted)
PARAMETER
IMODOSC
Current consumption
fMODOSC
MODOSC frequency
fMODOSC,DC
Duty cycle
26
Specifications
TEST CONDITIONS
Enabled
Measured at ACLK, divide by 1
2 V to 3.6 V
2 V to 3.6 V
4.5
5.0
5.5
2 V to 3.6 V
40%
50%
60%
UNIT
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
5.18 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE(AM)
Core voltage, active mode
2 V ≤ DVCC ≤ 3.6 V
1.5
V
VCORE(LPM)
Core voltage, low-current mode
2 V ≤ DVCC ≤ 3.6 V
1.5
V
5.19 PMM, SVS, BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISVSH,AM
SVSH current consumption, active mode
VCC = 3.6 V
5
ISVSH,LPM
SVSH current consumption, low power modes
VCC = 3.6 V
0.8
1.5
µA
VSVSH-
SVSH on voltage level, falling supply voltage
1.83
1.88
1.93
V
VSVSH+
SVSH off voltage level, rising supply voltage
1.88
1.93
1.98
tPD,SVSH, AM
SVSH propagation delay, active mode
dVCC/dt = 10 mV/µs
10
µs
tPD,SVSH, LPM
SVSH propagation delay, low power modes
dVCC/dt = 1 mV/µs
30
µs
ISVSL
SVSL current consumption
VSVSL–
SVSL on voltage level
1.42
V
VSVSL+
SVSL off voltage level
1.47
V
0.3
µA
0.5
V
µA
5.20 Wake-up Times From Low-Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA
MIN
TYP
MAX
UNIT
tWAKE-UP LPM0
Wake-up time from LPM0 to active
mode (1)
2 V, 3 V
–40°C to 85°C
0.58
1
µs
tWAKE-UP LPM12
Wake-up time from LPM1, LPM2 to
active mode (1)
2 V, 3 V
–40°C to 85°C
12
25
µs
tWAKE-UP LPM34
Wake-up time from LPM3 or LPM4 to
active mode (1)
2 V, 3 V
–40°C to 85°C
78
120
µs
2 V, 3 V
0°C to 85°C
310
575
tWAKE-UP LPMx.5
Wake-up time from LPM3.5 or
LPM4.5 to active mode (1)
2 V, 3 V
–40°C to 85°C
310
1100
280
µs
tWAKE-UP RESET
Wake-up time from RST to active
mode (2)
VCC stable
2 V, 3 V
–40°C to 85°C
230
tWAKE-UP BOR
Wake-up time from BOR or power-up
to active mode
dVCC/dt = 2400 V/s
2 V, 3 V
–40°C to 85°C
1.6
tRESET
Pulse duration required at RST/NMI
terminal to accept a reset event (3)
(1)
(2)
(3)
2 V, 3 V
–40°C to 85°C
4
µs
ms
ns
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
The wake-up time is measured from the rising edge of the RST signal until the first instruction of the user program is executed.
Meeting or exceeding this time makes sures a reset event occurs. Pulses shorter than this minimum time may or may not cause a reset
event to occur.
Specifications
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
27
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
5.21 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTA
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ±10%
2 V, 3 V
tTA,cap
Timer_A capture timing
All capture inputs, Minimum pulse
duration required for capture
2 V, 3 V
MIN
TYP
MAX
UNIT
8
MHz
20
ns
5.22 Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTB
Timer_B input clock frequency
Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ±10%
tTB,cap
Timer_B capture timing
All capture inputs, Minimum pulse
duration required for capture
VCC
2 V, 3 V
2 V, 3 V
MIN
TYP
MAX
UNIT
8
MHz
20
ns
5.23 eUSCI (UART Mode) Clock Frequency
PARAMETER
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
MAX
UNIT
fSYSTEM
MHz
5
MHz
UNIT
5.24 eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
UCGLITx = 0
tt
UART receive deglitch time (1)
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
(1)
28
2 V, 3 V
MIN
TYP
MAX
5
15
20
20
45
60
35
80
120
50
110
180
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Specifications
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
5.25 eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
feUSCI
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
Duty cycle = 50% ±10%
eUSCI input clock frequency
MAX
UNIT
fSYSTEM
MHz
5.26 eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
TEST CONDITIONS
STE lead time, STE active to clock
STE lag time, Last clock to STE
inactive
STE access time, STE active to SIMO
data out
STE disable time, STE inactive to
SIMO high impedance
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time
(2)
tHD,MO
SIMO output data hold time
(3)
(1)
(2)
(3)
VCC
MIN
(1)
TYP
MAX
UCSTEM = 0,
UCMODEx = 01 or 10
2 V, 3 V
1
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
1
UCSTEM = 0,
UCMODEx = 01 or 10
2 V, 3 V
1
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
1
UCSTEM = 0,
UCMODEx = 01 or 10
2 V, 3 V
55
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
35
UCSTEM = 0,
UCMODEx = 01 or 10
2 V, 3 V
40
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
30
UCLK edge to SIMO valid,
CL = 20 pF
CL = 20 pF
UNIT
UCxCLK
cycles
UCxCLK
cycles
ns
ns
2V
35
3V
35
2V
0
3V
0
ns
ns
2V
30
3V
30
2V
0
3V
0
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in 图 5-6 and 图 5-7.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in 图 5-6
and 图 5-7.
Specifications
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
29
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
图 5-6. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
图 5-7. SPI Master Mode, CKPH = 1
30
Specifications
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
5.27 eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
(2)
tHD,SO
SOMI output data hold time
(3)
(1)
(2)
(3)
UCLK edge to SOMI valid,
CL = 20 pF
CL = 20 pF
VCC
MIN
2V
7
3V
7
2V
0
3V
0
(1)
TYP
MAX
ns
ns
2V
65
3V
40
2V
40
3V
35
2V
2
3V
2
2V
5
3V
5
30
30
4
4
ns
ns
3V
3V
ns
ns
2V
2V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in 图 5-8 and 图 5-9.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in 图 5-8 and
图 5-9.
Specifications
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
31
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SIMO
tLOW/HIGH
tHD,SIMO
SIMO
tVALID,SOMI
tACC
tDIS
SOMI
图 5-8. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tVALID,SO
tDIS
SOMI
图 5-9. SPI Slave Mode, CKPH = 1
32
Specifications
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
5.28 eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图 5-10)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2 V, 3 V
0
ns
tSU,DAT
Data setup time
2 V, 3 V
250
ns
tSU,STO
2 V, 3 V
2 V, 3 V
fSCL > 100 kHz
fSCL = 100 kHz
2 V, 3 V
fSCL > 100 kHz
fSCL = 100 kHz
Setup time for STOP
2 V, 3 V
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
tSP
fSCL = 100 kHz
0
4.0
µs
0.6
4.7
µs
0.6
4.0
µs
0.6
UCGLITx = 0
50
600
UCGLITx = 1
25
300
12.5
150
2 V, 3 V
UCGLITx = 2
UCGLITx = 3
6.25
75
UCCLTOx = 1
tTIMEOUT
Clock low time-out
27
UCCLTOx = 2
2 V, 3 V
30
UCCLTOx = 3
tSU,STA
tHD,STA
ns
ms
33
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
图 5-10. I2C Mode Timing
Specifications
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产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
33
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
5.29
www.ti.com.cn
10-Bit ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range
All ADC10 pins
IADC10_A
Operating supply current into
AVCC terminal, reference
current not included
fADC10CLK = 5 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0
CI
Input capacitance
Only one terminal Ax can be selected at one
time from the pad to the ADC10_A capacitor
array including wiring and pad
RI
Input MUX ON resistance
AVCC ≥ 2 V, 0 V ≤ VAx ≤ AVCC
5.30
VCC
MIN
TYP
MAX
UNIT
2.0
3.6
V
0
AVCC
V
2V
90
140
3V
100
160
6
8
pF
36
kΩ
2.2 V
µA
10-Bit ADC, Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fADC10CLK
fADC10OSC
tCONVERT
VCC
MIN
TYP
MAX
UNIT
2 V to
3.6 V
0.45
5
5.5
MHz
2 V to
3.6 V
4.5
4.5
5.5
MHz
REFON = 0, Internal oscillator,
12 ADC10CLK cycles, 10-bit mode,
fADC10OSC = 4.5 MHz to 5.5 MHz
2 V to
3.6 V
2.18
External fADC10CLK from ACLK, MCLK, or SMCLK,
ADC10SSEL ≠ 0
2 V to
3.6 V
For specified performance of ADC10 linearity
parameters
Internal ADC10 oscillator
ADC10DIV = 0, fADC10CLK = fADC10OSC
(MODOSC)
Conversion time
tADC10ON
Turnon settling time of
the ADC
The error in a conversion started after tADC10ON is
less than ±0.5 LSB,
Reference and input signal already settled
tSample
Sampling time
RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF,
Approximately eight Tau (τ) are required to get an
error of less than ±0.5 LSB
(1)
2.67
µs
(1)
100
2V
1.5
3V
2.0
VCC
MIN
2 V to
3.6 V
–1.4
1.4
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC
–1.1
1.1
ns
µs
12 × ADC10DIV × 1/fADC10CLK
5.31 10-Bit ADC, Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V
TYP
MAX
UNIT
EI
Integral
linearity error
ED
Differential
linearity error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)
2 V to
3.6 V
–1
1
LSB
EO
Offset error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)
2 V to
3.6 V
–6.5
6.5
mV
Gain error, external
reference
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)
2 V to
3.6 V
–1.2
1.2
LSB
–4%
4%
–2
2
–4%
4%
EG
ET
(1)
34
Gain error, internal
reference (1)
Total unadjusted
error, external
reference
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)
Total unadjusted
error, internal
reference (1)
2 V to
3.6 V
LSB
LSB
Error is dominated by the internal reference.
Specifications
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
5.32 REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
(1)
TYP
MAX
UNIT
VeREF+
Positive external reference voltage input
VeREF+ > VeREF–
(2)
1.4
AVCC
V
VeREF–
Negative external reference voltage input
VeREF+ > VeREF–
(3)
0
1.2
V
VeREF+ > VeREF–
(4)
1.4
AVCC
V
–6
6
(VeREF+ –
Differential external reference voltage input
VREF–/VeREF–)
IVeREF+,
IVeREF–
Static input current
CVREF+,
CVREF(1)
(2)
(3)
(4)
(5)
1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF– = 0 V,
fADC10CLK = 5 MHz,
ADC10SHTx = 1h,
Conversion rate 200 ksps
2.2 V, 3 V
1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF– = 0 V,
fADC10CLK = 5 MHz,
ADC10SHTx = 8h,
Conversion rate 20 ksps
2.2 V, 3 V
µA
Capacitance at VREF+ or VREF- terminal (5)
–1
1
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_B. Also see the MSP430FR57xx Family User's Guide.
5.33 REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Positive built-in reference
voltage output
VREF+
AVCC minimum voltage,
Positive built-in reference
active
AVCC(min)
TEST CONDITIONS
2.4
2.5
2.6
3V
1.92
2.0
2.08
REFVSEL = {0} for 1.5 V, REFON = 1
3V
1.44
1.5
1.56
REFVSEL = {0} for 1.5 V
2.0
REFVSEL = {1} for 2 V
2.2
REFVSEL = {2} for 2.5 V
2.7
TREF+
Temperature coefficient of
built-in reference
REFVSEL = (0, 1, 2}, REFON = 1
(1)
(2)
Settling time of reference
voltage (2)
MAX
3V
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0
tSETTLE
TYP
REFVSEL = {1} for 2 V, REFON = 1
Operating supply current into
AVCC terminal (1)
Power supply rejection ratio
(DC)
MIN
REFVSEL = {2} for 2.5 V, REFON = 1
IREF+
PSRR_DC
VCC
3V
V
V
33
45
±35
AVCC = AVCC (min) - AVCC(max),
TA = 25°C, REFON = 1,
REFVSEL = (0} for 1.5 V
1600
AVCC = AVCC (min) - AVCC(max),
TA = 25°C, REFON = 1,
REFVSEL = (1} for 2 V
1900
AVCC = AVCC (min) - AVCC(max),
TA = 25°C, REFON = 1,
REFVSEL = (2} for 2.5 V
3600
AVCC = AVCC (min) - AVCC(max),
REFVSEL = (0, 1, 2}, REFON = 0 → 1
UNIT
30
µA
ppm/
°C
µV/V
µs
The internal reference current is supplied by terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
Specifications
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产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
35
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
5.34 REF, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VSENSOR
See
TEST CONDITIONS
(1)
TCSENSOR
VCC
ADC10ON = 1, INCH = 0Ah,
TA = 0°C
2 V, 3 V
ADC10ON = 1, INCH = 0Ah
2 V, 3 V
MIN
MAX
mV
2.55
mV/°C
tSENSOR(sample)
Sample time required if
channel 10 is selected (2)
ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
3V
30
VMID
AVCC divider at channel 11
ADC10ON = 1, INCH = 0Bh,
VMID is ~0.5 × VAVCC
2V
0.97
1.0
1.03
3V
1.46
1.5
1.54
tVMID(sample)
Sample time required if
channel 11 is selected (3)
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2 V, 3 V
1000
(2)
(3)
UNIT
790
2V
(1)
30
TYP
µs
V
ns
The temperature sensor offset can vary significantly. A single-point calibration is recommended to minimize the offset error of the built-in
temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
1050
Typical Temperature Sensor Voltage (mA)
1000
950
900
850
800
750
700
650
600
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Ambient Temperature (°C)
图 5-11. Typical Temperature Sensor Voltage
36
Specifications
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
5.35 Comparator_D
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Overdrive = 10 mV,
VIN- = (VIN+ – 400 mV) to (VIN+ + 10 mV)
Propagation delay,
AVCC = 2 V to 3.6 V
tpd
MIN
TYP
MAX
50
100
200
Overdrive = 100 mV,
VIN- = (VIN+ – 400 mV) to (VIN+ + 100 mV)
80
Overdrive = 250 mV,
(VIN+ – 400 mV) to (VIN+ + 250 mV)
50
UNIT
ns
CDF = 1, CDFDLY = 00
0.3
0.5
0.9
CDF = 1, CDFDLY = 01
0.5
0.9
1.5
CDF = 1, CDFDLY = 10
0.9
1.6
2.8
3.0
5.5
tfilter
Filter timer added to the
propagation delay of the
comparator
CDF = 1, CDFDLY = 11
1.6
Voffset
Input offset
AVCC = 2 V to 3.6 V
–20
Vic
Common mode input range
AVCC = 2 V to 3.6 V
0
AVCC - 1
V
Icomp(AVCC)
Comparator only
CDON = 1, AVCC = 2 V to 3.6 V
29
34
µA
Iref(AVCC)
Reference buffer and R‑ladder
CDREFLx = 01, AVCC = 2 V to 3.6 V
20
24
µA
tenable,comp
Comparator enable time
CDON = 0 to CDON = 1,
AVCC = 2 V to 3.6 V
1.1
2.0
µs
tenable,rladder
Resistor ladder enable time
CDON = 0 to CDON = 1,
AVCC = 2 V to 3.6 V
1.1
2.0
µs
VCB_REF
Reference voltage for a tap
VIN = voltage input to the R-ladder,
n = 0 to 31
VIN ×
(n + 1)
/ 32
VIN ×
(n + 1.5)
/ 32
V
VIN ×
(n + 0.5)
/ 32
20
µs
mV
5.36 FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
DVCC(WRITE)
Write supply voltage
tWRITE
Word or byte write time
tACCESS
Read access time
TEST CONDITIONS
2.0
(1)
(1)
tPRECHARGE
Precharge time
tCYCLE
Cycle time, read or write operation
(1)
(1)
Data retention duration
TYP
MAX
V
120
ns
60
ns
60
ns
15
10
TJ = 25°C
100
TJ = 70°C
40
TJ = 85°C
10
UNIT
3.6
120
Read and write endurance
tRetention
MIN
ns
cycles
years
When using manual wait state control, see the MSP430FR57xx Family User's Guide for recommended settings for common system
frequencies.
Specifications
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
37
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
5.37 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2 V, 3 V
0.025
15
µs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)
1
µs
tSBW,Rst
Spy-Bi-Wire return to normal operation time
35
µs
fTCK
TCK input frequency, 4-wire JTAG
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
38
(2)
(1)
2 V, 3 V
19
2V
0
5
3V
0
10
2 V, 3 V
20
35
50
MHz
kΩ
Tools that access the Spy-Bi-Wire and BSL interfaces must wait for the tSBW,En time after the first transition of the TEST/SBWTCK pin
(low to high), before the second transition of the pin (high to low) during the entry sequence.
fTCK may be restricted to meet the timing requirements of the module selected.
Specifications
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6 Detailed Description
6.1
Functional Block Diagrams
图 6-1 shows the functional block diagram for the MSP430FR5721, MSP430FR5725, and
MSP430FR5729 in the RHA package.
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16KB
Clock
System
ACLK
8KB
SMCLK
4KB
(FR5721)
FRAM
MCLK
CPUXV2
and
Working
Registers
1KB
Boot
ROM
Power
Management
SYS
Watchdog
P3.x
I/O Ports
P1/P2
2×8 I/Os
(FR5729)
(FR5725)
PA
P2.x
REF
Interrupt,
Wake up
PA
1×16 I/Os
SVS
RAM
Memory
Protection
Unit
PB
P4.x
I/O Ports
P3/P4
1×8 I/Os
1x 2 I/Os
Interrupt,
Wake up
PB
1×10 I/Os
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
TA0
TA1
JTAG,
SBW
Interface
TB0
TB1
TB2
RTC_B
MPY32
(2) Timer_A
3 CC
Registers
(3) Timer_B
3 CC
Registers
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
eUSCI_A1:
UART,
IrDA, SPI
ADC10_B
10 bit
200 ksps
Comp_D
16 channels
14 channels
(12 ext/2 int)
Copyright © 2016, Texas Instruments Incorporated
图 6-1. Functional Block Diagram – RHA Package – MSP430FR5721, MSP430FR5725, MSP430FR5729
图 6-2 shows the functional block diagram for the MSP430FR5723 and MSP430FR5727 devices in the
RHA package.
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
39
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
PJ.4/XIN
www.ti.com.cn
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16KB
Clock
System
ACLK
8KB
SMCLK
FRAM
MCLK
CPUXV2
and
Working
Registers
1KB
Boot
ROM
Power
Management
P3.x
I/O Ports
P1/P2
2×8 I/Os
(FR5727)
(FR5723)
PA
P2.x
SYS
Watchdog
Interrupt,
Wake up
PA
1×16 I/Os
SVS
RAM
Memory
Protection
Unit
PB
P4.x
I/O Ports
P3/P4
1×8 I/Os
1x 2 I/Os
Interrupt,
Wake up
PB
1×10 I/Os
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG,
SBW
Interface
TA0
TA1
TB0
TB1
TB2
(2) Timer_A
3 CC
Registers
(3) Timer_B
3 CC
Registers
RTC_B
MPY32
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
eUSCI_A1:
UART,
IrDA, SPI
Comp_D
REF
16 channels
Copyright © 2016, Texas Instruments Incorporated
图 6-2. Functional Block Diagram – RHA Package – MSP430FR5723, MSP430FR5727
40
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
图 6-3 shows the functional block diagram for the MSP430FR5721, MSP430FR5725, and
MSP430FR5729 devices in the DA package.
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16KB
Clock
System
ACLK
(FR5729)
8KB
(FR5725)
SMCLK
1KB
4KB
(FR5721)
CPUXV2
and
Working
Registers
SYS
Watchdog
PB
P3.x
I/O Ports
P1/P2
2×8 I/Os
I/O Ports
P3
1×8 I/Os
Interrupt,
Wake up
PA
1×16 I/Os
Interrupt,
Wake up
PB
1×8 I/Os
REF
SVS
FRAM
MCLK
Power
Management
Boot
ROM
PA
P2.x
RAM
Memory
Protection
Unit
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG,
SBW
Interface
TA0
TA1
TB0
TB1
TB2
(2) Timer_A
3 CC
Registers
(3) Timer_B
3 CC
Registers
RTC_B
MPY32
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_A1:
UART,
IrDA, SPI
ADC10_B
10 bit
200 ksps
Comp_D
16 channels
eUSCI_B0:
SPI, I2C
14 channels
(12 ext/2 int)
Copyright © 2016, Texas Instruments Incorporated
图 6-3. Functional Block Diagram – DA Package – MSP430FR5721, MSP430FR5725, MSP430FR5729
图 6-4 shows the functional block diagram for the MSP430FR5723 and MSP430FR5727 devices in the DA
package.
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16KB
Clock
System
ACLK
(FR5727)
8KB
(FR5723)
SMCLK
FRAM
MCLK
CPUXV2
and
Working
Registers
1KB
Boot
ROM
Power
Management
SYS
PA
P2.x
PB
P3.x
I/O Ports
P1/P2
2×8 I/Os
I/O Ports
P3
1×8 I/Os
Interrupt,
Wake up
PA
1×16 I/Os
Interrupt,
Wake up
PB
1×8 I/Os
Watchdog
SVS
RAM
Memory
Protection
Unit
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG,
SBW
Interface
TA0
TA1
TB0
TB1
TB2
(2) Timer_A
3 CC
Registers
(3) Timer_B
3 CC
Registers
RTC_B
MPY32
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
eUSCI_A1:
UART,
IrDA, SPI
Comp_D
REF
16 channels
Copyright © 2016, Texas Instruments Incorporated
图 6-4. Functional Block Diagram – DA Package – MSP430FR5723, MSP430FR5727
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
41
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
图 6-5 shows the functional block diagram for the MSP430FR5720, MSP430FR5724, and
MSP430FR5728 devices in the RGE package.
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16KB
Clock
System
ACLK
SMCLK
8KB
4KB
CPUXV2
and
Working
Registers
1KB
(FR5720)
FRAM
MCLK
I/O Ports
P1/P2
1×8 I/Os
1×3 I/Os
(FR5728)
(FR5724)
Power
Management
Boot
ROM
SYS
Watchdog
PA
P2.x
REF
SVS
Interrupt,
Wake up
PA
1×11 I/Os
RAM
Memory
Protection
Unit
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG,
SBW
Interface
TA0
TA1
TB0
(2) Timer_A
3 CC
Registers
(1) Timer_B
3 CC
Registers
RTC_B
MPY32
CRC
ADC10_B
eUSCI_A0:
UART,
IrDA, SPI
10 bit
200 ksps
Comp_D
10 channels
eUSCI_B0:
SPI, I2C
8 channels
(6 ext/2 int)
Copyright © 2016, Texas Instruments Incorporated
图 6-5. Functional Block Diagram – RGE Package – MSP430FR5720, MSP430FR5724, MSP430FR5728
图 6-6 shows the functional block diagram for the MSP430FR5722 and MSP430FR5726 devices in the
RGE package.
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16KB
Clock
System
ACLK
(FR5722)
SMCLK
FRAM
MCLK
CPUXV2
and
Working
Registers
I/O Ports
P1/P2
1×8 I/Os
1×3 I/Os
(FR5726)
8KB
1KB
Boot
ROM
Power
Management
PA
P2.x
SYS
Watchdog
SVS
Interrupt,
Wake up
PA
1×11 I/Os
RAM
Memory
Protection
Unit
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG,
SBW
Interface
TA0
TA1
TB0
(2) Timer_A
3 CC
Registers
(1) Timer_B
3 CC
Registers
RTC_B
MPY32
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
Comp_D
REF
10 channels
Copyright © 2016, Texas Instruments Incorporated
图 6-6. Functional Block Diagram – RGE Package – MSP430FR5722, MSP430FR5726
42
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
图 6-7 shows the functional block diagram for the MSP430FR5720, MSP430FR5724, and
MSP430FR5728 devices in the PW package.
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16KB
Clock
System
ACLK
(FR5728)
8KB
(FR5724)
SMCLK
1KB
4KB
(FR5720)
CPUXV2
and
Working
Registers
Boot
ROM
SYS
Watchdog
REF
SVS
FRAM
MCLK
Power
Management
PA
P2.x
I/O Ports
P1/P2
1×8 I/Os
1×7 I/Os
Interrupt,
Wake up
PA
1×15 I/Os
RAM
Memory
Protection
Unit
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG,
SBW
Interface
TA0
TA1
TB0
(2) Timer_A
3 CC
Registers
(1) Timer_B
3 CC
Registers
RTC_B
MPY32
CRC
ADC10_B
eUSCI_A0:
UART,
IrDA, SPI
10 bit
200 ksps
Comp_D
12 channels
eUSCI_B0:
SPI, I2C
10 channels
(8 ext/2 int)
Copyright © 2016, Texas Instruments Incorporated
图 6-7. Functional Block Diagram – PW Package – MSP430FR5720, MSP430FR5724, MSP430FR5728
图 6-8 shows the functional block diagram for the MSP430FR5722 and MSP430FR5726 devices in the
PW package.
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16KB
Clock
System
ACLK
(FR5722)
SMCLK
FRAM
MCLK
CPUXV2
and
Working
Registers
I/O Ports
P1/P2
1×8 I/Os
1×7 I/Os
(FR5726)
8KB
1KB
Boot
ROM
Power
Management
PA
P2.x
SYS
Watchdog
SVS
Interrupt,
Wake up
PA
1×15 I/Os
RAM
Memory
Protection
Unit
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG,
SBW
Interface
TA0
TA1
TB0
(2) Timer_A
3 CC
Registers
(1) Timer_B
3 CC
Registers
RTC_B
MPY32
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
Comp_D
REF
12 channels
Copyright © 2016, Texas Instruments Incorporated
图 6-8. Functional Block Diagram – PW Package – MSP430FR5722, MSP430FR5726
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
43
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.2
www.ti.com.cn
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
6.3
Operating Modes
The MSP430 has one active mode and seven software-selectable low-power modes of operation. An
interrupt event can wake up the device from low-power modes LPM0 through LPM4, service the request,
and restore back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5
and LPM4.5 disable the core supply to minimize power consumption.
The following eight operating modes can be configured by software:
• Active mode (AM)
• Low-power mode 3 (LPM3)
– All clocks are active
– CPU is disabled
– ACLK active
• Low-power mode 0 (LPM0)
– MCLK and SMCLK disabled
– CPU is disabled
– DCO disabled
– ACLK active
– Complete data retention
– MCLK disabled
– SMCLK optionally active
• Low-power mode 4 (LPM4)
– Complete data retention
– CPU is disabled
– ACLK, MCLK, SMCLK disabled
• Low-power mode 1 (LPM1)
– Complete data retention
– CPU is disabled
– ACLK active
• Low-power mode 3.5 (LPM3.5)
– MCLK disabled
– RTC operation
– SMCLK optionally active
– Internal regulator disabled
– DCO disabled
– No data retention
– Complete data retention
– I/O pad state retention
– Wake-up input from RST, general• Low-power mode 2 (LPM2)
purpose I/O, RTC events
– CPU is disabled
•
Low-power
mode 4.5 (LPM4.5)
– ACLK active
– Internal regulator disabled
– MCLK disabled
– No data retention
– SMCLK optionally active
– I/O pad state retention
– DCO disabled
– Wake-up input from RST and general– Complete data retention
purpose I/O
44
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
6.4
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see 表
6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
表 6-1. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power-Up, Brownout, Supply
Supervisors
External Reset RST
Watchdog Time-out (Watchdog
mode)
WDT, FRCTL MPU, CS, PMM
Password Violation
FRAM double bit error detection
MPU segment violation
Software POR, BOR
SVSLIFG, SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
DBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
PMMPORIFG, PMMBORIFG
(SYSRSTIV) (1) (2)
Reset
0FFFEh
63, highest
System NMI
Vacant Memory Access
JTAG Mailbox
FRAM access time error
FRAM single, double bit error
detection
VMAIFG
JMBNIFG, JMBOUTIFG
ACCTIMIFG
SBDIFG, DBDIFG
(SYSSNIV) (1)
(Non)maskable
0FFFCh
62
User NMI
External NMI
Oscillator Fault
NMIIFG, OFIFG
(SYSUNIV) (1) (2)
(Non)maskable
0FFFAh
61
Comparator_D
Comparator_D interrupt flags
(CBIV) (1) (3)
Maskable
0FFF8h
60
TB0
TB0CCR0 CCIFG0
(3)
Maskable
0FFF6h
59
TB0
TB0CCR1 CCIFG1 to TB0CCR2 CCIFG2,
TB0IFG
(TB0IV) (1) (3)
Maskable
0FFF4h
58
Watchdog Timer
(Interval Timer Mode)
WDTIFG
Maskable
0FFF2h
57
eUSCI_A0 Receive and Transmit
UCA0RXIFG, UCA0TXIFG (SPI mode)
UCA0STTIFG, UCA0TXCPTIFG, UCA0RXIFG,
UXA0TXIFG (UART mode)
(UCA0IV) (1) (3)
Maskable
0FFF0h
56
eUSCI_B0 Receive and Transmit
UCB0STTIFG, UCB0TXCPTIFG, UCB0RXIFG,
UCB0TXIFG (SPI mode)
UCB0ALIFG, UCB0NACKIFG, UCB0STTIFG,
UCB0STPIFG, UCB0RXIFG0, UCB0TXIFG0,
UCB0RXIFG1, UCB0TXIFG1, UCB0RXIFG2,
UCB0TXIFG2, UCB0RXIFG3, UCB0TXIFG3,
UCB0CNTIFG, UCB0BIT9IFG (I2C mode)
(UCB0IV) (1) (3)
Maskable
0FFEEh
55
ADC10_B
ADC10OVIFG, ADC10TOVIFG, ADC10HIIFG,
ADC10LOIFG
ADC10INIFG, ADC10IFG0
(ADC10IV) (1) (3) (4)
Maskable
0FFECh
54
Maskable
0FFEAh
53
Maskable
0FFE8h
52
TA0
TA0
(1)
(2)
(3)
(4)
TA0CCR0 CCIFG0
(3)
TA0CCR1 CCIFG1 to TA0CCR2 CCIFG2,
TA0IFG
(TA0IV) (1) (3)
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
Only on devices with ADC, otherwise reserved.
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
45
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 6-1. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
eUSCI_A1 Receive and Transmit
UCA1RXIFG, UCA1TXIFG (SPI mode)
UCA1STTIFG, UCA1TXCPTIFG, UCA1RXIFG,
UXA1TXIFG (UART mode)
(UCA1IV) (1) (3)
Maskable
0FFE6h
51
DMA
DMA0IFG, DMA1IFG, DMA2IFG
(DMAIV) (1) (3)
Maskable
0FFE4h
50
Maskable
0FFE2h
49
TA1
TA1
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG
(TA1IV) (1) (3)
Maskable
0FFE0h
48
I/O Port P1
P1IFG.0 to P1IFG.7
(P1IV) (1) (3)
Maskable
0FFDEh
47
TB1
Maskable
0FFDCh
46
TB1
Maskable
0FFDAh
45
I/O Port P2
P2IFG.0 to P2IFG.7
(P2IV) (1) (3)
Maskable
0FFD8h
44
TB2CCR0 CCIFG0
(3)
Maskable
0FFD6h
43
TB2
TB2CCR1 CCIFG1 to TB2CCR2 CCIFG2,
TB2IFG
(TB2IV) (1) (3)
Maskable
0FFD4h
42
I/O Port P3
P3IFG.0 to P3IFG.7
(P3IV) (1) (3)
Maskable
0FFD2h
41
I/O Port P4
P4IFG.0 to P4IFG.2
(P4IV) (1) (3)
Maskable
0FFD0h
40
RTC_B
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG
(RTCIV) (1) (3)
Maskable
0FFCEh
39
0FFCCh
38
Reserved
46
TB1CCR0 CCIFG0
(3)
TB1CCR1 CCIFG1 to TB1CCR2 CCIFG2,
TB1IFG
(TB1IV) (1) (3)
TB2
(5)
TA1CCR0 CCIFG0
(3)
Reserved
(5)
⋮
⋮
0FF80h
0, lowest
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
Detailed Description
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
6.5
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
Memory Organization
表 6-2 describes the memory organization for all device variants.
表 6-2. Memory Organization (1) (2)
MSP430FR5726
MSP430FR5727
MSP430FR5728
MSP430FR5729
MSP430FR5722
MSP430FR5723
MSP430FR5724
MSP430FR5725
MSP430FR5720
MSP430FR5721
15.5KB
00FFFFh–00FF80h
00FF7Fh–00C200h
8.0KB
00FFFFh–00FF80h
00FF7Fh–00E000h
4KB
00FFFFh–00FF80h
00FF7Fh–00F000h
RAM
1KB
001FFFh–001C00h
1KB
001FFFh–001C00h
1KB
001FFFh–001C00h
Device Descriptor Info
(TLV) (FRAM)
128 B
001A7Fh–001A00h
128 B
001A7Fh–001A00h
128 B
001A7Fh–001A00h
N/A
0019FFh–001980h
Address space mirrored to
Info A
0019FFh–001980h
Address space mirrored to
Info A
0019FFh–001980h
Address space mirrored to
Info A
N/A
00197Fh–001900h
Address space mirrored to
Info B
00197Fh–001900h
Address space mirrored to
Info B
00197Fh–001900h
Address space mirrored to
Info B
Info A
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
Info B
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
BSL 3
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
BSL 2
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
BSL 1
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
BSL 0
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
4KB
000FFFh–0h
4KB
000FFFh–0h
4KB
000FFFh–0h
Memory (FRAM)
Main: interrupt vectors
Main: code memory
Information memory
(FRAM)
Bootloader (BSL)
memory (ROM)
Peripherals
(1)
(2)
Total Size
Size
N/A = Not available
All address space not listed in this table is considered vacant memory.
Detailed Description
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
47
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.6
www.ti.com.cn
Bootloader (BSL)
The BSL enables users to program the FRAM or RAM using a UART serial interface. Access to the device
memory by the BSL is protected by an user-defined password. Use of the BSL requires four pins (see 表
6-3). BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins.
For complete description of the features of the BSL and its implementation, see the MSP430
Programming With the Bootloader User's Guide.
表 6-3. BSL Pin Requirements and Functions
6.7
6.7.1
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P2.0
Data transmit
P2.1
Data receive
VCC
Power supply
VSS
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. 表 6-4 lists the JTAG pin requirements. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools
User's Guide. For a complete description of the features of the JTAG interface and its implementation, see
MSP430 Programming Via the JTAG Interface.
表 6-4. JTAG Pin Requirements and Functions
48
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
Detailed Description
VCC
Power supply
VSS
Ground supply
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
6.7.2
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. 表 6-5
lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the
features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface.
表 6-5. Spy-Bi-Wire Pin Requirements and Functions
6.8
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
VCC
Power supply
VSS
Ground supply
FRAM
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
• Low-power ultra-fast write nonvolatile memory
• Byte and word access capability
• Programmable and automated wait state generation
• Error correction coding (ECC) with single bit detection and correction, double bit detection
For important software design information regarding FRAM including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the memory protection unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
MSP430™ FRAM Technology – How To and Best Practices.
6.9
Memory Protection Unit (MPU)
The FRAM can be protected from inadvertent CPU execution or write access by the MPU. Features of the
MPU include:
• Main memory partitioning programmable up to three segments
• Access rights for each segment (main and information memory) can be individually selected
• Access violation flags with interrupt capability for easy servicing of access violations
6.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430FR57xx Family User's
Guide.
6.10.1 Digital I/O
Up to four 8-bit I/O ports are implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all ports.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
Detailed Description
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
49
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
6.10.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch crystal oscillator XT1 (LF mode), an internal verylow-power low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator XT1 (HF mode). The clock system module is designed to meet the
requirements of both low system cost and low power consumption. A fail-safe mechanism exists for all
crystal sources. The clock system module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1 LF mode), a high-frequency crystal
(XT1 HF mode), the internal VLO, or the internal DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by the same sources
made available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by the same sources made available to ACLK.
6.10.3 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is
available on the primary and core supplies.
6.10.4 Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication
as well as signed and unsigned multiply-and-accumulate operations.
6.10.5 Real-Time Clock (RTC_B)
The RTC_B module contains an integrated real-time clock (RTC) (calendar mode). Calendar mode
integrates an internal calendar which compensates for months with fewer than 31 days and includes leap
year correction. The RTC_B also supports flexible alarm functions and offset-calibration hardware. RTC
operation is available in LPM3.5 mode to minimize power consumption.
6.10.6 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
6.10.7 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset
(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators (see 表 6-6), bootloader entry mechanisms, and configuration management (device
descriptors). It also includes a data exchange mechanism using JTAG called a JTAG mailbox that can be
used in the application.
50
Detailed Description
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
表 6-6. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
SYSRSTIV,
System Reset
SYSSNIV, System NMI
ADDRESS
019Eh
019Ch
INTERRUPT EVENT
No interrupt pending
00h
Brownout (BOR)
02h
RSTIFG RST/NMI (BOR)
04h
PMMSWBOR software BOR (BOR)
06h
LPMx.5 wake up (BOR)
08h
Security violation (BOR)
0Ah
SVSLIFG SVSL event (BOR)
0Ch
SVSHIFG SVSH event (BOR)
0Eh
Reserved
10h
Reserved
12h
PMMSWPOR software POR (POR)
14h
WDTIFG watchdog time-out (PUC)
16h
WDTPW password violation (PUC)
18h
FRCTLPW password violation (PUC)
1Ah
DBDIFG FRAM double bit error (PUC)
1Ch
Peripheral area fetch (PUC)
1Eh
PMMPW PMM password violation (PUC)
20h
MPUPW MPU password violation (PUC)
22h
CSPW CS password violation (PUC)
24h
MPUSEGIIFG information memory segment violation (PUC)
26h
MPUSEG1IFG segment 1 memory violation (PUC)
28h
MPUSEG2IFG segment 2 memory violation (PUC)
2Ah
MPUSEG3IFG segment 3 memory violation (PUC)
2Ch
Reserved
2Eh
Reserved
30h to 3Eh
No interrupt pending
00h
DBDIFG FRAM double bit error
02h
ACCTIMIFG access time error
04h
Reserved
0Eh
VMAIFG Vacant memory access
10h
JMBINIFG JTAG mailbox input
12h
JMBOUTIFG JTAG mailbox output
14h
SBDIFG FRAM single bit error
Reserved
SYSUNIV, User NMI
019Ah
VALUE
PRIORITY
Highest
Lowest
Highest
16h
18h to 1Eh
No interrupt pending
00h
NMIIFG NMI pin
02h
OFIFG oscillator fault
04h
Reserved
06h
Reserved
08h
Reserved
0Ah to 1Eh
Lowest
Highest
Lowest
Detailed Description
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
51
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
6.10.8 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC10_B conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. 表 6-7 lists all triggers to start DMA transfers.
表 6-7. DMA Trigger Assignments
TRIGGER
CHANNEL 0
CHANNEL 1
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
5
Reserved
Reserved
Reserved
6
Reserved
Reserved
Reserved
7
TB0CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR0 CCIFG
8
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB1CCR0 CCIFG
TB1CCR0 CCIFG
(2)
TB1CCR0 CCIFG
(2)
10
TB1CCR2 CCIFG
(2)
TB1CCR2 CCIFG
(2)
TB1CCR2 CCIFG
(2)
11
TB2CCR0 CCIFG
(3)
TB2CCR0 CCIFG
(3)
TB2CCR0 CCIFG
(3)
TB2CCR2 CCIFG
(3)
TB2CCR2 CCIFG
(3)
TB2CCR2 CCIFG
(3)
12
13
Reserved
Reserved
Reserved
14
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
15
16
17
18
(1)
(2)
(3)
(4)
(5)
CHANNEL 2
(2)
9
52
(1)
UCA0TXIFG
UCA1RXIFG
(4)
UCA1TXIFG
(4)
UCB0RXIFG0
UCA0TXIFG
UCA1RXIFG
(4)
UCA1TXIFG
(4)
UCB0RXIFG0
UCA0TXIFG
UCA1RXIFG
(4)
UCA1TXIFG
(4)
UCB0RXIFG0
19
UCB0TXIFG0
UCB0TXIFG0
UCB0TXIFG0
20
UCB0RXIFG1
UCB0RXIFG1
UCB0RXIFG1
21
UCB0TXIFG1
UCB0TXIFG1
UCB0TXIFG1
22
UCB0RXIFG2
UCB0RXIFG2
UCB0RXIFG2
23
UCB0TXIFG2
UCB0TXIFG2
UCB0TXIFG2
24
UCB0RXIFG3
UCB0RXIFG3
UCB0RXIFG3
25
UCB0TXIFG3
26
ADC10IFGx
27
Reserved
Reserved
Reserved
28
Reserved
Reserved
Reserved
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
DMA1IFG
31
DMAE0
DMAE0
DMAE0
(5)
UCB0TXIFG3
ADC10IFGx
(5)
UCB0TXIFG3
ADC10IFGx
(5)
If a reserved trigger source is selected, no trigger is generated.
Only on devices with TB1, otherwise reserved
Only on devices with TB2, otherwise reserved
Only on devices with eUSCI_A1, otherwise reserved
Only on devices with ADC, otherwise reserved
Detailed Description
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.10.9 Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication
protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each eUSCI
module contains two portions, A and B.
The eUSCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA.
The eUSCI_Bn module provides support for SPI (3-pin or 4-pin) or I2C.
The MSP430FR572x series include one or two eUSCI_An modules (eUSCI_A0, eUSCI_A1) and one
eUSCI_Bn module (eUSCI_B).
6.10.10 TA0, TA1
TA0 and TA1 are 16-bit timers/counters (Timer_A type) with three capture/compare registers each. TA0
and TA1 can support multiple capture/compares, PWM outputs, and interval timing (see 表 6-8 and 表 69). TA0 and TA1 have extensive interrupt capabilities. Interrupts may be generated from the counter on
overflow conditions and from each of the capture/compare registers.
表 6-8. TA0 Signal Connections
RHA
INPUT PIN NUMBER
RGE
DA
PW
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
3-P1.2
3-P1.2
7-P1.2
7-P1.2
TA0CLK
TACLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
OUTPUT PIN NUMBER
RHA
RGE
DA
PW
3-P1.2
3-P1.2
7-P1.2
7-P1.2
TA0CLK
TACLK
28-P1.6
16-P1.6
30-P1.6
22-P1.6
TA0.0
CCI0A
28-P1.6
16-P1.6
30-P1.6
22-P1.6
34-P2.3
N/A
36-P2.3
27-P2.3
TA0.0
CCI0B
34-P2.3
N/A
36-P2.3
27-P2.3
DVSS
GND
1-P1.0
1-P1.0
5-P1.0
5-P1.0
CCR0
1-P1.0
2-P1.1
(1)
1-P1.0
2-P1.1
5-P1.0
6-P1.1
5-P1.0
6-P1.1
DVCC
VCC
TA0.1
CCI1A
CDOUT
(internal)
CCI1B
DVSS
GND
CCR1
DVCC
VCC
TA0.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
TA0
TA1
TA0.0
TA0.1
ADC10
ADC10
ADC10
ADC10
(internal) (1)
(internal) (1)
(internal) (1)
(internal) (1)
ADC10SHSx = ADC10SHSx = ADC10SHSx = ADC10SHSx =
{1}
{1}
{1}
{1}
2-P1.1
CCR2
TA2
2-P1.1
6-P1.1
6-P1.1
TA0.2
Only on devices with ADC
Detailed Description
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MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
53
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 6-9. TA1 Signal Connections
RHA
INPUT PIN NUMBER
RGE
DA
PW
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
2-P1.1
2-P1.1
6-P1.1
6-P1.1
TA1CLK
TACLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
OUTPUT PIN NUMBER
RHA
RGE
DA
PW
2-P1.1
2-P1.1
6-P1.1
6-P1.1
TA1CLK
TACLK
29-P1.7
17-P1.7
31-P1.7
23-P1.7
TA1.0
CCI0A
29-P1.7
17-P1.7
31-P1.7
23-P1.7
35-P2.4
N/A
37-P2.4
28-P2.4
TA1.0
CCI0B
35-P2.4
N/A
37-P2.4
28-P2.4
DVSS
GND
3-P1.2
3-P1.2
7-P1.2
7-P1.2
8-P1.3
4-P1.3
12-P1.3
8-P1.3
CCR0
3-P1.2
8-P1.3
54
3-P1.2
4-P1.3
7-P1.2
12-P1.3
Detailed Description
7-P1.2
8-P1.3
DVCC
VCC
TA1.1
CCI1A
CDOUT
(internal)
CCI1B
DVSS
GND
CCR1
DVCC
VCC
TA1.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
CCR2
TA0
TA1
TA2
TA1.0
TA1.1
TA1.2
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.10.11 TB0, TB1, TB2
TB0, TB1, and TB2 are 16-bit timers/counters (Timer_B type) with three capture/compare registers each.
TB0, TB1, and TB2 can support multiple capture/compares, PWM outputs, and interval timing (see 表 610 through 表 6-12). TB0, TB1, and TB2 have extensive interrupt capabilities. Interrupts may be generated
from the counter on overflow conditions and from each of the capture/compare registers.
表 6-10. TB0 Signal Connections
RHA
INPUT PIN NUMBER
RGE
DA
PW
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
21-P2.0
13-P2.0
23-P2.0
19-P2.0
TB0CLK
TBCLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
OUTPUT PIN NUMBER
RHA
RGE
DA
PW
21-P2.0
13-P2.0
23-P2.0
19-P2.0
TB0CLK
TBCLK
22-P2.1
14-P2.1
24-P2.1
20-P2.1
TB0.0
CCI0A
22-P2.1
14-P2.1
24-P2.1
20-P2.1
17-P2.5
N/A
19-P2.5
15-P2.5
TB0.0
CCI0B
17-P2.5
N/A
19-P2.5
15-P2.5
CCR0
DVSS
9-P1.4
10-P1.5
(1)
5-P1.4
6‑P1.5
13-P1.4
14-P1.5
9-P1.4
19-P1.5
TB0
TB0.0
GND
DVCC
VCC
TB0.1
CCI1A
CDOUT
(internal)
CCI1B
DVSS
GND
9-P1.4
CCR1
DVCC
VCC
TB0.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
ADC10
ADC10
ADC10
ADC10
(internal) (1)
(internal) (1)
(internal) (1)
(internal) (1)
ADC10SHSx = ADC10SHSx = ADC10SHSx = ADC10SHSx =
{2}
{2}
{2}
{2}
TB1
TB0.1
10-P1.5
CCR2
TB2
5-P1.4
13-P1.4
9-P1.4
ADC10
ADC10
ADC10
ADC10
(internal) (1)
(internal) (1)
(internal) (1)
(internal) (1)
ADC10SHSx = ADC10SHSx = ADC10SHSx = ADC10SHSx =
{3}
{3}
{3}
{3}
6-P1.5
14-P1.5
19-P1.5
TB0.2
Only on devices with ADC
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
55
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 6-11. TB1 Signal Connections
RHA
INPUT PIN NUMBER
RGE
DA
PW
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
26-P3.6
N/A (DVSS)
28-P3.6
N/A (DVSS)
TB1CLK
TBCLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
(1)
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
OUTPUT PIN NUMBER
RHA
RGE
DA
PW
26-P3.6
N/A (DVSS)
28-P3.6
N/A (DVSS)
TB1CLK
TBCLK
23-P2.2
N/A (DVSS)
25-P2.2
N/A (DVSS)
TB1.0
CCI0A
23-P2.2
N/A
25-P2.2
N/A
18-P2.6
N/A (DVSS)
20-P2.6
N/A (DVSS)
TB1.0
CCI0B
18-P2.6
N/A
20-P2.6
N/A
DVSS
GND
CCR0
TB0
TB1.0
DVCC
VCC
28-P1.6
N/A (DVSS)
30-P1.6
N/A (DVSS)
TB1.1
CCI1A
28-P1.6
N/A
30-P1.6
N/A
24-P3.4
N/A (DVSS)
26-P3.4
N/A (DVSS)
TB1.1
CCI1B
24-P3.4
N/A
26-P3.4
N/A
DVSS
GND
CCR1
TB1
TB1.1
DVCC
VCC
29-P1.7
N/A (DVSS)
31-P1.7
N/A (DVSS)
TB1.2
CCI2A
29-P1.7
N/A
31-P1.7
N/A
25-P3.5
N/A (DVSS)
27-P3.5
N/A (DVSS)
TB1.2
CCI2B
25-P3.5
N/A
27-P3.5
N/A
DVSS
GND
DVCC
VCC
(1)
CCR2
TB2
TB1.2
TB1 is not present on all device types.
表 6-12. TB2 Signal Connections
RHA
INPUT PIN NUMBER
RGE
DA
PW
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
24-P3.4
N/A (DVSS)
26-P3.4
N/A (DVSS)
TB2CLK
TBCLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
(1)
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
OUTPUT PIN NUMBER
RHA
RGE
DA
PW
24-P3.4
N/A (DVSS)
26-P3.4
N/A (DVSS)
TB2CLK
TBCLK
21-P2.0
N/A (DVSS)
23-P2.0
N/A (DVSS)
TB2.0
CCI0A
21-P2.0
N/A
23-P2.0
N/A
15-P4.0
N/A (DVSS)
N/A (DVSS)
N/A (DVSS)
TB2.0
CCI0B
15-P4.0
N/A
36-P4.0
N/A
DVSS
GND
CCR0
TB0
TB2.0
DVCC
VCC
22-P2.1
N/A (DVSS)
24-P2.1
N/A (DVSS)
TB2.1
CCI1A
22-P2.1
N/A
24-P2.1
N/A
26-P3.6
N/A (DVSS)
28-P3.6
N/A (DVSS)
TB2.1
CCI1B
26-P3.6
N/A
28-P3.6
N/A
DVSS
GND
CCR1
TB1
TB2.1
DVCC
VCC
23-P2.2
N/A (DVSS)
25-P2.2
N/A (DVSS)
TB2.2
CCI2A
23-P2.2
N/A
25-P2.2
N/A
27-P3.7
N/A (DVSS)
29-P3.7
N/A (DVSS)
TB2.2
CCI2B
27-P3.7
N/A
29-P3.7
N/A
DVSS
GND
DVCC
VCC
(1)
56
CCR2
TB2
TB2.2
TB2 is not present on all device types.
Detailed Description
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提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.10.12 ADC10_B
The ADC10_B module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit
SAR core, sample select control, reference generator, and a conversion result buffer. A window
comparator with lower and an upper limits allows CPU-independent result monitoring with three window
comparator interrupt flags.
6.10.13 Comparator_D
The primary function of the Comparator_D module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
6.10.14 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
6.10.15 Shared Reference (REF)
The REF module generates all of the critical reference voltages that can be used by the various analog
peripherals in the device.
6.10.16 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
57
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
6.10.17 Peripheral File Map
表 6-13 lists the base address and offset range of all available peripherals.
表 6-13. Peripherals
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see 表 6-14)
0100h
000h–01Fh
PMM (see 表 6-15)
0120h
000h–010h
FRAM Control (see 表 6-16)
0140h
000h–00Fh
CRC16 (see 表 6-17)
0150h
000h–007h
Watchdog (see 表 6-18)
015Ch
000h–001h
CS (see 表 6-19)
0160h
000h–00Fh
SYS (see 表 6-20)
0180h
000h–01Fh
Shared Reference (see 表 6-21)
01B0h
000h–001h
Port P1, P2 (see 表 6-22)
0200h
000h–01Fh
Port P3, P4 (see 表 6-23)
0220h
000h–01Fh
Port PJ (see 表 6-24)
0320h
000h–01Fh
TA0 (see 表 6-25)
0340h
000h–02Fh
TA1 (see 表 6-26)
0380h
000h–02Fh
TB0 (see 表 6-27)
03C0h
000h–02Fh
TB1 (see 表 6-28)
0400h
000h–02Fh
TB2 (see 表 6-29)
0440h
000h–02Fh
Real-Time Clock (RTC_B) (see 表 6-30)
04A0h
000h–01Fh
32-Bit Hardware Multiplier (see 表 6-31)
04C0h
000h–02Fh
DMA General Control (see 表 6-32)
0500h
000h–00Fh
DMA Channel 0 (see 表 6-32)
0510h
000h–00Ah
DMA Channel 1 (see 表 6-32)
0520h
000h–00Ah
DMA Channel 2 (see 表 6-32)
0530h
000h–00Ah
MPU Control (see 表 6-33)
05A0h
000h–00Fh
eUSCI_A0 (see 表 6-34)
05C0h
000h–01Fh
eUSCI_A1 (see 表 6-35)
05E0h
000h–01Fh
eUSCI_B0 (see 表 6-36)
0640h
000h–02Fh
ADC10_B (see 表 6-37)
0700h
000h–03Fh
Comparator_D (see 表 6-38)
08C0h
000h–00Fh
MODULE NAME
58
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
表 6-14. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
表 6-15. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM Control 0
PMMCTL0
00h
PMM interrupt flags
PMMIFG
0Ah
PM5 control 0
PM5CTL0
10h
表 6-16. FRAM Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
FRAM control 0
FRCTLCTL0
00h
General control 0
GCCTL0
04h
General control 1
GCCTL1
06h
表 6-17. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
表 6-18. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
表 6-19. CS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CS control 0
CSCTL0
00h
CS control 1
CSCTL1
02h
CS control 2
CSCTL2
04h
CS control 3
CSCTL3
06h
CS control 4
CSCTL4
08h
CS control 5
CSCTL5
0Ah
CS control 6
CSCTL6
0Ch
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
59
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 6-20. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus Error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
表 6-21. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
表 6-22. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 selection 0
P1SEL0
0Ah
Port P1 selection 1
P1SEL1
0Ch
Port P1 interrupt vector word
P1IV
0Eh
Port P1 complement selection
P1SELC
16h
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pullup/pulldown enable
P2REN
07h
Port P2 selection 0
P2SEL0
0Bh
Port P2 selection 1
P2SEL1
0Dh
Port P2 complement selection
P2SELC
17h
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
60
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
表 6-23. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 selection 0
P3SEL0
0Ah
Port P3 selection 1
P3SEL1
0Ch
Port P3 interrupt vector word
P3IV
0Eh
Port P3 complement selection
P3SELC
16h
Port P3 interrupt edge select
P3IES
18h
Port P3 interrupt enable
P3IE
1Ah
Port P3 interrupt flag
P3IFG
1Ch
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 pullup/pulldown enable
P4REN
07h
Port P4 selection 0
P4SEL0
0Bh
Port P4 selection 1
P4SEL1
0Dh
Port P4 complement selection
P4SELC
17h
Port P4 interrupt vector word
P4IV
1Eh
Port P4 interrupt edge select
P4IES
19h
Port P4 interrupt enable
P4IE
1Bh
Port P4 interrupt flag
P4IFG
1Dh
表 6-24. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ pullup/pulldown enable
PJREN
06h
Port PJ selection 0
PJSEL0
0Ah
Port PJ selection 1
PJSEL1
0Ch
Port PJ complement selection
PJSELC
16h
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
61
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 6-25. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
TA0 counter
TA0R
10h
Capture/compare 0
TA0CCR0
12h
Capture/compare 1
TA0CCR1
14h
Capture/compare 2
TA0CCR2
16h
TA0 expansion 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
表 6-26. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1 counter
TA1R
10h
Capture/compare 0
TA1CCR0
12h
Capture/compare 1
TA1CCR1
14h
Capture/compare 2
TA1CCR2
16h
TA1 expansion 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
表 6-27. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
TB0 counter
TB0R
10h
Capture/compare 0
TB0CCR0
12h
Capture/compare 1
TB0CCR1
14h
Capture/compare 2
TB0CCR2
16h
TB0 expansion 0
TB0EX0
20h
TB0 interrupt vector
TB0IV
2Eh
62
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
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ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
表 6-28. TB1 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB1 control
TB1CTL
00h
Capture/compare control 0
TB1CCTL0
02h
Capture/compare control 1
TB1CCTL1
04h
Capture/compare control 2
TB1CCTL2
06h
TB1 counter
TB1R
10h
Capture/compare 0
TB1CCR0
12h
Capture/compare 1
TB1CCR1
14h
Capture/compare 2
TB1CCR2
16h
TB1 expansion 0
TB1EX0
20h
TB1 interrupt vector
TB1IV
2Eh
表 6-29. TB2 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB2 control
TB2CTL
00h
Capture/compare control 0
TB2CCTL0
02h
Capture/compare control 1
TB2CCTL1
04h
Capture/compare control 2
TB2CCTL2
06h
TB2 counter
TB2R
10h
Capture/compare 0
TB2CCR0
12h
Capture/compare 1
TB2CCR1
14h
Capture/compare 2
TB2CCR2
16h
TB2 expansion 0
TB2EX0
20h
TB2 interrupt vector
TB2IV
2Eh
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
63
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 6-30. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC control 1
RTCCTL1
01h
RTC control 2
RTCCTL2
02h
RTC control 3
RTCCTL3
03h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds, RTC counter 1
RTCSEC, RTCNT1
10h
RTC minutes, RTC counter 2
RTCMIN, RTCNT2
11h
RTC hours, RTC counter 3
RTCHOUR, RTCNT3
12h
RTC day of week, RTC counter 4
RTCDOW, RTCNT4
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year low
RTCYEARL
16h
RTC year high
RTCYEARH
17h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Binary-to-BCD conversion register
BIN2BCD
1Ch
BCD-to-binary conversion register
BCD2BIN
1Eh
64
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
表 6-31. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension register
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control register 0
MPY32CTL0
2Ch
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
65
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 6-32. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
00h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 destination address high
DMA0DAH
08h
DMA channel 0 transfer size
DMA0SZ
0Ah
DMA channel 1 control
DMA1CTL
00h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 destination address high
DMA1DAH
08h
DMA channel 1 transfer size
DMA1SZ
0Ah
DMA channel 2 control
DMA2CTL
00h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 destination address high
DMA2DAH
08h
DMA channel 2 transfer size
DMA2SZ
0Ah
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Ah
表 6-33. MPU Control Registers (Base Address: 05A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
MPU control 0
MPUCTL0
00h
MPU control 1
MPUCTL1
02h
MPU segmentation
MPUSEG
04h
MPU access management
MPUSAM
06h
66
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
表 6-34. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA0CTLW0
00h
eUSCI _A control word 1
UCA0CTLW1
02h
eUSCI_A baud rate 0
UCA0BR0
06h
eUSCI_A baud rate 1
UCA0BR1
07h
eUSCI_A modulation control
UCA0MCTLW
08h
eUSCI_A status
UCA0STAT
0Ah
eUSCI_A receive buffer
UCA0RXBUF
0Ch
eUSCI_A transmit buffer
UCA0TXBUF
0Eh
eUSCI_A LIN control
UCA0ABCTL
10h
eUSCI_A IrDA transmit control
UCA0IRTCTL
12h
eUSCI_A IrDA receive control
UCA0IRRCTL
13h
eUSCI_A interrupt enable
UCA0IE
1Ah
eUSCI_A interrupt flags
UCA0IFG
1Ch
eUSCI_A interrupt vector word
UCA0IV
1Eh
表 6-35. eUSCI_A1 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA1CTLW0
00h
eUSCI _A control word 1
UCA1CTLW1
02h
eUSCI_A baud rate 0
UCA1BR0
06h
eUSCI_A baud rate 1
UCA1BR1
07h
eUSCI_A modulation control
UCA1MCTLW
08h
eUSCI_A status
UCA1STAT
0Ah
eUSCI_A receive buffer
UCA1RXBUF
0Ch
eUSCI_A transmit buffer
UCA1TXBUF
0Eh
eUSCI_A LIN control
UCA1ABCTL
10h
eUSCI_A IrDA transmit control
UCA1IRTCTL
12h
eUSCI_A IrDA receive control
UCA1IRRCTL
13h
eUSCI_A interrupt enable
UCA1IE
1Ah
eUSCI_A interrupt flags
UCA1IFG
1Ch
eUSCI_A interrupt vector word
UCA1IV
1Eh
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
67
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 6-36. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_B control word 0
UCB0CTLW0
00h
eUSCI_B control word 1
UCB0CTLW1
02h
eUSCI_B bit rate 0
UCB0BR0
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
08h
eUSCI_B byte counter threshold
UCB0TBCNT
0Ah
eUSCI_B receive buffer
UCB0RXBUF
0Ch
eUSCI_B transmit buffer
UCB0TXBUF
0Eh
eUSCI_B I2C own address 0
UCB0I2COA0
14h
eUSCI_B I2C own address 1
UCB0I2COA1
16h
eUSCI_B I2C own address 2
UCB0I2COA2
18h
eUSCI_B I2C own address 3
UCB0I2COA3
1Ah
eUSCI_B received address
UCB0ADDRX
1Ch
eUSCI_B address mask
UCB0ADDMASK
1Eh
eUSCI I2C slave address
UCB0I2CSA
20h
eUSCI interrupt enable
UCB0IE
2Ah
eUSCI interrupt flags
UCB0IFG
2Ch
eUSCI interrupt vector word
UCB0IV
2Eh
表 6-37. ADC10_B Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC10_B control 0
ADC10CTL0
00h
ADC10_B control 1
ADC10CTL1
02h
ADC10_B control 2
ADC10CTL2
04h
ADC10_B window comparator low threshold
ADC10LO
06h
ADC10_B window comparator high threshold
ADC10HI
08h
ADC10_B memory control 0
ADC10MCTL0
0Ah
ADC10_B conversion memory
ADC10MEM0
12h
ADC10_B Interrupt enable
ADC10IE
1Ah
ADC10_B interrupt flags
ADC10IGH
1Ch
ADC10_B interrupt vector word
ADC10IV
1Eh
表 6-38. Comparator_D Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comparator_D control 0
CDCTL0
00h
Comparator_D control 1
CDCTL1
02h
Comparator_D control 2
CDCTL2
04h
Comparator_D control 3
CDCTL3
06h
Comparator_D interrupt
CDINT
0Ch
Comparator_D interrupt vector word
CDIV
0Eh
68
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.11 Input/Output Diagrams
6.11.1 Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
图 6-9 shows the port diagram. 表 6-39 summarizes the selection of the pin functions.
Pad Logic
External ADC reference
(P1.0, P1.1)
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P1REN.x
P1DIR.x
00
01
10
Direction
0: Input
1: Output
11
P1OUT.x
DVSS
0
DVCC
1
1
00
From module 1
01
From module 2
10
DVSS
11
P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREFP1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+
P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2
P1SEL1.x
P1SEL0.x
P1IN.x
EN
To modules
Bus
Keeper
D
图 6-9. Port P1 (P1.0 to P1.2) Diagram
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
69
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 6-39. Port P1 (P1.0 to P1.2) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.0 (I/O)
P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF-
0
(1)
(2)
(3)
70
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
1
DMAE0
0
RTCCLK
1
(2)
TA0.CCI2A
0
TA0.2
1
TA1CLK
0
CDOUT
1
P1.2 (I/O)
2
0
TA0.1
A1 (1) (2)
CD1 (1) (3)
VeREF+ (1)
P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2
P1SEL0.x
0
0
P1.1 (I/O)
1
P1SEL1.x
I: 0; O: 1
TA0.CCI1A
A0 (1) (2)
CD0 (1) (3)
VeREF- (1)
P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+
CONTROL BITS OR SIGNALS
P1DIR.x
(2)
TA1.CCI1A
0
TA1.1
1
TA0CLK
0
CDOUT
1
A2 (1) (2)
CD2 (1) (3)
X
Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Not available on all devices and package types.
Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.11.2 Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
图 6-10 shows the port diagram. 表 6-40 summarizes the selection of the pin functions.
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P1REN.x
P1DIR.x
00
From module 2
10
01
Direction
0: Input
1: Output
11
P1OUT.x
00
From module 1
01
From module 2
10
DVSS
11
DVSS
0
DVCC
1
1
P1.3/TA1.2/UCB0STE/A3/CD3
P1.4/TB0.1/UCA0STE/A4/CD4
P1.5/TB0.2/UCA0CLK/A5/CD5
P1SEL1.x
P1SEL0.x
P1IN.x
Bus
Keeper
EN
To modules
D
图 6-10. Port P1 (P1.3 to P1.5) Diagram
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
71
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 6-40. Port P1 (P1.3 to P1.5) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.3 (I/O)
P1.3/TA1.2/UCB0STE/A3/CD3
3
4
0
(1)
1
1
P1.4 (I/O)
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
TB0.CCI1A
0
TB0.1
1
X
(5)
TB0.CCI2A
0
TB0.2
1
(2) (3)
(2) (4)
A5
CD5
72
1
X
X
UCA0CLK
(5)
1
A3 (2) (3)
CD3 (2) (4)
P1.5(I/O)
(3)
(4)
0
1
A4
CD4
(1)
(2)
0
TA1.2
(2) (3)
(2) (4)
5
P1SEL0.x
0
0
UCA0STE
P1.5/TB0.2/UCA0CLK/A5/CD5
P1SEL1.x
I: 0; O: 1
TA1.CCI2A
UCB0STE
P1.4/TB0.1/UCA0STE/A4/CD4
CONTROL BITS OR SIGNALS
P1DIR.x
X
(5)
X
Direction controlled by eUSCI_B0 module.
Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Not available on all devices and package types.
Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit
Direction controlled by eUSCI_A0 module.
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.11.3 Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
图 6-11 shows the port diagram. 表 6-41 summarizes the selection of the pin functions.
Pad Logic
DVSS
P1REN.x
P1DIR.x
00
From module 2
10
01
Direction
0: Input
1: Output
11
P1OUT.x
DVSS
0
DVCC
1
1
00
From module 1
01
From module 2
10
From module 3
11
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
P1SEL1.x
P1SEL0.x
P1IN.x
Bus
Keeper
EN
To modules
D
图 6-11. Port P1 (P1.6 and P1.7) Diagram
表 6-41. Port P1 (P1.6 and P1.7) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.6 (I/O)
TB1.CCI1A
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
6
TB1.1
(1)
(2)
P1SEL1.x
P1SEL0.x
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
(1)
1
UCB0SIMO/UCB0SDA
X
(2)
TA0.CCI0A
0
TA0.0
1
TB1.CCI2A
7
P1DIR.x
I: 0; O: 1
(1)
P1.7 (I/O)
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
CONTROL BITS OR SIGNALS
TB1.2
I: 0; O: 1
(1)
(1)
UCB0SOMI/UCB0SCL
0
1
X (2)
TA1.CCI0A
0
TA1.0
1
Not available on all devices and package types.
Direction controlled by eUSCI_B0 module.
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
73
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
6.11.4 Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
图 6-12 shows the port diagram. 表 6-42 summarizes the selection of the pin functions.
Pad Logic
DVSS
P2REN.x
P2DIR.x
00
From module 2
10
01
Direction
0: Input
1: Output
11
P2OUT.x
DVSS
0
DVCC
1
1
00
From module 1
01
From module 2
10
From module 3
11
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.2/TB2.2/UCB0CLK/TB1.0
P2SEL1.x
P2SEL0.x
P2IN.x
Bus
Keeper
EN
D
To modules
图 6-12. Port P2 (P2.0 to P2.2) Diagram
表 6-42. Port P2 (P2.0 to P2.2) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.0 (I/O)
TB2.CCI0A
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
0
TB2.0
UCA0TXD/UCA0SIMO
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
X
(2)
0
1
TB2.1
I: 0; O: 1
(1)
0
(1)
1
UCA0RXD/UCA0SOMI
X
(2)
TB0.CCI0A
0
TB0.0
1
TB2.2
I: 0; O: 1
(1)
0
(1)
1
UCB0CLK
TB1.0
74
1
ACLK
TB1.CCI0A
(1)
(2)
(3)
0
0
TB0CLK
TB2.CCI2A
2
0
1
P2.2 (I/O)
P2.2/TB2.2/UCB0CLK/TB1.0
P2SEL0.x
0
(1)
TB2.CCI1A
1
P2SEL1.x
I: 0; O: 1
(1)
P2.1 (I/O)
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
CONTROL BITS OR SIGNALS
P2DIR.x
(1)
X
(1)
(3)
0
1
Not available on all devices and package types.
Direction controlled by eUSCI_A0 module.
Direction controlled by eUSCI_B0 module.
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.11.5 Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
图 6-13 shows the port diagram. 表 6-43 summarizes the selection of the pin functions.
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P2REN.x
P2DIR.x
00
From module 2
10
01
Direction
0: Input
1: Output
11
P2OUT.x
DVSS
0
DVCC
1
1
00
From module 1
01
From module 2
10
DVSS
11
P2.3/TA0.0/UCA1STE/A6/CD10
P2.4/TA1.0/UCA1CLK/A7/CD11
P2SEL1.x
P2SEL0.x
P2IN.x
Bus
Keeper
EN
To modules
D
图 6-13. Port P2 (P2.3 and P2.4) Diagram
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
75
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 6-43. Port P2 (P2.3 and P2.4) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.3 (I/O)
P2.3/TA0.0/UCA1STE/A6/CD10
3
(3)
(2) (4)
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
X
(1)
TA1.CCI0B
0
TA1.0
1
(2) (3)
(2) (4)
A7
CD11
76
0
1
UCA1CLK
(3)
(4)
0
TA0.0
P2.4 (I/O)
(1)
(2)
P2SEL0.x
0
0
A6 (2)
CD10
4
P2SEL1.x
I: 0; O: 1
TA0.CCI0B
UCA1STE
P2.4/TA1.0/UCA1CLK/A7/CD11
CONTROL BITS OR SIGNALS
P2DIR.x
X
(1)
X
Direction controlled by eUSCI_A1 module.
Setting P2SEL1.x and P2SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Not available on all devices and package types.
Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.11.6 Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
图 6-14 shows the port diagram. 表 6-44 summarizes the selection of the pin functions.
Pad Logic
P2REN.x
P2DIR.x
00
From module 2
10
01
Direction
0: Input
1: Output
11
P2OUT.x
DVSS
0
DVCC
1
1
00
From module 1
01
From module 2
10
DVSS
11
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P2.6/TB1.0/UCA1RXD/UCA1SOMI
P2SEL1.x
P2SEL0.x
P2IN.x
Bus
Keeper
EN
To modules
D
图 6-14. Port P2 (P2.5 and P2.6) Diagram
表 6-44. Port P2 (P2.5 and P2.6) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.5(I/O)
P2.5/TB0.0/UCA1TXD/UCA1SIMO
5
(1)
TB0.CCI0B
TB0.0
0
0
0
1
1
0
0
0
0
1
1
0
0
(1)
(1)
X
(2)
I: 0; O: 1
(1)
0
(1)
UCA1RXD/UCA1SOMI
(1)
(2)
I: 0; O: 1
1
TB1.CCI0B
TB1.0
P2SEL0.x
(1)
P2.6(I/O)
6
P2SEL1.x
(1)
UCA1TXD/UCA1SIMO
P2.6/TB1.0/UCA1RXD/UCA1SOMI
CONTROL BITS OR SIGNALS
P2DIR.x
1
(1)
X
(2)
Not available on all devices and package types.
Direction controlled by eUSCI_A1 module.
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
77
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
6.11.7 Port P2 (P2.7) Input/Output With Schmitt Trigger
图 6-15 shows the port diagram. 表 6-45 summarizes the selection of the pin functions.
Pad Logic
P2REN.x
P2DIR.x
00
01
10
Direction
0: Input
1: Output
11
P2OUT.x
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
P2.7
P2SEL1.x
P2SEL0.x
P2IN.x
Bus
Keeper
EN
To modules
D
图 6-15. Port P2 (P2.7) Diagram
表 6-45. Port P2 (P2.7) Pin Functions
PIN NAME (P2.x)
P2.7
(1)
78
x
7
FUNCTION
P2.7(I/O)
(1)
CONTROL BITS OR SIGNALS
P2DIR.x
P2SEL1.x
P2SEL0.x
I: 0; O: 1
0
0
Not available on all devices and package types.
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.11.8 Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
图 6-16 shows the port diagram. 表 6-46 summarizes the selection of the pin functions.
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P3REN.x
P3DIR.x
00
01
10
Direction
0: Input
1: Output
11
P3OUT.x
00
DVSS
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
P3.0/A12/CD12
P3.1/A13/CD13
P3.2/A14/CD14
P3.3/A15/CD15
P3SEL1.x
P3SEL0.x
P3IN.x
Bus
Keeper
EN
To modules
D
图 6-16. Port P3 (P3.0 to P3.3) Diagram
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
79
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 6-46. Port P3 (P3.0 to P3.3) Pin Functions
PIN NAME (P3.x)
x
FUNCTION
P3.0 (I/O)
P3.0/A12/CD12
0
P3.1/A13/CD13
1
P3.2/A14/CD14
2
P3.3/A15/CD15
3
A12 (1) (2)
CD12 (1) (3)
P3.1 (I/O)
A13 (1) (2)
CD13 (1) (3)
P3.2 (I/O)
A14 (1) (2)
CD14 (1) (3)
P3.3 (I/O)
(1)
(2)
(3)
80
A15 (1) (2)
CD15 (1) (3)
CONTROL BITS OR SIGNALS
P3DIR.x
P3SEL1.x
P3SEL0.x
I: 0; O: 1
0
0
X
1
1
I: 0; O: 1
0
0
X
1
1
I: 0; O: 1
0
0
X
1
1
I: 0; O: 1
0
0
X
1
1
Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Not available on all devices and package types.
Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.11.9 Port P3 (P3.4 to P3.6) Input/Output With Schmitt Trigger
图 6-17 shows the port diagram. 表 6-47 summarizes the selection of the pin functions.
Pad Logic
DVSS
P3REN.x
P3DIR.x
00
01
10
Direction
0: Input
1: Output
11
P3OUT.x
DVSS
0
DVCC
1
1
00
From module 1
01
DVSS
10
From module 2
11
P3.4/TB1.1/TB2CLK/SMCLK
P3.5/TB1.2/CDOUT
P3.6/TB2.1/TB1CLK
P3SEL1.x
P3SEL0.x
P3IN.x
Bus
Keeper
EN
To modules
D
图 6-17. Port P3 (P3.4 to P3.6) Diagram
表 6-47. Port P3 (P3.4 to P3.6) Pin Functions
PIN NAME (P3.x)
x
FUNCTION
P3.4 (I/O)
(1)
TB1.CCI1B
P3.4/TB1.1/TB2CLK/SMCLK
4
TB1.1
(1)
SMCLK
6
(1)
(1)
TB1CLK
(1)
(1)
TB2.CCI1B
TB2.1
0
1
1
1
0
0
0
1
1
1
1
I: 0; O: 1
0
0
0
1
1
1
0
I: 0; O: 1
0
1
P3.6 (I/O)
P3.6/TB2.1/TB1CLK
(1)
(1)
CDOUT
0
1
(1)
TB1.CCI2B
TB1.2
P3SEL0.x
0
0
(1)
P3.5 (I/O)
5
P3SEL1.x
I: 0; O: 1
1
(1)
TB2CLK
P3.5/TB1.2/CDOUT
(1)
CONTROL BITS OR SIGNALS
P3DIR.x
(1)
0
1
(1)
0
Not available on all devices and package types.
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
81
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
6.11.10 Port Port P3 (P3.7) Input/Output With Schmitt Trigger
图 6-18 shows the port diagram. 表 6-48 summarizes the selection of the pin functions.
Pad Logic
P3REN.x
P3DIR.x
00
01
10
Direction
0: Input
1: Output
11
P3OUT.x
00
From module 1
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
P3.7/TB2.2
P3SEL1.x
P3SEL0.x
P3IN.x
Bus
Keeper
EN
To modules
D
图 6-18. Port P3 (P3.7) Diagram
表 6-48. Port P3 (P3.7) Pin Functions
PIN NAME (P3.x)
x
FUNCTION
P3.7 (I/O)
P3.7/TB2.2
7
TB2.CCI2B
TB2.2
(1)
82
(1)
(1)
(1)
CONTROL BITS OR SIGNALS
P3DIR.x
P3SEL1.x
P3SEL0.x
I: 0; O: 1
0
0
0
1
0
1
Not available on all devices and package types.
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.11.11 Port Port P4 (P4.0) Input/Output With Schmitt Trigger
图 6-19 shows the port diagram. 表 6-49 summarizes the selection of the pin functions.
Pad Logic
P4REN.x
P4DIR.x
00
01
10
Direction
0: Input
1: Output
11
P4OUT.x
00
From module 1
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
P4.0/TB2.0
P4SEL1.x
P4SEL0.x
P4IN.x
Bus
Keeper
EN
To modules
D
图 6-19. Port P4 (P4.0) Diagram
表 6-49. Port P4 (P4.0) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4.0 (I/O)
P4.0/TB2.0
0
TB2.CCI0B
TB2.0
(1)
(1)
(1)
(1)
CONTROL BITS OR SIGNALS
P4DIR.x
P4SEL1.x
P4SEL0.x
I: 0; O: 1
0
0
0
1
0
1
Not available on all devices and package types.
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
83
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
6.11.12 Port Port P4 (P4.1) Input/Output With Schmitt Trigger
图 6-20 shows the port diagram. 表 6-50 summarizes the selection of the pin functions.
Pad Logic
P4REN.x
P4DIR.x
00
01
10
Direction
0: Input
1: Output
11
P4OUT.x
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
P4.1
P4SEL1.x
P4SEL0.x
P4IN.x
Bus
Keeper
EN
To modules
D
图 6-20. Port P4 (P4.1) Diagram
表 6-50. Port P4 (P4.1) Pin Functions
PIN NAME (P4.x)
P4.1
(1)
84
x
1
FUNCTION
P4.1 (I/O)
(1)
CONTROL BITS OR SIGNALS
P4DIR.x
P4SEL1.x
P4SEL0.x
I: 0; O: 1
0
0
Not available on all devices and package types.
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
6.11.13 Port Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output
With Schmitt Trigger or Output
图 6-21 and 图 6-22 show the port diagrams. 表 6-51 summarizes the selection of the pin functions.
To Comparator
From Comparator
CDPD.x
From JTAG
From JTAG
From JTAG
Pad Logic
1
PJREN.x
PJDIR.x
0
00
1
01
10
DVSS
0
DVCC
1
0
Direction
0: Input
1: Output
11
1
JTAG enable
PJOUT.x
00
From module 1
01
1
DVSS
10
0
DVSS
11
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJSEL1.x
PJSEL0.x
PJIN.x
Bus
Keeper
EN
To modules
and JTAG
D
图 6-21. Port PJ (PJ.0 to PJ.2) Diagram
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
85
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
To Comparator
From Comparator
CDPD.x
Pad Logic
From JTAG
From JTAG
From JTAG
1
PJREN.x
PJDIR.x
0
00
1
01
10
DVSS
0
DVCC
1
0
Direction
0: Input
1: Output
11
1
JTAG enable
PJOUT.x
00
DVSS
01
1
DVSS
10
0
DVSS
11
PJ.3/TCK/CD9
PJSEL1.x
PJSEL0.x
PJIN.x
EN
To modules
and JTAG
Bus
Keeper
D
图 6-22. Port PJ (PJ.3) Diagram
86
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
表 6-51. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
x
FUNCTION
PJ.0 (I/O)
TDO
PJ.0/TDO/TB0OUTH/SMCLK/CD6
0
(2)
(3)
1
PJ.1 (I/O)
TDI/TCLK
(3) (4)
0
1
1
1
PJSEL0.x
I: 0; O: 1
0
0
X
X
X
0
1
1
0
MCLK
1
X
1
I: 0; O: 1
0
0
(3) (4)
X
X
X
TB2OUTH
0
ACLK
1
0
1
1
1
TCK
CD9
(4)
X
TB1OUTH
(2)
X
PJ.3 (I/O)
(1)
(2)
(3)
X
X
(2)
CD8
3
0
X
1
TMS
PJ.3/TCK/CD9
0
0
PJ.2 (I/O)
2
PJSEL1.x
SMCLK
CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJDIR.x
I: 0; O: 1
TB0OUTH
CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
CONTROL BITS OR SIGNALS (1)
(3) (4)
(2)
I: 0; O: 1
0
0
X
X
X
X
1
1
X = Don't care
Default condition
The pin direction is controlled by the JTAG module. JTAG mode selection is made by the SYS module or by the Spy-Bi-Wire four-wire
entry sequence. PJSEL1.x and PJSEL0.x have no effect in these cases.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
87
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
6.11.14 Port Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
图 6-23 and 图 6-24 show the port diagrams. 表 6-52 summarizes the selection of the pin functions.
Pad Logic
To XT1 XIN
PJREN.4
PJDIR.4
00
01
10
Direction
0: Input
1: Output
11
PJOUT.4
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
PJ.4/XIN
PJSEL1.4
PJSEL0.4
PJIN.4
EN
To modules
Bus
Keeper
D
图 6-23. Port PJ (PJ.4) Diagram
88
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
Pad Logic
To XT1 XOUT
PJSEL0.4
XT1BYPASS
PJREN.5
PJDIR.5
00
01
10
Direction
0: Input
1: Output
11
PJOUT.5
00
DVSS
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
PJ.5/XOUT
PJSEL1.5
PJSEL0.5
PJIN.5
Bus
Keeper
EN
To modules
D
图 6-24. Port PJ (PJ.5) Diagram
表 6-52. Port PJ (PJ.4 and PJ.5) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P7.x)
x
FUNCTION
PJ.4 (I/O)
PJ.4/XIN
4
XIN crystal mode
XIN bypass mode
(2)
(2)
PJ.5 (I/O)
PJ.5/XOUT
5
XOUT crystal mode
(2)
PJ.5 (I/O)
(1)
(2)
(3)
(3)
(1)
PJSEL0.4
XT1
BYPASS
0
0
X
0
1
0
X
0
1
1
0
0
0
0
X
X
X
X
0
1
0
I: 0; O: 1
X
X
0
1
1
PJDIR.x
PJSEL1.5
PJSEL0.5 PJSEL1.4
I: 0; O: 1
X
X
X
X
X
X
X
I: 0; O: 1
X = Don't care
Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When XT1BYPASS = 0, PJ.4 and PJ.5 are
configured for crystal operation and PJSEL1.5 and PJSEL0.5 are don't care. When XT1BYPASS = 1, PJ.4 is configured for bypass
operation and PJ.5 is configured as general-purpose I/O.
When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
89
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
6.12 Device Descriptors (TLV)
表 6-53 and 表 6-54 list the complete contents of the device descriptor tag-length-value (TLV) structure for
each device type.
表 6-53. Device Descriptor Table
DESCRIPTION
FR5726
FR5725
05h
05h
05h
05h
05h
01A01h
05h
05h
05h
05h
05h
01A02h
per unit
per unit
per unit
per unit
per unit
01A03h
per unit
per unit
per unit
per unit
per unit
Device ID
01A04h
7Bh
7Ah
79h
74h
78h
Device ID
01A05h
80h
80h
80h
81h
80h
Hardware revision
01A06h
per unit
per unit
per unit
per unit
per unit
Firmware revision
01A07h
per unit
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
08h
08h
08h
08h
08h
Die record length
01A09h
0Ah
0Ah
0Ah
0Ah
0Ah
01A0Ah
per unit
per unit
per unit
per unit
per unit
01A0Bh
per unit
per unit
per unit
per unit
per unit
01A0Ch
per unit
per unit
per unit
per unit
per unit
01A0Dh
per unit
per unit
per unit
per unit
per unit
01A0Eh
per unit
per unit
per unit
per unit
per unit
01A0Fh
per unit
per unit
per unit
per unit
per unit
01A10h
per unit
per unit
per unit
per unit
per unit
01A11h
per unit
per unit
per unit
per unit
per unit
01A12h
per unit
per unit
per unit
per unit
per unit
01A13h
per unit
per unit
per unit
per unit
per unit
ADC10 calibration
tag
01A14h
13h
13h
13h
05h
13h
ADC10 calibration
length
01A15h
10h
10h
10h
10h
10h
01A16h
per unit
per unit
NA
NA
per unit
01A17h
per unit
per unit
NA
NA
per unit
01A18h
per unit
per unit
NA
NA
per unit
01A19h
per unit
per unit
NA
NA
per unit
ADC 1.5-V reference
Temp. sensor 30°C
01A1Ah
per unit
per unit
NA
NA
per unit
01A1Bh
per unit
per unit
NA
NA
per unit
ADC 1.5-V reference
Temp. sensor 85°C
01A1Ch
per unit
per unit
NA
NA
per unit
01A1Dh
per unit
per unit
NA
NA
per unit
ADC 2.0-V reference
Temp. sensor 30°C
01A1Eh
per unit
per unit
NA
NA
per unit
01A1Fh
per unit
per unit
NA
NA
per unit
ADC 2.0-V reference
Temp. sensor 85°C
01A20h
per unit
per unit
NA
NA
per unit
01A21h
per unit
per unit
NA
NA
per unit
ADC 2.5-V reference
Temp. sensor 30°C
01A22h
per unit
per unit
NA
NA
per unit
01A23h
per unit
per unit
NA
NA
per unit
ADC 2.5-V reference
Temp. sensor 85°C
01A24h
per unit
per unit
NA
NA
per unit
01A25h
per unit
per unit
NA
NA
per unit
Die X position
Die Y position
Test results
ADC gain factor
ADC offset
90
FR5727
CRC length
Die Record
(1)
FR5728
01A00h
Lot/wafer ID
ADC10
Calibration
VALUE
FR5729
Info length
CRC value
Info Block
ADDRESS
(1)
NA = Not applicable
Detailed Description
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
表 6-53. Device Descriptor Table (1) (continued)
DESCRIPTION
REF
Calibration
ADDRESS
VALUE
FR5729
FR5728
FR5727
FR5726
FR5725
REF calibration tag
01A26h
12h
12h
12h
12h
12h
REF calibration
length
01A27h
06h
06h
06h
06h
06h
01A28h
per unit
per unit
per unit
per unit
per unit
01A29h
per unit
per unit
per unit
per unit
per unit
01A2Ah
per unit
per unit
per unit
per unit
per unit
01A2Bh
per unit
per unit
per unit
per unit
per unit
01A2Ch
per unit
per unit
per unit
per unit
per unit
01A2Dh
per unit
per unit
per unit
per unit
per unit
REF 1.5-V
Reference
REF 2.0-V reference
REF 2.5-V reference
表 6-54. Device Descriptor Table
DESCRIPTION
FR5723
FR5722
FR5721
FR5720
05h
Info length
01A00h
05h
05h
05h
05h
01A01h
05h
05h
05h
05h
05h
01A02h
per unit
per unit
per unit
per unit
per unit
01A03h
per unit
per unit
per unit
per unit
per unit
Device ID
01A04h
73h
72h
71h
77h
70h
Device ID
01A05h
81h
81h
81h
80h
81h
Hardware revision
01A06h
per unit
per unit
per unit
per unit
per unit
Firmware revision
01A07h
per unit
per unit
per unit
per unit
per unit
Die record tag
01A08h
08h
08h
08h
08h
08h
Die record length
01A09h
0Ah
0Ah
0Ah
0Ah
0Ah
01A0Ah
per unit
per unit
per unit
per unit
per unit
01A0Bh
per unit
per unit
per unit
per unit
per unit
01A0Ch
per unit
per unit
per unit
per unit
per unit
01A0Dh
per unit
per unit
per unit
per unit
per unit
01A0Eh
per unit
per unit
per unit
per unit
per unit
01A0Fh
per unit
per unit
per unit
per unit
per unit
01A10h
per unit
per unit
per unit
per unit
per unit
01A11h
per unit
per unit
per unit
per unit
per unit
01A12h
per unit
per unit
per unit
per unit
per unit
01A13h
per unit
per unit
per unit
per unit
per unit
Lot/wafer ID
Die Record
Die X position
Die Y position
Test results
(1)
VALUE
FR5724
CRC length
CRC value
Info Block
ADDRESS
(1)
NA = Not applicable
Detailed Description
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
91
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
表 6-54. Device Descriptor Table (1) (continued)
DESCRIPTION
FR5722
FR5721
FR5720
13h
13h
13h
05h
13h
ADC10 calibration
length
01A15h
10h
10h
10h
10h
10h
01A16h
per unit
NA
NA
per unit
per unit
01A17h
per unit
NA
NA
per unit
per unit
01A18h
per unit
NA
NA
per unit
per unit
01A19h
per unit
NA
NA
per unit
per unit
ADC 1.5-V reference
Temp. sensor 30°C
01A1Ah
per unit
NA
NA
per unit
per unit
01A1Bh
per unit
NA
NA
per unit
per unit
ADC 1.5-V reference
Temp. sensor 85°C
01A1Ch
per unit
NA
NA
per unit
per unit
01A1Dh
per unit
NA
NA
per unit
per unit
ADC 2.0-V reference
Temp. sensor 30°C
01A1Eh
per unit
NA
NA
per unit
per unit
01A1Fh
per unit
NA
NA
per unit
per unit
ADC 2.0-V reference
Temp. sensor 85°C
01A20h
per unit
NA
NA
per unit
per unit
01A21h
per unit
NA
NA
per unit
per unit
ADC 2.5-V reference
Temp. sensor 30°C
01A22h
per unit
NA
NA
per unit
per unit
01A23h
per unit
NA
NA
per unit
per unit
ADC 2.5-V reference
Temp. sensor 85°C
01A24h
per unit
NA
NA
per unit
per unit
01A25h
per unit
NA
NA
per unit
per unit
REF calibration tag
01A26h
12h
12h
12h
12h
12h
REF calibration
length
01A27h
06h
06h
06h
06h
06h
01A28h
per unit
per unit
per unit
per unit
per unit
REF 1.5-V reference
REF 2.0-V reference
REF 2.5-V reference
92
FR5723
01A14h
ADC offset
REF
Calibration
VALUE
FR5724
ADC10 calibration
tag
ADC gain factor
ADC10
Calibration
ADDRESS
Detailed Description
01A29h
per unit
per unit
per unit
per unit
per unit
01A2Ah
per unit
per unit
per unit
per unit
per unit
01A2Bh
per unit
per unit
per unit
per unit
per unit
01A2Ch
per unit
per unit
per unit
per unit
per unit
01A2Dh
per unit
per unit
per unit
per unit
per unit
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
7 器件和文档支持
7.1
开始使用
TI 还提供了立即入门必备的所有硬件平台和软件组件以及工具！不仅如此，TI 还拥有众多辅助组件以满足您
的需求。要获得 MSP430™MCU 产品线、可用开发工具和评估套件，以及高级开发资源，请访问 MSP430
入门网页。
7.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP430F5438A). TI recommends two of three possible
prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the electrical specifications for the
final device
PMS – Final silicon die that conforms to the electrical specifications for the device but has not completed
quality and reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI's internal qualification testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard
production devices. TI recommends that these devices not be used in any production system because
their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PZP) and temperature range (for example, T). 图 7-1 provides a legend for
reading the complete device name for any family member.
器件和文档支持
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
93
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
MSP 430 F 5 438 A I ZQW T -EP
Processor Family
Optional: Additional Features
MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
MCU Platform
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Specialized Application
AFE = Analog Front End
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD
0 = Low-Voltage Series
Feature Set
Various levels of integration within a series
Optional: A = Revision
N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
图 7-1. Device Nomenclature
94
器件和文档支持
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
7.3
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
工具和软件
表 7-1列出了这些微控制器 支持 的调试功能。关于可用特性的详细信息，请参见《适用于 MSP430 的
Code Composer Studio 用户指南 》。
表 7-1. 硬件 功能
MSP430 架构
4 线 JTAG
2 线 JTAG
断点
(N)
范围断点
时钟控制
状态序列发生器
跟踪缓冲
器
LPMx.5 调试支
持
MSP430Xv2
有
有
3
有
是
否
否
有
设计套件与评估模块
《使用 MSP430 FRAM 微控制器实现 EEPROM 仿真和感测》 此 TI 参考设计描述了如何将 MSP430™ 超
低功耗微控制器 (MCU) 上的铁电随机存取存储器 (FRAM) 技术与使用 MCU 时可启用的附加
感测功能搭配用来仿真 EEPROM。此参考设计支持通过 I2C 和 SPI 接口连接至主机处理器，
以进行多从器件寻址。
MSP-EXP430FR5739 实验板 MSP-EXP430FR5739 实验板是一套适用于 MSP430FR57xx 器件的开发平
台。它支持集成有铁电随机存取存储器 (FRAM) 的新一代微控制器器件 MSP430。该实验板兼
容多种 TI 低功耗 RF 无线评估模块（例如，CC2520EMK）。该实验板可帮助设计人员快速了
解全新的 MSP430FR57xx MCU 并使用它来进行开发。MSP430FR57xx MCU 整体功耗极
低，并且支持数据的快速读写，存储器的耐擦写次数无与伦比。MSP-EXP430FR5739 实验板
能够帮助评估并促进数据日志 应用、能源采集、无线感测、自动计量基础设施 (AMI) 以及许多
其他应用的开发。
《MSP-TS430RHA40A - 适用于 MSP430FRxx FRAM MCU 的 40 引脚目标开发板》
MSPTS430RHA40A 是一款独立的 40 引脚 ZIF 插接目标板，适用于通过 JTAG 接口或 Spy BiWire（双线制 JTAG）协议对 MSP430 MCU 系统进行在线编程和调试。
软件
MSP430Ware™ 软件 MSP430Ware 软件集合了所有 MSP430 器件的代码示例、产品说明书以及其他设计
资源，打包提供给用户。除了提供已有 MSP430 设计资源的完整集合外，MSP430Ware 软件
还包含名为 MSP430 驱动程序库的高级 API。借助该库可以轻松地对 MSP430 硬件进行编
程。MSP430Ware 软件以 CCS 组件或独立软件包两种形式提供。
MSP430FR573x、
、MSP430FR572x C 代码示例 根据不同应用需求配置各集成外设的每个 MSP 器件均具备
相应的 C 代码示例。
MSP 驱动程序库 驱动程序库的抽象化 API 通过提供易于使用的函数调用使您不再拘泥于 MSP430 硬件的
细节。完整的文档通过具有帮助意义的 API 指南交付，其中包括有关每个函数调用和经过验证
的参数的详细信息。开发人员可以使用驱动程序库功能，以最低开销编写完整项目。
MSP EnergyTrace™ 技术 MSP430 微控制器的 EnergyTrace 技术是基于能量的代码分析工具，用于测量
和显示应用的能量配置，同时协助优化应用以实现超低功耗。
器件和文档支持
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
95
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
ULP（
（超低功耗）Advisor ULP Advisor™软件是一款辅助工具，旨在指导开发人员编写更为高效的代码，
从而充分利用 MSP 和 MSP432 微控制器独特的 超低功耗 功能。ULP Advisor 的目标人群是
微控制器的资深开发者和开发新手，可以根据详尽的 ULP 检验表检查代码，以便最大限度地
利用应用程序。在编译时，ULP Advisor 会提供通知和备注以突出显示代码中可以进一步优化
的区域，进而实现更低功耗。
IEC60730 软件包 IEC60730 MSP430 软件包经过专门开发，用于协助客户达到 IEC 60730-1:2010（家用
及类似用途的自动化电气控制 - 第 1 部分：一般要求）B 类产品的要求。其中涵盖家用电器、
电弧检测器、电源转换器、电动工具、电动自行车及其他诸多产品。IEC60730 MSP430 软件
包可以嵌入在 MSP430 中 运行的客户应用， 从而帮助客户简化其消费类器件在功能安全方面
遵循 IEC 60730-1:2010 B 类规范的认证工作。
适用于 MSP 的定点数学运算库 MSP IQmath 和 Qmath 库是一套经过高度优化的高精度数学运算函数集
合，适用于 C 语言开发者，能够将浮点算法无缝嵌入 MSP430 和 MSP432 器件的定点代码
中。这些例程通常用于计算密集的实时 应用， 而优化的执行速度、高精度以及超低能耗通常
是影响这些实时应用的关键因素。与使用浮点数学算法编写的同等代码相比，使用 IQmath 和
Qmath 库可以大幅提高执行速度并显著降低能耗。
适用于 MSP430 的浮点数学运算库
TI
在低功耗和低成本微控制器领域锐意创新，为您提供
MSPMATHLIB。这是标量函数的浮点数学运算库，能够充分利用器件的智能外设，使性能提
升高达 26 倍。Mathlib 能够轻松集成到您的设计中。该运算库免费使用并集成在 Code
Composer Studio 和 IAR IDE 中。如需深入了解该数学运算库及相关基准，请阅读用户指南。
开发工具
适用于 MSP 微控制器的 Code Composer Studio™ 集成开发环境 Code Composer Studio 是一种集成开
发环境 (IDE)，支持所有 MSP 微控制器。Code Composer Studio 包含一整套开发和调试嵌入
式应用 的嵌入式软件实用程序。它包含了优化的 C/C++ 编译器、源代码编辑器、项目构建环
境、调试器、描述器以及其他多种 功能。直观的 IDE 提供了单个用户界面，有助于完成应用
程序开发流程的每个步骤。熟悉的实用程序和界面可提升用户的入门速度。Code Composer
Studio 将 Eclipse 软件框架的优点和 TI 先进的嵌入式调试功能相结合，为嵌入式开发人员提
供了一种功能丰富的优异开发环境。当 CCS 与 MSP MCU 搭配使用时，可以使用独特而强大
的插件和嵌入式软件实用程序，从而充分利用 MSP 微控制器的功能。
命令行编程器 MSP Flasher 是一款基于 shell 的开源接口，可使用 JTAG 或 Spy-Bi-Wire (SBW) 通信通过
FET 编程器或 eZ430 对 MSP 微控制器进行编程。MSP Flasher 可用于将二进制文件（.txt 或
.hex 文件）直接下载到 MSP 微控制器，而无需使用 IDE。
96
器件和文档支持
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
MSP MCU 编程器和调试器 MSP-FET 是一款强大的仿真开发工具（通常称为调试探针），可帮助用户在
MSP 低功耗微控制器 (MCU) 中快速开发应用。创建 MCU 软件通常需要将生成的二进制程序
下载到 MSP 器件，以进行验证和调试。MSP-FET 在主机和目标 MSP 间提供调试通信通道。
此外，MSP-FET 还可在计算机的 USB 接口和 MSP UART 间提供反向通道 UART 连接。这
为 MSP 编程器提供了一种在 MSP 和计算机上运行的终端之间进行串行通信的便捷方法。它
还支持使用 BSL（引导加载程序）通过 UART 和 I2C 通信协议将程序（通常称为固件）加载
到 MSP 目标中。
MSP-GANG 生产编程器 MSP Gang 编程器是一款 MSP430 或 MSP432 器件编程器，可同时对多达八个完
全相同的 MSP430 或 MSP432 闪存或 FRAM 器件进行编程。MSP Gang 编程器可使用标准
的 RS-232 或 USB 连接与主机 PC 相连并提供灵活的编程选项，允许用户完全自定义流程。
MSP Gang 编程器配有扩展板，即“Gang 分离器”，可在 MSP Gang 编程器和多个目标器件间
实施互连。提供了八条电缆，用于将扩展板与八个目标器件相连（通过 JTAG 或 SPY-Bi-Wire
连接器）。编程工作可在 PC 或独立设备上完成。PC 端具备基于 DLL 的图形化用户界面。
7.4
文档支持
以下文档介绍了 MCU。www.ti.com 网站上提供了这些文档的副本。
如需接收文档更新通知（包括芯片勘误表），请访问
ti.com
上您的器件对应的产品文件夹（例如，
MSP430FR5729）。请单击右上角的“通知我”按钮。点击后，您将每周定期收到已更改的产品信息（如果有
的话）。有关更改的详细信息，请查阅已修订文档的修订历史记录。
勘误
《MSP430FR5729 器件勘误表》 描述了针对这款器件每个芯片修订版本功能技术规格的已知例外情况。
《MSP430FR5728 器件勘误表》 描述了针对这款器件每个芯片修订版本功能技术规格的已知例外情况。
《MSP430FR5727 器件勘误表》 描述了针对这款器件每个芯片修订版本功能技术规格的已知例外情况。
《MSP430FR5726 器件勘误表》 描述了针对这款器件每个芯片修订版本功能技术规格的已知例外情况。
《MSP430FR5725 器件勘误表》 描述了针对这款器件每个芯片修订版本功能技术规格的已知例外情况。
《MSP430FR5724 器件勘误表》 描述了针对这款器件每个芯片修订版本功能技术规格的已知例外情况。
《MSP430FR5723 器件勘误表》 描述了针对这款器件每个芯片修订版本功能技术规格的已知例外情况。
《MSP430FR5722 器件勘误表》 描述了针对这款器件每个芯片修订版本功能技术规格的已知例外情况。
《MSP430FR5721 器件勘误表》 描述了针对这款器件每个芯片修订版本功能技术规格的已知例外情况。
器件和文档支持
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
97
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
www.ti.com.cn
《MSP430FR5720 器件勘误表》 描述了针对这款器件每个芯片修订版本功能技术规格的已知例外情况。
用户指南
MSP430FR57xx 系列用户指南 该器件系列提供的所有模块和 外设 的详细说明。
《使用引导加载程序 (BSL) 对 MSP430 进行编程》 MSP430 引导加载程序（BSL，之前称为引导装载程
序）方便用户在原型建模阶段、最终生产和维修期间与 MSP430 微控制器中的嵌入式存储器
进行通信。可编程存储器（闪存）和数据存储器 (RAM) 能够按照要求进行变更。不要将此处
的引导加载程序与某些数字信号处理器 (DSP) 中将外部存储器中的程序代码（和数据）自动加
载到 DSP 内部存储器的引导装载程序混为一谈。
《通过 JTAG 接口对 MSP430 进行编程》 本文档介绍了使用 JTAG 通信端口擦除、编程和验证基于
MSP430 闪存和 FRAM 的微控制器系列的存储器模块所需的功能。此外，该文档还描述了如
何设定所有 MSP430 器件提供的 JTAG 访问安全熔丝。本文档介绍了使用标准 4 线 JTAG 接
口和 2 线 JTAG 接口（也称为 Spy-Bi-Wire (SBW)）访问 MCU。
《MSP430 硬件工具用户指南》 本手册介绍了 TI MSP-FET430 闪存仿真工具 (FET) 的硬件。FET 是针对
MSP430 超低功耗微控制器的程序开发工具。对提供的接口类型，即并行端口接口和 USB 接
口进行了说明。
应用报告
MSP430 FRAM 技术 – 操作方法和最佳实践 FRAM 采用非易失性存储器技术，行为与 SRAM 类似，支持
大量新 应用的同时，还改变了固件的设计方式。该应用程序报告从嵌入式软件开发方面概述了
FRAM 技术在 MSP430 中的使用方法和最佳实践。其中讨论了如何根据应用特定的代码、常
量和数据空间要求来实施存储器布局，如何使用 FRAM 来优化应用程序能耗以及如何使用存
储器保护单元 (MPU) 为程序代码提供意外写访问保护，从而最大程度提高应用的稳健性。
《MSP430 FRAM 质量和可靠性》 FRAM 是一种非易失性嵌入式存储器技术并因其超低功耗特性而广为人
知，同时它也是当今较为灵活且易于使用的通用型存储器解决方案。该应用报告旨在为 FRAM
的新用户和从基于闪存的 应用 转化来的用户提供有关 FRAM 如何满足关键质量和可靠性要求
（诸如数据保存和耐擦写能力）的知识。
《最大限度提高 MSP430™ FRAM 的写入速度》 非易失性低功耗铁电 RAM (FRAM) 支持极其高速的写访
问。该应用报告重点围绕 MSP430FRxx 系列讨论了如何使用简单技术最大限度地提高 FRAM
的写入速度。该文档以 MSP430FR5739 器件为例进行了基准测试（这些测试适用于所有基于
MSP430™ FRAM 的器件），并且讨论了 CPU 时钟频率和块大小等方面的权衡以及它们如何
影响 FRAM 写入速度。
《MSP430 系统级 ESD 注意事项》 系统级 ESD 对于低电压下的硅晶技术以及经济高效型和超低功耗组件
的需求日益增加。此应用报告重点讨论了三个不同的 ESD 主题，以帮助板卡设计师和原始设
备制造商 (OEM) 理解和设计稳健的系统级设计产品：(1) 组件级 ESD 测试和系统级 ESD 测
试，二者的差异以及为何组件级 ESD 无法确保达到系统级的稳健性。(2) 系统级 ESD 保护在
不同电平下的通用设计指南（包括外壳、电缆、PCB 布局和板载 ESD 防护器件）。(3) 介绍
了系统高效 ESD 设计 (SEED)。这是一种板上和片上 ESD 保护协同设计的方法论，用于实现
系统级 ESD 的稳健性，配备仿真示例和测试结果。另外，还讨论了一些真实的系统级 ESD 保
护设计示例及其成果。
MSP430 32kHz 晶体振荡器 对于稳定的晶体振荡器，选择合适的晶振、正确的负载电路和适当的电路板布
局布线至关重要。该应用报告总结了晶体振荡器的功能，介绍了为实现 MSP430 超低功耗运
行而选择正确晶体的参数。此外，还给出了正确电路板布局布线的提示和示例。本文档还包含
与可能振荡器测试相关的详细信息以确保大批量生产中的稳定振荡器运行。
98
器件和文档支持
版权 © 2014–2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
MSP430FR5729, MSP430FR5728, MSP430FR5727, MSP430FR5726, MSP430FR5725
MSP430FR5724, MSP430FR5723, MSP430FR5722, MSP430FR5721, MSP430FR5720
www.ti.com.cn
7.5
ZHCSCG3C – MAY 2014 – REVISED DECEMBER 2017
相关链接
表 7-2 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品
的快速链接。
表 7-2. 相关链接
器件
产品文件夹
立即订购
技术文档
工具和软件
支持和社区
MSP430FR5729
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
MSP430FR5728
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
MSP430FR5727
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
MSP430FR5726
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
MSP430FR5725
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
MSP430FR5724
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
MSP430FR5723
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
MSP430FR5722
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
MSP430FR5721
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
MSP430FR5720
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
7.6
社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参见 TI 的 《使用条款》。
TI E2E™ 社区
TI 的工程师交流 (E2E) 社区. 此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您可以提
问、共享知识、拓展思路，在同领域工程师的帮助下解决问题。
TI 嵌入式处理器维基网页
德州仪器 (TI) 嵌入式处理器维基网页。此网站的建立是为了帮助开发人员熟悉德州仪器 (TI) 的嵌入式处理
器，并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长。
7.7
商标
MSP430, MSP430Ware, EnergyTrace, ULP Advisor, 适用于 MSP 微控制器的 Code Composer Studio,
E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
7.8
静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
7.9
出口管制提示
接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据
（其中包括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制
产品或此项技术的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政
府机构授权的情况下，接收方不得在知情的情况下，以直接或间接的方式将其出口。
7.10 术语表
TI 术语表
这份术语表列出并解释术语、缩写和定义。
8 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通
知和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
机械、封装和可订购信息
提交文档反馈意见
产品主页链接: MSP430FR5729 MSP430FR5728 MSP430FR5727 MSP430FR5726 MSP430FR5725 MSP430FR5724
MSP430FR5723 MSP430FR5722 MSP430FR5721 MSP430FR5720
版权 © 2014–2017, Texas Instruments Incorporated
99
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2025
PACKAGING INFORMATION
Orderable part number
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
M430FR5720IRGERG4
Active
Production
VQFN (RGE) | 24
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5720
M430FR5720IRGERG4.A
Active
Production
VQFN (RGE) | 24
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5720
M430FR5728IRGERG4
Active
Production
VQFN (RGE) | 24
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5728
M430FR5728IRGERG4.A
Active
Production
VQFN (RGE) | 24
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5728
MSP430FR5720IPW
Active
Production
TSSOP (PW) | 28
50 | TUBE
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5720
MSP430FR5720IPW.A
Active
Production
TSSOP (PW) | 28
50 | TUBE
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5720
MSP430FR5720IPWR
Active
Production
TSSOP (PW) | 28
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5720
MSP430FR5720IPWR.A
Active
Production
TSSOP (PW) | 28
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5720
MSP430FR5720IRGER
Active
Production
VQFN (RGE) | 24
3000 | LARGE T&R
Yes
NIPDAU | NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5720
MSP430FR5720IRGER.A
Active
Production
VQFN (RGE) | 24
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5720
MSP430FR5720IRGET
Active
Production
VQFN (RGE) | 24
250 | SMALL T&R
Yes
NIPDAU | NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5720
MSP430FR5720IRGET.A
Active
Production
VQFN (RGE) | 24
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5720
MSP430FR5721IDA
Active
Production
TSSOP (DA) | 38
40 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5721
MSP430FR5721IDA.A
Active
Production
TSSOP (DA) | 38
40 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5721
MSP430FR5721IDAR
Active
Production
TSSOP (DA) | 38
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5721
MSP430FR5721IDAR.A
Active
Production
TSSOP (DA) | 38
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5721
MSP430FR5721IRHAR
Active
Production
VQFN (RHA) | 40
2500 | LARGE T&R
Yes
NIPDAU | NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5721
MSP430FR5721IRHAR.A
Active
Production
VQFN (RHA) | 40
2500 | LARGE T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5721
MSP430FR5721IRHAT
Active
Production
VQFN (RHA) | 40
250 | SMALL T&R
Yes
NIPDAU | NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5721
MSP430FR5721IRHAT.A
Active
Production
VQFN (RHA) | 40
250 | SMALL T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5721
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable part number
17-Jun-2025
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
MSP430FR5722IPW
Active
Production
TSSOP (PW) | 28
50 | TUBE
Yes
Lead finish/
Ball material
MSL rating/
Peak reflow
Op temp (°C)
Part marking
(4)
(5)
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5722
(6)
MSP430FR5722IPW.A
Active
Production
TSSOP (PW) | 28
50 | TUBE
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5722
MSP430FR5722IRGET
Active
Production
VQFN (RGE) | 24
250 | SMALL T&R
Yes
NIPDAU | NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5722
MSP430FR5722IRGET.A
Active
Production
VQFN (RGE) | 24
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5722
MSP430FR5723IRHAR
Active
Production
VQFN (RHA) | 40
2500 | LARGE T&R
Yes
NIPDAU | NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5723
MSP430FR5723IRHAR.A
Active
Production
VQFN (RHA) | 40
2500 | LARGE T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5723
MSP430FR5723IRHAT
Active
Production
VQFN (RHA) | 40
250 | SMALL T&R
Yes
NIPDAU | NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5723
MSP430FR5723IRHAT.A
Active
Production
VQFN (RHA) | 40
250 | SMALL T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5723
MSP430FR5724IPW
Active
Production
TSSOP (PW) | 28
50 | TUBE
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5724
MSP430FR5724IPW.A
Active
Production
TSSOP (PW) | 28
50 | TUBE
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5724
MSP430FR5724IPWR
Active
Production
TSSOP (PW) | 28
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5724
MSP430FR5724IPWR.A
Active
Production
TSSOP (PW) | 28
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5724
MSP430FR5724IPWRG4.A
Active
Production
TSSOP (PW) | 28
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5724
MSP430FR5724IRGER
Active
Production
VQFN (RGE) | 24
3000 | LARGE T&R
Yes
NIPDAU | NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5724
MSP430FR5724IRGER.A
Active
Production
VQFN (RGE) | 24
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5724
MSP430FR5724IRGET
Active
Production
VQFN (RGE) | 24
250 | SMALL T&R
Yes
NIPDAU | NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5724
MSP430FR5724IRGET.A
Active
Production
VQFN (RGE) | 24
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5724
MSP430FR5725IDA
Active
Production
TSSOP (DA) | 38
40 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5725
MSP430FR5725IDA.A
Active
Production
TSSOP (DA) | 38
40 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5725
MSP430FR5725IDAR
Active
Production
TSSOP (DA) | 38
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5725
MSP430FR5725IDAR.A
Active
Production
TSSOP (DA) | 38
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5725
MSP430FR5725IRHAR
Active
Production
VQFN (RHA) | 40
2500 | LARGE T&R
Yes
NIPDAU | NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5725
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable part number
17-Jun-2025
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
MSP430FR5725IRHAR.A
Active
Production
VQFN (RHA) | 40
2500 | LARGE T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5725
MSP430FR5725IRHAT
Active
Production
VQFN (RHA) | 40
250 | SMALL T&R
Yes
NIPDAU | NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5725
MSP430FR5725IRHAT.A
Active
Production
VQFN (RHA) | 40
250 | SMALL T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5725
MSP430FR5726IPW
Active
Production
TSSOP (PW) | 28
50 | TUBE
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5726
MSP430FR5726IPW.A
Active
Production
TSSOP (PW) | 28
50 | TUBE
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5726
MSP430FR5726IRGER
Active
Production
VQFN (RGE) | 24
3000 | LARGE T&R
Yes
NIPDAU | NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5726
MSP430FR5726IRGER.A
Active
Production
VQFN (RGE) | 24
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5726
MSP430FR5726IRGET.A
Active
Production
VQFN (RGE) | 24
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5726
MSP430FR5727IDAR
Active
Production
TSSOP (DA) | 38
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5727
MSP430FR5727IDAR.A
Active
Production
TSSOP (DA) | 38
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5727
MSP430FR5727IRHAT
Active
Production
VQFN (RHA) | 40
250 | SMALL T&R
Yes
NIPDAU | NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5727
MSP430FR5727IRHAT.A
Active
Production
VQFN (RHA) | 40
250 | SMALL T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5727
MSP430FR5728IPW
Active
Production
TSSOP (PW) | 28
50 | TUBE
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5728
MSP430FR5728IPW.A
Active
Production
TSSOP (PW) | 28
50 | TUBE
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5728
MSP430FR5728IPWG4.A
Active
Production
TSSOP (PW) | 28
50 | TUBE
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5728
MSP430FR5728IPWR
Active
Production
TSSOP (PW) | 28
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5728
MSP430FR5728IPWR.A
Active
Production
TSSOP (PW) | 28
2000 | LARGE T&R
Yes
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430FR5728
MSP430FR5728IRGER
Active
Production
VQFN (RGE) | 24
3000 | LARGE T&R
Yes
NIPDAU | NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5728
MSP430FR5728IRGER.A
Active
Production
VQFN (RGE) | 24
3000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5728
MSP430FR5728IRGET
Active
Production
VQFN (RGE) | 24
250 | SMALL T&R
Yes
NIPDAU | NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5728
MSP430FR5728IRGET.A
Active
Production
VQFN (RGE) | 24
250 | SMALL T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
430FR
5728
MSP430FR5729IDA
Active
Production
TSSOP (DA) | 38
40 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5729
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable part number
(1)
17-Jun-2025
Status
Material type
(1)
(2)
Package | Pins
Package qty | Carrier
RoHS
(3)
Lead finish/
Ball material
MSL rating/
Peak reflow
(4)
(5)
Op temp (°C)
Part marking
(6)
MSP430FR5729IDA.A
Active
Production
TSSOP (DA) | 38
40 | TUBE
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5729
MSP430FR5729IDAR
Active
Production
TSSOP (DA) | 38
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5729
MSP430FR5729IDAR.A
Active
Production
TSSOP (DA) | 38
2000 | LARGE T&R
Yes
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430FR5729
MSP430FR5729IRHAR
Active
Production
VQFN (RHA) | 40
2500 | LARGE T&R
Yes
NIPDAU | NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5729
MSP430FR5729IRHAR.A
Active
Production
VQFN (RHA) | 40
2500 | LARGE T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5729
MSP430FR5729IRHAT
Active
Production
VQFN (RHA) | 40
250 | SMALL T&R
Yes
NIPDAU | NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5729
MSP430FR5729IRHAT.A
Active
Production
VQFN (RHA) | 40
250 | SMALL T&R
Yes
NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
FR5729
Status: For more details on status, see our product life cycle.
(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.
(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.
(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.
(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.
(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.
Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2025
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2025
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
M430FR5720IRGERG4
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.0
12.0
Q2
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
M430FR5728IRGERG4
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5720IPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
MSP430FR5720IRGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5720IRGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5720IRGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5720IRGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5721IDAR
TSSOP
DA
38
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
MSP430FR5721IRHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5721IRHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5721IRHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5721IRHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5722IRGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5722IRGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5723IRHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5723IRHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2025
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430FR5723IRHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5723IRHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5724IPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
MSP430FR5724IRGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5724IRGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5724IRGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5724IRGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5725IDAR
TSSOP
DA
38
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
MSP430FR5725IRHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5725IRHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5725IRHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5725IRHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5726IRGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5726IRGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5727IDAR
TSSOP
DA
38
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
MSP430FR5727IRHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5727IRHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5728IPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
MSP430FR5728IRGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5728IRGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5728IRGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5728IRGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430FR5729IDAR
TSSOP
DA
38
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
MSP430FR5729IRHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5729IRHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
MSP430FR5729IRHAT
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2025
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
M430FR5720IRGERG4
VQFN
RGE
24
3000
346.0
346.0
33.0
M430FR5728IRGERG4
VQFN
RGE
24
3000
346.0
346.0
33.0
MSP430FR5720IPWR
TSSOP
PW
28
2000
350.0
350.0
43.0
MSP430FR5720IRGER
VQFN
RGE
24
3000
356.0
356.0
35.0
MSP430FR5720IRGER
VQFN
RGE
24
3000
346.0
346.0
33.0
MSP430FR5720IRGET
VQFN
RGE
24
250
210.0
185.0
35.0
MSP430FR5720IRGET
VQFN
RGE
24
250
210.0
185.0
35.0
MSP430FR5721IDAR
TSSOP
DA
38
2000
350.0
350.0
43.0
MSP430FR5721IRHAR
VQFN
RHA
40
2500
356.0
356.0
35.0
MSP430FR5721IRHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
MSP430FR5721IRHAT
VQFN
RHA
40
250
210.0
185.0
35.0
MSP430FR5721IRHAT
VQFN
RHA
40
250
210.0
185.0
35.0
MSP430FR5722IRGET
VQFN
RGE
24
250
210.0
185.0
35.0
MSP430FR5722IRGET
VQFN
RGE
24
250
213.0
191.0
35.0
MSP430FR5723IRHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
MSP430FR5723IRHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
MSP430FR5723IRHAT
VQFN
RHA
40
250
210.0
185.0
35.0
MSP430FR5723IRHAT
VQFN
RHA
40
250
210.0
185.0
35.0
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2025
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430FR5724IPWR
TSSOP
PW
28
2000
350.0
350.0
43.0
MSP430FR5724IRGER
VQFN
RGE
24
3000
346.0
346.0
33.0
MSP430FR5724IRGER
VQFN
RGE
24
3000
356.0
356.0
35.0
MSP430FR5724IRGET
VQFN
RGE
24
250
210.0
185.0
35.0
MSP430FR5724IRGET
VQFN
RGE
24
250
210.0
185.0
35.0
MSP430FR5725IDAR
TSSOP
DA
38
2000
350.0
350.0
43.0
MSP430FR5725IRHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
MSP430FR5725IRHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
MSP430FR5725IRHAT
VQFN
RHA
40
250
210.0
185.0
35.0
MSP430FR5725IRHAT
VQFN
RHA
40
250
210.0
185.0
35.0
MSP430FR5726IRGER
VQFN
RGE
24
3000
356.0
356.0
35.0
MSP430FR5726IRGER
VQFN
RGE
24
3000
346.0
346.0
33.0
MSP430FR5727IDAR
TSSOP
DA
38
2000
350.0
350.0
43.0
MSP430FR5727IRHAT
VQFN
RHA
40
250
210.0
185.0
35.0
MSP430FR5727IRHAT
VQFN
RHA
40
250
210.0
185.0
35.0
MSP430FR5728IPWR
TSSOP
PW
28
2000
350.0
350.0
43.0
MSP430FR5728IRGER
VQFN
RGE
24
3000
346.0
346.0
33.0
MSP430FR5728IRGER
VQFN
RGE
24
3000
356.0
356.0
35.0
MSP430FR5728IRGET
VQFN
RGE
24
250
213.0
191.0
35.0
MSP430FR5728IRGET
VQFN
RGE
24
250
210.0
185.0
35.0
MSP430FR5729IDAR
TSSOP
DA
38
2000
350.0
350.0
43.0
MSP430FR5729IRHAR
VQFN
RHA
40
2500
367.0
367.0
38.0
MSP430FR5729IRHAT
VQFN
RHA
40
250
210.0
185.0
35.0
MSP430FR5729IRHAT
VQFN
RHA
40
250
213.0
191.0
35.0
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2025
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name
Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
MSP430FR5720IPW
PW
TSSOP
28
50
530
10.2
3600
3.5
MSP430FR5720IPW.A
PW
TSSOP
28
50
530
10.2
3600
3.5
MSP430FR5721IDA
DA
TSSOP
38
40
530
11.89
3600
4.9
MSP430FR5721IDA.A
DA
TSSOP
38
40
530
11.89
3600
4.9
MSP430FR5722IPW
PW
TSSOP
28
50
530
10.2
3600
3.5
MSP430FR5722IPW.A
PW
TSSOP
28
50
530
10.2
3600
3.5
MSP430FR5724IPW
PW
TSSOP
28
50
530
10.2
3600
3.5
MSP430FR5724IPW.A
PW
TSSOP
28
50
530
10.2
3600
3.5
MSP430FR5725IDA
DA
TSSOP
38
40
530
11.89
3600
4.9
MSP430FR5725IDA.A
DA
TSSOP
38
40
530
11.89
3600
4.9
MSP430FR5726IPW
PW
TSSOP
28
50
530
10.2
3600
3.5
MSP430FR5726IPW.A
PW
TSSOP
28
50
530
10.2
3600
3.5
MSP430FR5728IPW
PW
TSSOP
28
50
530
10.2
3600
3.5
MSP430FR5728IPW.A
PW
TSSOP
28
50
530
10.2
3600
3.5
MSP430FR5728IPWG4.A
PW
TSSOP
28
50
530
10.2
3600
3.5
MSP430FR5729IDA
DA
TSSOP
38
40
530
11.89
3600
4.9
MSP430FR5729IDA.A
DA
TSSOP
38
40
530
11.89
3600
4.9
Pack Materials-Page 5
GENERIC PACKAGE VIEW
RHA 40
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
6 x 6, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040D
VQFN - 1 mm max height
SCALE 2.200
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
A
B
PIN 1 INDEX AREA
0.5
0.3
6.1
5.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 4.5
(0.1) TYP
2.9 0.1
11
EXPOSED
THERMAL PAD
20
36X 0.5
10
21
2X
4.5
41
SYMM
1
SEE TERMINAL
DETAIL
PIN 1 ID
(OPTIONAL)
30
40
31
SYMM
40X
0.5
0.3
40X
0.3
0.2
0.1
0.05
C A
B
4225822/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHA0040D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 2.9)
SYMM
31
40
40X (0.6)
1
30
40X (0.25)
(1.2)
TYP
41
SYMM
(5.8)
36X (0.5)
( 0.2) TYP
VIA
10
21
(R0.05)
TYP
11
20
(5.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225822/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view.
www.ti.com
EXAMPLE STENCIL DESIGN
RHA0040D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(R0.05) TYP
SYMM
40
31
40X (0.6)
1
30
4X ( 1.27)
40X (0.25)
(0.735) TYP
(0.735)
TYP
41
SYMM
(5.8)
36X (0.5)
METAL
TYP
21
10
20
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
76.46% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4225822/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
4.1
3.9
B
A
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 2.5
2.1±0.1
20X 0.5
6
13
SYMM
25
2X
2.5
1
PIN 1 ID
(OPTIONAL)
(0.2) TYP
12
7
18
24
SYMM
19
24X 0.50
0.30
24X 0.30
0.18
0.1
0.05
C A B
C
4224376 / C 07/2021
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
(3.8)
(
2.1)
19
24
24X (0.6)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.8)
2X
(0.8)
(Ø0.2) VIA
TYP
6
13
(R0.05)
12
7
2X(0.8)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224376 / C 06/2021
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
RGE0024C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
(3.8)
4X ( 0.94)
24
19
24X (0.6)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.8)
(0.57)
TYP
6
13
(R0.05) TYP
METAL
TYP
25
7
SYMM
12
(0.57)
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 20X
4224376 / C 06/2021
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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