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Design
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
SLASE34E – MAY 2014 – REVISED AUGUST 2018
MSP430FR586x, MSP430FR584x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Embedded Microcontroller
– 16-Bit RISC Architecture up to 16‑MHz Clock
– Wide Supply Voltage Range From 3.6 V Down
to 1.8 V (Minimum Supply Voltage is Restricted
by SVS Levels, See the SVS Specifications)
• Optimized Ultra-Low-Power Modes
– Active Mode: Approximately 100 µA/MHz
– Standby (LPM3 With VLO): 0.4 µA (Typical)
– Real-Time Clock (LPM3.5): 0.25 µA (Typical) (1)
– Shutdown (LPM4.5): 0.02 µA (Typical)
• Ultra-Low-Power Ferroelectric RAM (FRAM)
– Up to 64KB of Nonvolatile Memory
– Ultra-Low-Power Writes
– Fast Write at 125 ns Per Word (64KB in 4 ms)
– Unified Memory = Program + Data + Storage in
One Single Space
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
• Intelligent Digital Peripherals
– 32-Bit Hardware Multiplier (MPY)
– 3-Channel Internal DMA
– Real-Time Clock (RTC) With Calendar and
Alarm Functions
– Five 16-Bit Timers With up to Seven
Capture/Compare Registers Each
– 16-Bit Cyclic Redundancy Checker (CRC)
• High-Performance Analog
– 16-Channel Analog Comparator
– 12-Bit Analog-to-Digital Converter (ADC)
With Internal Reference and Sample-and-Hold
and up to 16 External Input Channels
• Multifunction Input/Output Ports
– All Pins Support Capacitive Touch Capability
With No Need for External Components
(1)
•
•
•
•
•
RTC is clocked by a 3.7-pF crystal.
1.2
•
•
•
•
– Accessible Bit-, Byte-, and Word-Wise (in Pairs)
– Edge-Selectable Wake From LPM on All Ports
– Programmable Pullup and Pulldown on All Ports
Code Security and Encryption
– Random Number Seed for Random Number
Generation Algorithms
Enhanced Serial Communication
– eUSCI_A0 and eUSCI_A1 Support
– UART With Automatic Baud-Rate Detection
– IrDA Encode and Decode
– SPI
– eUSCI_B0 Supports
– I2C With Multiple Slave Addressing
– SPI
– Hardware UART and I2C Bootloader (BSL)
Flexible Clock System
– Fixed-Frequency DCO With 10 Selectable
Factory-Trimmed Frequencies
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– 32-kHz Crystals (LFXT)
– High-Frequency Crystals (HFXT)
Development Tools and Software
– Free Professional Development Environments
With EnergyTrace++™ Technology
– Development Kit (MSP-TS430RGZ48C)
Family Members
– Device Comparison Summarizes the Available
Device Variants and Package Types
For Complete Module Descriptions, See the
MSP430FR58xx, MSP430FR59xx, and
MSP430FR6xx Family User's Guide
Applications
Metering
Energy Harvested Sensor Nodes
Wearable Electronics
1.3
•
•
Sensor Management
Data Logging
Description
The MSP430™ ultra-low-power (ULP) FRAM platform combines uniquely embedded FRAM and a holistic
ultra-low-power system architecture, allowing innovators to increase performance at lowered energy
budgets. FRAM technology combines the speed, flexibility, and endurance of SRAM with the stability and
reliability of flash at much lower power.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
SLASE34E – MAY 2014 – REVISED AUGUST 2018
www.ti.com
The MSP430 ULP FRAM portfolio consists of a diverse set of devices featuring FRAM, the ULP 16-bit
MSP430 CPU, and intelligent peripherals targeted for various applications. The ULP architecture
showcases seven low-power modes, optimized to achieve extended battery life in energy-challenged
applications.
Device Information (1)
PART NUMBER
MSP430FR5869IRGZ
BODY SIZE (2)
VQFN (48)
7 mm × 7 mm
MSP430FR5859IRHA
VQFN (40)
6 mm × 6 mm
MSP430FR5859IDA
TSSOP (38)
12.5 mm × 6.2 mm
(1)
(2)
1.4
PACKAGE
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 9, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
Functional Block Diagram
Figure 1-1 shows the functional block diagram of the devices.
LFXIN,
HFXIN
LFXOUT,
HFXOUT
P1.x, P2.x
P3.x, P4.x
2x8
2x8
PJ.x
1x8
Capacitive Touch I/O 0,
Capacitive Touch I/O 1
ADC12_B
MCLK
Clock
System
ACLK
SMCLK
Comp_E
(up to 16
inputs)
DMA
Controller
3 Channel
Bus
Control
Logic
REF_A
(up to 16
standard
inputs,
up to 8
differential
inputs)
Voltage
Reference
I/O Ports
P1, P2
2x8 I/Os
I/O Ports
P3, P4
2x8 I/Os
PA
1x16 I/Os
PB
1x16 I/Os
I/O Port
PJ
1x8 I/Os
MAB
MDB
CPUXV2
incl. 16
Registers
MPU
IP Encap
EEM
(S: 3 + 1)
FRAM
RAM
64KB
48KB
32KB
2KB
1KB
TA2
TA3
Power
Mgmt
LDO
SVS
Brownout
CRC16
Watchdog
MPY32
Timer_A
2 CC
Registers
(int. only)
EnergyTrace++
MDB
JTAG
Interface
MAB
Spy-Bi-Wire
TB0
TA0
TA1
eUSCI_A0
eUSCI_A1
Timer_B
7 CC
Registers
(int, ext)
Timer_A
3 CC
Registers
(int, ext)
Timer_A
3 CC
Registers
(int, ext)
eUSCI_B0
2
(UART,
IrDA,
SPI)
(I C,
SPI)
RTC_B
LPM3.5 Domain
Copyright © 2016, Texas Instruments Incorporated
A.
B.
The low-frequency (LF) crystal oscillator and the corresponding LFXIN and LFXOUT pins are available in the
MSP430FR5x6x and MSP430FR5x4x devices only.
RTC_B is available only in conjunction with the LF crystal oscillator in MSP430FR5x6x and MSP430FR5x4x devices.
The high-frequency (HF) crystal oscillator and the corresponding HFXIN and HFXOUT pins are available in the
MSP430FR5x6x and MSP430FR5x5x devices only.
MSP430FR5x5x devices with the HF crystal oscillator only do not include the RTC_B module.
Figure 1-1. Functional Block Diagram
2
Device Overview
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859
MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
www.ti.com
SLASE34E – MAY 2014 – REVISED AUGUST 2018
Table of Contents
1
2
3
Device Overview ......................................... 1
1.2
Applications ........................................... 1
6.1
Overview
1.3
Description ............................................ 1
6.2
CPU
1.4
Functional Block Diagram ............................ 2
6.3
Revision History ......................................... 4
Device Comparison ..................................... 5
6.4
Related Products ..................................... 6
6.6
Terminal Configuration and Functions .............. 7
6.7
4.1
Pin Diagrams ......................................... 7
6.8
4.2
Signal Descriptions .................................. 12
6.9
.....................................
4.4
Connection of Unused Pins .........................
Specifications ...........................................
5.1
Absolute Maximum Ratings .........................
5.2
ESD Ratings ........................................
5.3
Recommended Operating Conditions ...............
4.3
5
Emulation and Debug ............................... 52
Features .............................................. 1
3.1
4
5.13
1.1
5.4
5.5
5.6
5.7
5.8
5.9
5.10
Pin Multiplexing
Active Mode Supply Current Into VCC Excluding
External Current ....................................
Typical Characteristics – Active Mode Supply
Currents .............................................
Low-Power Mode (LPM0, LPM1) Supply Currents
Into VCC Excluding External Current ................
Low-Power Mode (LPM2, LPM3, LPM4) Supply
Currents (Into VCC) Excluding External Current ....
Low-Power Mode (LPM3.5, LPM4.5) Supply
Currents (Into VCC) Excluding External Current ....
Typical Characteristics, Low-Power Mode Supply
Currents .............................................
Typical Characteristics, Current Consumption per
Module ..............................................
6
6.5
16
16
17
17
17
Detailed Description ................................... 53
7
17
8
19
20
21
22
23
5.11
Thermal Resistance Characteristics ................ 23
5.12
Timing and Switching Characteristics ............... 24
9
53
54
57
60
60
61
62
Memory Protection Unit Including IP Encapsulation 62
.......................................... 63
............................. 84
6.12 Device Descriptor (TLV) ........................... 112
6.13 Identification........................................ 115
Applications, Implementation, and Layout ...... 116
7.1
Device Connection and Layout Fundamentals .... 116
Peripherals
6.11
Input/Output Diagrams
7.2
Peripheral- and Interface-Specific Design
Information ......................................... 120
Device and Documentation Support .............. 122
...................
8.1
Getting Started and Next Steps
8.2
Device Nomenclature .............................. 122
8.3
Tools and Software ................................ 123
8.4
Documentation Support ............................ 125
8.5
Related Links
8.6
Community Resources............................. 127
8.7
Trademarks ........................................ 127
8.8
Electrostatic Discharge Caution
8.9
Export Control Notice .............................. 127
8.10
Glossary............................................ 127
......................................
...................
122
126
127
Mechanical, Packaging, and Orderable
Information ............................................. 128
Table of Contents
Submit Documentation Feedback
Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859
MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
Copyright © 2014–2018, Texas Instruments Incorporated
53
6.10
18
19
............................................
.................................................
Operating Modes ....................................
Interrupt Vector Table and Signatures ..............
Memory Organization ...............................
Bootloader (BSL) ....................................
JTAG Operation .....................................
FRAM................................................
3
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
SLASE34E – MAY 2014 – REVISED AUGUST 2018
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from March 10, 2017 to August 29, 2018
•
•
•
•
•
4
Page
Updated Section 3.1, Related Products ........................................................................................... 6
Added note (1) to Table 5-2, SVS................................................................................................. 25
Changed capacitor value from 4.7 µF to 470 nF in Figure 7-5, ADC12_B Grounding and Noise Considerations ... 120
Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of Section 7.2.1.2, Design Requirements ... 121
Updated text and figure in Section 8.2, Device Nomenclature .............................................................. 122
Revision History
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859
MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
www.ti.com
SLASE34E – MAY 2014 – REVISED AUGUST 2018
3 Device Comparison
Table 3-1 summarizes the available family members.
Table 3-1. Device Comparison (1) (2)
DEVICE
FRAM
(KB)
SRAM
(KB)
CLOCK
SYSTEM
ADC12_B
Comp_E
Timer_A (3)
Timer_B (4)
MSP430FR5869
64
2
DCO
HFXT
LFXT
16 ext, 2 int
ch.
16 ch.
3, 3 (7)
2, 2 (8)
MSP430FR5868
48
2
DCO
HFXT
LFXT
16 ext, 2 int
ch.
16 ch.
MSP430FR5867
32
1
DCO
HFXT
LFXT
16 ext, 2 int
ch.
MSP430FR58671
32
1
DCO
HFXT
LFXT
16 ext, 2 int
ch.
MSP430FR5849
64
2
DCO
LFXT
MSP430FR5848
MSP430FR5847
(3)
(4)
(5)
(6)
(7)
(8)
1
DCO
LFXT
DCO
LFXT
32
1
DCO
LFXT
MSP430FR5859
64
2
DCO
HFXT
MSP430FR5857
(2)
32
2
MSP430FR58471
MSP430FR5858
(1)
48
48
32
2
1
DCO
HFXT
DCO
HFXT
BSL
I/O
PACKAGE
1
no
UART
40
48 RGZ
2
1
no
UART
40
48 RGZ
7
2
1
no
UART
40
48 RGZ
3, 3 (7)
2, 2 (8)
7
2
1
no
I2C
40
48 RGZ
3, 3 (7)
2, 2 (8)
33
40 RHA
7
2
1
no
UART
31
38 DA
33
40 RHA
31
38 DA
33
40 RHA
31
38 DA
33
40 RHA
33
40 RHA
31
38 DA
33
40 RHA
31
38 DA
33
40 RHA
31
38 DA
7
2
3, 3 (7)
2, 2 (8)
7
16 ch.
3, 3 (7)
2, 2 (8)
16 ch.
16 ch.
12 ext,
2 int ch.
14 ext,
2 int ch.
16 ch.
12 ext,
2 int ch.
14 ext,
2 int ch.
16 ch.
12 ext,
2 int ch.
3, 3 (7)
2, 2 (8)
3, 3 (7)
2, 2 (8)
7
7
2
2
1
1
no
no
UART
UART
(7)
16 ch.
3, 3
2, 2 (8)
7
2
1
no
I2C
16 ch.
3, 3 (7)
2, 2 (8)
7
2
1
no
UART
14 ext,
2 int ch.
12 ext,
2 int ch.
14 ext,
2 int ch.
16 ch.
12 ext,
2 int ch.
14 ext,
2 int ch.
16 ch.
12 ext,
2 int ch.
AES
B (6)
14 ext,
2 int ch.
14 ext,
2 int ch.
eUSCI
A (5)
3, 3 (7)
2, 2 (8)
3, 3 (7)
2, 2 (8)
7
7
2
2
1
1
no
no
UART
UART
For the most current device, package, and ordering information for all available devices, see the Package Option Addendum in
Section 9, or see the TI website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare
registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare
registers and PWM output generators, respectively.
eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
eUSCI_B supports I2C with multiple slave addresses and SPI.
Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any).
Device Comparison
Submit Documentation Feedback
Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859
MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
Copyright © 2014–2018, Texas Instruments Incorporated
5
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
SLASE34E – MAY 2014 – REVISED AUGUST 2018
3.1
www.ti.com
Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers High-performance, low-power solutions to enable the autonomous
future
Products for MSP430 ultra-low-power sensing and measurement microcontrollers
One ecosystem. Endless possibilities.
One
platform.
Products for MSP430 ultrasonic and performance sensing microcontrollers Ultra-low-power singlechip MCUs with integrated sensing peripherals
Companion Products for MSP430FR5869 Review products that are frequently purchased or used with
this product.
Reference Designs for MSP430FR5869 The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
6
Device Comparison
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859
MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
www.ti.com
SLASE34E – MAY 2014 – REVISED AUGUST 2018
4 Terminal Configuration and Functions
4.1
Pin Diagrams
DVCC
P2.7
P2.3/TA0.0/UCA1STE/A6/C10
P2.4/TA1.0/UCA1CLK/A7/C11
AVSS
PJ.6/HFXIN
PJ.7/HFXOUT
AVSS
PJ.4/LFXIN
PJ.5/LFXOUT
AVSS
AVCC
Figure 4-1 shows the 48-pin RGZ package for the MSP430FR586x and MSP430FR586x1 MCUs.
48 47 46 45 44 43 42 41 40 39 38 37
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
1
36
DVSS
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
2
35
P4.6
P1.2/TA1.1/TA0CLK/COUT/A2/C2
3
34
P4.5
P3.0/A12/C12
4
33
P4.4/TB0.5
P3.1/A13/C13
5
32
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P3.2/A14/C14
6
31
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.3/A15/C15
7
30
P3.7/TB0.6
P4.7
8
29
P3.6/TB0.5
P1.3/TA1.2/UCB0STE/A3/C3
9
28
P3.5/TB0.4/COUT
P1.4/TB0.1/UCA0STE/A4/C4
10
27
P3.4/TB0.3/SMCLK
P1.5/TB0.2/UCA0CLK/A5/C5
11
26
P2.2/TB0.2/UCB0CLK
P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.6/TB0.1/UCA1RXD/UCA1SOMI
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P4.3/A11
P4.2/A10
P4.1/A9
P4.0/A8
PJ.3/TCK/SRCPUOFF/C9
PJ.2/TMS/ACLK/SROSCOFF/C8
25
12
13 14 15 16 17 18 19 20 21 22 23 24
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
NOTE: TI recommends connecting the QFN package pad to VSS.
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
NOTE: On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-1. 48-Pin RGZ Package (Top View) – MSP430FR586x and MSP430FR586x1
Terminal Configuration and Functions
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Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859
MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
Copyright © 2014–2018, Texas Instruments Incorporated
7
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
SLASE34E – MAY 2014 – REVISED AUGUST 2018
www.ti.com
DVSS
DVCC
P2.7
P2.3/TA0.0/UCA1STE/A6/C10
P2.4/TA1.0/UCA1CLK/A7/C11
AVSS
PJ.4/LFXIN
PJ.5/LFXOUT
AVSS
AVCC
Figure 4-2 shows the 40-pin RHA package for the MSP430FR584x and MSP430FR584x1 MCUs (LFXT
only).
40 39 38 37 36 35 34 33 32 31
4
27
P3.7/TB0.6
P3.1/A13/C13
5
26
P3.6/TB0.5
P3.2/A14/C14
6
25
P3.5/TB0.4/COUT
P3.3/A15/C15
7
24
P3.4/TB0.3/SMCLK
P1.3/TA1.2/UCB0STE/A3/C3
8
23
P2.2/TB0.2/UCB0CLK
P1.4/TB0.1/UCA0STE/A4/C4
9
22
P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
P1.5/TB0.2/UCA0CLK/A5/C5
10
21
11 12 13 14 15 16 17 18 19 20
P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.0/A12/C12
P2.6/TB0.1/UCA1RXD/UCA1SOMI
28
P2.5/TB0.0/UCA1TXD/UCA1SIMO
3
P4.1/A9
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P4.0/A8
29
PJ.3/TCK/SRCPUOFF/C9
P4.4/TB0.5
2
PJ.2/TMS/ACLK/SROSCOFF/C8
30
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7
1
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
NOTE: TI recommends connecting the QFN package pad to VSS.
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
NOTE: On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-2. 40-Pin RHA Package (Top View) – MSP430FR584x and MSP430FR584x1
8
Terminal Configuration and Functions
Copyright © 2014–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859
MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
www.ti.com
SLASE34E – MAY 2014 – REVISED AUGUST 2018
Figure 4-3 shows the 38-pin DA package for the MSP430FR584x MCUs (LFXT only).
PJ.4/LFXIN
1
38
AVSS
PJ.5/LFXOUT
2
37
P2.4/TA1.0/UCA1CLK/A7/C11
AVSS
3
36
P2.3/TA0.0/UCA1STE/A6/C10
AVCC
4
35
P2.7
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
5
34
DVCC
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
6
33
DVSS
P1.2/TA1.1/TA0CLK/COUT/A2/C2
7
32
P4.4/TB0.5
P3.0/A12/C12
8
31
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P3.1/A13/C13
9
30
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.2/A14/C14
10
29
P3.7/TB0.6
P3.3/A15/C15
11
28
P3.6/TB0.5
P1.3/TA1.2/UCB0STE/A3/C3
12
27
P3.5/TB0.4/COUT
P1.4/TB0.1/UCA0STE/A4/C4
13
26
P3.4/TB0.3/SMCLK
P1.5/TB0.2/UCA0CLK/A5/C5
14
25
P2.2/TB0.2/UCB0CLK
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
15
24
P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7
16
23
P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
PJ.2/TMS/ACLK/SROSCOFF/C8
17
22
RST/NMI/SBWTDIO
PJ.3/TCK/SRCPUOFF/C9
18
21
TEST/SBWTCK
P2.5/TB0.0/UCA1TXD/UCA1SIMO
19
20
P2.6/TB0.1/UCA1RXD/UCA1SOMI
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
Figure 4-3. 38-Pin DA Package (Top View) – MSP430FR584x
Terminal Configuration and Functions
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MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
Copyright © 2014–2018, Texas Instruments Incorporated
9
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
SLASE34E – MAY 2014 – REVISED AUGUST 2018
www.ti.com
DVSS
DVCC
P2.7
P2.3/TA0.0/UCA1STE/A6/C10
P2.4/TA1.0/UCA1CLK/A7/C11
AVSS
PJ.6/HFXIN
PJ.7/HFXOUT
AVSS
AVCC
Figure 4-4 shows the 40-pin RHA package for the MSP430FR585x MCUs (HFXT only).
40 39 38 37 36 35 34 33 32 31
4
27
P3.7/TB0.6
P3.1/A13/C13
5
26
P3.6/TB0.5
P3.2/A14/C14
6
25
P3.5/TB0.4/COUT
P3.3/A15/C15
7
24
P3.4/TB0.3/SMCLK
P1.3/TA1.2/UCB0STE/A3/C3
8
23
P2.2/TB0.2/UCB0CLK
P1.4/TB0.1/UCA0STE/A4/C4
9
22
P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
P1.5/TB0.2/UCA0CLK/A5/C5
21
10
11 12 13 14 15 16 17 18 19 20
P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.0/A12/C12
P2.6/TB0.1/UCA1RXD/UCA1SOMI
28
P2.5/TB0.0/UCA1TXD/UCA1SIMO
3
P4.1/A9
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P4.0/A8
29
PJ.3/TCK/SRCPUOFF/C9
P4.4/TB0.5
2
PJ.2/TMS/ACLK/SROSCOFF/C8
30
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7
1
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
P1.0/TA0.1/DMAE0/A0/C0/VREF-/VeREF-
NOTE: TI recommends connecting the QFN package pad to VSS.
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
Figure 4-4. 40-Pin RHA Package (Top View) – MSP430FR585x
10
Terminal Configuration and Functions
Copyright © 2014–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859
MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
www.ti.com
SLASE34E – MAY 2014 – REVISED AUGUST 2018
Figure 4-5 shows the 38-pin DA package for the MSP430FR585x MCUs (HFXT only).
PJ.6/HFXIN
1
38
AVSS
PJ.7/HFXOUT
2
37
P2.4/TA1.0/UCA1CLK/A7/C11
AVSS
3
36
P2.3/TA0.0/UCA1STE/A6/C10
AVCC
4
35
P2.7
P1.0/TA0.1/DMAE0/A0/C0/VREF-/VeREF-
5
34
DVCC
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
6
33
DVSS
P1.2/TA1.1/TA0CLK/COUT/A2/C2
7
32
P4.4/TB0.5
P3.0/A12/C12
8
31
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P3.1/A13/C13
9
30
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.2/A14/C14
10
29
P3.7/TB0.6
P3.3/A15/C15
11
28
P3.6/TB0.5
P1.3/TA1.2/UCB0STE/A3/C3
12
27
P3.5/TB0.4/COUT
P1.4/TB0.1/UCA0STE/A4/C4
13
26
P3.4/TB0.3/SMCLK
P1.5/TB0.2/UCA0CLK/A5/C5
14
25
P2.2/TB0.2/UCB0CLK
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
15
24
P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7
16
23
P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
PJ.2/TMS/ACLK/SROSCOFF/C8
17
22
RST/NMI/SBWTDIO
PJ.3/TCK/SRCPUOFF/C9
18
21
TEST/SBWTCK
P2.5/TB0.0/UCA1TXD/UCA1SIMO
19
20
P2.6/TB0.1/UCA1RXD/UCA1SOMI
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
Figure 4-5. 38-Pin DA Package (Top View) – MSP430FR585x
Terminal Configuration and Functions
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Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859
MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
Copyright © 2014–2018, Texas Instruments Incorporated
11
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
SLASE34E – MAY 2014 – REVISED AUGUST 2018
4.2
www.ti.com
Signal Descriptions
Table 4-1 describes the signals for all device variants and package options.
Table 4-1. Signal Descriptions
TERMINAL
NAME
NO. (2)
RGZ
RHA
I/O (1)
DESCRIPTION
DA
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA0 CCR1 capture: CCI1A input, compare: Out1
External DMA trigger
P1.0/TA0.1/DMAE0/
RTCCLK/A0/C0/VREF-/
VeREF-
1
1
5
I/O
RTC clock calibration output (not available on MSP430FR5x5x devices)
Analog input A0 for ADC
Comparator input C0
Output of negative reference voltage
Input for an external negative reference voltage to the ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA0 CCR2 capture: CCI2A input, compare: Out2
TA1 input clock
P1.1/TA0.2/TA1CLK/
COUT/A1/C1/VREF+/
VeREF+
2
2
6
I/O
Comparator output
Analog input A1 for ADC
Comparator input C1
Output of positive reference voltage
Input for an external positive reference voltage to the ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA1 CCR1 capture: CCI1A input, compare: Out1
P1.2/TA1.1/TA0CLK/
COUT/A2/C2
3
3
7
I/O
TA0 input clock
Comparator output
Analog input A2 for ADC
Comparator input C2
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.0/A12/C12
4
4
8
I/O
Analog input A12 for ADC
Comparator input C12
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.1/A13/C13
5
5
9
I/O
Analog input A13 for ADC
Comparator input C13
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.2/A14/C14
6
6
10
I/O
Analog input A14 for ADC
Comparator input C14
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.3/A15/C15
7
7
11
I/O
P4.7
8
N/A
N/A
I/O
Analog input A15 for ADC
Comparator input C15
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA1 CCR2 capture: CCI2A input, compare: Out2
P1.3/TA1.2/UCB0STE/
A3/C3
9
8
12
I/O
Slave transmit enable – eUSCI_B0 SPI mode
Analog input A3 for ADC
Comparator input C3
(1)
(2)
12
I = input, O = output
N/A = not available
Terminal Configuration and Functions
Copyright © 2014–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859
MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
www.ti.com
SLASE34E – MAY 2014 – REVISED AUGUST 2018
Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO. (2)
RGZ
RHA
I/O (1)
DESCRIPTION
DA
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR1 capture: CCI1A input, compare: Out1
P1.4/TB0.1/UCA0STE/
A4/C4
10
9
13
I/O
Slave transmit enable – eUSCI_A0 SPI mode
Analog input A4 for ADC
Comparator input C4
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR2 capture: CCI2A input, compare: Out2
P1.5/TB0.2/UCA0CLK/
A5/C5
11
10
14
I/O
Clock signal input – eUSCI_A0 SPI slave mode,
Clock signal output – eUSCI_A0 SPI master mode
Analog input A5 for ADC
Comparator input C5
General-purpose digital I/O
Test data output port
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1/C6
12
11
15
I/O
Switch all PWM outputs high impedance input – TB0
SMCLK output
Low-Power Debug: CPU Status Register Bit SCG1
Comparator input C6
General-purpose digital I/O
Test data input or test clock input
PJ.1/TDI/TCLK/MCLK/
SRSCG0/C7
13
12
16
I/O
MCLK output
Low-Power Debug: CPU Status Register Bit SCG0
Comparator input C7
General-purpose digital I/O
Test mode select
PJ.2/TMS/ACLK/
SROSCOFF/C8
14
13
17
I/O
ACLK output
Low-Power Debug: CPU Status Register Bit OSCOFF
Comparator input C8
General-purpose digital I/O
PJ.3/TCK/
SRCPUOFF/C9
15
14
18
I/O
Test clock
Low-Power Debug: CPU Status Register Bit CPUOFF
Comparator input C9
P4.0/A8
16
15
N/A
I/O
P4.1/A9
17
16
N/A
I/O
P4.2/A10
18
N/A
N/A
I/O
P4.3/A11
19
N/A
N/A
I/O
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
Analog input A8 for ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
Analog input A9 for ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
Analog input A10 for ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
Analog input A11 for ADC
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.5/TB0.0/UCA1TXD/
UCA1SIMO
20
17
19
I/O
TB0 CCR0 capture: CCI0B input, compare: Out0
Transmit data – eUSCI_A1 UART mode
Slave in, master out – eUSCI_A1 SPI mode
Terminal Configuration and Functions
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Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859
MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
Copyright © 2014–2018, Texas Instruments Incorporated
13
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
SLASE34E – MAY 2014 – REVISED AUGUST 2018
www.ti.com
Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO. (2)
RGZ
RHA
I/O (1)
DESCRIPTION
DA
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.6/TB0.1/UCA1RXD/
UCA1SOMI
21
18
20
I/O
TB0 CCR1 compare: Out1
Receive data – eUSCI_A1 UART mode
Slave out, master in – eUSCI_A1 SPI mode
TEST/SBWTCK
22
19
21
I
RST/NMI/SBWTDIO
23
20
22
I/O
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
Reset input active low
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR6 capture: CCI6B input, compare: Out6
P2.0/TB0.6/UCA0TXD/
UCA0SIMO/TB0CLK/
ACLK
Transmit data – eUSCI_A0 UART mode
24
21
23
I/O
BSL Transmit (UART BSL)
Slave in, master out – eUSCI_A0 SPI mode
TB0 clock input
ACLK output
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR0 capture: CCI0A input, compare: Out0
P2.1/TB0.0/UCA0RXD/
UCA0SOMI/TB0.0
25
22
24
I/O
Receive data – eUSCI_A0 UART mode
BSL receive (UART BSL)
Slave out, master in – eUSCI_A0 SPI mode
TB0 CCR0 capture: CCI0A input, compare: Out0
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.2/TB0.2/UCB0CLK
26
23
25
I/O
TB0 CCR2 compare: Out2
Clock signal input – eUSCI_B0 SPI slave mode
Clock signal output – eUSCI_B0 SPI master mode
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.4/TB0.3/SMCLK
27
24
26
I/O
TB0 CCR3 capture: CCI3A input, compare: Out3
SMCLK output
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.5/TB0.4/COUT
28
25
27
I/O
TB0 CCR4 capture: CCI4A input, compare: Out4
Comparator output
P3.6/TB0.5
29
26
28
I/O
P3.7/TB0.6
30
27
29
I/O
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR5 capture: CCI5A input, compare: Out5
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR6 capture: CCI6A input, compare: Out6
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR3 capture: CCI3B input, compare: Out3
P1.6/TB0.3/UCB0SIMO/
UCB0SDA/TA0.0
31
28
30
I/O
Slave in, master out – eUSCI_B0 SPI mode
I2C data – eUSCI_B0 I2C mode
BSL Data (I2C BSL)
TA0 CCR0 capture: CCI0A input, compare: Out0
14
Terminal Configuration and Functions
Copyright © 2014–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859
MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
www.ti.com
SLASE34E – MAY 2014 – REVISED AUGUST 2018
Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO. (2)
RGZ
RHA
I/O (1)
DESCRIPTION
DA
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TB0 CCR4 capture: CCI4B input, compare: Out4
P1.7/TB0.4/UCB0SOMI/
UCB0SCL/TA1.0
32
29
31
I/O
Slave out, master in – eUSCI_B0 SPI mode
I2C clock – eUSCI_B0 I2C mode
BSL clock (I2C BSL)
TA1 CCR0 capture: CCI0A input, compare: Out0
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.4/TB0.5
33
30
32
I/O
P4.5
34
N/A
N/A
I/O
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.6
35
N/A
N/A
I/O
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
DVSS
36
31
33
Digital ground supply
DVCC
37
32
34
Digital power supply
P2.7
38
33
35
I/O
TB0CCR5 capture: CCI5B input, compare: Out5
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA0 CCR0 capture: CCI0B input, compare: Out0
P2.3/TA0.0/UCA1STE/
A6/C10
39
34
36
I/O
Slave transmit enable – eUSCI_A1 SPI mode
Analog input A6 for ADC
Comparator input C10
General-purpose digital I/O with port interrupt and wakeup from LPMx.5
TA1 CCR0 capture: CCI0B input, compare: Out0
P2.4/TA1.0/UCA1CLK/
A7/C11
40
35
37
I/O
Clock signal input – eUSCI_A1 SPI slave mode
Clock signal output – eUSCI_A1 SPI master mode
Analog input A7 for ADC
Comparator input C11
AVSS
41
36
38
Analog ground supply
PJ.6/HFXIN
42
37
1
I/O
PJ.7/HFXOUT
43
38
2
I/O
AVSS
44
N/A
N/A
PJ.4/LFXIN
45
37
1
I/O
PJ.5/LFXOUT
46
38
2
I/O
AVSS
47
39
3
Analog ground supply
Analog power supply
General-purpose digital I/O
Input for high-frequency crystal oscillator HFXT (in RHA and DA packages:
MSP430FR585x devices only)
General-purpose digital I/O
Output for high-frequency crystal oscillator HFXT (in RHA and DA packages:
MSP430FR585x devices only)
Analog ground supply
General-purpose digital I/O
Input for low-frequency crystal oscillator LFXT (in RHA and DA packages:
MSP430FR584x devices only)
General-purpose digital I/O
AVCC
QFN Pad
48
40
4
Pad
Pad
N/A
Output of low-frequency crystal oscillator LFXT (in RHA and DA packages:
MSP430FR584x devices only)
QFN package exposed thermal pad. TI recommends connection to VSS.
Terminal Configuration and Functions
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MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
Copyright © 2014–2018, Texas Instruments Incorporated
15
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
SLASE34E – MAY 2014 – REVISED AUGUST 2018
4.3
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Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and diagrams of the
multiplexed ports, see Section 6.11.
4.4
Connection of Unused Pins
Table 4-2 lists the correct termination of all unused pins.
Table 4-2. Connection of Unused Pins (1)
PIN
POTENTIAL
AVCC
DVCC
AVSS
DVSS
Px.0 to Px.7
Open
RST/NMI
Set to port function, output direction (PxDIR.n = 1)
DVCC or VCC 47-kΩ pullup or internal pullup selected with 2.2-nF (10-nF (2)) pulldown
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
Open
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not
used as JTAG pins, these pins should be switched to port function, output
direction. When used as JTAG pins, these pins should remain open.
TEST
Open
This pin always has an internal pulldown enabled.
(1)
(2)
16
COMMENT
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the
Px.0 to Px.7 unused pin connection guidelines.
The pulldown capacitor should not exceed 2.2 nF when using devices in Spy-Bi-Wire mode or in 4wire JTAG mode with TI tools like FET interfaces or GANG programmers. If JTAG or Spy-Bi-Wire
access is not needed, up to a 10-nF pulldown capacitor may be used.
Terminal Configuration and Functions
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
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SLASE34E – MAY 2014 – REVISED AUGUST 2018
5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to VSS
Voltage difference between DVCC and AVCC pins
Voltage applied to any pin
MIN
MAX
–0.3
4.1
V
±0.3
V
–0.3
VCC + 0.3 V
(4.1 Max)
V
(2)
(3)
Diode current at any device pin
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(4)
–40
UNIT
±2
mA
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3
Recommended Operating Conditions
Typical data are based on VCC = 3.0 V, TA = 25°C (unless otherwise noted)
MIN
VCC
Supply voltage range applied at all DVCC and AVCC
pins (1) (2) (3)
VSS
Supply voltage applied at all DVSS and AVSS pins
TA
Operating free-air temperature
TJ
Operating junction temperature
CDVCC
fSYSTEM
Capacitor value at DVCC
fACLK
Maximum ACLK frequency
fSMCLK
Maximum SMCLK frequency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
1.8 (4)
MAX
UNIT
3.6
V
–40
85
°C
–40
85
°C
0
(5)
Processor frequency (maximum MCLK frequency) (6)
NOM
V
1–20%
µF
No FRAM wait states
(NWAITSx = 0)
0
8
With FRAM wait states
(NWAITSx = 1) (8)
0
16 (9)
(7)
MHz
50
kHz
16 (9)
MHz
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device
operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in Absolute Maximum Ratings.
Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
See Table 5-1 for additional important information.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
The minimum supply voltage is defined by the supervisor SVS levels. See Table 5-2 for the values.
Connect a low-ESR capacitor with at least the value specified and a maximum tolerance of 20% as close as possible to the DVCC pin.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
DCO settings and HF crystals with a typical value less or equal the specified MAX value are permitted.
Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always executed
without wait states.
DCO settings and HF crystals with a typical value less or equal the specified MAX value are permitted. If a clock sources with a larger
typical value is used, the clock must be divided in the clock system.
Specifications
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SLASE34E – MAY 2014 – REVISED AUGUST 2018
5.4
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Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2)
FREQUENCY (fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
VCC
1 MHz
0 wait states
(NWAITSx = 0)
TYP
IAM, FRAM_UNI
(Unified memory) (3)
IAM, FRAM (0%) (4)
(5)
MAX
4 MHz
0 wait states
(NWAITSx = 0)
TYP
MAX
8 MHz
0 wait states
(NWAITSx = 0)
TYP
MAX
12 MHz
1 wait states
(NWAITSx = 1)
TYP
MAX
16 MHz
1 wait states
(NWAITSx = 1)
TYP
UNIT
MAX
FRAM
3.0 V
210
640
1220
1475
1845
µA
FRAM
0% cache hit
ratio
3.0 V
370
1280
2510
2080
2650
µA
IAM, FRAM (50%) (4)
(5)
FRAM
50% cache hit
ratio
3.0 V
240
745
1440
1575
1990
µA
IAM, FRAM (66%) (4)
(5)
FRAM
66% cache hit
ratio
3.0 V
200
560
1070
1300
1620
µA
IAM, FRAM (75%) (4)
(5)
FRAM
75% cache hit
ratio
3.0 V
170
480
890
FRAM
100% cache hit
ratio
3.0 V
110
235
420
640
730
RAM
3.0 V
130
320
585
890
1070
RAM
3.0 V
100
290
555
860
1040
IAM, FRAM (100%) (4)
IAM,
RAM
(6)
IAM, RAM only
(1)
(2)
(3)
(4)
(5)
(6)
(7)
18
(5)
(7) (5)
255
180
1085
1155
1310
1420
1620
µA
µA
µA
1300
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO= 24 MHz and
fMCLK = fSMCLK = fDCO/2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff:
fMCLK,eff = fMCLK / [wait states × (1 – cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio, fMCKL,eff = fMCLK / [1 × (1 – 0.75) + 1] = fMCLK / 1.25.
Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio implies three of
every four accesses is from cache, and the remaining are FRAM accesses.
See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data from Section 5.4.
Program and data reside entirely in RAM. All execution is from RAM.
Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Specifications
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
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5.5
SLASE34E – MAY 2014 – REVISED AUGUST 2018
Typical Characteristics – Active Mode Supply Currents
3000
I(AM,0%)
I(AM,50%)
2500
I(AM,66%)
Active Mode Current (µA)
I(AM,75%)
2000
I(AM,100%)
I(AM,75%) [µA] = 103 × f [MHz] + 68
I(AM,RAMonly)
1500
1000
500
0
0
1
2
3
4
5
6
7
8
9
MCLK Frequency (MHz)
C001
NOTE: I(AM, cache hit ratio): Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with
cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of
FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are
FRAM accesses.
NOTE: I(AM, RAMonly): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Figure 5-1. Typical Active Mode Supply Currents vs MCLK frequency, No Wait States
5.6
Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2)
FREQUENCY (fSMCLK)
PARAMETER
VCC
1 MHz
TYP
ILPM0
ILPM1
(1)
(2)
2.2 V
70
3.0 V
80
2.2 V
35
3.0 V
35
4 MHz
8 MHz
TYP
MAX
TYP
16 MHz
TYP
95
150
250
215
115
105
160
260
225
60
115
215
180
60
115
215
180
60
MAX
12 MHz
MAX
MAX
TYP
UNIT
MAX
260
205
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO = 24 MHz and fSMCLK =
fDCO / 2.
Specifications
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
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SLASE34E – MAY 2014 – REVISED AUGUST 2018
5.7
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Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
–40°C
TYP
MAX
25°C
TYP
ILPM2,XT12
Low-power mode 2, 12-pF
crystal (2) (3) (4)
2.2 V
0.5
0.9
3.0 V
0.5
0.9
ILPM2,XT3.7
Low-power mode 2, 3.7-pF
cyrstal (2) (5) (4)
2.2 V
0.5
3.0 V
0.5
ILPM2,VLO
Low-power mode 2, VLO,
includes SVS (6)
2.2 V
0.3
0.7
3.0 V
0.3
0.7
Low-power mode 3, 12-pF
crystal, excludes SVS (2) (3)
2.2 V
0.5
0.6
ILPM3,XT12
(7)
3.0 V
0.5
0.6
Low-power mode 3, 3.7-pF
cyrstal, excludes SVS (2) (5)
2.2 V
0.4
3.0 V
ILPM3,XT3.7
(8)
(also see Figure 5-2)
(1)
60°C
MAX
TYP
MAX
85°C
TYP
2.2
6.1
2.2
6.1
0.9
2.2
6.0
0.9
2.2
6.0
1.9
5.8
1.9
5.8
0.9
1.85
0.9
1.85
0.5
0.8
1.7
0.4
0.5
0.8
1.7
0.7
1.6
0.7
1.6
0.8
1.7
0.8
1.7
0.6
1.5
0.6
1.5
ILPM3,VLO
Low-power mode 3,
VLO, excludes SVS (9)
2.2 V
0.3
0.4
3.0 V
0.3
0.4
Low-power mode 4, includes
SVS (10)
(also see Figure 5-3)
2.2 V
0.4
0.5
ILPM4,SVS
3.0 V
0.4
0.5
ILPM4
Low-power mode 4,
excludes SVS (11)
2.2 V
0.2
0.3
3.0 V
0.2
0.3
1.8
1.6
0.9
0.7
0.8
0.6
MAX
17
UNIT
μA
μA
16.7
4.9
μA
μA
μA
4.7
4.8
4.6
μA
μA
μA
(1)
(2)
(3)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
(4) Low-power mode 2, crystal oscillator test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout and SVS are included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen
to closely match the required 3.7-pF load.
(6) Low-power mode 2, VLO test conditions:
Current for watchdog timer clocked by ACLK is included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS are included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 3, 12-pF crystal, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout is included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(8) Low-power mode 3, 3.7-pF crystal, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 are included. Current for brownout is included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(9) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK is included. RTC disabled (RTCHOLD = 1). Current for brownout is included. SVS is
disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(10) Low-power mode 4, includes SVS test conditions:
Current for brownout and SVS are included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
(11) Low-power mode 4, excludes SVS test conditions:
Current for brownout is included. SVS is disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
20
Specifications
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
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SLASE34E – MAY 2014 – REVISED AUGUST 2018
Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
–40°C
25°C
(1)
60°C
85°C
PARAMETER
VCC
IIDLE,GroupA
Additional idle current if one
or more modules from Group
A (see Table 6-3) are
activated in LPM3 or LPM4.
3.0V
0.02
0.33
1.3
μA
IIDLE,GroupB
Additional idle current if one
or more modules from Group
B (see Table 6-3) are
activated in LPM3 or LPM4
3.0V
0.015
0.25
1.0
μA
5.8
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
UNIT
Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
–40°C
TYP
25°C
MAX
TYP
ILPM3.5,XT12
Low-power mode 3.5, 12-pF
crystal, includes SVS (2) (3) (4)
2.2 V
0.4
0.45
3.0 V
0.4
0.45
Low-power mode 3.5, 3.7-pF
cyrstal, excludes SVS (2) (5) (6)
(also see Figure 5-4)
2.2 V
0.2
ILPM3.5,XT3.7
3.0 V
ILPM4.5,SVS
Low-power mode 4.5,
includes SVS (7)
(also see Figure 5-5)
ILPM4.5
Low-power mode 4.5,
excludes SVS (8)
(also see Figure 5-5)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
60°C
MAX
TYP
85°C
MAX
TYP
0.5
0.7
0.5
0.7
0.25
0.3
0.45
0.2
0.25
0.3
0.5
2.2 V
0.2
0.2
0.2
0.3
3.0 V
0.2
0.2
0.2
0.3
2.2 V
0.02
0.02
0.02
0.08
3.0 V
0.02
0.02
0.02
0.08
0.7
0.4
MAX
1.2
UNIT
μA
μA
0.55
0.35
μA
μA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5-pF load.
Low-power mode 3.5, 12-pF crystal, includes SVS test conditions:
Current for RTC clocked by XT1 is included. Current for brownout and SVS are included (SVSHE = 1). Core regulator is disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Characterized with a SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are chosen
to closely match the required 3.7-pF load.
Low-power mode 3.5, 3.7-pF crystal, excludes SVS test conditions:
Current for RTC clocked by XT1 is included. Current for brownout is included. SVS is disabled (SVSHE = 0). Core regulator isdisabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS are included (SVSHE = 1). Core regulator is disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, excludes SVS test conditions:
Current for brownout is included. SVS is disabled (SVSHE = 0). Core regulator is disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Specifications
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Copyright © 2014–2018, Texas Instruments Incorporated
21
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
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SLASE34E – MAY 2014 – REVISED AUGUST 2018
5.9
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Typical Characteristics, Low-Power Mode Supply Currents
2
2
3.0 V, SVS on
2.2 V, SVS on
1.8
3.0 V, SVS on
1.8
2.2 V, SVS on
3.0 V, SVS off
1.6
2.2 V, SVS off
LPM4 Supply Current (µA)
LPM3 Supply Current (µA)
1.6
1.4
1.2
1
0.8
0.6
1.4
1.2
1
0.8
0.6
0.4
0.4
0.2
0.2
0
-50.00
0.00
50.00
0
-50.00
100.00
0.00
Temperature (°C)
50.00
100.00
Temperature (°C)
C003
C001
Figure 5-2. LPM3,XT3.7 Supply Current vs Temperature
Figure 5-3. LPM4,SVS Supply Current vs Temperature
0.5
0.5
3.0 V, SVS on
2.2 V, SVS on
3.0 V, SVS off
2.2 V, SVS off
3.0 V, SVS off
2.2 V, SVS off
0.4
LPM4.5 Supply Current (µA)
LPM3.5 Supply Current (µA)
0.4
0.3
0.2
0.1
0.3
0.2
0.1
0
-50.00
0.00
50.00
100.00
Temperature (°C)
0
-50.00
0.00
50.00
C003
Figure 5-4. LPM3.5,XT3.7 Supply Current vs Temperature
22
Specifications
100.00
Temperature (°C)
C004
Figure 5-5. LPM4.5 Supply Current vs Temperature
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SLASE34E – MAY 2014 – REVISED AUGUST 2018
5.10 Typical Characteristics, Current Consumption per Module (1)
MODULE
TEST CONDITIONS
REFERENCE CLOCK
Timer_A
Module input clock
Timer_B
MIN
TYP
MAX
UNIT
3
μA/MHz
Module input clock
5
μA/MHz
eUSCI_A
UART mode
Module input clock
5.5
μA/MHz
eUSCI_A
SPI mode
Module input clock
3.5
μA/MHz
eUSCI_B
SPI mode
Module input clock
3.5
μA/MHz
eUSCI_B
I2C mode, 100 kbaud
Module input clock
3.5
μA/MHz
32 kHz
100
nA
RTC_B
MPY
Only from start to end of operation
MCLK
25
μA/MHz
CRC
Only from start to end of operation
MCLK
2.5
μA/MHz
(1)
For other module currents not listed here, see the module specific parameter sections.
5.11 Thermal Resistance Characteristics
VALUE
UNIT
θJA
Junction-to-ambient thermal resistance, still air (1)
THERMAL METRIC
PACKAGE
30.6
°C/W
θJC(TOP)
Junction-to-case (top) thermal resistance (2)
17.2
°C/W
θJB
Junction-to-board thermal resistance (3)
7.2
°C/W
ΨJB
Junction-to-board thermal characterization parameter
7.2
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.2
°C/W
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance (4)
1.2
°C/W
θJA
Junction-to-ambient thermal resistance, still air (1)
30.1
°C/W
18.7
°C/W
6.4
°C/W
6.3
°C/W
0.3
°C/W
QFN-48 (RGZ)
(2)
θJC(TOP)
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (3)
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
QFN-40 (RHA)
(4)
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance
1.5
°C/W
θJA
Junction-to-ambient thermal resistance, still air (1)
65.5
°C/W
θJC(TOP)
Junction-to-case (top) thermal resistance (2)
12.5
°C/W
32.3
°C/W
31.8
°C/W
0.3
°C/W
N/A
°C/W
(3)
θJB
Junction-to-board thermal resistance
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
θJC(BOTTOM)
(1)
(2)
(3)
(4)
Junction-to-case (bottom) thermal resistance
(4)
TSSOP-38 (DA)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Specifications
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5.12 Timing and Switching Characteristics
5.12.1 Power Supply Sequencing
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the
device including erroneous writes to RAM and FRAM.
At power up, the device does not start executing code before the supply voltage reaches VSVSH+ if the
supply rises monotonically to this level.
Table 5-1 lists the reset power ramp requirements.
Table 5-1. Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VVCC_BOR–
Brownout power-down level (1) (2)
VVCC_BOR+
Brownout power-up level (2)
(1)
(2)
(3)
(4)
| dDVCC/dt | < 3 V/s (3)
| dDVCC/dt | > 300 V/s
MIN
TYP
0.7
(3)
MAX
UNIT
1.66
V
0
| dDVCC/dt | < 3 V/s (4)
0.79
V
1.68
V
In case of a supply voltage brownout, the device supply voltages need to ramp down to the specified brownout power-down level
VVCC_BOR- before the voltage is ramped up again to ensure a reliable device start-up and performance according to the data sheet
including the correct operation of the on-chip SVS module.
Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
The brownout levels are measured with a slowly changing supply. With faster slopes the MIN level required to reset the device properly
can decrease to 0 V. Use the graph in Figure 5-6 to estimate the VVCC_BOR- level based on the down slope of the supply voltage. After
removing VCC the down slope can be estimated based on the current consumption and the capacitance on DVCC: dV/dt = I/C with
dV/dt: slope, I: current, C: capacitance.
The brownout levels are measured with a slowly changing supply.
2
Brownout Power-Down Level (V)
Process-Temperature Corner Case 1
1.5
Typical
1
Process-Temperature Corner Case 2
MIN Limit
0.5
V VCC_BOR- for reliable
device start-up
0
1
10
100
1000
10000
100000
Supply Voltage Power-Down Slope (V/s)
Figure 5-6. Brownout Power-Down Level vs Supply Voltage Down Slope
24
Specifications
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Table 5-2 lists the characteristics of the SVS.
Table 5-2. SVS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISVSH,LPM
TEST CONDITIONS
(1)
VSVSH-
SVSH power-down level
VSVSH+
SVSH power-up level (1)
VSVSH_hys
SVSH hysteresis
tPD,SVSH, AM
SVSH propagation delay, active mode
(1)
MIN
TYP
MAX
UNIT
170
300
nA
1.75
1.80
1.85
V
1.77
1.88
1.99
V
120
mV
10
µs
SVSH current consumption, low power modes
40
dVVcc/dt = –10 mV/µs
For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference
Design.
5.12.2 Reset Timing
Table 5-11 lists the required reset input timing.
Table 5-3. Reset Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
t(RST)
(1)
External reset pulse duration on RST (1)
2.2 V, 3.0 V
MIN
MAX
2
UNIT
µs
Not applicable if RST/NMI pin configured as NMI.
Specifications
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5.12.3 Clock Specifications
Table 5-4 lists the characteristics of the LFXT.
Table 5-4. Low-Frequency Crystal Oscillator, LFXT (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF, ESR ≈ 44 kΩ
IVCC.LFXT
Current consumption
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {1},
TA = 25°C, CL,eff = 6 pF, ESR ≈ 40 kΩ
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {2},
TA = 25°C, CL,eff = 9 pF, ESR ≈ 40 kΩ
LFXT oscillator crystal frequency
LFXTBYPASS = 0
DCLFXT
LFXT oscillator duty cycle
Measured at ACLK,
fLFXT = 32768 Hz
fLFXT,SW
LFXT oscillator logic-level
square-wave input frequency
LFXTBYPASS = 1 (2)
DCLFXT, SW
LFXT oscillator logic-level
square-wave input duty cycle
LFXTBYPASS = 1
OALFXT
Oscillation allowance for
LF crystals (4)
MAX
185
3.0 V
nA
225
330
32768
30%
(3)
UNIT
180
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF, ESR ≈ 40 kΩ
fLFXT
TYP
10.5
Hz
70%
32.768
30%
50
kHz
70%
LFXTBYPASS = 0, LFXTDRIVE = {1},
fLFXT = 32768 Hz, CL,eff = 6 pF
210
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
300
kΩ
CLFXIN
Integrated load capacitance at
LFXIN terminal (5) (6)
2
pF
CLFXOUT
Integrated load capacitance at
LFXOUT terminal (5) (6)
2
pF
(1)
(2)
(3)
(4)
(5)
(6)
26
To improve EMI on the LFXT oscillator, observe the following guidelines.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
• Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
• For LFXTDRIVE = {1}, CL,eff = 6 pF
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 9 pF
• For LFXTDRIVE = {3}, 9 pF ≤ CL,eff ≤ 12.5 pF
This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the LFXIN and LFXOUT terminals, respectively.
Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
Specifications
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
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SLASE34E – MAY 2014 – REVISED AUGUST 2018
Table 5-4. Low-Frequency Crystal Oscillator, LFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tSTART,LFXT
(9)
(7)
Oscillator fault frequency (8)
fFault,LFXT
(7)
(8)
Start-up time
TEST CONDITIONS
VCC
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF
3.0 V
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
3.0 V
MIN
TYP
MAX
UNIT
800
ms
(9)
1000
0
3500
Hz
Includes start-up counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition sets the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Table 5-5 lists the characteristics of the HFXT.
Table 5-5. High-Frequency Crystal Oscillator, HFXT (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1 (2)
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
IDVCC.HFXT
HFXT oscillator
crystal current HF
mode at typical
ESR
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 1,
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 2, HFFREQ = 2,
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
fHFXT
HFXT oscillator
duty cycle
DCHFXT
HFXT oscillator
logic-level squarewave input
frequency, bypass
mode
fHFXT,SW
DCHFXT,
(1)
(2)
(3)
(4)
SW
HFXTBYPASS = 0, HFFREQ = 1 (2) (3)
MAX
120
3.0 V
μA
190
250
4
8
HFXTBYPASS = 0, HFFREQ = 2 (3)
8.01
16
HFXTBYPASS = 0, HFFREQ = 3 (3)
16.01
24
Measured at SMCLK, fHFXT = 16 MHz
40%
50%
0.9
4
HFXTBYPASS = 1, HFFREQ = 1 (4) (3)
4.01
8
(4) (3)
8.01
16
HFXTBYPASS = 1, HFFREQ = 3 (4) (3)
16.01
24
40%
60%
HFXTBYPASS = 1, HFFREQ = 2
HFXT oscillator
logic-level squareHFXTBYPASS = 1
wave input duty
cycle
MHz
60%
(4) (3)
HFXTBYPASS = 1, HFFREQ = 0
UNIT
75
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
HFXT oscillator
crystal frequency,
crystal mode
TYP
MHz
To improve EMI on the HFXT oscillator, observe the following guidelines.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
• Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
HFFREQ = {0} is not supported for HFXT crystal mode of operation.
Maximum frequency of operation of the entire device cannot be exceeded.
When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT, SW.
Specifications
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Table 5-5. High-Frequency Crystal Oscillator, HFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tSTART,HFXT
Start-up time
TEST CONDITIONS
(5)
VCC
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1,
TA = 25°C, CL,eff = 16 pF
3.0 V
fOSC = 24 MHz ,
HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TA = 25°C, CL,eff = 16 pF
3.0 V
MIN
MAX
UNIT
1.6
ms
0.6
Integrated load
capacitance at
HFXIN terminaI (6)
CHFXIN
TYP
2
pF
2
pF
(7)
CHFXOUT
Integrated load
capacitance at
HFXOUT
terminaI (6) (7)
fFault,HFXT
Oscillator fault
frequency (8) (9)
(5)
(6)
(7)
(8)
(9)
28
0
800
kHz
Includes start-up counter of 1024 clock cycles.
This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the HFXIN and HFXOUT terminals, respectively.
Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static
condition or stuck at fault condition set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
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SLASE34E – MAY 2014 – REVISED AUGUST 2018
Table 5-6 lists the characteristics of the DCO.
Table 5-6. DCO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
1
±3.5%
MHz
fDCO1
DCO frequency range
1 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 0,
DCORSEL = 1, DCOFSEL = 0
fDCO2.7
DCO frequency range
2.7 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 1
2.667
±3.5%
MHz
fDCO3.5
DCO frequency range
3.5 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 2
3.5
±3.5%
MHz
fDCO4
DCO frequency range
4 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 3
4
±3.5%
MHz
fDCO5.3
DCO frequency range
5.3 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 4,
DCORSEL = 1, DCOFSEL = 1
5.333
±3.5%
MHz
fDCO7
DCO frequency range
7 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 5,
DCORSEL = 1, DCOFSEL = 2
7
±3.5%
MHz
fDCO8
DCO frequency range
8 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 6,
DCORSEL = 1, DCOFSEL = 3
8
±3.5%
MHz
fDCO16
DCO frequency range
16 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 1, DCOFSEL = 4
16
±3.5% (1)
MHz
fDCO21
DCO frequency range
21 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 5
21
±3.5% (1)
MHz
fDCO24
DCO frequency range
24 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 6
24
±3.5% (1)
MHz
Duty cycle
Measured at SMCLK, divide by 1,
no external divide, all
DCORSEL/DCOFSEL settings except
DCORSEL = 1, DCOFSEL = 5 and
DCORSEL = 1, DCOFSEL = 6
50%
52%
DCO jitter
Based on fsignal = 10 kHz and DCO used
for 12-bit SAR ADC sampling source.
This achieves >74 dB SNR due to jitter
(that is, it is limited by ADC
performance).
2
3
fDCO,DC
tDCO,
JITTER
dfDCO/dT
(1)
(2)
DCO temperature drift (2)
48%
3.0 V
0.01
ns
%/ºC
After a wakeup from LPM1, LPM2, LPM3, or LPM4, the DCO frequency fDCO might exceed the specified frequency range for a few clock
cycles by up to 5% before settling into the specified steady-state frequency range.
Calculated using the box method: (MAX(–40ºC to 85ºC) – MIN(–40ºC to 85ºC)) / MIN(–40ºC to 85ºC) / (85ºC – (–40ºC))
Specifications
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Table 5-7 lists the characteristics of the VLO.
Table 5-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IVLO
Current consumption
fVLO
VLO frequency
Measured at ACLK
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
dfVLO/dVCC
VLO frequency supply voltage drift
Measured at ACLK (2)
fVLO,DC
Duty cycle
Measured at ACLK
(1)
(2)
MIN
TYP
MAX
100
6
nA
9.4
14
0.2
kHz
%/°C
0.7
40%
UNIT
%/V
50%
60%
Calculated using the box method: (MAX(–40ºC to 85°C) – MIN(–40ºC to 85°C)) / MIN(–40ºC to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Table 5-8 lists the characteristics of the MODOSC.
Table 5-8. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IMODOSC
Current consumption
fMODOSC
MODOSC frequency
fMODOSC/dT
MODOSC frequency temperature drift (1)
fMODOSC/dVCC
MODOSC frequency supply voltage
drift (2)
DCMODOSC
Duty cycle
(1)
(2)
30
TEST CONDITIONS
MIN
TYP
4.0
4.8
Enabled
MAX
UNIT
5.4
MHz
25
Measured at SMCLK, divide by 1
40%
μA
0.08
%/℃
1.4
%/V
50%
60%
Calculated using the box method: (MAX(–40ºC to 85°C) – MIN(–40ºC to 85°C)) / MIN(–40ºC to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
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5.12.4 Wake-up Characteristics
Table 5-9 list the device wake-up times.
Table 5-9. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
6
10
μs
400 +
1.5 / fDCO
ns
tWAKE-UP FRAM
(Additional) wake-up time to activate the FRAM
in AM if previously disabled by the FRAM
controller or from an LPM if immediate
activation is selected for wakeup
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode (1)
2.2 V, 3.0 V
tWAKE-UP LPM1
Wake-up time from LPM1 to active mode (1)
2.2 V, 3.0 V
6
tWAKE-UP LPM2
Wake-up time from LPM2 to active mode
(1)
2.2 V, 3.0 V
6
tWAKE-UP LPM3
Wake-up time from LPM3 to active mode (1)
2.2 V, 3.0 V
7
10
μs
tWAKE-UP LPM4
Wake-up time from LPM4 to active mode (1)
2.2 V, 3.0 V
7
10
μs
μs
tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode
(2)
tWAKE-UP-BOR
(1)
(2)
μs
2.2 V, 3.0 V
250
350
SVSHE = 1
2.2 V, 3.0 V
250
350
μs
SVSHE = 0
2.2 V, 3.0 V
1
1.5
ms
Wake-up time from a RST pin triggered reset to
active mode (2)
2.2 V, 3.0 V
250
350
μs
(2)
2.2 V, 3.0 V
1
1.5
ms
tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode (2)
tWAKE-UP-RST
μs
Wake-up time from power-up to active mode
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge. MCLK is sourced by the DCO and the MCLK divider is set to divide-by-1 (DIVMx = 000b,
fMCLK = fDCO). This time includes the activation of the FRAM during wakeup.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
Table 5-10 list the typical wake-up charges.
Table 5-10. Typical Wake-up Charge (1)
also see Figure 5-7 and Figure 5-8
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QWAKE-UP FRAM
Charge used for activating the FRAM in AM or during wakeup
from LPM0 if previously disabled by the FRAM controller.
15.1
nAs
QWAKE-UP LPM0
Charge used for wakeup from LPM0 to active mode (with FRAM
active)
4.4
nAs
QWAKE-UP LPM1
Charge used for wakeup from LPM1 to active mode (with FRAM
active)
15.1
nAs
QWAKE-UP LPM2
Charge used for wakeup from LPM2 to active mode (with FRAM
active)
15.3
nAs
QWAKE-UP LPM3
Charge used for wakeup from LPM3 to active mode (with FRAM
active)
16.5
nAs
QWAKE-UP LPM4
Charge used for wakeup from LPM4 to active mode (with FRAM
active)
16.5
nAs
76
nAs
SVSHE = 1
77
nAs
SVSHE = 0
77.5
nAs
75
nAs
(2)
QWAKE-UP LPM3.5
Charge used for wakeup from LPM3.5 to active mode
QWAKE-UP LPM4.5
Charge used for wakeup from LPM4.5 to active mode (2)
QWAKE-UP-RESET
Charge used for reset from RST or BOR event to active mode (2)
(1)
(2)
Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active
mode (for example, for an interrupt service routine).
Charge required until start of user code. This does not include the energy required to reconfigure the device.
Specifications
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5.12.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
10000.00
LPM0
LPM1
Average Wake-up Current (µA)
1000.00
LPM2,XT12
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wakeup current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 5-7. Average LPM Currents vs Wake-up Frequency at 25°C
10000.00
LPM0
LPM1
Average Wake-up Current (µA)
1000.00
LPM2,XT12
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wakeup current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 5-8. Average LPM Currents vs Wake-up Frequency at 85°C
32
Specifications
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
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5.12.5 Digital I/Os
Table 5-11 lists the characteristics of the digital inputs.
Table 5-11. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
2.2 V
1.2
1.65
3.0 V
1.65
2.25
2.2 V
0.55
1.00
3.0 V
0.75
1.35
2.2 V
0.44
0.98
3.0 V
0.60
1.30
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
3
pF
CI,ana
Input capacitance, port pins with shared analog
VIN = VSS or VCC
functions (1)
5
pF
Ilkg(Px.y)
High-impedance input leakage current
See
t(int)
External interrupt timing (external trigger pulse
duration to set interrupt flag) (4)
Ports with interrupt capability
(see Section 1.4 and
Section 4.2)
t(RST)
External reset pulse duration on RST (5)
(1)
(2)
(3)
(4)
(5)
(2) (3)
20
35
50
V
V
V
kΩ
2.2 V,
3.0 V
–20
2.2 V,
3.0 V
20
ns
2.2 V,
3.0 V
2
µs
+20
nA
If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in
series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and/or
PJ.5/LFXOUT.
The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The input leakage of the digital port pins is measured individually. The port pin is selected for input, and the pullup or pulldown resistor is
disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Not applicable if RST/NMI pin configured as NMI.
Specifications
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
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Table 5-12 lists the characteristics of the digital outputs.
Table 5-12. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (also see Figure 59, Figure 5-10, Figure 5-11, and Figure 5-12)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA (1)
VOH
High-level output voltage
I(OHmax) = –3 mA (2)
I(OHmax) = –2 mA
I(OLmax) = 1 mA (1)
Low-level output voltage
I(OLmax) = 3 mA (2)
I(OLmax) = 2 mA (1)
I(OLmax) = 6 mA (2)
fPx.y
Port output frequency (with load) (3)
CL = 20 pF, RL
fPort_CLK
Clock output frequency (3)
ACLK, MCLK, or SMCLK at
configured output port,
CL = 20 pF (5)
trise,dig
Port output rise time, digital only port
pins
CL = 20 pF
tfall,dig
Port output fall time, digital only port
pins
CL = 20 pF
trise,ana
Port output rise time, port pins with
shared analog functions
CL = 20 pF
tfall,ana
Port output fall time, port pins with
shared analog functions
CL = 20 pF
(1)
(2)
(3)
(4)
(5)
34
2.2 V
(1)
I(OHmax) = –6 mA (2)
VOL
VCC
(4) (5)
3.0 V
2.2 V
3.0 V
MIN
TYP
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
2.2 V
16
3.0 V
16
2.2 V
16
3.0 V
16
UNIT
V
V
MHz
MHz
2.2 V
4
15
3.0 V
3
15
2.2 V
4
15
3.0 V
3
15
2.2 V
6
15
3.0 V
4
15
2.2 V
6
15
3.0 V
4
15
ns
ns
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
The port can output frequencies at least up to the specified limit, and the port might support higher frequencies.
A resistive divider with 2 × R1 and R1 = 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 20 pF is connected from the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Specifications
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
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5.12.5.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
30
25°C
85°C
Low-Level Output Current (mA)
Low-Level Output Current (mA)
15
10
5
25°C
85°C
20
10
P1.1
P1.1
0
0
0
0.5
1
1.5
2
0
0.5
Low-Level Output Voltage (V)
1
1.5
2
2.5
3
Low-Level Output Voltage (V)
C001
C001
VCC = 2.2 V
VCC = 3.0 V
Figure 5-9. Typical Low-Level Output Current vs
Low-Level Output Voltage
0
25°C
85°C
High-Level Output Current (mA)
High-Level Output Current (mA)
0
Figure 5-10. Typical Low-Level Output Current vs
Low-Level Output Voltage
-5
-10
25°C
85°C
-10
-20
P1.1
P1.1
-15
-30
0
0.5
1
1.5
2
0
0.5
High-Level Output Voltage (V)
1
1.5
2
2.5
C001
VCC = 2.2 V
Figure 5-11. Typical High-Level Output Current vs
High-Level Output Voltage
C001
VCC = 3.0 V
Figure 5-12. Typical High-Level Output Current vs
High-Level Output Voltage
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3
High-Level Output Voltage (V)
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Table 5-13 lists the frequencies of the pin oscillator.
Table 5-13. Pin-Oscillator Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-13
and Figure 5-14)
PARAMETER
foPx.y
(1)
TEST CONDITIONS
VCC
Px.y, CL = 10 pF (1)
Pin-oscillator frequency
3.0 V
Px.y, CL = 20 pF (1)
MIN
TYP
MAX
UNIT
1640
kHz
870
CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.
1000
Fitted
Fitted
25°C
25°C
85°C
Pin Oscillator Frequency (kHz)
Pin Oscillator Frequency (kHz)
5.12.5.2 Typical Characteristics, Pin-Oscillator Frequency
100
1000
85°C
100
10
100
10
External Load Capacitance (pF) (Including Board)
100
External Load Capacitance (pF) (Including Board)
C002
VCC = 2.2 V
One output active at a time.
Figure 5-13. Typical Oscillation Frequency vs Load Capacitance
36
Specifications
C002
VCC = 3.0 V
One output active at a time.
Figure 5-14. Typical Oscillation Frequency vs Load Capacitance
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5.12.6 Timer_A and Timer_B
Table 5-14 lists the characteristics of the Timer_A.
Table 5-14. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTA
Timer_A input clock frequency
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
2.2 V,
3.0 V
tTA,cap
Timer_A capture timing
All capture inputs, minimum pulse
duration required for capture
2.2 V,
3.0 V
MIN
TYP
MAX
UNIT
16
MHz
20
ns
Table 5-15 lists the characteristics of the Timer_B.
Table 5-15. Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTB
Timer_B input clock frequency
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
2.2 V,
3.0 V
tTB,cap
Timer_B capture timing
All capture inputs, minimum pulse
duration required for capture
2.2 V,
3.0 V
MIN
TYP
MAX
UNIT
16
MHz
20
Specifications
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5.12.7 eUSCI
Table 5-16 lists the supported clock frequencies of the eUSCI in UART mode.
Table 5-16. eUSCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
TEST CONDITIONS
MIN
MAX
UNIT
16
MHz
4
MHz
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
Table 5-17 lists the deglitch times of the eUSCI in UART mode.
Table 5-17. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UART receive deglitch time (1)
tt
VCC
TYP
MAX
UCGLITx = 0
5
UCGLITx = 1
20
90
35
160
50
220
2.2 V, 3.0 V
UCGLITx = 2
UCGLITx = 3
(1)
MIN
UNIT
30
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch
time can limit the maximum usable baud rate. To ensure that pulses are correctly recognized, their duration should exceed the
maximum specification of the deglitch time.
Table 5-18 lists the supported clock frequencies of the eUSCI in SPI master mode.
Table 5-18. eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
feUSCI
38
eUSCI input clock frequency
Specifications
TEST CONDITIONS
MIN
MAX
UNIT
16
MHz
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
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Table 5-19 lists the characteristics of the eUSCI in SPI master mode.
Table 5-19. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see note
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
(1)
)
UNIT
tSTE,LEAD
STE lead time, STE active to clock
UCSTEM = 1, UCMODEx = 01 or 10
1
tSTE,LAG
STE lag time, last clock to STE inactive UCSTEM = 1, UCMODEx = 01 or 10
1
tSTE,ACC
STE access time, STE active to SIMO
data out
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V, 3.0 V
60
ns
tSTE,DIS
STE disable time, STE inactive to
SOMI high impedance
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V, 3.0 V
60
ns
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid, CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
2.2 V
35
3.0 V
35
2.2 V
0
3.0 V
0
UCxCLK
cycles
ns
ns
2.2 V
10
3.0 V
10
2.2 V
0
3.0 V
0
ns
ns
fUCxCLK = 1 / 2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-15 and Figure 5-16.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 515 and Figure 5-16.
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 5-15. SPI Master Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
tHD,MO
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 5-16. SPI Master Mode, CKPH = 1
40
Specifications
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
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MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
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SLASE34E – MAY 2014 – REVISED AUGUST 2018
Table 5-20 lists the characteristics of the eUSCI in SPI slave mode.
Table 5-20. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
UCLK edge to SOMI valid,
CL = 20 pF
tHD,SO
SOMI output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
VCC
MIN
2.2 V
45
3.0 V
40
2.2 V
0
3.0 V
0
(1)
ns
45
3.0 V
40
2.2 V
40
3.0 V
35
4
3.0 V
4
2.2 V
7
3.0 V
7
35
35
3.0 V
0
ns
ns
3.0 V
0
ns
ns
2.2 V
2.2 V
UNIT
ns
2.2 V
2.2 V
)
MAX
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-17 and Figure 5-18.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-17
and Figure 5-18.
Specifications
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41
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SLASE34E – MAY 2014 – REVISED AUGUST 2018
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SI
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tSTE,ACC
tSTE,DIS
tVALID,SO
SOMI
Figure 5-17. SPI Slave Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tSTE,ACC
tSTE,DIS
tVALID,SO
SOMI
Figure 5-18. SPI Slave Mode, CKPH = 1
42
Specifications
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
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SLASE34E – MAY 2014 – REVISED AUGUST 2018
Table 5-21 lists the characteristics of the eUSCI in I2C mode.
Table 5-21. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-19)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
TYP
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
2.2 V, 3.0 V
fSCL = 100 kHz
UNIT
16
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3.0 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3.0 V
100
ns
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
tSU,STO
Setup time for STOP
tBUF
Bus free time between a STOP and
START condition
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
tSP
2.2 V, 3.0 V
0
MAX
2.2 V, 3.0 V
2.2 V, 3.0 V
4.7
4.0
4.7
1.3
UCGLITx = 0
50
2.2 V, 3.0 V
UCGLITx = 3
µs
0.6
fSCL > 100 kHz
UCGLITx = 2
µs
0.6
fSCL = 100 kHz
UCGLITx = 1
µs
0.6
µs
250
25
125
12.5
62.5
6.3
31.5
UCCLTOx = 1
tTIMEOUT
Clock low time-out
UCCLTOx = 2
27
2.2 V, 3.0 V
30
UCCLTOx = 3
tSU,STA
tHD,STA
ns
ms
33
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-19. I2C Mode Timing
Specifications
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5.12.8 ADC
Table 5-22 lists the input requirements of the ADC.
Table 5-22. 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(Ax)
Analog input voltage range
TEST CONDITIONS
(1)
I(ADC12_B)
Operating supply current into
singleAVCC plus DVCC terminals (2)
ended mode
I(ADC12_B)
Operating supply current into
differential
AVCC plus DVCC terminals (2)
mode
All ADC12 analog input pins Ax
NOM
0
MAX
UNIT
AVCC
V
3.0 V
145
185
(3)
2.2 V
140
180
3.0 V
175
225
(3)
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 1,
REFON = 0, ADC12SHTx= 0,
ADC12DIV = 0
2.2 V
170
220
2.2 V
10
15
pF
>2 V
0.5
4
kΩ
50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Timer_B, TBx
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Ax in
UART mode
Clocked by SMCLK
Clocked by ACLK
Waiting for first edge of START bit
eUSCI_Ax in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Ax in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Bx in I C
master mode
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Not applicable
eUSCI_Bx in I2C
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Waiting for START condition or
clocked by external clock ≤50 kHz
eUSCI_Bx in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Bx in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
ADC12_B
Clocked by SMCLK or by MODOSC
Clocked by ACLK
Waiting for a trigger
REF_A
Not applicable
Not applicable
Always
COMP_E
Not applicable
Not applicable
Always
CRC (5)
Not applicable
Not applicable
Not applicable
MPY (5)
Not applicable
Not applicable
Not applicable
DMA
2
(1)
(2)
(3)
(4)
(5)
56
Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz.
Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.
Peripherals are in a state that does not require or does not use an internal clock.
The DMA always transfers data in active mode but can wait for a trigger in any low power mode. A DMA trigger during a low power
mode will cause a temporary transition into active mode for the time of the transfer.
Operates only during active mode and will eventually delay the transition into a low power mode until its operation is completed.
Detailed Description
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
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6.3.1.1
SLASE34E – MAY 2014 – REVISED AUGUST 2018
Idle Currents of Peripherals in LPM3 and LPM4
Most peripherals can be activated to be operational in LPM3 if clocked by ACLK. Some modules are
operational in LPM4, because they do not require a clock to operate (for example, the comparator).
Activating a peripheral in LPM3 or LPM4 increases the current consumption due to its active supply
current contribution but also due to an additional idle current. To limit the idle current adder, certain
peripherals are grouped together. To achieve optimal current consumption, use modules within one group
and limit the number of groups with active modules. Table 6-3 lists the grouping of the peripherals.
Modules not listed in this table are either already included in the standard LPM3 current consumption or
cannot be used in LPM3 or LPM4.
The idle current adder is very small at room temperature (25°C) but increases at high temperatures
(85°C), See the IIDLE current parameters in Section 5.7 for details.
Table 6-3. Peripheral Groups
Group A
Group B
Timer TA1
Timer TA0
Timer TA2
Timer TA3
Timer TB0
Comparator
eUSCI_A0
ADC12_B
eUSCI_A1
REF_A
eUSCI_B0
6.4
Interrupt Vector Table and Signatures
The interrupt vectors, the power-up start address and signatures are in the address range 0FFFFh to
0FF80h. Figure 6-1 summarizes the content of this address range.
Reset Vector
0FFFFh
BSL Password
Interrupt
Vectors
0FFE0h
JTAG Password
Reserved
Signatures
0FF88h
0FF80h
Figure 6-1. Interrupt Vectors, Signatures and Passwords
The power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains a 16-bit address that
points to the start address of the application program.
The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit
address of the appropriate interrupt-handler instruction sequence. Table 6-4 lists the device specific
interrupt vector locations.
Detailed Description
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
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The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if
enabled by the corresponding signature).
The signatures are located at 0FF80h extending to higher addresses. Signatures are evaluated during
device start-up. Table 6-5 lists the device specific signature locations.
A JTAG password can be programmed starting from address 0FF88h and extending to higher addresses.
The password can extend into the interrupt vector locations using the interrupt vector addresses as
additional bits for the password. The length of the JTAG password depends on the JTAG signature.
See the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.
Table 6-4. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
System Reset
Power up, Brownout, Supply Supervisor
External Reset RST
Watchdog Time-out (Watchdog mode)
WDT, FRCTL MPU, CS, PMM Password
Violation
FRAM uncorrectable bit error detection
MPU segment violation
FRAM access time error
Software POR, BOR
System NMI
Vacant Memory Access
JTAG Mailbox
FRAM bit error detection
MPU segment violation
INTERRUPT FLAG
SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
ACCTEIFG
PMMPORIFG, PMMBORIFG
(SYSRSTIV) (1) (2)
VMAIFG
JMBNIFG, JMBOUTIFG
CBDIFG, UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
(SYSSNIV) (1) (3)
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
0FFFEh
highest
(Non)maskable
0FFFCh
User NMI
External NMI
Oscillator Fault
NMIIFG, OFIFG
(SYSUNIV) (1) (3)
(Non)maskable
0FFFAh
Comparator_E
CEIFG, CEIIFG
(CEIV) (1)
Maskable
0FFF8h
TB0
TB0CCR0.CCIFG
Maskable
0FFF6h
TB0
TB0CCR1.CCIFG ... TB0CCR6.CCIFG,
TB0CTL.TBIFG
(TB0IV) (1)
Maskable
0FFF4h
Watchdog Timer (Interval Timer Mode)
WDTIFG
Maskable
0FFF2h
eUSCI_A0 Receive or Transmit
UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA0IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA0IV) (1)
Maskable
0FFF0h
eUSCI_B0 Receive or Transmit
UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV) (1)
Maskable
0FFEEh
ADC12_B
ADC12IFG0 to ADC12IFG31
ADC12LOIFG, ADC12INIFG, ADC12HIIFG,
ADC12RDYIFG, ADC21OVIFG, ADC12TOVIFG
(ADC12IV) (1)
Maskable
0FFECh
TA0
TA0CCR0.CCIFG
Maskable
0FFEAh
TA0
TA0CCR1.CCIFG, TA0CCR2.CCIFG,
TA0CTL.TAIFG
(TA0IV) (1)
Maskable
0FFE8h
(1)
(2)
(3)
58
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.
Detailed Description
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
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SLASE34E – MAY 2014 – REVISED AUGUST 2018
Table 6-4. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
eUSCI_A1 Receive or Transmit
UCA1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA1IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA1IV) (1)
Maskable
0FFE6h
DMA
DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,
DMA2CTL.DMAIFG
(DMAIV) (1)
Maskable
0FFE4h
TA1
TA1CCR0.CCIFG
Maskable
0FFE2h
TA1
TA1CCR1.CCIFG, TA1CCR2.CCIFG,
TA1CTL.TAIFG
(TA1IV) (1)
Maskable
0FFE0h
I/O Port P1
P1IFG.0 to P1IFG.7
(P1IV) (1)
Maskable
0FFDEh
TA2
TA2CCR0.CCIFG
Maskable
0FFDCh
TA2
TA2CCR1.CCIFG
TA2CTL.TAIFG
(TA2IV) (1)
Maskable
0FFDAh
I/O Port P2
P2IFG.0 to P2IFG.7
(P2IV) (1)
Maskable
0FFD8h
TA3
TA3CCR0.CCIFG
Maskable
0FFD6h
TA3
TA3CCR1.CCIFG
TA3CTL.TAIFG
(TA3IV) (1)
Maskable
0FFD4h
I/O Port P3
P3IFG.0 to P3IFG.7
(P3IV) (1)
Maskable
0FFD2h
I/O Port P4
P4IFG.0 to P4IFG.2
(P4IV) (1)
Maskable
0FFD0h
RTC_B
RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG,
RT1PSIFG, RTCOFIFG
(RTCIV) (1)
Maskable
0FFCEh
PRIORITY
lowest
Table 6-5. Signatures
(1)
SIGNATURE
WORD ADDRESS
IP Encapsulation Signature 2
0FF8Ah
IP Encapsulation Signature 1 (1)
0FF88h
BSL Signature 2
0FF86h
BSL Signature 1
0FF84h
JTAG Signature 2
0FF82h
JTAG Signature 1
0FF80h
Must not contain 0AAAAh if used as JTAG password and IP encapsulation functionality is not desired.
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SLASE34E – MAY 2014 – REVISED AUGUST 2018
6.5
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Memory Organization
Table 6-6 summarizes the memory map for all device variants.
Table 6-6. Memory Organization (1)
MSP430FR58x9
MSP430FR58x8
MSP430FR58x7
63KB
00FFFFh to 00FF80h
013FFFh to 004400h
47KB
00FFFFh to 00FF80h
00FF7Fh to 004400h
32KB
00FFFFh to 00FF80h
00FF7Fh to 008000h
RAM
2KB
0023FFh to 001C00h
2KB
0023FFh to 001C00h
1KB
001FFFh to 001C00h
Device Descriptor Info
(TLV) (FRAM)
256 B
001AFFh to 001A00h
256 B
001AFFh to 001A00h
256 B
001AFFh to 001A00h
Info A
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
Info B
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Info C
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
Info D
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
BSL 3
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
BSL 2
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
BSL 1
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
BSL 0
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
4KB
000FFFh to 0h
4KB
000FFFh to 0h
4KB
000FFFh to 0h
Memory (FRAM)
Main: interrupt vectors
and signatures
Main: code memory
Information memory
(FRAM)
Bootloader (BSL)
memory (ROM)
Total Size
Peripherals
(1)
6.6
Size
All address space not listed is considered vacant memory.
Bootloader (BSL)
The BSL enables users to program the FRAM or RAM using a UART serial interface (FRxxxx devices) or
an I2C interface (FRxxxx1 devices). Access to the device memory through the BSL is protected by an
user-defined password. Table 6-7 list the BSL pins requirements. BSL entry requires a specific entry
sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the
features of the BSL and its implementation, see the MSP430 FRAM Device Bootloader (BSL) User's
Guide.
Table 6-7. BSL Pin Requirements and Functions
60
Detailed Description
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P2.0
Devices with UART BSL (FRxxxx): Data transmit
P2.1
Devices with UART BSL (FRxxxx): Data receive
P1.6
Devices with I2C BSL (FRxxxx1): Data
P1.7
Devices with I2C BSL (FRxxxx1): Clock
VCC
Power supply
VSS
Ground supply
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MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
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6.7
6.7.1
SLASE34E – MAY 2014 – REVISED AUGUST 2018
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. Table 6-8 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide. For a complete description of the features of the JTAG interface and its
implementation, see MSP430 Programming With the JTAG Interface.
Table 6-8. JTAG Pin Requirements and Functions
6.7.2
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-9
lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the
features of the JTAG interface and its implementation, see MSP430 Programming With the JTAG
Interface.
Table 6-9. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
VCC
Power supply
VSS
Ground supply
Detailed Description
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Copyright © 2014–2018, Texas Instruments Incorporated
61
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
SLASE34E – MAY 2014 – REVISED AUGUST 2018
6.8
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FRAM
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
• Ultra-low-power ultra-fast-write nonvolatile memory
• Byte and word access capability
• Programmable wait state generation
• Error correction coding (ECC)
NOTE
Wait States
For MCLK frequencies > 8 MHz, wait states must be configured following the flow described
in the Wait State Control section of the FRAM Controller (FRCTRL) chapter in the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.
For important software design information regarding FRAM including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
MSP430™ FRAM Technology – How To and Best Practices.
6.9
Memory Protection Unit Including IP Encapsulation
The FRAM can be protected from inadvertent CPU execution, read access, or write access by the MPU.
Features of the MPU include:
• IP encapsulation with programmable boundaries in steps of 1KB (prevents reads from "outside"; for
example, JTAG or non-IP software).
• Main memory partitioning is programmable up to three segments in steps of 1KB.
• Each segment's access rights can be individually selected (main and information memory).
• Access violation flags with interrupt capability for easy servicing of access violations.
62
Detailed Description
Copyright © 2014–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5869 MSP430FR5868 MSP430FR5867 MSP430FR58671 MSP430FR5859
MSP430FR5858 MSP430FR5857 MSP430FR5849 MSP430FR5848 MSP430FR5847 MSP430FR58471
MSP430FR5869, MSP430FR5868, MSP430FR5867, MSP430FR58671
MSP430FR5859, MSP430FR5858, MSP430FR5857
MSP430FR5849, MSP430FR5848, MSP430FR5847, MSP430FR58471
www.ti.com
SLASE34E – MAY 2014 – REVISED AUGUST 2018
6.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
handled using all instructions. For complete module descriptions, see the MSP430FR58xx,
MSP430FR59xx, and MSP430FR6xx Family User's Guide.
6.10.1 Digital I/O
Up to four 8-bit I/O ports are implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all ports.
• Read and write access to port control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• All pins of ports P1, P2, P3, P4, and PJ support Capacitive Touch I/O functionality.
• No cross-currents during start-up.
NOTE
Configuration of Digital I/Os After BOR Reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers, and their module functions disabled. To enable the I/O functionality
after a BOR reset, the ports must be configured first and then the LOCKLPM5 bit must be
cleared. For details, see the Configuration After Reset section of the Digital I/O chapter in the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.
6.10.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch-crystal oscillator (XT1), an internal very-low-power
low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a highfrequency crystal oscillator XT2. The clock system module is designed to meet the requirements of both
low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources. The
clock system module provides the following clock signals:
• Auxiliary clock (ACLK). ACLK can be sourced from a 32-kHz watch crystal (LFXT1), the internal lowfrequency oscillator (VLO), or a digital external low-frequency (
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