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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
MSP430FR597x(1),MSP430FR592x(1) MSP430FR587x(1) Mixed‑‑Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Embedded Microcontroller
– 16-Bit RISC Architecture up to 16-MHz Clock
– Wide Supply Voltage Range From 3.6 V Down
to 1.8 V (Minimum Supply Voltage is Restricted
by SVS Levels, See the SVS Specifications)
• Optimized Ultra-Low-Power Modes
– Active Mode: Approximately 100 µA/MHz
– Standby (LPM3 With VLO): 0.4 µA (Typical)
– Real-Time Clock (RTC) (LPM3.5):
0.35 µA (Typical) (1)
– Shutdown (LPM4.5): 0.04 µA (Typical)
• Ultra-Low-Power Ferroelectric RAM (FRAM)
– Up to 64KB of Nonvolatile Memory
– Ultra-Low-Power Writes
– Fast Write at 125 ns per Word (64KB in 4 ms)
– Unified Memory = Program, Data, and Storage
in One Single Space
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
• Intelligent Digital Peripherals
– 32-Bit Hardware Multiplier (MPY)
– Three-Channel Internal Direct Memory Access
(DMA)
– RTC With Calendar and Alarm Functions
– Five 16-Bit Timers With up to Seven
Capture/Compare Registers
– 16-Bit and 32-Bit Cyclic Redundancy Checker
(CRC16, CRC32)
• High-Performance Analog
– Up to 8-Channel Analog Comparator
– 12-Bit Analog-to-Digital Converter (ADC) With
Internal Reference and Sample-and-Hold and
up to 8 External Input Channels
• Code Security and Encryption
– 128-Bit or 256-Bit AES Security Encryption and
Decryption Coprocessor (MSP430FR59xx(1)
Only)
(1)
•
•
•
•
•
•
– True Random Number Seed for Random
Number Generation Algorithm
– Lockable Memory Segments for IP
Encapsulation and Secure Storage
Multifunction Input/Output Ports
– All I/O Pins Support Capacitive Touch Capability
Without Need for External Components
– Accessible Bit-, Byte- and Word-Wise (in Pairs)
– Edge-Selectable Wakeup From LPM on Ports
P1 to P4
– Programmable Pullup and Pulldown on All Ports
Enhanced Serial Communication
– eUSCI_A0 and eUSCI_A1 Support:
– UART With Automatic Baud-Rate Detection
– IrDA Encode and Decode
– SPI at Rates up to 10 Mbps
– eUSCI_B0 and eUSCI_B1 Support:
– I2C With Multiple-Slave Addressing
– SPI at Rates up to 10 Mbps
Flexible Clock System
– Fixed-Frequency DCO With 10 Selectable
Factory-Trimmed Frequencies
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– 32-kHz Crystals (LFXT)
– High-Frequency Crystals (HFXT)
Development Tools and Software
– Free Professional Development Environments
With EnergyTrace++™ Technology for Power
Profiling and Debugging
– Microcontroller Development Boards Available
Family Members
– Device Comparison Summarizes the Available
Variants and Packages
For Complete Module Descriptions, See the
MSP430FR58xx, MSP430FR59xx, and
MSP430FR6xx Family User's Guide
The RTC is clocked by a 3.7-pF crystal.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
1.2
•
•
•
Applications
Metering
Energy Harvested Sensor Nodes
Wearable Electronics
1.3
www.ti.com
•
•
Sensor Management
Data Logging
Description
This ultra-low-power MSP430FRxx FRAM microcontroller family consists of several devices featuring
embedded nonvolatile FRAM, a 16-bit CPU, and different sets of peripherals targeted for various
applications. The architecture, FRAM, and peripherals, combined with seven low-power modes, are
optimized to achieve extended battery life in portable and wireless sensing applications. FRAM is a new
nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and
reliability of flash, all at lower total power consumption.
Device Information (1)
PACKAGE
BODY SIZE (2)
MSP430FR5972IPMR
LQFP (64)
10 mm × 10 mm
MSP430FR5972IRGC
VQFN (64)
9 mm × 9 mm
MSP430FR5922IG56
TSSOP (56)
6.1 mm × 14 mm
PART NUMBER
(1)
(2)
2
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 9, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
Device Overview
Copyright © 2015–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com
1.4
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Functional Block Diagram
Figure 1-1 shows the functional block diagram.
LFXIN/
HFXIN
P1.x,P2.x P3.x,P4.x P5.x,P6.x
up to
up to
up to
2x8
2x8
2x8
LFXOUT/
HFXOUT
P7.x
up to
1x8
P9.x
up to
1x8
PJ.x
up to
1x8
Capacitive Touch IO 0, Capacitive Touch IO 1
MCLK
Clock
System
Comp_E
ADC12_B
(up to 16
inputs)
(up to 16
std. inputs,
up to 8
diff. inputs)
SMCLK
DMA
Controller
3 Channel
Bus
Control
Logic
MAB
I/O Ports
P1, P2
2x8 I/Os
Voltage
Reference
I/O Ports
P3, P4
2x8 I/Os
I/O Port
P5, P6
2x8 I/Os
I/O Port
P7
1x8 I/Os
I/O Port
P9
1x8 I/Os
PA
PB
PC
1x16 I/Os 1x16 I/Os 1x16 I/Os
PD
1x8 I/Os
PE
1x8 I/Os
REF_A
ACLK
I/O Port
PJ
1x8 I/Os
MAB
MDB
CPUXV2
incl. 16
Registers
MPU
IP Encap
MDB
CRC16
Power
Mgmt
RAM
FRAM
2KB
64KB
32KB
EEM
(S: 3+1)
Tiny RAM
26B
LDO
SVS
Brownout
TA2
TA 3
Timer_A
Timer_A
2 CC
Registers
(int. only)
5 CC
Registers
AES256
CRC-16CCITT
CRC32
CRC-32ISO-3309
MPY32
Watchdog
Security
En-/Decryption
(128/256)
MDB
JTAG
Interface
MAB
Spy-BiWire
TB0
TA0
TA1
Timer_B
Timer_A
Timer_A
7 CC
Registers
(int./ext.)
3 CC
Registers
(int./ext.)
3 CC
Registers
(int./ext.)
RTC_C
Calendar
RTC_A
and
Counter
Mode
eUSCI_A0
eUSCI_A1
eUSCI_B0
eUSCI_B1
(UART,
IrDA,
SPI)
(I C, SPI)
2
LPM3.5 Domain
Copyright © 2016, Texas Instruments Incorporated
NOTE: AES256 is not implemented in the MSP430FR587x and MSP430FR587x1 devices.
NOTE: HFXIN and HFOUT are not implemented in the MSP430FR592x and MSP430FR592x1 devices.
Figure 1-1. Functional Block Diagram
Device Overview
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
Copyright © 2015–2018, Texas Instruments Incorporated
3
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
www.ti.com
Table of Contents
1
2
3
Device Overview ......................................... 1
6.1
Overview
1.2
Applications ........................................... 2
6.2
CPU
1.3
Description ............................................ 2
6.3
1.4
Functional Block Diagram ............................ 3
6.4
Revision History ......................................... 5
Device Comparison ..................................... 6
6.5
Related Products ..................................... 8
6.7
Terminal Configuration and Functions .............. 9
6.8
4.1
Pin Diagrams ......................................... 9
4.2
Pin Attributes ........................................ 12
4.3
Signal Descriptions .................................. 17
.....................................
4.5
Buffer Type ..........................................
4.6
Connection of Unused Pins .........................
Specifications ...........................................
5.1
Absolute Maximum Ratings .........................
5.2
ESD Ratings ........................................
5.3
Recommended Operating Conditions ...............
4.4
5
Pin Multiplexing
5.4
5.5
5.6
5.7
5.8
5.9
5.10
4
Detailed Description ................................... 58
Features .............................................. 1
3.1
4
6
1.1
Active Mode Supply Current Into VCC Excluding
External Current ....................................
Typical Characteristics - Active Mode Supply
Currents .............................................
Low-Power Mode (LPM0, LPM1) Supply Currents
Into VCC Excluding External Current ................
Low-Power Mode LPM2, LPM3, LPM4 Supply
Currents (Into VCC) Excluding External Current ....
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current ....................
Typical Characteristics, Low-Power Mode Supply
Currents .............................................
Typical Characteristics, Current Consumption per
Module ..............................................
................
58
58
59
61
64
64
65
65
6.9
6.10
65
Memory Protection Unit (MPU) Including IP
Encapsulation ....................................... 65
23
6.11
Peripherals
23
6.12
Device Descriptors (TLV) .......................... 101
23
6.13
Memory
24
6.14
Identification........................................ 118
24
7
24
25
8
26
26
27
29
30
31
Thermal Resistance Characteristics
5.12
Timing and Switching Characteristics ............... 32
31
9
..........................................
............................................
66
104
Applications, Implementation, and Layout ...... 119
7.1
7.2
24
5.11
Table of Contents
6.6
............................................
.................................................
Operating Modes ....................................
Interrupt Vector Table and Signatures ..............
Bootloader (BSL) ....................................
JTAG Operation .....................................
FRAM................................................
RAM .................................................
Tiny RAM ............................................
Device Connection and Layout Fundamentals .... 119
Peripheral- and Interface-Specific Design
Information ......................................... 123
Device and Documentation Support .............. 125
...................
8.1
Getting Started and Next Steps
8.2
Device Nomenclature .............................. 125
8.3
Tools and Software ................................ 126
8.4
Documentation Support ............................ 128
8.5
Related Links
8.6
Community Resources............................. 129
8.7
Trademarks ........................................ 130
8.8
Electrostatic Discharge Caution
8.9
Export Control Notice .............................. 130
8.10
Glossary............................................ 130
......................................
...................
125
129
130
Mechanical, Packaging, and Orderable
Information ............................................. 131
Copyright © 2015–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from January 25, 2017 to August 30, 2018
•
•
•
•
•
Page
Updated Section 3.1, Related Products ........................................................................................... 8
Added note (1) to Table 5-2, SVS................................................................................................. 32
Changed capacitor value from 4.7 µF to 470 nF in Figure 7-5, ADC12_B Grounding and Noise Considerations ... 123
Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of Section 7.2.1.2, Design Requirements .. 124
Updated text and figure in Section 8.2, Device Nomenclature .............................................................. 125
Revision History
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
Copyright © 2015–2018, Texas Instruments Incorporated
5
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
www.ti.com
3 Device Comparison
Table 3-1 and Table 3-2 summarize the available family members.
Table 3-1. Device Comparison – Family Members With UART BSL
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
DEVICE
FRAM
(KB)
SRAM
(KB)
CLOCK
SYSTEM
Timer_A (1)
Timer_B (2)
MSP430FR5972
64
2
DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6) (7)
MSP430FR5872
64
2
DCO
HFXT
LFXT
MSP430FR5970
32
2
MSP430FR5922
64
MSP430FR5870
32
eUSCI
AES
ADC12_B
I/O
PACKAGE
2
yes
8 ext
51
64 PM
64 RGC
2
2
no
8 ext
51
64 PM
64 RGC
7
2
2
yes
8 ext
51
64 PM
64 RGC
3, 3 (5)
2, 5 (6) (7)
7
2
2
yes
8 ext
51
46 (DGG)
64 PM
64 RGC
56 DGG
3, 3 (5)
2, 5 (6) (7)
7
2
2
no
8 ext
51
64 PM
64 RGC
A (3)
B (4)
7
2
3, 3 (5)
2, 5 (6) (7)
7
DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6) (7)
2
DCO
LFXT
2
DCO
HFXT
LFXT
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
eUSCI_B supports I2C with multiple slave addresses and SPI.
Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
Timer_A TA2 provides only internal capture/compare inputs and only internal PWM outputs (if any).
Timer_A TA3 provides only internal capture/compare inputs and only internal PWM outputs (if any) for FR592x(1) with RGC and PM packages. For FR592x(1) with DGG package and all
other devices, Timer_A TA3 provides internal, external capture/compare inputs and internal, external PWM outputs (if any).
Device Comparison
Copyright © 2015–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Table 3-2. Device Comparison – Family Members With I2C BSL
(1)
(2)
(3)
(4)
(5)
(6)
(7)
DEVICE
FRAM
(KB)
SRAM
(KB)
CLOCK
SYSTEM
Timer_A (1)
Timer_B (2)
MSP430FR59721
64
2
DCO
HFXT
LFXT
3, 3 (5)
2, 5 (6) (7)
MSP430FR59221
64
2
DCO
LFXT
MSP430FR58721
64
2
DCO
HFXT
LFXT
eUSCI
AES
ADC12_B
I/O
PACKAGE
2
yes
8 ext
51
64 PM
64 RGC
2
2
yes
8 ext
51
46 (DGG)
64 PM
64 RGC
56 DGG
2
2
no
8 ext
51
64 PM
64 RGC
A (3)
B (4)
7
2
3, 3 (5)
2, 5 (6) (7)
7
3, 3 (5)
2, 5 (6) (7)
7
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
eUSCI_B supports I2C with multiple slave addresses and SPI.
Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
Timer_A TA2 provides only internal capture/compare inputs and only internal PWM outputs (if any).
Timer_A TA3 provides only internal capture/compare inputs and only internal PWM outputs (if any) for FR592x(1) with RGC and PM packages. For FR592x(1) with DGG package and all
other devices, Timer_A TA3 provides internal, external capture/compare inputs and internal, external PWM outputs (if any).
Copyright © 2015–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
Device Comparison
7
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
3.1
www.ti.com
Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers High-performance, low-power solutions to enable the autonomous
future
Products for MSP430 ultra-low-power sensing and measurement microcontrollers
One ecosystem. Endless possibilities.
One
platform.
Products for MSP430 ultrasonic and performance sensing microcontrollers Ultra-low-power singlechip MCUs with integrated sensing peripherals
Companion Products for MSP430FR5972 Review products that are frequently purchased or used with
this product.
Reference Designs for MSP430FR5972 The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
8
Device Comparison
Copyright © 2015–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
4 Terminal Configuration and Functions
4.1
Pin Diagrams
AVCC1
AVSS1
PJ.4/LFXIN
PJ.5/LFXOUT
PJ.7/HFXOUT
AVSS2
AVSS3
PJ.6/HFXIN
P5.7/UCA1STE/TB0CLK
P4.4/UCB1STE/TA1CLK
P4.5/UCB1CLK/TA1.0
P4.6/UCB1SIMO/UCB1SDA/TA1.1
P4.7/UCB1SOMI/UCB1SCL/TA1.2
DVSS3
DVCC3
P4.2/UCA0SIMO/UCA0TXD/UCB1CLK
Figure 4-1 shows the pinout for the 64-pin PM and RGC packages of the MSP430FR597x(1) and
MSP430FR587x(1) MCUs.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
P9.7/A15/C15
P1.4/UCB0CLK/UCA0STE/TA1.0
2
47
P9.6/A14/C14
P1.5/UCB0STE/UCA0CLK/TA0.0
3
46
P9.5/A13/C13
P1.6/UCB0SIMO/UCB0SDA/TA0.1
4
45
P9.4/A12/C12
P1.7/UCB0SOMI/UCB0SCL/TA0.2
5
44
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
DNC
6
43
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P6.0
7
42
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P6.1
8
41
P1.3/TA1.2/A3/C3
P6.2/COUT
9
40
DVCC2
P6.3
10
39
DVSS2
P6.4/TB0.0
11
38
P7.4/SMCLK
P6.5/TB0.1
12
37
P7.3/TA0.2
P6.6/TB0.2
13
36
P7.2/TA0.1
P3.0/UCB1CLK/TA3.2
14
35
P7.1/TA0.0/ACLK
P3.1/UCB1SIMO/UCB1SDA/TA3.3
15
34
P7.0/TA0CLK
P3.2/UCB1SOMI/UCB1SCL/TA3.4
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK
P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0
P2.2/UCA0CLK/TB0.4/RTCCLK
P3.7/UCA1STE/TB0.3
P2.3/UCA0STE/TB0OUTH
P3.6/UCA1CLK/TB0.2
P3.5/UCA1SOMI/UCA1RXD/TB0.1
P3.4/UCA1SIMO/UCA1TXD/TB0.0
P3.3/TA1.1/TB0CLK
PJ.3/TCK/COUT/SRCPUOFF
PJ.2/TMS/ACLK/SROSCOFF
PJ.1/TDI/TCLK/MCLK/SRSCG0
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1
RST/NMI/SBWTDIO
TEST/SBWTCK
DVSS1
MSP430FR597x
MSP430FR587x
DVCC1
P4.3/UCA0SOMI/UCA0RXD/UCB1STE
On devices with UART BSL: P2.0: BSL_TX; P2.1: BSL_RX
On devices with I2C BSL: P1.6: BSL_DAT; P1.7: BSL_CLK
NOTE: TI recommends connecting the RGC package thermal pad to VSS.
Figure 4-1. 64-Pin PM and RGC Packages (Top View) – MSP430FR597x(1), MSP430FR587x(1)
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
Copyright © 2015–2018, Texas Instruments Incorporated
9
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
www.ti.com
AVCC1
AVSS1
PJ.4/LFXIN
PJ.5/LFXOUT
AVSS2
P5.4/UCA1SIMO/UCA1TXD
P5.5/UCA1SOMI/UCA1RXD
P5.6/UCA1CLK
P5.7/UCA1STE/TB0CLK
P4.4/UCB1STE/TA1CLK
P4.5/UCB1CLK/TA1.0
P4.6/UCB1SIMO/UCB1SDA/TA1.1
P4.7/UCB1SOMI/UCB1SCL/TA1.2
DVSS3
DVCC3
P4.2/UCA0SIMO/UCA0TXD/UCB1CLK
Figure 4-2 shows the pinout for the 64-pin PM and RGC packages of the MSP430FR592x(1) MCUs.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
P9.7/A15/C15
P1.4/UCB0CLK/UCA0STE/TA1.0
2
47
P9.6/A14/C14
P1.5/UCB0STE/UCA0CLK/TA0.0
3
46
P9.5/A13/C13
P1.6/UCB0SIMO/UCB0SDA/TA0.1
4
45
P9.4/A12/C12
P1.7/UCB0SOMI/UCB0SCL/TA0.2
5
44
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
DNC
6
43
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P6.0
7
42
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P6.1
8
41
P1.3/TA1.2/A3/C3
P6.2/COUT
9
40
DVCC2
P6.3
10
39
DVSS2
P6.4/TB0.0
11
38
P7.4/SMCLK
P6.5/TB0.1
12
37
P7.3/TA0.2
P6.6/TB0.2
13
36
P7.2/TA0.1
P3.0/UCB1CLK/TA3.2
14
35
P7.1/TA0.0/ACLK
P3.1/UCB1SIMO/UCB1SDA/TA3.3
15
34
P7.0/TA0CLK
P3.2/UCB1SOMI/UCB1SCL/TA3.4
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK
P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0
P2.2/UCA0CLK/TB0.4/RTCCLK
P2.3/UCA0STE/TB0OUTH
P3.7/UCA1STE/TB0.3
P3.6/UCA1CLK/TB0.2
P3.5/UCA1SOMI/UCA1RXD/TB0.1
P3.4/UCA1SIMO/UCA1TXD/TB0.0
P3.3/TA1.1/TB0CLK
PJ.3/TCK/COUT/SRCPUOFF
PJ.2/TMS/ACLK/SROSCOFF
PJ.1/TDI/TCLK/MCLK/SRSCG0
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1
RST/NMI/SBWTDIO
TEST/SBWTCK
DVSS1
MSP430FR592x
DVCC1
P4.3/UCA0SOMI/UCA0RXD/UCB1STE
A.
On devices with UART BSL: P2.0: BSL_TX; P2.1: BSL_RX
On devices with I2C BSL: P1.6: BSL_DAT; P1.7: BSL_CLK
NOTE: TI recommends connecting the RGC package thermal pad to VSS.
Figure 4-2. 64-Pin PM and RGC Packages (Top View) – MSP430FR592x(1)
10
Terminal Configuration and Functions
Copyright © 2015–2018, Texas Instruments Incorporated
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Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Figure 4-3 shows the pinout for the 56-pin DGG package of the MSP430FR592x(1) MCUs.
P4.4/UCB1STE/TA1CLK
P4.5/UCB1CLK/TA1.0
P4.6/UCB1SIMO/UCB1SDA/TA1.1
P4.7/UCB1SOMI/UCB1SCL/TA1.2
DVSS3
DVCC3
P1.4/UCB0CLK/UCA0STE/TA1.0
P1.5/UCB0STE/UCA0CLK/TA0.0
P1.6/UCB0SIMO/UCB0SDA/TA0.1
P1.7/UCB0SOMI/UCB0SCL/TA0.2
DNC
P6.0
P6.1
P6.2/COUT
P6.3
P6.4/TB0.0
P6.5/TB0.1
P6.6/TB0.2
P3.0/UCB1CLK/TA3.2
P3.1/UCB1SIMO/UCB1SDA/TA3.3
P3.2/UCB1SOMI/UCB1SCL/TA3.4
TEST/SBWTCK
RST/NMI/SBWTDIO
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1
PJ.1/TDI/TCLK/MCLK/SRSCG0
PJ.2/TMS/ACLK/SROSCOFF
PJ.3/TCK/COUT/SRCPUOFF
P3.3/TA1.1/TB0CLK
A.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MSP430FR592x
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
AVSS2
PJ.5/LFXOUT
PJ.4/LFXIN
AVSS1
AVCC1
P9.7/A15/C15
P9.6/A14/C14
P9.5/A13/C13
P9.4/A12/C12
P1.0/TA0.1/RTCCLK/DMAE0/A0/C0/VREF-/VeREFP1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P1.3/TA1.2/A3/C3
DVCC2
DVSS2
P7.4/SMCLK
P7.3/TA0.2
P7.2/TA0.1
P7.1/TA0.0/ACLK
P7.0/TA0CLK
P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK
P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0
P2.2/UCA0CLK/TB0.4/RTCCLK
P2.3/UCA0STE/TB0OUTH
P3.7/UCA1STE/TB0.3
P3.6/UCA1CLK/TB0.2
P3.5/UCA1SOMI/UCA1RXD/TB0.1
P3.4/UCA1SIMO/UCA1TXD/TB0.0
On devices with UART BSL: P2.0: BSL_TX; P2.1: BSL_RX
On devices with I2C BSL: P1.6: BSL_DAT; P1.7: BSL_CLK
Figure 4-3. 56-Pin DGG Package (Top View) – MSP430FR592x(1)
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
Copyright © 2015–2018, Texas Instruments Incorporated
11
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
4.2
www.ti.com
Pin Attributes
Table 4-1 lists the attributes of each pin.
Table 4-1. Pin Attributes
FR597x(1),
FR587x(1)
PM, RGC
PM, RGC
DGG
PIN NO.
PIN NO.
PIN NO.
1
2
3
4
5
SIGNAL
TYPE (3)
BUFFER
TYPE (4)
POWER
SOURCE
RESET
STATE
AFTER
BOR (5)
P4.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0SOMI
I/O
LVCMOS
DVCC
–
UCA0RXD
I
LVCMOS
DVCC
–
UCB1STE
I/O
LVCMOS
DVCC
–
P1.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0CLK
I/O
LVCMOS
DVCC
–
UCA0STE
I/O
LVCMOS
DVCC
–
TA1.0
I/O
LVCMOS
DVCC
–
P1.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0STE
I/O
LVCMOS
DVCC
–
UCA0CLK
I/O
LVCMOS
DVCC
–
TA0.0
I/O
LVCMOS
DVCC
–
P1.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SIMO
I/O
LVCMOS
DVCC
–
UCB0SDA
I/O
LVCMOS
DVCC
–
BSL_DAT
I
LVCMOS
DVCC
–
TA0.1
I/O
LVCMOS
DVCC
–
P1.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SOMI
I/O
LVCMOS
DVCC
–
UCB0SCL
I/O
LVCMOS
DVCC
–
BSL_CLK
I
LVCMOS
DVCC
–
I/O
LVCMOS
DVCC
–
FR592x(1)
1
2
3
4
5
7
8
9
10
SIGNAL NAME (1)
TA0.2
(1)
(2)
(3)
(4)
(5)
(6)
12
(6)
(2)
6
6
11
DNC
–
–
–
–
7
7
12
P6.0 (RD)
I/O
LVCMOS
DVCC
OFF
8
8
13
P6.1 (RD)
I/O
LVCMOS
DVCC
OFF
P6.2 (RD)
I/O
LVCMOS
DVCC
OFF
COUT
O
LVCMOS
DVCC
–
P6.3 (RD)
I/O
LVCMOS
DVCC
OFF
P6.4 (RD)
I/O
LVCMOS
DVCC
OFF
TB0.0
I/O
LVCMOS
DVCC
–
P6.5 (RD)
I/O
LVCMOS
DVCC
OFF
TB0.1
I/O
LVCMOS
DVCC
–
P6.6 (RD)
I/O
LVCMOS
DVCC
OFF
TB0.2
I/O
LVCMOS
DVCC
–
9
9
14
10
10
15
11
11
16
12
12
17
13
13
18
Signals names with (RD) denote the reset default pin name.
To determine the pin mux encodings for each pin, see the Port I/O Diagrams section.
Signal Types: I = Input, O = Output, I/O = Input or Output.
Buffer Types: LVCMOS, Analog, or Power (see Table 4-3 for details)
Reset States:
OFF = High impedance with Schmitt-trigger inputs and pullup or pulldown (if available) disabled
N/A = Not applicable
DNC = Do not connect
Terminal Configuration and Functions
Copyright © 2015–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Table 4-1. Pin Attributes (continued)
FR597x(1),
FR587x(1)
PM, RGC
PM, RGC
DGG
PIN NO.
PIN NO.
PIN NO.
14
15
16
SIGNAL
TYPE (3)
BUFFER
TYPE (4)
POWER
SOURCE
RESET
STATE
AFTER
BOR (5)
P3.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1CLK
I/O
LVCMOS
DVCC
–
TA3.2
I/O
LVCMOS
DVCC
–
P3.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SIMO
I/O
LVCMOS
DVCC
–
UCB1SDA
I/O
LVCMOS
DVCC
–
TA3.3
I/O
LVCMOS
DVCC
–
P3.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SOMI
I/O
LVCMOS
DVCC
–
UCB1SCL
I/O
LVCMOS
DVCC
–
TA3.4
I/O
LVCMOS
DVCC
–
N/A
FR592x(1)
14
15
16
19
20
21
SIGNAL NAME
(1) (2)
17
17
DVSS1
P
Power
–
18
18
DVCC1
P
Power
–
N/A
TEST
I
LVCMOS
DVCC
OFF
SBWTCK
I
LVCMOS
DVCC
–
RST
I
LVCMOS
DVCC
OFF
NMI
I
LVCMOS
DVCC
–
SBWTDIO
I/O
LVCMOS
DVCC
–
PJ.0 (RD)
I/O
LVCMOS
DVCC
OFF
TDO
O
LVCMOS
DVCC
–
TB0OUTH
I
LVCMOS
DVCC
–
SMCLK
O
LVCMOS
DVCC
–
SRSCG1
O
LVCMOS
DVCC
–
PJ.1 (RD)
I/O
LVCMOS
DVCC
OFF
I
LVCMOS
DVCC
–
TCLK
I
LVCMOS
DVCC
–
MCLK
O
LVCMOS
DVCC
–
SRSCG0
O
LVCMOS
DVCC
–
PJ.2 (RD)
19
19
22
20
20
23
21
21
24
TDI
22
23
24
25
22
23
24
25
25
26
27
28
I/O
LVCMOS
DVCC
OFF
TMS
I
LVCMOS
DVCC
–
ACLK
O
LVCMOS
DVCC
–
SROSCOFF
O
LVCMOS
DVCC
–
PJ.3 (RD)
I/O
LVCMOS
DVCC
OFF
TCK
I
LVCMOS
DVCC
–
COUT
O
LVCMOS
DVCC
–
SRCPUOFF
O
LVCMOS
DVCC
–
P3.3 (RD)
I/O
LVCMOS
DVCC
OFF
TA1.1
I/O
LVCMOS
DVCC
–
TB0CLK
26
26
29
I
LVCMOS
DVCC
–
P3.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1SIMO
I/O
LVCMOS
DVCC
–
UCA1TXD
O
LVCMOS
DVCC
–
TB0.0
I/O
LVCMOS
DVCC
–
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
Copyright © 2015–2018, Texas Instruments Incorporated
13
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
www.ti.com
Table 4-1. Pin Attributes (continued)
FR597x(1),
FR587x(1)
PM, RGC
PM, RGC
DGG
PIN NO.
PIN NO.
PIN NO.
27
28
29
30
31
32
SIGNAL
TYPE (3)
BUFFER
TYPE (4)
POWER
SOURCE
RESET
STATE
AFTER
BOR (5)
P3.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1SOMI
I/O
LVCMOS
DVCC
–
UCA1RXD
I
LVCMOS
DVCC
–
TB0.1
I/O
LVCMOS
DVCC
–
P3.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1CLK
I/O
LVCMOS
DVCC
–
TB0.2
I/O
LVCMOS
DVCC
–
P3.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1STE
I/O
LVCMOS
DVCC
–
TB0.3
I/O
LVCMOS
DVCC
–
P2.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0STE
I/O
LVCMOS
DVCC
–
TB0OUTH
I
LVCMOS
DVCC
–
P2.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0CLK
I/O
LVCMOS
DVCC
–
TB0.4
I/O
LVCMOS
DVCC
–
RTCCLK
O
LVCMOS
DVCC
–
P2.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0SOMI
I/O
LVCMOS
DVCC
–
UCA0RXD
I
LVCMOS
DVCC
–
BSL_RX
I
LVCMOS
DVCC
–
I/O
LVCMOS
DVCC
–
I
LVCMOS
DVCC
–
P2.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0SIMO
I/O
LVCMOS
DVCC
–
UCA0TXD
O
LVCMOS
DVCC
–
BSL_TX
O
LVCMOS
DVCC
–
TB0.6
I/O
LVCMOS
DVCC
–
FR592x(1)
27
28
29
30
31
32
30
31
32
33
34
35
SIGNAL NAME
TB0.5
DMAE0
33
33
36
TB0CLK
34
34
37
35
35
38
36
14
36
39
(1) (2)
I
LVCMOS
DVCC
–
I/O
LVCMOS
DVCC
OFF
I
LVCMOS
DVCC
–
P7.1 (RD)
I/O
LVCMOS
DVCC
OFF
TA0.0
I/O
LVCMOS
DVCC
–
ACLK
O
LVCMOS
DVCC
–
P7.2 (RD)
I/O
LVCMOS
DVCC
OFF
TA0.1
I/O
LVCMOS
DVCC
–
P7.3 (RD)
I/O
LVCMOS
DVCC
OFF
TA0.2
I/O
LVCMOS
DVCC
–
P7.4 (RD)
I/O
LVCMOS
DVCC
OFF
SMCLK
O
LVCMOS
DVCC
–
P7.0 (RD)
TA0CLK
37
37
40
38
38
41
39
39
42
DVSS2
P
Power
–
N/A
40
40
43
DVCC2
P
Power
–
N/A
Terminal Configuration and Functions
Copyright © 2015–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
www.ti.com
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Table 4-1. Pin Attributes (continued)
FR597x(1),
FR587x(1)
PM, RGC
PM, RGC
DGG
PIN NO.
PIN NO.
PIN NO.
41
42
43
44
SIGNAL
TYPE (3)
BUFFER
TYPE (4)
POWER
SOURCE
RESET
STATE
AFTER
BOR (5)
P1.3 (RD)
I/O
LVCMOS
DVCC
OFF
TA1.2
FR592x(1)
41
42
43
44
44
45
46
47
SIGNAL NAME
I/O
LVCMOS
DVCC
–
A3
I
Analog
AVCC
–
C3
I
Analog
AVCC
–
P1.2 (RD)
I/O
LVCMOS
DVCC
OFF
TA1.1
I/O
LVCMOS
DVCC
–
TA0CLK
I
LVCMOS
DVCC
–
COUT
O
LVCMOS
DVCC
–
A2
I
Analog
AVCC
–
C2
I
Analog
AVCC
–
P1.1 (RD)
I/O
LVCMOS
DVCC
OFF
TA0.2
I/O
LVCMOS
DVCC
–
TA1CLK
I
LVCMOS
DVCC
–
COUT
O
LVCMOS
DVCC
–
A1
I
Analog
AVCC
–
C1
I
Analog
AVCC
–
VREF+
O
Analog
AVCC
–
VeREF+
I
Analog
–
–
P1.0 (RD)
I/O
LVCMOS
DVCC
OFF
TA0.1
I/O
LVCMOS
DVCC
–
DMAE0
I
LVCMOS
DVCC
–
RTCCLK
O
LVCMOS
DVCC
–
A0
I
Analog
AVCC
–
C0
I
Analog
AVCC
–
VREF-
O
Analog
AVCC
–
VeREFP9.4 (RD)
45
45
48
A12
C12
P9.5 (RD)
46
46
49
A13
C13
47
50
48
51
Analog
–
–
LVCMOS
DVCC
OFF
I
Analog
AVCC
–
I
Analog
AVCC
–
I/O
LVCMOS
DVCC
OFF
I
Analog
AVCC
–
I
Analog
AVCC
–
LVCMOS
DVCC
OFF
A14
I
Analog
AVCC
–
C14
I
Analog
AVCC
–
P9.7 (RD)
48
I
I/O
I/O
P9.6 (RD)
47
(1) (2)
I/O
LVCMOS
DVCC
OFF
A15
I
Analog
AVCC
–
C15
I
Analog
AVCC
–
N/A
49
49
52
AVCC1
P
Power
–
50
50
53
AVSS1
P
Power
–
N/A
I/O
LVCMOS
DVCC
OFF
51
51
54
52
52
55
53
53
56
PJ.4 (RD)
LFXIN
I
Analog
AVCC
–
PJ.5 (RD)
I/O
LVCMOS
DVCC
OFF
LFXOUT
O
Analog
AVCC
–
AVSS2
P
Power
–
N/A
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
Copyright © 2015–2018, Texas Instruments Incorporated
15
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
www.ti.com
Table 4-1. Pin Attributes (continued)
FR597x(1),
FR587x(1)
PM, RGC
PM, RGC
DGG
PIN NO.
PIN NO.
PIN NO.
SIGNAL NAME
PJ.7 (RD)
54
55
56
54
55
56
57
57
58
1
60
61
16
POWER
SOURCE
RESET
STATE
AFTER
BOR (5)
I/O
LVCMOS
DVCC
OFF
O
Analog
AVCC
–
I/O
LVCMOS
DVCC
OFF
HFXIN
I
Analog
AVCC
–
AVSS3
P
Power
–
N/A
P5.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1SIMO
I/O
LVCMOS
DVCC
–
UCA1TXD
O
LVCMOS
DVCC
–
P5.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1SOMI
I/O
LVCMOS
DVCC
–
UCA1RXD
I
LVCMOS
DVCC
–
P5.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1CLK
I/O
LVCMOS
DVCC
–
P5.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCA1STE
I/O
LVCMOS
DVCC
–
I
LVCMOS
DVCC
–
P4.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1STE
I/O
LVCMOS
DVCC
–
59
60
61
2
3
4
I
LVCMOS
DVCC
–
P4.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1CLK
I/O
LVCMOS
DVCC
–
TA1.0
I/O
LVCMOS
DVCC
–
P4.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SIMO
I/O
LVCMOS
DVCC
–
UCB1SDA
I/O
LVCMOS
DVCC
–
TA1.1
I/O
LVCMOS
DVCC
–
P4.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SOMI
I/O
LVCMOS
DVCC
–
UCB1SCL
I/O
LVCMOS
DVCC
–
TA1.2
I/O
LVCMOS
DVCC
–
P
Power
–
N/A
62
62
5
DVSS3
63
63
6
DVCC3
64
BUFFER
TYPE (4)
PJ.6 (RD)
TA1CLK
59
64
Terminal Configuration and Functions
(1) (2)
HFXOUT
TB0CLK
58
SIGNAL
TYPE (3)
FR592x(1)
P
Power
–
N/A
P4.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0SIMO
I/O
LVCMOS
DVCC
–
UCA0TXD
O
LVCMOS
DVCC
–
UCB1CLK
I/O
LVCMOS
DVCC
–
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MSP430FR5872, MSP430FR58721, MSP430FR5870
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4.3
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Signal Descriptions
Table 4-2 describes the signals.
Table 4-2. Signal Descriptions
FR597x(1),
FR587x(1)
FUNCTION
ADC
BSL (I2C)
BSL (UART)
Clock
Comparator
DMA
SIGNAL NAME
FR592x(1)
SIGNAL
TYPE
PM, RGC
PM,
RGC
DGG
DESCRIPTION
PIN NO.
PIN NO.
PIN NO.
A0
44
44
47
I
Analog input A0
A1
43
43
46
I
Analog input A1
A2
42
42
45
I
Analog input A2
A3
41
41
44
I
Analog input A3
A12
45
45
48
I
Analog input A12
A13
46
46
49
I
Analog input A13
A14
47
47
50
I
Analog input A14
A15
48
48
51
I
Analog input A15
VREF+
43
43
46
O
Output of positive reference voltage
VREF-
44
44
47
O
Output of negative reference voltage
VeREF+
43
43
46
I
Input for an external positive reference voltage
to the ADC
VeREF-
44
44
47
I
Input for an external negative reference
voltage to the ADC
BSL_CLK
5
5
10
I
BSL Clock (I2C BSL)
BSL_DAT
4
4
9
I
BSL Data (I2C BSL)
BSL_RX
32
32
35
I
BSL Receive (UART BSL)
BSL_TX
33
33
36
O
BSL Transmit (UART BSL)
ACLK
23
35
23
35
26
38
O
ACLK output
HFXIN
55
I
Input terminal of crystal oscillator XT2
HFXOUT
54
O
Output terminal for crystal oscillator XT2
LFXIN
51
51
54
I
Input terminal for crystal oscillator XT1
LFXOUT
52
52
55
O
Output terminal of crystal oscillator XT1
MCLK
22
22
25
O
MCLK output
RTCCLK
31
44
31
44
34
47
O
RTC clock output for calibration
SMCLK
21
38
21
38
24
41
O
SMCLK output
C0
44
44
47
I
Comparator input C0
C1
43
43
46
I
Comparator input C1
C2
42
42
45
I
Comparator input C2
C3
41
41
44
I
Comparator input C3
C12
45
45
48
I
Comparator input C12
C13
46
46
49
I
Comparator input C13
C14
47
47
50
I
Comparator input C14
C15
48
48
51
I
Comparator input C15
COUT
9
24
42
43
9
24
42
43
14
27
45
46
O
Comparator output
DMAE0
32
44
32
44
32
44
I
DMA external trigger input
Terminal Configuration and Functions
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
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Table 4-2. Signal Descriptions (continued)
FR597x(1),
FR587x(1)
FUNCTION
DNC
Debug
18
SIGNAL NAME
FR592x(1)
PM, RGC
PM,
RGC
DGG
PIN NO.
PIN NO.
PIN NO.
DNC
6
6
22
SBWTCK
19
19
SBWTDIO
20
20
SRCPUOFF
24
SROSCOFF
SIGNAL
TYPE
DESCRIPTION
–
Do Not Connect (DNC). TI strongly
recommends leaving this pin not connected.
23
I
Spy-Bi-Wire input clock
27
I/O
Spy-Bi-Wire data input/output
24
26
O
Low-power debug: CPU status register
CPUOFF
23
23
25
O
Low-power debug: CPU status register
OSCOFF
SRSCG0
22
22
24
O
Low-power debug: CPU status register SCG0
SRSCG1
21
21
27
O
Low-power debug: CPU status register SCG1
TCK
24
24
25
I
Test clock
TCLK
22
22
25
I
Test clock input
TDI
22
22
24
I
Test data input
TDO
21
21
22
O
Test data output port
TEST
19
19
26
I
Test mode pin - select digital I/O on JTAG pins
TMS
23
23
23
I
Test mode select
Terminal Configuration and Functions
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MSP430FR5872, MSP430FR58721, MSP430FR5870
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Table 4-2. Signal Descriptions (continued)
FR597x(1),
FR587x(1)
FUNCTION
GPIO
SIGNAL NAME
FR592x(1)
SIGNAL
TYPE
PM, RGC
PM,
RGC
DGG
DESCRIPTION
PIN NO.
PIN NO.
PIN NO.
P1.0
44
44
47
I/O
General-purpose digital I/O
P1.1
43
43
46
I/O
General-purpose digital I/O
P1.2
42
42
45
I/O
General-purpose digital I/O
P1.3
41
41
44
I/O
General-purpose digital I/O
P1.4
2
2
7
I/O
General-purpose digital I/O
P1.5
3
3
8
I/O
General-purpose digital I/O
P1.6
4
4
9
I/O
General-purpose digital I/O
P1.7
5
5
10
I/O
General-purpose digital I/O
P2.0
33
33
36
I/O
General-purpose digital I/O
P2.1
32
32
35
I/O
General-purpose digital I/O
P2.2
31
31
34
I/O
General-purpose digital I/O
P2.3
30
30
33
I/O
General-purpose digital I/O
P3.0
14
14
19
I/O
General-purpose digital I/O
P3.1
15
15
20
I/O
General-purpose digital I/O
P3.2
16
16
21
I/O
General-purpose digital I/O
P3.3
25
25
28
I/O
General-purpose digital I/O
P3.4
26
26
29
I/O
General-purpose digital I/O
P3.5
27
27
30
I/O
General-purpose digital I/O
P3.6
28
28
31
I/O
General-purpose digital I/O
P3.7
29
29
32
I/O
General-purpose digital I/O
P4.2
64
64
I/O
General-purpose digital I/O
P4.3
1
1
I/O
General-purpose digital I/O
P4.4
58
58
1
I/O
General-purpose digital I/O
P4.5
59
59
2
I/O
General-purpose digital I/O
P4.6
60
60
3
I/O
General-purpose digital I/O
P4.7
61
61
4
I/O
General-purpose digital I/O
P5.4
54
I/O
General-purpose digital I/O
P5.5
55
I/O
General-purpose digital I/O
P5.6
56
I/O
General-purpose digital I/O
57
I/O
General-purpose digital I/O
P5.7
57
Terminal Configuration and Functions
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19
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
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Table 4-2. Signal Descriptions (continued)
FR597x(1),
FR587x(1)
FUNCTION
GPIO
I2C
Power
20
SIGNAL NAME
FR592x(1)
SIGNAL
TYPE
PM, RGC
PM,
RGC
DGG
PIN NO.
PIN NO.
PIN NO.
P6.0
7
7
12
I/O
General-purpose digital I/O
P6.1
8
8
13
I/O
General-purpose digital I/O
P6.2
9
9
14
I/O
General-purpose digital I/O
P6.3
10
10
15
I/O
General-purpose digital I/O
P6.4
11
11
16
I/O
General-purpose digital I/O
P6.5
12
12
17
I/O
General-purpose digital I/O
P6.6
13
13
18
I/O
General-purpose digital I/O
P7.0
34
34
37
I/O
General-purpose digital I/O
P7.1
35
35
38
I/O
General-purpose digital I/O
P7.2
36
36
39
I/O
General-purpose digital I/O
P7.3
37
37
40
I/O
General-purpose digital I/O
P7.4
38
38
41
I/O
General-purpose digital I/O
P9.4
45
45
48
I/O
General-purpose digital I/O
P9.5
46
46
49
I/O
General-purpose digital I/O
P9.6
47
47
50
I/O
General-purpose digital I/O
P9.7
48
48
51
I/O
General-purpose digital I/O
PJ.0
21
21
24
I/O
General-purpose digital I/O
PJ.1
22
22
25
I/O
General-purpose digital I/O
PJ.2
23
23
26
I/O
General-purpose digital I/O
PJ.3
24
24
27
I/O
General-purpose digital I/O
PJ.4
51
51
54
I/O
General-purpose digital I/O
PJ.5
52
52
55
I/O
General-purpose digital I/O
PJ.6
55
55
I/O
General-purpose digital I/O
PJ.7
54
54
I/O
General-purpose digital I/O
UCB0SCL
5
5
10
I/O
USCI_B0: I2C clock (I2C mode)
UCB0SDA
4
4
9
I/O
USCI_B0: I2C data (I2C mode)
UCB1SCL
16
61
16
61
21
4
I/O
USCI_B1: I2C clock (I2C mode)
UCB1SDA
15
60
15
60
20
3
I/O
USCI_B1: I2C data (I2C mode)
AVCC1
49
49
52
P
Analog power supply
AVSS1
50
50
53
P
Analog ground supply
AVSS2
53
53
56
P
Analog ground supply
AVSS3
56
P
Analog ground supply
DVCC1
18
18
P
Digital power supply
DVCC2
40
40
43
P
Digital power supply
DVCC3
63
63
6
P
Digital power supply
DVSS1
17
17
P
Digital ground supply
DVSS2
39
39
42
P
Digital ground supply
DVSS3
62
62
5
P
Digital ground supply
Terminal Configuration and Functions
DESCRIPTION
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Table 4-2. Signal Descriptions (continued)
FR597x(1),
FR587x(1)
FUNCTION
SPI
System
FR592x(1)
SIGNAL
TYPE
DESCRIPTION
8
34
I/O
USCI_A0: Clock signal input (SPI slave mode),
Clock signal output (SPI master mode)
33
64
36
I/O
USCI_A0: Slave in, master out (SPI mode)
1
32
1
32
35
I/O
USCI_A0: Slave out, master in (SPI mode)
UCA0STE
2
30
2
30
7
33
I/O
USCI_A0: Slave transmit enable (SPI mode)
UCA1CLK
28
28
56
31
I/O
USCI_A1: Clock signal input (SPI slave mode),
Clock signal output (SPI master mode)
UCA1SIMO
26
26
54
29
I/O
USCI_A1: Slave in, master out (SPI mode)
UCA1SOMI
27
27
55
30
I/O
USCI_A1: Slave out, master in (SPI mode)
UCA1STE
29
57
29
57
32
I/O
USCI_A1: Slave transmit enable (SPI mode)
UCB0CLK
2
2
7
I/O
USCI_B0: Clock signal input (SPI slave mode),
Clock signal output (SPI master mode)
UCB0SIMO
4
4
9
I/O
USCI_B0: Slave in, master out (SPI mode)
UCB0SOMI
5
5
10
I/O
USCI_B0: Slave out, master in (SPI mode)
UCB0STE
3
3
8
I/O
USCI_B0: Slave transmit enable (SPI mode)
UCB1CLK
14
59
64
14
59
64
19
2
I/O
USCI_B1: Clock signal input (SPI slave mode),
Clock signal output (SPI master mode)
UCB1SIMO
15
60
15
60
3
20
I/O
USCI_B1: Slave in, master out (SPI mode)
UCB1SOMI
16
61
16
61
21
4
I/O
USCI_B1: Slave out, master in (SPI mode)
UCB1STE
1
58
1
58
1
I/O
USCI_B1: Slave transmit enable (SPI mode)
NMI
20
20
23
I
Nonmaskable interrupt input
RST
20
20
23
I
Reset input active low
SIGNAL NAME
PM, RGC
PM,
RGC
DGG
PIN NO.
PIN NO.
PIN NO.
UCA0CLK
3
31
3
31
UCA0SIMO
33
64
UCA0SOMI
Terminal Configuration and Functions
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21
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
www.ti.com
Table 4-2. Signal Descriptions (continued)
FR597x(1),
FR587x(1)
FUNCTION
SIGNAL NAME
UART
PM,
RGC
DGG
PIN NO.
PIN NO.
PIN NO.
TA0.0
3
35
3
35
8
38
I/O
Timer_A TA0 CCR0 capture: CCI0A input,
compare: Out0 output
TA0.1
4
36
44
4
36
44
9
39
47
I/O
Timer_A TA0 CCR1 capture: CCI1A input,
compare: Out1 output
TA0.2
5
37
43
5
37
43
10
40
46
I/O
Timer_A TA0 CCR2 capture: CCI2A input,
compare: Out2 output
TA0CLK
34
42
34
42
37
45
I
TA1.0
2
59
2
59
7
2
I/O
Timer_A TA1 CCR0 capture: CCI0A input,
compare: Out0 output
TA1.1
25
42
60
25
42
60
28
45
3
I/O
Timer_A TA1 CCR1 capture: CCI1A input,
compare: Out1 output
TA1.2
41
61
41
61
44
4
I/O
Timer_A TA1 CCR2 capture: CCI2A input,
compare: Out2 output
TA1CLK
43
58
43
58
46
1
I
TA3.2
14
14
19
I/O
Timer_A TA3 CCR2 capture: CCI2B input,
compare: Out2 output
TA3.3
15
15
20
I/O
Timer_A TA3 CCR3 capture: CCI3B input,
compare: Out3 output
TA3.4
16
16
21
I/O
Timer_A TA3 CCR4 capture: CCI4B input,
compare: Out4 output
TB0.0
11
26
11
26
16
29
I/O
Timer_B TB0 CCR0 capture: CCI0B input,
compare: Out0 output
TB0.1
12
27
12
27
17
30
I/O
Timer_B TB0 CCR1 capture: CCI1A input,
compare: Out1 output
TB0.2
13
28
13
28
18
31
I/O
Timer_B TB0 CCR2 capture: CCI2A input,
compare: Out2 output
TB0.3
29
29
32
I/O
Timer_B TB0 CCR3 capture: CCI3B input,
compare: Out3 output
TB0.4
31
31
34
I/O
Timer_B TB0 CCR4 capture: CCI4B input,
compare: Out4 output
TB0.5
32
32
35
I/O
Timer_B TB0 CCR5 capture: CCI5B input,
compare: Out5 output
TB0.6
33
33
36
I/O
Timer_B TB0 CCR6 capture: CCI6B input,
compare: Out6 output
TB0CLK
25
33
57
25
33
57
28
36
I
Timer_B TB0 clock signal TB0CLK input
TB0OUTH
21
30
21
30
24
33
I
Switch all PWM outputs high impedance input Timer_B TB0
UCA0RXD
1
32
1
32
35
I
USCI_A0: Receive data (UART mode)
UCA0TXD
33
64
33
64
36
O
USCI_A0: Transmit data (UART mode)
UCA1RXD
27
27
30
I
USCI_A1: Receive data (UART mode)
UCA1TXD
26
26
29
O
USCI_A1: Transmit data (UART mode)
DESCRIPTION
Timer_A TA0 clock signal TA0CLK input
Timer_A TA1 clock signal TA1CLK input
RGC package only. VQFN package exposed
thermal pad. TI recommends connection to
VSS.
Thermal Pad
22
SIGNAL
TYPE
PM, RGC
Timer_A
Timer_B
FR592x(1)
Terminal Configuration and Functions
Copyright © 2015–2018, Texas Instruments Incorporated
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
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4.4
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.11.22.
4.5
Buffer Type
Table 4-3 describes the buffer types that are referenced in Section 4.2.
Table 4-3. Buffer Type
NOMINAL
VOLTAGE
HYSTERESIS
PU OR PD
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT
DRIVE
STRENGTH
(mA)
LVCMOS
3.0 V
Y (1)
Programmable
See Table 5-11
See
Section 5.12.5.1
Analog
3.0 V
N
N/A
N/A
N/A
See analog modules in
Section 5 for details
Power (DVCC)
3.0 V
N
N/A
N/A
N/A
SVS enables hysteresis on
DVCC
Power (AVCC)
3.0 V
N
N/A
N/A
N/A
BUFFER TYPE
(STANDARD)
(1)
OTHER
CHARACTERISTICS
Only for Input pins.
4.6
Connection of Unused Pins
Table 4-4 lists the correct termination of all unused pins.
Table 4-4. Connection of Unused Pins (1)
PIN
POTENTIAL
COMMENT
AVCC
DVCC
AVSS
DVSS
Px.0 to Px.7
Open
Switched to port function, output direction (PxDIR.n = 1)
RST/NMI
DVCC or VCC
47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF (2)) pulldown
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
Open
The JTAG pins are shared with general-purpose I/O function (PJ.x). If these pins are not used, they
should be set to port function and output direction. When used as JTAG pins, these pins should
remain open.
TEST
Open
This pin always has an internal pulldown enabled.
(1)
(2)
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG
mode with TI tools like FET interfaces or GANG programmers.
Terminal Configuration and Functions
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23
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MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
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5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to VSS
Voltage difference between DVCC and AVCC pins
Voltage applied to any pin
MIN
MAX
–0.3
4.1
V
±0.3
V
VCC + 0.3
–0.3
(4.1 Maximum)
V
(2)
(3)
Diode current at any device pin
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(4)
–40
UNIT
±2
mA
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3
Recommended Operating Conditions
Typical data are based on VCC = 3.0 V, TA = 25°C (unless otherwise noted)
MIN
VCC
Supply voltage applied at all DVCC and AVCC pins
VSS
Supply voltage applied at all DVSS and AVSS pins
TA
Operating free-air temperature
TJ
Operating junction temperature
CDVCC
Capacitor value at DVCC (5)
fSYSTEM
Processor frequency (maximum MCLK
frequency) (6)
fACLK
Maximum ACLK frequency
fSMCLK
Maximum SMCLK frequency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
24
(1) (2) (3)
1.8
NOM
MAX
(4)
UNIT
3.6
V
–40
85
°C
–40
85
0
V
1–20%
°C
µF
No FRAM wait states (NWAITSx = 0)
0
8 (7)
With FRAM wait states (NWAITSx = 1) (8)
0
16 (9)
MHz
50
kHz
16 (9)
MHz
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device
operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in Absolute Maximum Ratings.
Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
The minimum supply voltage is defined by the supervisor SVS levels. See the PMM SVS threshold parameters in Table 5-2 for the exact
values.
As decoupling capacitor for each supply pin pair (DVCC and DVSS, AVCC and AVSS), a low-ESR ceramic capacitor of 100 nF
(minimum) should be placed as close as possible (within a few millimeters) to the respective pin pairs.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted.
Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always excecuted
without wait states.
DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted. If a clock source with a
higher typical value is used, the clock must be divided in the clock system.
Specifications
Copyright © 2015–2018, Texas Instruments Incorporated
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5.4
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2)
FREQUENCY (fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
VCC
1 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
IAM, FRAM_UNI
(Unified memory) (3)
(4) (5)
MAX
4 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
MAX
8 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
MAX
12 MHz
1 WAIT
STATES
(NWAITSx = 1)
TYP
MAX
16 MHz
1 WAIT
STATES
(NWAITSx = 1)
TYP
UNIT
MAX
FRAM
3.0 V
210
640
1220
1475
1845
µA
FRAM
0% cache hit
ratio
3.0 V
370
1280
2510
2080
2650
µA
IAM,
FRAM(0%)
IAM,
FRAM(50%)
(4) (5)
FRAM
50% cache hit
ratio
3.0 V
240
745
1440
1575
1990
µA
IAM,
FRAM(66%)
(4) (5)
FRAM
66% cache hit
ratio
3.0 V
200
560
1070
1300
1620
µA
IAM,
FRAM(75%)
(4) (5)
FRAM
75% cache hit
ratio
3.0 V
170
480
890
IAM,
FRAM(100%
FRAM
100% cache hit
ratio
3.0 V
110
235
420
640
730
IAM,
RAM
RAM
3.0 V
130
320
585
890
1070
RAM
3.0 V
100
290
555
860
1040
(6) (5)
IAM, RAM only
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(4) (5)
(7) (5)
255
180
1085
1155
1310
1420
1620
µA
µA
µA
1300
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO= 24 MHz and
fMCLK = fSMCLK = fDCO/2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff:
fMCLK,eff = fMCLK / [wait states × (1 - cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio fMCKL,eff = fMCLK / [1 × (1 - 0.75) + 1] = fMCLK / 1.25.
Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesess divided by the total number of FRAM accesses. For example, a 75% ratio implies three of
every four accesses is from cache, and the remaining are FRAM accesses.
See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in Section 5.4.
Program and data reside entirely in RAM. All execution is from RAM.
Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Specifications
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25
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
5.5
www.ti.com
Typical Characteristics - Active Mode Supply Currents
3000
I(AM,0%)
I(AM,50%)
2500
I(AM,66%)
Active Mode Current [µA]
I(AM,75%)
2000
I(AM,100%)
I(AM,75%)[uA] = 103*f[MHz] + 68
I(AM,RAMonly)
1500
1000
500
0
0
1
2
3
4
5
6
7
8
9
MCLK Frequency [MHz]
C001
NOTE: I(AM, cache hit ratio): Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with
cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of
FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are
FRAM accesses.
NOTE: I(AM, RAMonly): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Figure 5-1. Typical Active Mode Supply Currents, No Wait States
5.6
Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2)
FREQUENCY (fSMCLK)
PARAMETER
VCC
1 MHz
TYP
ILPM0
ILPM1
(1)
(2)
26
2.2 V
75
3.0 V
80
2.2 V
40
3.0 V
40
4 MHz
MAX
120
65
TYP
8 MHz
MAX
TYP
12 MHz
MAX
TYP
16 MHz
MAX
TYP
105
165
250
230
115
175
260
240
65
130
215
195
65
130
215
195
UNIT
MAX
275
220
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency - except for 12 MHz: here fDCO=24MHz and fSMCLK = fDCO/2.
Specifications
Copyright © 2015–2018, Texas Instruments Incorporated
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MSP430FR5872, MSP430FR58721, MSP430FR5870
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5.7
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Low-Power Mode LPM2, LPM3, LPM4 Supply Currents (Into VCC) Excluding External
Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
–40°C
TYP
25°C
MAX
TYP
ILPM2,XT12
Low-power mode 2, 12-pF
crystal (2) (3) (4)
2.2 V
0.8
1.2
3.0 V
0.8
1.2
ILPM2,XT3.7
Low-power mode 2, 3.7-pF
crystal (2) (5) (4)
2.2 V
0.7
3.0 V
0.7
ILPM2,VLO
Low-power mode 2, VLO,
includes SVS (6)
2.2 V
0.5
0.9
3.0 V
0.5
0.9
ILPM3,XT12
Low-power mode 3, 12-pF
crystal, includes SVS (2) (3) (7)
2.2 V
0.7
0.9
3.0 V
0.7
0.9
Low-power mode 3, 3.7-pF
crystal, excludes SVS (2) (5) (8)
(also see Figure 5-2)
2.2 V
0.6
ILPM3,XT3.7
3.0 V
ILPM3,VLO
Low-power mode 3,
VLO, excludes SVS (9)
Low-power mode 3,
VLO, excludes SVS, RAM
powered down completely (10)
ILPM3,VLO,
RAMoff
60°C
MAX
TYP
(1)
85°C
MAX
TYP
3.1
8.8
3.1
8.8
1.1
3.0
8.7
1.1
3.0
8.7
2.8
8.5
2.8
8.5
1.2
2.5
1.2
2.5
0.7
1.1
2.4
0.6
0.7
1.1
2.4
2.2 V
0.35
0.4
0.9
1.8
3.0 V
0.35
0.4
0.9
1.8
2.2 V
0.35
0.4
0.8
1.7
3.0 V
0.35
0.4
0.8
1.7
2.2
2.0
1.2
0.8
0.7
MAX
17
UNIT
μA
μA
16.7
6.4
μA
μA
μA
6.1
5.2
μA
μA
(1)
(2)
(3)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5 pF load.
(4) Low-power mode 2, crystal oscillator test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
(6) Low-power mode 2, VLO test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 3, 12-pF crystal, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(8) Low-power mode 3, 3.7-pF crystal, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =
0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(9) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(10) Low-power mode 3, VLO, excludes SVS, RAM powered down completely test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout included. SVS disabled
(SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
Specifications
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27
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
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Low-Power Mode LPM2, LPM3, LPM4 Supply Currents (Into VCC) Excluding External
Current (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
–40°C
TYP
25°C
MAX
TYP
ILPM4,SVS
Low-power mode 4, includes
SVS (11)
2.2 V
0.45
0.55
3.0 V
0.45
0.55
ILPM4
Low-power mode 4, excludes
SVS (12)
2.2 V
0.25
0.4
3.0 V
0.25
0.4
Low-power mode 4, excludes
SVS, RAM powered down
completely (13)
2.2 V
0.25
0.4
ILPM4,RAMoff
3.0 V
0.25
0.4
IIDLE,GroupA
Additional idle current if one or
more modules from Group A
(see Section 6.3.2) are
activated in LPM3 or LPM4
3.0 V
IIDLE,GroupB
Additional idle current if one or
more modules from Group B
(see Section 6.3.2) are
activated in LPM3 or LPM4
IIDLE,GroupC
Additional idle current if one or
more modules from Group C
(see Section 6.3.2) are
activated in LPM3 or LPM4
60°C
MAX
TYP
(1)
85°C
MAX
TYP
MAX
UNIT
0.9
1.8
0.9
1.8
0.7
1.6
0.7
1.6
0.7
1.4
0.7
1.4
4.6
0.02
0.4
1.0
μA
3.0 V
0.02
0.4
1.0
μA
3.0 V
0.02
0.3
0.8
μA
0.8
0.65
0.65
6.2
4.6
μA
μA
μA
(11) Low-power mode 4, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(12) Low-power mode 4, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(13) Low-power mode 4, excludes SVS, RAM powered down completely test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
28
Specifications
Copyright © 2015–2018, Texas Instruments Incorporated
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www.ti.com
5.8
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
–40°C
TYP
25°C
MAX
TYP
ILPM3.5,XT12
Low-power mode 3.5, 12-pF
crystal including SVS (2) (3) (4)
2.2 V
0.45
0.5
3.0 V
0.45
0.5
ILPM3.5,XT3.7
Low-power mode 3.5, 3.7-pF
crystal excluding SVS (2) (5) (6)
2.2 V
0.3
3.0 V
0.3
ILPM4.5,SVS
Low-power mode 4.5, including
SVS (7)
2.2 V
0.2
0.3
3.0 V
0.2
0.3
ILPM4.5
Low-power mode 4.5,
excluding SVS (8)
2.2 V
0.03
3.0 V
0.03
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
60°C
MAX
TYP
85°C
MAX
TYP
0.6
0.75
0.6
0.75
0.35
0.4
0.65
0.35
0.4
0.65
0.35
0.4
0.35
0.4
0.04
0.06
0.14
0.04
0.06
0.14
0.75
0.5
MAX
1.4
UNIT
μA
μA
0.7
0.5
μA
μA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5 pF load.
Low-power mode 3.5, 1-pF crystal including SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
Low-power mode 3.5, 3.7-pF crystal excluding SVS test conditions:
Current for RTC clocked by XT1 included.Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Specifications
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5.9
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Typical Characteristics, Low-Power Mode Supply Currents
3
3
@ 3.0V, SVS off
@ 3.0V, SVS off
@ 2.2V, SVS off
@ 2.2V, SVS off
@ 3.0V, SVS on
2.5
@ 3.0V, SVS on
2.5
@ 2.2V, SVS on
LPM4 Supply Current [ A]
LPM3 Supply Current [ A]
@ 2.2V, SVS on
2
1.5
1
0.5
2
1.5
1
0.5
0
0
-50
-25
0
25
50
75
100
-50
-25
0
25
Temperature [ƒC]
50
75
C003
Figure 5-2. LPM3 Supply Current vs Temperature (LPM3,XT3.7)
C001
Figure 5-3. LPM4 Supply Current vs Temperature (LPM4,SVS)
7.00E-01
0.7
@ 3.0V, SVS off
@ 3.0V, SVS off
@ 2.2V, SVS off
@ 2.2V, SVS off
6.00E-01
@ 3.0V, SVS on
LPM.54 Supply Current [ A]
LPM3.5 Supply Current [ A]
0.6
0.5
0.4
0.3
0.2
-50.00
100
Temperature [ƒC]
@ 2.2V, SVS on
5.00E-01
4.00E-01
3.00E-01
2.00E-01
1.00E-01
0.00E+00
-25.00
0.00
25.00
50.00
75.00
100.00
Temperature [ƒC]
-50
-25
0
25
50
75
100
Temperature [ƒC]
C004
C003
Figure 5-4. LPM3.5 Supply Current vs Temperature
(LPM3.5,XT3.7)
30
Specifications
Figure 5-5. LPM4.5 Supply Current vs Temperature (LPM4.5)
Copyright © 2015–2018, Texas Instruments Incorporated
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
5.10 Typical Characteristics, Current Consumption per Module
MODULE
TEST CONDITIONS
REFERENCE CLOCK
Timer_A
Module input clock
Timer_B
MIN
TYP
MAX
UNIT
3
μA/MHz
Module input clock
5
μA/MHz
eUSCI_A
UART mode
Module input clock
5.5
μA/MHz
eUSCI_A
SPI mode
Module input clock
3.5
μA/MHz
eUSCI_B
SPI mode
Module input clock
3.5
μA/MHz
eUSCI_B
I2C mode, 100 kbaud
Module input clock
3.5
μA/MHz
32 kHz
100
nA
RTC_C
MPY
Only from start to end of operation
MCLK
25
μA/MHz
AES
Only from start to end of operation
MCLK
21
μA/MHz
CRC16
Only from start to end of operation
MCLK
2.5
μA/MHz
CRC32
Only from start to end of operation
MCLK
2.5
μA/MHz
5.11 Thermal Resistance Characteristics (1)
PARAMETER
PACKAGE
VALUE (1)
UNIT
θJA
Junction-to-ambient thermal resistance, still air (2)
57.7
°C/W
θJC(TOP)
Junction-to-case (top) thermal resistance (3)
15.1
°C/W
θJB
Junction-to-board thermal resistance (4)
26.5
°C/W
ΨJB
Junction-to-board thermal characterization parameter
26.2
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.5
°C/W
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance (5)
N/A
°C/W
θJA
Junction-to-ambient thermal resistance, still air (2)
59.3
°C/W
θJC(TOP)
Junction-to-case (top) thermal resistance (3)
19.5
°C/W
30.8
°C/W
30.5
°C/W
1.0
°C/W
TSSOP-56 (DGG)
(4)
θJB
Junction-to-board thermal resistance
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
QFP-64 (PN)
(5)
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
θJA
Junction-to-ambient thermal resistance, still air (2)
29.6
°C/W
θJC(TOP)
Junction-to-case (top) thermal resistance (3)
15.8
°C/W
8.5
°C/W
8.5
°C/W
(4)
θJB
Junction-to-board thermal resistance
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
0.2
°C/W
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance (5)
1.2
°C/W
(1)
(2)
(3)
(4)
(5)
QFN-64 (RGC)
N/A = not applicable
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Specifications
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5.12 Timing and Switching Characteristics
5.12.1 Power Supply Sequencing
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the
device including erroneous writes to RAM and FRAM.
Table 5-1 lists the reset power ramp requirements.
Table 5-1. Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VVCC_BOR–
Brownout power-down level
VVCC_BOR+
Brownout power-up level (1)
(1)
(2)
TEST CONDITIONS
(1)
MIN
MAX
UNIT
(2)
0.73
1.66
V
| dDVCC/dt | < 3 V/s (2)
0.79
1.68
V
| dDVCC/dt | < 3 V/s
Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
The brownout levels are measured with a slowly changing supply.
Table 5-2 lists the characteristics of the SVS.
Table 5-2. SVS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISVSH,LPM
SVSH current consumption, low power modes
170
300
nA
VSVSH-
SVSH power-down level (1)
1.75
1.80
1.85
V
VSVSH+
SVSH power-up level (1)
1.77
1.88
1.99
V
VSVSH_hys
SVSH hysteresis
120
mV
tPD,SVSH, AM
SVSH propagation delay, active mode
10
µs
(1)
40
dVVcc/dt = –10 mV/µs
For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference
Design.
5.12.2 Reset Timing
Table 5-11 lists the required reset input timing.
Table 5-3. Reset Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(RST)
(1)
32
External reset pulse duration on RST
(1)
VCC
2.2 V, 3.0 V
MIN
MAX
2
UNIT
µs
Not applicable if the RST/NMI pin is configured as NMI.
Specifications
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5.12.3 Clock Specifications
Table 5-4 lists the characteristics of the LFXT.
Table 5-4. Low-Frequency Crystal Oscillator, LFXT (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IVCC.LFXT
Current consumption
TEST CONDITIONS
VCC
MIN
TYP
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF, ESR ≈ 44 kΩ
180
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {1},
TA = 25°C, CL,eff = 6 pF, ESR ≈ 40 kΩ
185
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {2},
TA = 25°C, CL,eff = 9 pF, ESR ≈ 40 kΩ
3.0 V
LFXT oscillator crystal
frequency
LFXTBYPASS = 0
DCLFXT
LFXT oscillator duty cycle
Measured at ACLK,
fLFXT = 32768 Hz
fLFXT,SW
LFXT oscillator logic-level
square-wave input frequency
LFXTBYPASS = 1 (2)
nA
DCLFXT, SW
LFXT oscillator logic-level
square-wave input duty cycle
LFXTBYPASS = 1
OALFXT
Oscillation allowance for
LF crystals (4)
330
32768
30%
(3)
UNIT
225
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF, ESR ≈
40 kΩ
fLFXT
MAX
10.5
Hz
70%
32.768
30%
50
kHz
70%
LFXTBYPASS = 0, LFXTDRIVE = {1},
fLFXT = 32768 Hz, CL,eff = 6 pF
210
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
300
kΩ
CLFXIN
Integrated load capacitance at
LFXIN terminal (5) (6)
2
pF
CLFXOUT
Integrated load capacitance at
LFXOUT terminal (5) (6)
2
pF
(1)
(2)
(3)
(4)
(5)
(6)
To improve EMI on the LFXT oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
• Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF
• For LFXTDRIVE = {1}, CL,eff = 6 pF
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 9 pF
• For LFXTDRIVE = {3}, 9 pF ≤ CL,eff ≤ 12.5 pF
This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT is the
total capacitance at the LFXIN and LFXOUT terminals, respectively.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are 3.7
pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds additional capacitance, so it must also be
considered in the overall capacitance. Verify that the recommended effective load capacitance of the selected crystal is met.
Specifications
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Table 5-4. Low-Frequency Crystal Oscillator, LFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tSTART,LFXT
fFault,LFXT
(7)
(8)
(9)
Start-up time
TEST CONDITIONS
(7)
Oscillator fault frequency (8)
VCC
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF
3.0 V
fOSC = 32768 Hz
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
3.0 V
MIN
TYP
MAX
UNIT
800
ms
(9)
1000
0
3500
Hz
Includes start-up counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition will set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Table 5-5 lists the characteristics of the HFXT.
Table 5-5. High-Frequency Crystal Oscillator, HFXT (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1 (2),
TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt
IDVCC.HFXT
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1
TA = 25°C,
HFXT oscillator crystal current HF CL,eff = 18 pF, typical ESR, Cshunt
mode at typical ESR
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 2,
HFFREQ = 2,
TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt
3.0 V
μA
190
(1)
(2)
(3)
34
250
(2)
4
8
HFXT oscillator crystal frequency,
crystal mode
HFXTBYPASS = 0, HFFREQ = 2
(3)
8.01
16
HFXTBYPASS = 0, HFFREQ = 3
(3)
16.01
24
HFXT oscillator duty cycle
Measured at SMCLK,
fHFXT = 16 MHz
UNIT
120
HFXTBYPASS = 0, HFFREQ = 1
(3)
DCHFXT
MAX
75
fOSC = 24 MHz
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3,
TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt
fHFXT
TYP
40%
50%
MHz
60%
To improve EMI on the HFXT oscillator the following guidelines should be observed.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
• Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
HFFREQ = {0} is not supported for HFXT crystal mode of operation.
Maximum frequency of operation of the entire device cannot be exceeded.
Specifications
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Table 5-5. High-Frequency Crystal Oscillator, HFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
HFXTBYPASS = 1, HFFREQ = 0 (4)
(3)
fHFXT,SW
HFXT oscillator logic-level
square-wave input frequency,
bypass mode
HFXTBYPASS = 1, HFFREQ = 1 (4)
(3)
HFXTBYPASS = 1, HFFREQ = 2
OAHFXT
HFXT oscillator logic-level
square-wave input duty cycle
Oscillation allowance for
HFXT crystals (5)
tSTART,HFXT Start-up time (6)
MAX
0.9
4
4.01
8
8.01
16
16.01
24
40%
60%
UNIT
MHz
(3)
(3)
SW
TYP
(4)
HFXTBYPASS = 1, HFFREQ = 3 (4)
DCHFXT,
MIN
HFXTBYPASS = 1
HFXTBYPASS = 0,
HFXTDRIVE = 0, HFFREQ = 1 (2),
fHFXT,HF = 4 MHz, CL,eff = 16 pF
450
HFXTBYPASS = 0,
HFXTDRIVE = 1, HFFREQ = 1,
fHFXT,HF = 8 MHz, CL,eff = 16 pF
320
HFXTBYPASS = 0,
HFXTDRIVE = 2, HFFREQ = 2,
fHFXT,HF = 16 MHz, CL,eff = 16 pF
200
HFXTBYPASS = 0,
HFXTDRIVE = 3, HFFREQ = 3,
fHFXT,HF = 24 MHz, CL,eff = 16 pF
200
Ω
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1,
TA = 25°C, CL,eff = 16 pF
3.0 V
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3,
TA = 25°C, CL,eff = 16 pF
3.0 V
1.6
ms
0.6
CHFXIN
Integrated load capacitance at
HFXIN terminaI (7) (8)
2
pF
CHFXOUT
Integrated load capacitance at
HFXOUT terminaI (7) (8)
2
pF
fFault,HFXT
Oscillator fault frequency
(9) (10)
0
800
kHz
(4)
When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT, SW.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes start-up counter of 1024 clock cycles.
(7) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN x COUT / (CIN + COUT), where CIN and COUT is the
total capacitance at the HFXIN and HFXOUT terminals, respectively.
(8) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are
14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds additional capacitance, so it must also be considered in
the overall capacitance. Verify that the recommended effective load capacitance of the selected crystal is met.
(9) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static
condition or stuck at fault condition will set the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
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Table 5-6 lists the characteristics of the DCO.
Table 5-6. DCO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
1
±3.5%
MHz
fDCO1
DCO frequency range 1 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 0
DCORSEL = 1, DCOFSEL = 0
fDCO2.7
DCO frequency range 2.7 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 1
2.667
±3.5%
MHz
fDCO3.5
DCO frequency range 3.5 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 2
3.5
±3.5%
MHz
fDCO4
DCO frequency range 4 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 3
4
±3.5%
MHz
fDCO5.3
DCO frequency range 5.3 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 4
DCORSEL = 1, DCOFSEL = 1
5.333
±3.5%
MHz
fDCO7
DCO frequency range 7 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 5
DCORSEL = 1, DCOFSEL = 2
7
±3.5%
MHz
fDCO8
DCO frequency range 8 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 6
DCORSEL = 1, DCOFSEL = 3
8
±3.5%
MHz
fDCO16
DCO frequency range 16 MHz,
trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 1, DCOFSEL = 4
16
±3.5% (1)
MHz
fDCO21
DCO frequency range 21 MHz,
trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 5
21
±3.5% (1)
MHz
fDCO24
DCO frequency range 24 MHz,
trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 6
24
±3.5% (1)
MHz
Duty cycle
Measured at SMCLK, divide by 1,
No external divide, all DCORSEL and
DCOFSEL settings except DCORSEL
= 1, DCOFSEL = 5 and DCORSEL =
1, DCOFSEL = 6
50%
52%
DCO jitter
Based on fsignal = 10 kHz and DCO
used for 12-bit SAR ADC sampling
source. This achieves >74-dB SNR
due to jitter; that is, it is limited by
ADC performance.
2
3
fDCO,DC
tDCO,
JITTER
dfDCO/dT
(1)
(2)
DCO temperature drift (2)
48%
3.0 V
0.01
ns
%/ºC
After a wakeup from LPM1, LPM2, LPM3 or LPM4, the DCO frequency fDCO might exceed the specified frequency range for a few
clocks cycles by up to 5% before settling into the specified steady state frequency range.
Calculated using the box method: (MAX(–40°C to 85ºC) – MIN(–40°C to 85ºC)) / MIN(–40°C to 85ºC) / (85ºC – (–40ºC))
Table 5-7 lists the characteristics of the VLO.
Table 5-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IVLO
Current consumption
fVLO
VLO frequency
Measured at ACLK
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
VLO frequency supply voltage drift
Measured at ACLK
fVLO,DC
Duty cycle
Measured at ACLK
36
MIN
TYP
MAX
100
dfVLO/dVCC
(1)
(2)
VCC
6
9.4
nA
14
0.2
(2)
50%
kHz
%/°C
0.7
40%
UNIT
%/V
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Table 5-8 lists the characteristics of the MODOSC.
Table 5-8. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IMODOSC
Current consumption
fMODOSC
MODOSC frequency
fMODOSC/dT
MODOSC frequency temperature drift (1)
fMODOSC/dVCC
MODOSC frequency supply voltage
drift (2)
DCMODOSC
Duty cycle
(1)
(2)
TEST CONDITIONS
MIN
Enabled
MAX
25
4.0
Measured at SMCLK, divide by 1
TYP
40%
4.8
UNIT
μA
5.4
MHz
0.08
%/℃
1.4
%/V
50%
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
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5.12.4 Wake-up Characteristics
Table 5-9 lists the device wake-up times.
Table 5-9. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
tWAKE-UP FRAM
MIN
Additional wake-up time to activate the FRAM
in AM if previously disabled by the FRAM
controller or from an LPM if immediate
activation is selected
MCLKREQEN = 1
(1)
tWAKE-UP LPM0
VCC
Wake-up time from LPM0 to active mode
MCLKREQEN = 0
(1) (2)
TYP
MAX
6
10
2.2 V, 3.0 V
400 ns +
1.5 / fDCO
2.2 V, 3.0 V
400 ns +
2.5 / fDCO
UNIT
μs
tWAKE-UP LPM1
Wake-up time from LPM1 to active mode (1)
2.2 V, 3.0 V
6
tWAKE-UP LPM2
Wake-up time from LPM2 to active mode
(1)
2.2 V, 3.0 V
6
tWAKE-UP LPM3
Wake-up time from LPM3 to active mode (1)
2.2 V, 3.0 V
7
10
μs
tWAKE-UP LPM4
Wake-up time from LPM4 to active mode (1)
2.2 V, 3.0 V
7
10
μs
μs
tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode
(3)
tWAKE-UP-BOR
(1)
(2)
(3)
μs
2.2 V, 3.0 V
250
350
SVSHE = 1
2.2 V, 3.0 V
250
350
μs
SVSHE = 0
2.2 V, 3.0 V
0.4
0.8
ms
Wake-up time from a RST pin triggered reset to
active mode (3)
2.2 V, 3.0 V
250
350
μs
(3)
2.2 V, 3.0 V
0.5
1.0
ms
tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode (3)
tWAKE-UP-RST
μs
Wake-up time from power-up to active mode
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge with MCLKREQEN = 1. This time includes the activation of the FRAM during wakeup.
With MCLKREQEN = 0, the MCLK is gated one additoinal one clock cycle (wake from LPM0, LPM1, LPM2, LPM3, and LPM4). The
device wake-up time is not affected by the status of the MCLKREQEN bit.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
Table 5-10 lists the typical charge required for wakeup.
Table 5-10. Typical Wake-up Charge (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QWAKE-UP FRAM
Charge used for activating the FRAM in AM or during wakeup
from LPM0 if previously disabled by the FRAM controller.
15.1
nAs
QWAKE-UP LPM0
Charge used to wake up from LPM0 to active mode (with FRAM
active)
4.4
nAs
QWAKE-UP LPM1
Charge used to wake up from LPM1 to active mode (with FRAM
active)
15.1
nAs
QWAKE-UP LPM2
Charge used to wake up from LPM2 to active mode (with FRAM
active)
15.3
nAs
QWAKE-UP LPM3
Charge used to wake up from LPM3 to active mode (with FRAM
active)
16.5
nAs
QWAKE-UP LPM4
Charge used to wake up from LPM4 to active mode (with FRAM
active)
16.5
nAs
QWAKE-UP LPM3.5
Charge used to wake up from LPM3.5 to active mode (2)
76
nAs
QWAKE-UP LPM4.5
Charge used to wake up from LPM4.5 to active mode (2)
QWAKE-UP-RESET
Charge used for reset from RST or BOR event to active mode (2)
(1)
(2)
38
SVSHE = 1
77
SVSHE = 0
77.5
75
nAs
nAs
Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active
mode (for example, for an interrupt service routine).
Charge required until start of user code. This does not include the energy required to reconfigure the device.
Specifications
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
5.12.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
10000.00
LPM0
LPM1
LPM2,XT12
Average Wake-up Current (µA)
1000.00
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 5-6. Average LPM Currents vs Wake-up Frequency at 25°C
10000.00
LPM0
LPM1
LPM2,XT12
Average Wake-up Current (µA)
1000.00
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 5-7. Average LPM Currents vs Wake-up Frequency at 85°C
Specifications
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
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5.12.5 Digital I/Os
Table 5-11 lists the characteristics of the digital inputs.
Table 5-11. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2 V
1.2
TYP
MAX
1.65
3.0 V
1.65
2.25
2.2 V
0.55
1.00
3.0 V
0.75
1.35
2.2 V
0.44
0.98
3.0 V
0.60
1.30
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
3
pF
CI,ana
Input capacitance, port pins with shared analog
VIN = VSS or VCC
functions (1)
5
pF
Ilkg(Px.y)
High-impedance input leakage current
See
t(int)
External interrupt timing (external trigger pulse
duration to set interrupt flag) (4)
Ports with interrupt capability
(see block diagram and
terminal function
descriptions).
t(RST)
External reset pulse duration on RST (5)
(1)
(2)
(3)
(4)
(5)
40
20
(2) (3)
35
50
V
V
V
kΩ
2.2 V,
3.0 V
–20
2.2 V,
3.0 V
20
ns
2.2 V,
3.0 V
2
µs
+20
nA
If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in
series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and
PJ.5/LFXOUT.
The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Not applicable if the RST/NMI pin is configured as NMI.
Specifications
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Table 5-12 lists the characteristics of the digital outputs.
Table 5-12. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TYP
I(OHmax) = –3 mA (2)
VCC –
0.60
VCC
I(OHmax) = –2 mA (1)
VCC –
0.25
VCC
VCC –
0.60
VCC
VSS
VSS +
0.25
I(OLmax) = 3 mA (2)
VSS
VSS +
0.60
I(OLmax) = 2 mA (1)
VSS
VSS +
0.25
VSS
VSS +
0.60
2.2 V
High-level output voltage
3.0 V
I(OHmax) = –6 mA (2)
I(OLmax) = 1 mA (1)
Low-level output voltage
3.0 V
I(OLmax) = 6 mA (2)
fPx.y
Port output frequency (with load) (3)
CL = 20 pF, RL
fPort_CLK
Clock output frequency (3)
ACLK, MCLK, or SMCLK at
configured output port
CL = 20 pF (5)
trise,dig
Port output rise time, digital only port pins
CL = 20 pF
tfall,dig
Port output fall time, digital only port pins
CL = 20 pF
trise,ana
Port output rise time, port pins with shared
analog functions
CL = 20 pF
tfall,ana
Port output fall time, port pins with shared
analog functions
CL = 20 pF
(1)
(2)
(3)
(4)
(5)
(4) (5)
2.2 V
16
3.0 V
16
2.2 V
16
3.0 V
16
UNIT
V
2.2 V
VOL
MAX
VCC
I(OHmax) = –1 mA (1)
VOH
MIN
VCC –
0.25
V
MHz
MHz
2.2 V
4
15
3.0 V
3
15
2.2 V
4
15
3.0 V
3
15
2.2 V
6
15
3.0 V
4
15
2.2 V
6
15
3.0 V
4
15
ns
ns
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
The port can output frequencies at least up to the specified limit. It might support higher frequencies.
A resistive divider with 2 × R1 and R1 = 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 20 pF is connected from the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Specifications
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5.12.5.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
30
25°C
85°C
Low-Level Output Current (mA)
Low-Level Output Current (mA)
15
10
5
25°C
85°C
20
10
P1.1
P1.1
0
0
0
0.5
1
1.5
2
0
0.5
1
Low-Level Output Voltage (V)
1.5
2
2.5
3
Low-Level Output Voltage (V)
C001
C001
VCC = 2.2 V
VCC = 3.0 V
Figure 5-8. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
25°C
85°C
High-Level Output Current (mA)
High-Level Output Current (mA)
0
Figure 5-9. Typical Low-Level Output Current vs Low-Level
Output Voltage
-5
-10
25°C
85°C
-10
-20
P1.1
P1.1
-15
-30
0
0.5
1
1.5
2
0
0.5
1
High-Level Output Voltage (V)
1.5
2
2.5
C001
VCC = 2.2 V
Figure 5-10. Typical High-Level Output Current vs High-Level
Output Voltage
42
Specifications
3
High-Level Output Voltage (V)
C001
VCC = 3.0 V
Figure 5-11. Typical High-Level Output Current vs High-Level
Output Voltage
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Table 5-13 lists the characteristics of the pin oscillator.
Table 5-13. Pin-Oscillator Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
foPx.y
(1)
TEST CONDITIONS
Pin-oscillator frequency
VCC
MIN
TYP
MAX
UNIT
Px.y, CL = 10 pF (1)
3.0 V
1200
kHz
(1)
3.0 V
650
kHz
Px.y, CL = 20 pF
CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.
1000
fitted
fitted
25°C
25°C
85°C
Pin Oscillator Frequency [kHz]
Pin Oscillator Frequency [kHz]
5.12.5.2 Typical Characteristics, Pin-Oscillator Frequency
100
1000
85°C
100
10
100
10
External Load Capacitance (incl. board etc.) [pF]
100
External Load Capacitance (incl. board etc.) [pF]
C002
VCC = 2.2 V
One output active at a time.
Figure 5-12. Typical Oscillation Frequency vs Load Capacitance
C002
VCC = 3.0 V
One output active at a time.
Figure 5-13. Typical Oscillation Frequency vs Load Capacitance
Specifications
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
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5.12.6 Timer_A and Timer_B
Table 5-14 lists the characteristics of the Timer_A.
Table 5-14. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
tTA,cap
Timer_A capture timing
All capture inputs, minimum pulse
duration required for capture
VCC
2.2 V,
3.0 V
2.2 V,
3.0 V
MIN
TYP
MAX
UNIT
16
MHz
20
ns
Table 5-15 lists the characteristics of the Timer_B.
Table 5-15. Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTB
Timer_B input clock frequency
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
tTB,cap
Timer_B capture timing
All capture inputs, minimum pulse
duration required for capture
VCC
2.2 V,
3.0 V
2.2 V,
3.0 V
MIN
TYP
MAX
UNIT
16
MHz
20
ns
5.12.7 eUSCI
Table 5-16 lists the supported clock frequencies for the eUSCI in UART mode.
Table 5-16. eUSCI (UART Mode) Clock Frequency
PARAMETER
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
CONDITIONS
VCC
MIN
MAX
UNIT
16
MHz
4
MHz
MAX
UNIT
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
Table 5-17 lists the characteristics of the eUSCI in UART mode.
Table 5-17. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tt
UART receive deglitch time (1)
TEST CONDITIONS
44
MIN
TYP
UCGLITx = 0
5
UCGLITx = 1
20
90
35
160
50
220
UCGLITx = 2
UCGLITx = 3
(1)
VCC
2.2 V,
3.0 V
30
ns
Pulses on the UART receive input (UCxRX) that are shorter than the UART receive deglitch time are suppressed. Thus the selected
deglitch time can limit the maximum usable baud rate. To make sure that pulses are correctly recognized, their duration should exceed
the maximum specification of the deglitch time.
Specifications
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Table 5-18 lists the supported clock frequencies for the eUSCI in SPI master mode.
Table 5-18. eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
feUSCI
CONDITIONS
VCC
MIN
MAX
UNIT
16
MHz
Internal: SMCLK, ACLK
Duty cycle = 50% ±10%
eUSCI input clock frequency
Table 5-19 lists the characteristics of the eUSCI in SPI master mode.
Table 5-19. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time, STE active to clock
UCSTEM = 1, UCMODEx = 01 or 10
1
tSTE,LAG
STE lag time, last clock to STE
inactive
UCSTEM = 1, UCMODEx = 01 or 10
1
tSTE,ACC
STE access time, STE active to
SIMO data out
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V,
3.0 V
60
ns
tSTE,DIS
STE disable time, STE inactive to
SOMI high impedance
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V,
3.0 V
80
ns
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
2.2 V
40
3.0 V
40
2.2 V
0
3.0 V
0
UCxCLK
cycles
ns
ns
2.2 V
10
3.0 V
10
2.2 V
0
3.0 V
0
ns
ns
fUCxCLK = 1 / 2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-14 and Figure 5-15.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 514 and Figure 5-15.
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 5-14. SPI Master Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
tHD,MO
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 5-15. SPI Master Mode, CKPH = 1
46
Specifications
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Table 5-20 lists the characteristics of the eUSCI in SPI slave mode.
Table 5-20. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
UCLK edge to SOMI valid,
CL = 20 pF
tHD,SO
SOMI output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
VCC
MIN
2.2 V
50
3.0 V
40
2.2 V
2
3.0 V
3
TYP
MAX
ns
ns
2.2 V
50
3.0 V
40
2.2 V
50
3.0 V
45
2.2 V
4
3.0 V
4
2.2 V
7
3.0 V
7
35
35
3.0 V
0
ns
ns
3.0 V
0
ns
ns
2.2 V
2.2 V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-16 and Figure 5-17.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-16
and Figure 5-17.
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SI
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tSTE,ACC
tSTE,DIS
tVALID,SO
SOMI
Figure 5-16. SPI Slave Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tSTE,ACC
tSTE,DIS
tVALID,SO
SOMI
Figure 5-17. SPI Slave Mode, CKPH = 1
48
Specifications
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Table 5-21 lists the characteristics of the eUSCI in I2C mode.
Table 5-21. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%
2.2 V, 3.0 V
fSCL = 100 kHz
UNIT
16
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3.0 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3.0 V
100
ns
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
tSU,STO
Setup time for STOP
tBUF
Bus free time between a STOP and
START condition
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
tSP
2.2 V, 3.0 V
0
MAX
2.2 V, 3.0 V
2.2 V, 3.0 V
4.7
4.0
4.7
1.3
UCGLITx = 0
50
2.2 V, 3.0 V
UCGLITx = 3
µs
0.6
fSCL > 100 kHz
UCGLITx = 2
µs
0.6
fSCL = 100 kHz
UCGLITx = 1
µs
0.6
us
250
25
125
12.5
62.5
6.3
31.5
UCCLTOx = 1
tTIMEOUT
Clock low time-out
UCCLTOx = 2
27
2.2 V, 3.0 V
30
UCCLTOx = 3
tSU,STA
tHD,STA
ns
ms
33
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-18. I2C Mode Timing
Specifications
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5.12.8 ADC12
Table 5-22 lists the power supply and input range conditions for the ADC.
Table 5-22. 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Analog input voltage (1)
V(Ax)
I(ADC12_B)
Operating supply current into
singleAVCC plus DVCC terminal (2)
ended mode
(3)
I(ADC12_B)
Operating supply current into
differential
AVCC and DVCC terminals (2)
mode
MIN
(3)
NOM
0
MAX
UNIT
AVCC
V
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 0
REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
3.0 V
145
199
2.2 V
140
190
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 1
REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
3.0 V
175
245
2.2 V
170
230
2.2 V
10
15
>2 V
0.5
4
50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Timer_B TBx
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Ax in
UART mode
Clocked by SMCLK
Clocked by ACLK
Waiting for first edge of START bit.
eUSCI_Ax in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Ax in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Bx in I C
master mode
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Not applicable
eUSCI_Bx in I2C
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Waiting for START condition or
clocked by external clock ≤50 kHz
eUSCI_Bx in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Bx in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
DMA
2
ADC12_B
Clocked by SMCLK or by MODOSC
Clocked by ACLK
Waiting for a trigger
REF_A
Not applicable
Not applicable
Always
COMP_E
Not applicable
Not applicable
Always
CRC (5)
Not applicable
Not applicable
Not applicable
MPY (5)
Not applicable
Not applicable
Not applicable
(5)
Not applicable
Not applicable
Not applicable
AES
(1)
(2)
(3)
(4)
(5)
60
Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz.
Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.
Peripherals are in a state that does not require or does not use an internal clock.
The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power
mode causes a temporary transition into active mode for the time of the transfer.
This peripheral operates during active mode only and delays the transition into a low-power mode until its operation is completed.
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6.3.2
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Idle Currents of Peripherals in LPM3 and LPM4
Most peripherals can be activated to be operational in LPM3 if clocked by ACLK. Some modules are even
operational in LPM4 because they do not require a clock to operate (for example, the comparator).
Activating a peripheral in LPM3 or LPM4 increases the current consumption due to its active supply
current contribution but also due to an additional idle current. To limit the idle current adder, certain
peripherals are group together. To achieve optimal current consumption, try to use modules within one
group and to limit the number of groups with active modules. Table 6-3 lists the grouping. Modules not
listed in this table are either already included in the standard LPM3 current consumption specifications or
cannot be used in LPM3 or LPM4.
The idle current adder is very small at room temperature (25°C) but increases at high temperatures
(85°C); see the IIDLE current parameters in Section 5.7 for details.
Table 6-3. Peripheral Groups
6.4
Group A
Group B
Group C
Timer TA0
Timer TA2
Timer TA3
Timer TA1
Timer B0
eUSCI_A1
Comparator
eUSCI_A0
ADC12_B
eUSCI_B0
REF_A
eUSCI_B1
Interrupt Vector Table and Signatures
The interrupt vectors, the power-up start address, and signatures are in the address range 0FFFFh to
0FF80h. Table 6-4 summarizes the content of this address range.
The power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains the 16-bit address pointing
to the start address of the application program.
The interrupt vectors start at 0FFFDh extending to lower addresses. Each vector contains the 16-bit
address of the appropriate interrupt-handler instruction sequence.
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if
enabled by the corresponding signature)
The signatures are at 0FF80h extending to higher addresses. Signatures are evaluated during device
start-up. Starting from address 0FF88h extending to higher addresses a JTAG password can
programmed. The password can extend into the interrupt vector locations using the interrupt vector
addresses as additional bits for the password.
See the chapter System Resets, Interrupts, and Operating Modes, System Control Module (SYS) in the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.
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Table 6-4. Interrupt Sources, Flags, Vectors, and Signatures
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power-up, Brownout, Supply
Supervisor
External Reset RST
Watchdog time-out (watchdog
mode)
WDT, FRCTL MPU, CS, PMM
password violation
FRAM uncorrectable bit error
detection
FRAM access time error
MPU segment violation
Software POR, BOR
SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
UBDIFG
ACCTEIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
PMMPORIFG, PMMBORIFG
(SYSRSTIV) (1) (2)
Reset
0FFFEh
Highest
System NMI
Vacant memory access
JTAG mailbox
FRAM bit error detection
MPU segment violation
VMAIFG
JMBNIFG, JMBOUTIFG
CBDIFG, UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
(SYSSNIV) (1) (3)
(Non)maskable
0FFFCh
User NMI
External NMI
Oscillator Fault
NMIIFG, OFIFG
(SYSUNIV) (1) (3)
(Non)maskable
0FFFAh
Comparator_E
Comparator_E interrupt flags
(CEIV) (1)
Maskable
0FFF8h
Timer_B TB0
TB0CCR0.CCIFG
Maskable
0FFF6h
Timer_B TB0
TB0CCR1.CCIFG to TB0CCR6.CCIFG,
TB0CTL.TBIFG
(TB0IV) (1)
Maskable
0FFF4h
Watchdog Timer
(Interval Timer Mode)
WDTIFG
Maskable
0FFF2h
Reserved
Reserved
Maskable
0FFF0h
eUSCI_A0 Receive or Transmit
UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA0IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA0IV) (1)
Maskable
0FFEEh
eUSCI_B0 Receive or Transmit
UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV) (1)
Maskable
0FFECh
ADC12_B
ADC12IFG0 to ADC12IFG31
ADC12LOIFG, ADC12INIFG, ADC12HIIFG,
ADC12RDYIFG, ADC12OVIFG, ADC12TOVIFG
(ADC12IV) (1) (4)
Maskable
0FFEAh
Timer_A TA0
TA0CCR0.CCIFG
Maskable
0FFE8h
Timer_A TA0
TA0CCR1.CCIFG to TA0CCR2.CCIFG,
TA0CTL.TAIFG
(TA0IV) (1)
Maskable
0FFE6h
eUSCI_A1 receive or transmit
UCA1IFG:UCRXIFG, UCTXIFG (SPI mode)
UCA1IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA1IV) (1)
Maskable
0FFE4h
(1)
(2)
(3)
(4)
62
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Only on devices with ADC, otherwise reserved.
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SLASE66C – APRIL 2015 – REVISED AUGUST 2018
Table 6-4. Interrupt Sources, Flags, Vectors, and Signatures (continued)
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
eUSCI_B1 receive or transmit
(Reserved on MSP430FR592x)
UCB1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB1IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB1IV) (1)
Maskable
0FFE2h
DMA
DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,
DMA2CTL.DMAIFG
(DMAIV) (1)
Maskable
0FFE0h
Timer_A TA1
TA1CCR0.CCIFG
Maskable
0FFDEh
Timer_A TA1
TA1CCR1.CCIFG to TA1CCR2.CCIFG,
TA1CTL.TAIFG
(TA1IV) (1)
Maskable
0FFDCh
I/O Port P1
P1IFG.0 to P1IFG.7
(P1IV) (1)
Maskable
0FFDAh
Timer_A TA2
TA2CCR0.CCIFG
Maskable
0FFD8h
Timer_A TA2
TA2CCR1.CCIFG
TA2CTL.TAIFG
(TA2IV) (1)
Maskable
0FFD6h
I/O Port P2
P2IFG.0 to P2IFG.3
(P2IV) (1)
Maskable
0FFD4h
Timer_A TA3
TA3CCR0.CCIFG
Maskable
0FFD2h
Timer_A TA3
TA3CCR1.CCIFG
TA3CTL.TAIFG
(TA3IV) (1)
Maskable
0FFD0h
I/O Port P3
P3IFG.0 to P3IFG.7
(P3IV) (1)
Maskable
0FFCEh
I/O Port P4
P4IFG.2 to P4IFG.7
(P4IV) (1)
Maskable
0FFCCh
Reserved
PRIORITY
0FFCAh
RTC_C
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG
(RTCIV) (1)
Maskable
0FFC8h
AES
AESRDYIFG
Maskable
0FFC6h
Lowest
0FFC4h
Reserved
Reserved
(5)
⋮
0FF8Ch
(5)
0FF8Ah
(5) (7)
0FF88h
IP Encapsulation Signature2
IP Encapsulation Signature1
Signatures
(5)
(6)
(7)
(6)
BSL Signature2
0FF86h
BSL Signature1
0FF84h
JTAG Signature2
0FF82h
JTAG Signature1
0FF80h
May contain a JTAG password required to enable JTAG access to the device.
Signatures are evaluated during device start-up. See the System Resets, Interrupts, and Operating Modes, System Control Module
(SYS) chapter in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.
Must not contain 0AAAAh if used as JTAG password.
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6.5
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Bootloader (BSL)
The BSL enables programming of the FRAM or RAM using a UART serial interface (FRxxxx devices) or
an I2C interface (FRxxxx1 devices). Access to the device memory through the BSL is protected by an
user-defined password. Use of the BSL requires four pins as shown in Table 6-5. BSL entry requires a
specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of
the features of the BSL and its implementation, see MSP430 FRAM Device Bootloader (BSL) User's
Guide
.
Table 6-5. BSL Pin Requirements and Functions
6.6
6.6.1
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
BSL_TX
Devices with UART BSL (FRxxxx): Data transmit
BSL_RX
Devices with UART BSL (FRxxxx): Data receive
BSL_DAT
Devices with I2C BSL (FRxxxx1): Data
BSL_CLK
Devices with I2C BSL (FRxxxx1): Clock
VCC
Power supply
VSS
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For
further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide. For a complete description of the features of the JTAG interface and its
implementation, see MSP430 Programming With the JTAG Interface.
Table 6-6. JTAG Pin Requirements and Functions
6.6.2
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-7
lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide.
64
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MSP430FR5872, MSP430FR58721, MSP430FR5870
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Table 6-7. Spy-Bi-Wire Pin Requirements and Functions
6.7
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
VSS
Ground supply
FRAM
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
• Ultra-low-power ultra-fast-write nonvolatile memory
• Byte and word access capability
• Programmable and automated wait-state generation
• Error correction coding (ECC)
NOTE
Wait States
For MCLK frequencies > 8 MHz, wait states must be configured following the flow described
in the "Wait State Control" section of the "FRAM Controller (FRCTRL)" chapter in the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.
For important software design information regarding FRAM including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
MSP430™ FRAM Technology – How To and Best Practices
6.8
RAM
The RAM is made up of one sector. The sector can be completely powered down in LPM3 and LPM4 to
save leakage; however, all data is lost during shutdown.
6.9
Tiny RAM
Twenty-six bytes of Tiny RAM are provided in addition to the complete RAM (see Table 6-36). This
memory is always available even in LPM3 and LPM4, while the complete RAM can be powered down in
LPM3 and LPM4. Tiny RAM can be used to hold data or a very small stack when the complete RAM is
powered down in LPM3 and LPM4. Tiny RAM is not available in LPMx.5.
6.10 Memory Protection Unit (MPU) Including IP Encapsulation
The FRAM can be protected by the MPU from inadvertent CPU execution and read or write access.
Features of the MPU include:
• IP encapsulation with programmable boundaries (prevents reads from "outside" like JTAG or non-IP
software) in steps of 1KB.
• Main memory partitioning that can be configured in up to three segments in steps of 1KB.
• The access rights for each main and information memory segment can be individually selected.
• Access violation flags with interrupt capability for easy servicing of access violations.
Detailed Description
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MSP430FR5872 MSP430FR58721 MSP430FR5870
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65
MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66C – APRIL 2015 – REVISED AUGUST 2018
www.ti.com
6.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430FR58xx,
MSP430FR59xx, and MSP430FR6xx Family User's Guide.
6.11.1 Digital I/O
There are up to nine 8-bit I/O ports implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all pins of
ports P1 to P4.
• Read and write access to port control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• Capacitive touch functionality is supported on all pins of ports P1 to P7, P9, and PJ.
NOTE
Configuration of Digital I/Os After BOR Reset
To prevent any cross-currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and their module functions disabled. To enable the I/O functionality after
a BOR reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared.
For details see the "Digital I/O" chapter, section "Configuration After Reset" in the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.
6.11.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch-crystal oscillator XT1 (LF), an internal very-lowpower low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements
of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources.
The clock system module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (LFXT1), the internal low-frequency
oscillator (VLO), or a digital external low frequency (
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