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MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
MSP430FR688x(1), MSP430FR588x(1) Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Embedded Microcontroller
– 16-Bit RISC Architecture up to 16-MHz Clock
– Wide Supply Voltage Range From 3.6 V Down
to 1.8 V (Minimum Supply Voltage is Restricted
by SVS Levels, See the SVS Specifications)
• Optimized Ultra-Low-Power Modes
– Active Mode: Approximately 100 µA/MHz
– Standby (LPM3 With VLO): 0.4 µA (Typical)
– Real-Time Clock (RTC) (LPM3.5): 0.35 µA
(Typical) (1)
– Shutdown (LPM4.5): 0.02 µA (Typical)
• Ultra-Low-Power Ferroelectric RAM (FRAM)
– Up to 128KB of Nonvolatile Memory
– Ultra-Low-Power Writes
– Fast Write at 125 ns per Word (64KB in 4 ms)
– Unified Memory = Program + Data + Storage in
One Single Space
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
• Intelligent Digital Peripherals
– 32-Bit Hardware Multiplier (MPY)
– Three-Channel Internal Direct Memory Access
(DMA)
– RTC With Calendar and Alarm Functions
– Five 16-Bit Timers With up to 7
Capture/Compare Registers Each
– 16-Bit and 32-Bit Cyclic Redundancy Checker
(CRC16, CRC32)
• High-Performance Analog
– Extended Scan Interface (ESI) for Background
Water, Heat, and Gas Volume Measurement
– 16-Channel Analog Comparator
– 12-Bit Analog-to-Digital Converter (ADC) With
Internal Reference and Sample-and-Hold and
up to 16 External Input Channels
– Integrated LCD Driver With Contrast Control for
up to 320 Segments
• Multifunction Input/Output Ports
– All P1 to P10 and PJ Pins Support Capacitive
Touch Capability Without Need for External
Components
(1)
•
•
•
•
•
•
– Accessible Bit-, Byte- and Word-Wise (in Pairs)
– Edge-Selectable Wakeup From LPM on Ports
P1, P2, P3, and P4
– Programmable Pullup and Pulldown on All Ports
Code Security
– True Random Number Seed for Random
Number Generation Algorithm
Enhanced Serial Communication
– eUSCI_A0 and eUSCI_A1 Support:
– UART With Automatic Baud-Rate Detection
– IrDA Encode and Decode
– SPI
– eUSCI_B0 and eUSCI_B1 Support:
– I2C With Multiple-Slave Addressing
– SPI
– Hardware UART and I2C Bootloader (BSL)
Flexible Clock System
– Fixed-Frequency DCO With 10 Selectable
Factory-Trimmed Frequencies
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– 32-kHz Crystals (LFXT)
– High-Frequency Crystals (HFXT)
Development Tools and Software
– Free Professional Development Environments
With EnergyTrace++™ Technology
– Experimenter and Development Kits
Family Members
– Device Comparison Summarizes the Device
Variants and Available Packages Types
For Complete Module Descriptions, See the
MSP430FR58xx, MSP430FR59xx, and
MSP430FR6xx Family User's Guide
RTC is clocked by a 3.7-pF crystal.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
1.2
•
•
•
•
Applications
Water Meters
Heat Meters
Heat Cost Allocators
Portable Medical Meters
1.3
www.ti.com
•
•
Data Logging
See Extended Scan Interface (ESI) Peripheral for
TI Designs
Description
The MSP430™ ultra-low-power (ULP) FRAM platform combines uniquely embedded FRAM and a holistic
ultra-low-power system architecture, allowing innovators to increase performance at lowered energy
budgets. FRAM technology combines the speed, flexibility, and endurance of SRAM with the stability and
reliability of flash at much lower power.
The MSP430 ULP FRAM portfolio consists of a diverse set of devices that feature FRAM, the ULP 16-bit
MSP430 CPU, and intelligent peripherals targeted for various applications. The ULP architecture
showcases seven low-power modes, which are optimized to achieve extended battery life in energychallenged applications.
Device Information (1)
PACKAGE
BODY SIZE (2)
MSP430FR6889IPZ
LQFP (100)
14 mm × 14 mm
MSP430FR6889IPN
LQFP (80)
12 mm × 12 mm
MSP430FR5889IPM
LQFP (64)
10 mm × 10 mm
MSP430FR5889IRGC
VQFN (64)
9 mm × 9 mm
PART NUMBER
(1)
(2)
2
For the most current part, package, and ordering information, see the Package Option Addendum in
Section 9, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
Device Overview
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6889 MSP430FR68891 MSP430FR6888 MSP430FR6887 MSP430FR5889
MSP430FR58891 MSP430FR5888 MSP430FR5887
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
www.ti.com
1.4
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Functional Block Diagram
Figure 1-1 and Figure 1-2 show the functional block diagrams.
P1.x/P2.x P3.x/P4.x P5.x/P6.x P7.x/P8.x
LFXIN,
HFXIN
2x8
LFXOUT,
HFXOUT
2x8
2x8
P9.x/P10.x
PJ.x
2x8
2x8
1x8
Capacitive Touch I/O 0, Capacitive Touch I/O 1
MCLK
Clock
System
Comp_E
ADC12_B
(up to 16
inputs)
(up to 16
std. inputs,
up to 8
diff. inputs)
SMCLK
DMA
Controller
3 Channel
Bus
Control
Logic
I/O Ports
P3, P4
2x8 I/Os
I/O Ports
P1, P2
2x8 I/Os
REF_A
ACLK
Voltage
Reference
I/O Port
P5, P6
2x8 I/Os
I/O Port
P7, P8
2x8 I/Os
I/O Port
P9, P10
1x8 I/Os
I/O Port
PJ
1x8 I/Os
PC
PD
PE
PB
PA
1x16 I/Os 1x16 I/Os 1x16 I/Os 1x16 I/Os 1x16 I/Os
MAB
MDB
CPUXV2
incl. 16
Registers
MPU
IP Encap
EEM
(S: 3 + 1)
EnergyTrace++
Technology
CRC16
FRAM
RAM
Up to
128KB
2KB
Power
Mgmt
LDO
SVS
Brownout
CRC-16CCITT
Watchdog
MPY32
CRC32
CRC-32ISO-3309
TA2
TA3
Timer_A
Timer_A
2 CC
Registers
(int. only)
5 CC
Registers
(int. only)
MDB
JTAG
Interface
MAB
Spy-BiWire
TB0
TA0
TA1
Timer_B
Timer_A
Timer_A
7 CC
Registers
(int./ext.)
3 CC
Registers
(int./ext.)
3 CC
Registers
(int./ext.)
RTC_C
Calendar
and
Counter
Mode
eUSCI_A0
eUSCI_A1
eUSCI_B0
eUSCI_B1
(UART,
IrDA,
SPI)
(I C,
SPI)
2
LCD_C
Extended
Scan
Interface
(up to
320 seg;
static,
2 - 8 mux)
LPM3.5 Domain
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. Functional Block Diagram – MSP430FR688x, MSP430FR688x1
Device Overview
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Product Folder Links: MSP430FR6889 MSP430FR68891 MSP430FR6888 MSP430FR6887 MSP430FR5889
MSP430FR58891 MSP430FR5888 MSP430FR5887
Copyright © 2014–2018, Texas Instruments Incorporated
3
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
www.ti.com
P1.x/P2.x P3.x/P4.x P5.x/P6.x P7.x/P8.x
LFXIN,
HFXIN
2x8
LFXOUT,
HFXOUT
2x8
2x8
P9.x/P10.x
2x8
2x8
PJ.x
1x8
Capacitive Touch I/O 0, Capacitive Touch I/O 1
MCLK
Clock
System
Comp_E
ADC12_B
(up to 16
inputs)
(up to 16
std. inputs,
up to 8
diff. inputs)
SMCLK
DMA
Controller
3 Channel
Bus
Control
Logic
I/O Ports
P3, P4
2x8 I/Os
I/O Ports
P1, P2
2x8 I/Os
REF_A
ACLK
Voltage
Reference
I/O Port
P5, P6
2x8 I/Os
I/O Port
P7, P8
2x8 I/Os
I/O Port
P9, P10
1x8 I/Os
I/O Port
PJ
1x8 I/Os
PC
PD
PE
PB
PA
1x16 I/Os 1x16 I/Os 1x16 I/Os 1x16 I/Os 1x16 I/Os
MAB
MDB
CPUXV2
incl. 16
Registers
MPU
IP Encap
EEM
(S: 3 + 1)
EnergyTrace++
Technology
CRC16
FRAM
RAM
Up to
128KB
2KB
Power
Mgmt
LDO
SVS
Brownout
CRC-16CCITT
Watchdog
MPY32
CRC32
CRC-32ISO-3309
TA2
TA3
Timer_A
Timer_A
2 CC
Registers
(int. only)
5 CC
Registers
(int. only)
MDB
JTAG
Interface
MAB
Spy-BiWire
TB0
TA0
TA1
Timer_B
Timer_A
Timer_A
7 CC
Registers
(int./ext.)
3 CC
Registers
(int./ext.)
3 CC
Registers
(int./ext.)
RTC_C
Calendar
and
Counter
Mode
eUSCI_A0
eUSCI_A1
eUSCI_B0
eUSCI_B1
(UART,
IrDA,
SPI)
(I C,
SPI)
2
Extended
Scan
Interface
LPM3.5 Domain
Copyright © 2016, Texas Instruments Incorporated
Figure 1-2. Functional Block Diagram – MSP430FR588x, MSP430FR588x1
4
Device Overview
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6889 MSP430FR68891 MSP430FR6888 MSP430FR6887 MSP430FR5889
MSP430FR58891 MSP430FR5888 MSP430FR5887
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
www.ti.com
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Table of Contents
1
2
3
Device Overview ......................................... 1
1.2
Applications ........................................... 2
6.1
Overview
1.3
Description ............................................ 2
6.2
CPU
1.4
Functional Block Diagram ............................ 3
6.3
Revision History ......................................... 6
Device Comparison ..................................... 7
6.4
Related Products ..................................... 8
6.6
Terminal Configuration and Functions .............. 9
6.7
4.1
Pin Diagrams ......................................... 9
6.8
4.2
Signal Descriptions .................................. 12
.....................................
4.4
Connection of Unused Pins .........................
Specifications ...........................................
5.1
Absolute Maximum Ratings .........................
5.2
ESD Ratings ........................................
5.3
Recommended Operating Conditions ...............
4.3
5
Timing and Switching Characteristics ............... 39
Features .............................................. 1
3.1
4
5.13
1.1
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
Pin Multiplexing
Active Mode Supply Current Into VCC Excluding
External Current ....................................
Typical Characteristics, Active Mode Supply
Currents .............................................
Low-Power Mode (LPM0, LPM1) Supply Currents
Into VCC Excluding External Current ................
Low-Power Mode (LPM2, LPM3, LPM4) Supply
Currents (Into VCC) Excluding External Current ....
Low-Power Mode With LCD Supply Currents (Into
VCC) Excluding External Current ....................
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current ....................
Typical Characteristics, Low-Power Mode Supply
Currents .............................................
Typical Characteristics, Current Consumption per
Module ..............................................
Thermal Resistance Characteristics
................
6
Detailed Description ................................... 74
6.9
............................................
.................................................
Operating Modes ....................................
Interrupt Vector Table and Signatures ..............
Bootloader (BSL) ....................................
JTAG Operation .....................................
FRAM................................................
RAM .................................................
Tiny RAM ............................................
28
6.10
Memory Protection Unit Including IP Encapsulation 82
6.5
..........................................
74
75
78
81
81
82
82
82
28
6.11
Peripherals
29
6.12
Device Descriptors (TLV) .......................... 130
29
6.13
Memory
29
6.14
Identification........................................ 151
29
7
31
8
31
32
34
35
36
38
Device Connection and Layout Fundamentals .... 152
Peripheral- and Interface-Specific Design
Information ......................................... 156
...................
8.1
Getting Started and Next Steps
8.2
Device Nomenclature .............................. 162
8.3
Tools and Software ................................ 163
8.4
Documentation Support ............................ 165
8.5
Related Links
8.6
Community Resources............................. 167
8.7
Trademarks ........................................ 167
8.8
...................
Export Control Notice ..............................
Glossary............................................
8.10
9
133
Device and Documentation Support .............. 162
8.9
37
83
Applications, Implementation, and Layout ...... 152
7.1
7.2
30
............................................
......................................
Electrostatic Discharge Caution
162
166
167
167
167
Mechanical, Packaging, and Orderable
Information ............................................. 168
Table of Contents
Submit Documentation Feedback
Product Folder Links: MSP430FR6889 MSP430FR68891 MSP430FR6888 MSP430FR6887 MSP430FR5889
MSP430FR58891 MSP430FR5888 MSP430FR5887
Copyright © 2014–2018, Texas Instruments Incorporated
74
5
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from March 10, 2017 to August 29, 2018
•
•
•
•
•
6
Page
Updated Section 3.1, Related Products ........................................................................................... 8
Added note (1) to Table 5-2, SVS................................................................................................. 40
Changed capacitor value from 4.7 µF to 470 nF in Figure 7-5, ADC12_B Grounding and Noise Considerations ... 156
Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of Section 7.2.1.2, Design Requirements .. 157
Updates to text and figure in Section 8.2, Device Nomenclature ........................................................... 162
Revision History
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6889 MSP430FR68891 MSP430FR6888 MSP430FR6887 MSP430FR5889
MSP430FR58891 MSP430FR5888 MSP430FR5887
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
www.ti.com
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
3 Device Comparison
Table 3-1 and Table 3-2 summarize the available family members.
Table 3-1. Device Comparison (With UART BSL) (1)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
DEVICE
FRAM
(KB)
SRAM
(KB)
CLOCK
SYSTEM
128
2
DCO
HFXT
LFXT
3, 3
2, 5
(7)
MSP430FR6889
96
2
DCO
HFXT
LFXT
3, 3
2, 5
(7)
MSP430FR6888
64
2
DCO
HFXT
LFXT
3, 3
2, 5
(7)
MSP430FR6887
128
2
DCO
HFXT
LFXT
3, 3
2, 5
(7)
MSP430FR5889
96
2
DCO
HFXT
LFXT
3, 3
2, 5
(7)
MSP430FR5888
64
2
DCO
HFXT
LFXT
3, 3
2, 5
(7)
MSP430FR5887
eUSCI
Timer_A
Timer_B
(3)
(4)
A (5)
B (6)
7
2
7
(8)
(8)
(8)
(8)
(8)
(8)
AES
ADC12_B
LCD_C
I/O
PACKAGE
2
no
12 ext
16 ext
240 seg
320 seg
63
83
80 PN
100 PZ
2
2
no
12 ext
16 ext
240 seg
320 seg
63
83
80 PN
100 PZ
7
2
2
no
12 ext
16 ext
240 seg
320 seg
63
83
80 PN
100 PZ
7
2
2
no
12 ext
N/A
48
64 PM
64 RGC
7
2
2
no
12 ext
N/A
48
64 PM
64 RGC
7
2
2
no
12 ext
N/A
48
64 PM
64 RGC
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/package.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
eUSCI_B supports I2C with multiple slave addresses and SPI.
Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
Timer_A TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any).
Table 3-2. Device Comparison (With I2C BSL)
DEVICE
FRAM
(KB)
SRAM
(KB)
CLOCK
SYSTEM
128
2
DCO
HFXT
LFXT
3, 3
2, 5
(7)
MSP430FR68891
128
2
DCO
HFXT
LFXT
3, 3
2, 5
(7)
MSP430FR58891
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(2)
eUSCI
Timer_A
Timer_B
(3)
(4)
A (5)
B (6)
7
2
7
2
(8)
(8)
(1) (2)
AES
ADC12_B
LCD_C
I/O
PACKAGE
TYPE
2
no
12 ext
16 ext
240 seg
320 seg
63
83
80 PN
100 PZ
2
no
12 ext
N/A
48
64 PM
64 RGC
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/package.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
eUSCI_B supports I2C with multiple slave addresses and SPI.
Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
Timer_A TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any).
Device Comparison
Submit Documentation Feedback
Product Folder Links: MSP430FR6889 MSP430FR68891 MSP430FR6888 MSP430FR6887 MSP430FR5889
MSP430FR58891 MSP430FR5888 MSP430FR5887
Copyright © 2014–2018, Texas Instruments Incorporated
7
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
3.1
www.ti.com
Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers High-performance, low-power solutions to enable the autonomous
future
Products for MSP430 ultra-low-power sensing and measurement microcontrollers
One ecosystem. Endless possibilities.
One
platform.
Products for MSP430 ultrasonic and performance sensing microcontrollers Ultra-low-power singlechip MCUs with integrated sensing peripherals
Companion products for MSP430FR6889 Review products that are frequently purchased or used with
this product.
Reference designs for MSP430FR6889 The TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
8
Device Comparison
Copyright © 2014–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FR6889 MSP430FR68891 MSP430FR6888 MSP430FR6887 MSP430FR5889
MSP430FR58891 MSP430FR5888 MSP430FR5887
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
www.ti.com
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
4 Terminal Configuration and Functions
4.1
Pin Diagrams
ESIDVSS
ESICI
ESICOM
AVCC1
AVSS3
PJ.7/HFXOUT
PJ.6/HFXIN
AVSS1
PJ.4/LFXIN
PJ.5/LFXOUT
AVSS2
P5.4/UCA1SIMO/UCA1TXD/S12
P5.5/UCA1SOMI/UCA1RXD/S11
P5.6/UCA1CLK/S10
P5.7/UCA1STE/TB0CLK/S9
P4.4/UCB1STE/TA1CLK/S8
P4.5/UCB1CLK/TA1.0/S7
P4.6/UCB1SIMO/UCB1SDA/TA1.1/S6
P4.7/UCB1SOMI/UCB1SCL/TA1.2/S5
P10.0/SMCLK/S4
P4.0/UCB1SIMO/UCB1SDA/MCLK/S3
P4.1/UCB1SOMI/UCB1SCL/ACLK/S2
DVSS3
DVCC3
P4.2/UCA0SIMO/UCA0TXD/UCB1CLK
Figure 4-1 shows the pinout of the 100-pin PZ package for the MSP430FR688x and MSP430FR688x1
MCUs.
9
67
P9.0/ESICH0/ESITEST0/A8/C8
P6.3/COM0
10
66
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P6.4/TB0.0/COM1
11
65
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P6.5/TB0.1/COM2
12
64
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P6.6/TB0.2/COM3
13
63
P1.3/TA1.2/ESITEST4/A3/C3
P2.4/TB0.3/COM4/S43
14
62
P8.7/A4/C4
P2.5/TB0.4/COM5/S42
15
61
P8.6/A5/C5
P2.6/TB0.5/ESIC1OUT/COM6/S41
16
60
P8.5/A6/C6
P2.7/TB0.6/ESIC2OUT/COM7/S40
17
59
P8.4/A7/C7
P10.2/TA1.0/SMCLK/S39
18
58
DVCC2
P5.0/TA1.1/MCLK/S38
19
57
DVSS2
P5.1/TA1.2/S37
20
56
P7.4/SMCLK/S13
P5.2/TA1.0/TA1CLK/ACLK/S36
21
55
P7.3/TA0.2/S14
P5.3/UCB1STE/S35
22
54
P7.2/TA0.1/S15
P3.0/UCB1CLK/S34
23
53
P7.1/TA0.0/ACLK/S16
P3.1/UCB1SIMO/UCB1SDA/S33
24
52
P7.0/TA0CLK/S17
P3.2/UCB1SOMI/UCB1SCL/S32
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK
P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0
DVSS1
P2.2/UCA0CLK/TB0.4/RTCCLK
P9.1/ESICH1/ESITEST1/A9/C9
P6.2/COUT/R03
P2.3/UCA0STE/TB0OUTH
68
P8.3/MCLK/S18
8
P8.2/S19
P9.2/ESICH2/ESITEST2/A10/C10
P6.1/R13/LCDREF
P8.1/DMAE0/S20
69
P8.0/RTCCLK/S21
7
P3.7/UCA1STE/TB0.3/S22
P9.3/ESICH3/ESITEST3/A11/C11
P6.0/R23
P3.6/UCA1CLK/TB0.2/S23
70
P3.5/UCA1SOMI/UCA1RXD/TB0.1/S24
6
P3.4/UCA1SIMO/UCA1TXD/TB0.0/S25
P9.4/ESICI0/A12/C12
R33/LCDCAP
P3.3/TA1.1/TB0CLK/S26
71
P7.7/TA1.2/TB0OUTH/S27
5
P10.1/TA0.0/S28
P9.5/ESICI1/A13/C13
P1.7/UCB0SOMI/UCB0SCL/TA0.2
P7.6/TA0.1/S29
72
P7.5/TA0.2/S30
4
P6.7/TA0CLK/S31
P9.6/ESICI2/A14/C14
P1.6/UCB0SIMO/UCB0SDA/TA0.1
PJ.3/TCK/COUT/SRCPUOFF
73
PJ.2/TMS/ACLK/SROSCOFF
3
PJ.1/TDI/TCLK/MCLK/SRSCG0
P9.7/ESICI3/A15/C15
P1.5/UCB0STE/UCA0CLK/TA0.0/S0
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1
74
RST/NMI/SBWTDIO
2
TEST/SBWTCK
ESIDVCC
P1.4/UCB0CLK/UCA0STE/TA1.0/S1
DVCC1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
P4.3/UCA0SOMI/UCA0RXD/UCB1STE
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
NOTE: On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-1. 100-Pin PZ Package (Top View) – MSP430FR688x and MSP430FR688x1
Terminal Configuration and Functions
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9
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
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ESIDVSS
ESICI
ESICOM
AVCC1
AVSS3
PJ.7/HFXOUT
PJ.6/HFXIN
AVSS1
PJ.4/LFXIN
PJ.5/LFXOUT
AVSS2
P4.4/UCB1STE/TA1CLK/S9
P4.5/UCB1CLK/TA1.0/S8
P4.6/UCB1SIMO/UCB1SDA/TA1.1/S7
P4.7/UCB1SOMI/UCB1SCL/TA1.2/S6
P4.0/UCB1SIMO/UCB1SDA/MCLK/S5
P4.1/UCB1SOMI/UCB1SCL/ACLK/S4
DVSS3
DVCC3
P4.2/UCA0SIMO/UCA0TXD/UCB1CLK
Figure 4-2 shows the pinout of the 80-pin PN package for the MSP430FR688x and MSP430FR688x1
MCUs.
54
P9.2/ESICH2/ESITEST2/A10/C10
P6.1/R13/LCDREF
8
53
P9.1/ESICH1/ESITEST1/A9/C9
P6.2/COUT/R03
9
52
P9.0/ESICH0/ESITEST0/A8/C8
P6.3/COM0
10
51
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P6.4/TB0.0/COM1/S36
11
50
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P6.5/TB0.1/COM2/S35
12
49
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P6.6/TB0.2/COM3/S34
13
48
P1.3/TA1.2/ESITEST4/A3/C3
P2.4/TB0.3/COM4/S33
14
47
DVCC2
P2.5/TB0.4/COM5/S32
15
46
DVSS2
P2.6/TB0.5/ESIC1OUT/COM6/S31
16
45
P7.3/TA0.2/S10
P2.7/TB0.6/ESIC2OUT/COM7/S30
17
44
P7.2/TA0.1/S11
P3.0/UCB1CLK/S29
18
43
P7.1/TA0.0/ACLK/S12
P3.1/UCB1SIMO/UCB1SDA/S28
19
42
P7.0/TA0CLK/S13
P3.2/UCB1SOMI/UCB1SCL/S27
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S14
P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0/S15
DVSS1
P2.2/UCA0CLK/TB0.4/RTCCLK/S16
7
P2.3/UCA0STE/TB0OUTH/S17
P9.3/ESICH3/ESITEST3/A11/C11
P6.0/R23
P3.7/UCA1STE/TB0.3/S18
55
P3.6/UCA1CLK/TB0.2/S19
6
P3.5/UCA1SOMI/UCA1RXD/TB0.1/S20
P9.4/ESICI0/A12/C12
R33/LCDCAP
P3.4/UCA1SIMO/UCA1TXD/TB0.0/S21
56
P3.3/TA1.1/TB0CLK/S22
5
P7.7/TA1.2/TB0OUTH/S23
P9.5/ESICI1/A13/C13
P1.7/UCB0SOMI/UCB0SCL/TA0.2/S0
P7.6/TA0.1/S24
57
P7.5/TA0.2/S25
4
P6.7/TA0CLK/S26
P9.6/ESICI2/A14/C14
P1.6/UCB0SIMO/UCB0SDA/TA0.1/S1
PJ.3/TCK/COUT/SRCPUOFF
58
PJ.2/TMS/ACLK/SROSCOFF
3
PJ.1/TDI/TCLK/MCLK/SRSCG0
P9.7/ESICI3/A15/C15
P1.5/UCB0STE/UCA0CLK/TA0.0/S2
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1
59
RST/NMI/SBWTDIO
2
TEST/SBWTCK
ESIDVCC
P1.4/UCB0CLK/UCA0STE/TA1.0/S3
DVCC1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
P4.3/UCA0SOMI/UCA0RXD/UCB1STE
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
NOTE: On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-2. 80-Pin PN Package (Top View) – MSP430FR688x and MSP430FR688x1
10
Terminal Configuration and Functions
Copyright © 2014–2018, Texas Instruments Incorporated
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MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
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SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
ESIDVSS
ESICI
ESICOM
AVCC1
AVSS3
PJ.7/HFXOUT
PJ.6/HFXIN
AVSS1
PJ.4/LFXIN
PJ.5/LFXOUT
AVSS2
P4.0/UCB1SIMO/UCB1SDA/MCLK
P4.1/UCB1SOMI/UCB1SCL/ACLK
DVSS3
DVCC3
P4.2/UCA0SIMO/UCA0TXD/UCB1CLK
Figure 4-3 shows the pinout of the 64-pin PM and RGC packages for the MSP430FR588x and
MSP430FR588x1 MCUs.
6
43
P9.3/ESICH3/ESITEST3/A11/C11
P2.5/TB0.4
7
42
P9.2/ESICH2/ESITEST2/A10/C10
P2.6/TB0.5/ESIC1OUT
8
41
P9.1/ESICH1/ESITEST1/A9/C9
P2.7/TB0.6/ESIC2OUT
9
40
P9.0/ESICH0/ESITEST0/A8/C8
P5.0/TA1.1/MCLK
10
39
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P5.1/TA1.2
11
38
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P5.2/TA1.0/TA1CLK/ACLK
12
37
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P5.3/UCB1STE
13
36
P1.3/TA1.2/ESITEST4/A3/C3
P3.0/UCB1CLK
14
35
DVCC2
P3.1/UCB1SIMO/UCB1SDA
15
34
DVSS2
P3.2/UCB1SOMI/UCB1SCL
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK
P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0
DVSS1
P2.2/UCA0CLK/TB0.4/RTCCLK
P9.4/ESICI0/A12/C12
P2.4/TB0.3
P2.3/UCA0STE/TB0OUTH
44
P3.7/UCA1STE/TB0.3
5
P3.6/UCA1CLK/TB0.2
P9.5/ESICI1/A13/C13
P1.7/UCB0SOMI/UCB0SCL/TA0.2
P3.5/UCA1SOMI/UCA1RXD/TB0.1
45
P3.4/UCA1SIMO/UCA1TXD/TB0.0
4
P3.3/TA1.1/TB0CLK
P9.6/ESICI2/A14/C14
P1.6/UCB0SIMO/UCB0SDA/TA0.1
PJ.3/TCK/COUT/SRCPUOFF
46
PJ.2/TMS/ACLK/SROSCOFF
3
PJ.1/TDI/TCLK/MCLK/SRSCG0
P9.7/ESICI3/A15/C15
P1.5/UCB0STE/UCA0CLK/TA0.0
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1
47
RST/NMI/SBWTDIO
2
TEST/SBWTCK
ESIDVCC
P1.4/UCB0CLK/UCA0STE/TA1.0
DVCC1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
P4.3/UCA0SOMI/UCA0RXD/UCB1STE
NOTE: TI recommends connecting the RGC package pad to VSS.
NOTE: On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
NOTE: On devices with I2C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-3. 64-Pin PM or RGC Package (Top View) – MSP430FR588x and MSP430FR588x1
Terminal Configuration and Functions
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Product Folder Links: MSP430FR6889 MSP430FR68891 MSP430FR6888 MSP430FR6887 MSP430FR5889
MSP430FR58891 MSP430FR5888 MSP430FR5887
Copyright © 2014–2018, Texas Instruments Incorporated
11
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
4.2
www.ti.com
Signal Descriptions
Table 4-1 and Table 4-2 describe the device signals.
Table 4-1. Signal Descriptions – MSP430FR688x and MSP430FR688x1
TERMINAL
NAME
PZ
NO.
PN
Seg.
NO.
DESCRIPTION
Seg.
General-purpose digital I/O
P4.3/UCA0SOMI/UCA0RXD/
UCB1STE
USCI_A0: Slave out, master in (SPI mode)
1
1
USCI_A0: Receive data (UART mode)
USCI_B1: Slave transmit enable (SPI mode)
General-purpose digital I/O
P1.4/UCB0CLK/UCA0STE/
TA1.0/Sx
USCI_B0: Clock signal input (SPI slave mode), Clock signal output (SPI
master mode)
2
S1
2
S3
USCI_A0: Slave transmit enable (SPI mode)
Timer_A TA1 CCR0 capture: CCI0A input, compare: Out0 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_B0: Slave transmit enable (SPI mode)
P1.5/UCB0STE/
UCA0CLK/TA0.0/Sx
3
S0
3
S2
USCI_A0: Clock signal input (SPI slave mode), Clock signal output (SPI
master mode)
Timer_A TA0 CCR0 capture: CCI0A input, compare: Out0 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_B0: Slave in, master out (SPI mode)
P1.6/UCB0SIMO/UCB0SDA/
TA0.1/Sx
USCI_B0: I2C data (I2C mode)
4
4
S1
BSL data (I2C BSL)
Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_B0: Slave out, master in (SPI mode)
P1.7/UCB0SOMI/UCB0SCL/
TA0.2/Sx
USCI_B0: I2C clock (I2C mode)
5
5
S0
BSL clock (I2C BSL)
Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output
LCD segment output (segment number is package specific)
Input/output port of most positive analog LCD voltage (V1)
R33/LCDCAP
6
6
LCD capacitor connection
General-purpose digital I/O
P6.0/R23
7
7
Input/output port of second most positive analog LCD voltage (V2)
General-purpose digital I/O
P6.1/R13/LCDREF
8
8
Input/output port of third most positive analog LCD voltage (V3 or V4)
External reference voltage input for regulated LCD voltage
General-purpose digital I/O
P6.2/COUT/R03
9
9
Comparator output
Input/output port of lowest analog LCD voltage (V5)
12
Terminal Configuration and Functions
Copyright © 2014–2018, Texas Instruments Incorporated
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MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
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SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Table 4-1. Signal Descriptions – MSP430FR688x and MSP430FR688x1 (continued)
TERMINAL
NAME
PZ
NO.
PN
Seg.
NO.
DESCRIPTION
Seg.
General-purpose digital I/O
P6.3/COM0
10
10
LCD common output COM0 for LCD backplane
General-purpose digital I/O
Timer_B TB0 CCR0 capture: CCI0B input, compare: Out0 output
P6.4/TB0.0/COM1/Sx
11
11
S36
LCD common output COM1 for LCD backplane
LCD segment output (segment number is package specific)
General-purpose digital I/O
Timer_B TB0 CCR1 capture: CCI1A input, compare: Out1 output
P6.5/TB0.1/COM2/Sx
12
12
S35
LCD common output COM2 for LCD backplane
LCD segment output (segment number is package specific)
General-purpose digital I/O
Timer_B TB0 CCR2 capture: CCI2A input, compare: Out2 output
P6.6/TB0.2/COM3/Sx
13
13
S34
LCD common output COM3 for LCD backplane
LCD segment output (segment number is package specific)
General-purpose digital I/O
Timer_B TB0 CCR3 capture: CCI3A input, compare: Out3 output
P2.4/TB0.3/COM4/Sx
14
S43
14
S33
LCD common output COM4 for LCD backplane
LCD segment output (segment number is package specific)
General-purpose digital I/O
Timer_B TB0 CCR4 capture: CCI4A input, compare: Out4 output
P2.5/TB0.4/COM5/Sx
15
S42
15
S32
LCD common output COM5 for LCD backplane
LCD segment output (segment number is package specific)
General-purpose digital I/O
Timer_B TB0 CCR5 capture: CCI5A input, compare: Out5 output
P2.6/TB0.5/ESIC1OUT/
COM6/Sx
16
S41
16
S31
ESI Comparator 1 output
LCD common output COM6 for LCD backplane
LCD segment output (segment number is package specific)
General-purpose digital I/O
Timer_B TB0 CCR6 capture: CCI6A input, compare: Out6 output
P2.7/TB0.6/ESIC2OUT/
COM7/Sx
17
S40
17
S30
ESI comparator 2 output
LCD common output COM7 for LCD backplane
LCD segment output (segment number is package specific)
General-purpose digital I/O
Timer_A TA1 CCR0 capture: CCI0B input, compare: Out0 output
P10.2/TA1.0/SMCLK/Sx
18
S39
SMCLK output
LCD segment output (segment number is package specific)
General-purpose digital I/O
Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output
P5.0/TA1.1/MCLK/Sx
19
S38
MCLK output
LCD segment output (segment number is package specific)
Terminal Configuration and Functions
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Copyright © 2014–2018, Texas Instruments Incorporated
13
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
www.ti.com
Table 4-1. Signal Descriptions – MSP430FR688x and MSP430FR688x1 (continued)
TERMINAL
NAME
PZ
NO.
PN
Seg.
NO.
DESCRIPTION
Seg.
General-purpose digital I/O
P5.1/TA1.2/Sx
20
S37
Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
Timer_A TA1 CCR0 capture: CCI0B input, compare: Out0 output
P5.2/TA1.0/TA1CLK/ACLK/Sx
21
S36
Timer_A TA1 clock signal TA0CLK input
ACLK output
LCD segment output (segment number is package specific)
General-purpose digital I/O
P5.3/UCB1STE/Sx
22
S35
USCI_B1: Slave transmit enable (SPI mode)
LCD segment output (segment number is package specific)
General-purpose digital I/O
P3.0/UCB1CLK/Sx
23
S34
18
S29
USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI
master mode)
LCD segment output (segment number is package specific)
General-purpose digital I/O
P3.1/UCB1SIMO/UCB1SDA/
Sx
USCI_B1: Slave in, master out (SPI mode)
24
S33
19
S28
USCI_B1: I2C data (I2C mode)
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_B1: Slave out, master in (SPI mode)
P3.2/UCB1SOMI/UCB1SCL/
Sx
25
DVSS1
26
21
Digital ground supply
DVCC1
27
22
Digital power supply
TEST/SBWTCK
28
23
S32
20
S27
USCI_B1: I2C clock (I2C mode)
LCD segment output (segment number is package specific)
Test mode pin - select digital I/O on JTAG pins
Spy-Bi-Wire input clock
Reset input, active low
RST/NMI/SBWTDIO
29
24
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
General-purpose digital I/O
Test data output port
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1
30
25
Switch all PWM outputs high impedance input - Timer_B TB0
SMCLK output
Low-power debug: CPU Status register SCG1
General-purpose digital I/O
PJ.1/TDI/TCLK/MCLK/
SRSCG0
Test data input or test clock input
31
26
MCLK output
Low-power debug: CPU Status register SCG0
14
Terminal Configuration and Functions
Copyright © 2014–2018, Texas Instruments Incorporated
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MSP430FR58891 MSP430FR5888 MSP430FR5887
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
www.ti.com
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Table 4-1. Signal Descriptions – MSP430FR688x and MSP430FR688x1 (continued)
TERMINAL
NAME
PZ
NO.
PN
Seg.
NO.
DESCRIPTION
Seg.
General-purpose digital I/O
Test mode select
PJ.2/TMS/ACLK/SROSCOFF
32
27
ACLK output
Low-power debug: CPU Status register OSCOFF
General-purpose digital I/O
Test clock
PJ.3/TCK/COUT/SRCPUOFF
33
28
Comparator output
Low-power debug: CPU Status register CPUOFF
General-purpose digital I/O
P6.7/TA0CLK/Sx
34
S31
29
S26
Timer_A TA0 clock signal TA0CLK input
LCD segment output (segment number is package specific)
General-purpose digital I/O
P7.5/TA0.2/Sx
35
S30
30
S25
Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
P7.6/TA0.1/Sx
36
S29
31
S24
Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
P10.1/TA0.0/Sx
37
S28
Timer_A TA0 CCR0 capture: CCI0B input, compare: Out0 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output
P7.7/TA1.2/TB0OUTH/Sx
38
S27
32
S23
Switch all PWM outputs high impedance input - Timer_B TB0
LCD segment output (segment number is package specific)
General-purpose digital I/O
Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output
P3.3/TA1.1/TB0CLK/Sx
39
S26
33
S22
Timer_B TB0 clock signal TB0CLK input
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_A1: Slave in, master out (SPI mode)
P3.4/UCA1SIMO/UCA1TXD/
TB0.0/Sx
40
S25
34
S21
USCI_A1: Transmit data (UART mode)
Timer_B TB0 CCR0 capture: CCI0A input, compare: Out0 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_A1: Slave out, master in (SPI mode)
P3.5/UCA1SOMI/UCA1RXD/
TB0.1/Sx
41
S24
35
S20
USCI_A1: Receive data (UART mode)
Timer_B TB0 CCR1 capture: CCI1A input, compare: Out1 output
LCD segment output (segment number is package specific)
Terminal Configuration and Functions
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15
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
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Table 4-1. Signal Descriptions – MSP430FR688x and MSP430FR688x1 (continued)
TERMINAL
NAME
PZ
NO.
PN
Seg.
NO.
DESCRIPTION
Seg.
General-purpose digital I/O
P3.6/UCA1CLK/TB0.2/Sx
42
S23
36
S19
USCI_A1: Clock signal input (SPI slave mode), Clock signal output (SPI
master mode)
Timer_B TB0 CCR2 capture: CCI2A input, compare: Out2 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_A1: Slave transmit enable (SPI mode)
P3.7/UCA1STE/TB0.3/Sx
43
S22
37
S18
Timer_B TB0 CCR3 capture: CCI3B input, compare: Out3 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
P8.0/RTCCLK/Sx
44
S21
RTC clock output for calibration
LCD segment output (segment number is package specific)
General-purpose digital I/O
P8.1/DMAE0/Sx
45
S20
DMA external trigger input
LCD segment output (segment number is package specific)
General-purpose digital I/O
P8.2/Sx
46
S19
LCD segment output (segment number is package specific)
General-purpose digital I/O
P8.3/MCLK/Sx
47
S18
MCLK output
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_A0: Slave transmit enable (SPI mode)
P2.3/UCA0STE/TB0OUTH/Sx
48
38
S17
Switch all PWM outputs high impedance input - Timer_B TB0
LCD segment output (segment number is package specific)
General-purpose digital I/O
P2.2/UCA0CLK/TB0.4/
RTCCLK/Sx
USCI_A0: Clock signal input (SPI slave mode), Clock signal output (SPI
master mode)
49
39
S16
Timer_B TB0 CCR4 capture: CCI4B input, compare: Out4 output
RTC clock output for calibration
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_A0: Slave out, master in (SPI mode)
USCI_A0: Receive data (UART mode)
P2.1/UCA0SOMI/UCA0RXD/
TB0.5/DMAE0/Sx
50
40
S15
BSL receive (UART BSL)
Timer_B TB0 CCR5 capture: CCI5B input, compare: Out5 output
DMA external trigger input
LCD segment output (segment number is package specific)
16
Terminal Configuration and Functions
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MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
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SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Table 4-1. Signal Descriptions – MSP430FR688x and MSP430FR688x1 (continued)
TERMINAL
NAME
PZ
NO.
PN
Seg.
NO.
DESCRIPTION
Seg.
General-purpose digital I/O
USCI_A0: Slave in, master out (SPI mode)
USCI_A0: Transmit data (UART mode)
P2.0/UCA0SIMO/UCA0TXD/
TB0.6/TB0CLK/Sx
51
41
S14
BSL transmit (UART BSL)
Timer_B TB0 CCR6 capture: CCI6B input, compare: Out6 output
Timer_B TB0 clock signal TB0CLK input
LCD segment output (segment number is package specific)
General-purpose digital I/O
P7.0/TA0CLK/Sx
52
S17
42
S13
Timer_A TA0 clock signal TA0CLK input
LCD segment output (segment number is package specific)
General-purpose digital I/O
Timer_A TA0 CCR0 capture: CCI0B input, compare: Out0 output
P7.1/TA0.0/ACLK/Sx
53
S16
43
S12
ACLK output
LCD segment output (segment number is package specific)
General-purpose digital I/O
P7.2/TA0.1/Sx
54
S15
44
S11
Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
P7.3/TA0.2/Sx
55
S14
45
S10
Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
P7.4/SMCLK/Sx
56
S13
SMCLK output
LCD segment output (segment number is package specific)
DVSS2
57
46
Digital ground supply
DVCC2
58
47
Digital power supply
General-purpose digital I/O
P8.4/A7/C7
59
Analog input A7
Comparator input C7
General-purpose digital I/O
P8.5/A6/C6
60
Analog input A6
Comparator input C6
General-purpose digital I/O
P8.6/A5/C5
61
Analog input A5
Comparator input C5
General-purpose digital I/O
P8.7/A4/C4
62
Analog input A4
Comparator input C4
Terminal Configuration and Functions
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Copyright © 2014–2018, Texas Instruments Incorporated
17
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
www.ti.com
Table 4-1. Signal Descriptions – MSP430FR688x and MSP430FR688x1 (continued)
TERMINAL
NAME
PZ
NO.
PN
Seg.
NO.
DESCRIPTION
Seg.
General-purpose digital I/O
ESI test signal 4
P1.3/ESITEST4/TA1.2/A3/C3
63
48
Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output
Analog input A3
Comparator input C3
General-purpose digital I/O
Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output
P1.2/TA1.1/TA0CLK/
COUT/A2/C2
Timer_A TA0 clock signal TA0CLK input
64
49
Comparator output
Analog input A2
Comparator input C2
General-purpose digital I/O
Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output
Timer_A TA1 clock signal TA1CLK input
P1.1/TA0.2/TA1CLK/
COUT/A1/C1/VREF+/VeREF+
Comparator output
65
50
Analog input A1
Comparator input C1
Output of positive reference voltage
Input for an external positive reference voltage to the ADC
General-purpose digital I/O
Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output
DMA external trigger input
P1.0/TA0.1/DMAE0/
RTCCLK/A0/C0/ VREF/VeREF-
RTC clock output for calibration
66
51
Analog input A0
Comparator input C0
Output of negative reference voltage
Input for an external negative reference voltage to the ADC
General-purpose digital I/O
ESI channel 0 sensor excitation output and signal input
P9.0/ESICH0/ESITEST0/
A8/C8
67
52
ESI test signal 0
Analog input A8
Comparator input C8
General-purpose digital I/O
ESI channel 1 sensor excitation output and signal input
P9.1/ESICH1/ESITEST1/
A9/C9
68
53
ESI test signal 1
Analog input A9
Comparator input C9
General-purpose digital I/O
P9.2/ESICH2/ESITEST2/
A10/C10
ESI channel 2 sensor excitation output and signal input
69
54
ESI test signal 2
Analog input A10; comparator input C10
18
Terminal Configuration and Functions
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MSP430FR58891 MSP430FR5888 MSP430FR5887
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MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
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SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Table 4-1. Signal Descriptions – MSP430FR688x and MSP430FR688x1 (continued)
TERMINAL
NAME
PZ
NO.
PN
Seg.
NO.
DESCRIPTION
Seg.
General-purpose digital I/O
ESI channel 3 sensor excitation output and signal input
P9.3/ESICH3/ESITEST3/
A11/C11
70
55
ESI test signal 3
Analog input A11
Comparator input C11
General-purpose digital I/O
ESI channel 0 signal input to comparator
P9.4/ESICI0/A12/C12
71
56
Analog input A12
Comparator input C12
General-purpose digital I/O
ESI channel 1 signal input to comparator
P9.5/ESICI1/A13/C13
72
57
Analog input A13
Comparator input C13
General-purpose digital I/O
ESI channel 2 signal input to comparator
P9.6/ESICI2/A14/C14
73
58
Analog input A14
Comparator input C14
General-purpose digital I/O
ESI channel 3 signal input to comparator
P9.7/ESICI3/A15/C15
74
59
Analog input A15
Comparator input C15
ESIDVCC
75
60
ESI power supply
ESIDVSS
76
61
ESI ground supply
ESICI
77
62
ESI Scan IF input to Comparator
ESICOM
78
63
ESI Common termination for Scan IF sensors
AVCC1
79
64
Analog power supply
AVSS3
80
65
Analog ground supply
PJ.7/HFXOUT
81
66
General-purpose digital I/O
Output terminal of crystal oscillator XT2
General-purpose digital I/O
PJ.6/HFXIN
82
67
AVSS1
83
68
PJ.4/LFXIN
84
69
Input terminal for crystal oscillator XT2
Analog ground supply
General-purpose digital I/O
Input terminal for crystal oscillator XT1
General-purpose digital I/O
PJ.5/LFXOUT
85
70
AVSS2
86
71
Output terminal of crystal oscillator XT1
Analog ground supply
General-purpose digital I/O
USCI_A1: Slave in, master out (SPI mode)
P5.4/UCA1SIMO/UCA1TXD/Sx
87
S12
USCI_A1: Transmit data (UART mode)
LCD segment output (segment number is package specific)
Terminal Configuration and Functions
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19
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
www.ti.com
Table 4-1. Signal Descriptions – MSP430FR688x and MSP430FR688x1 (continued)
TERMINAL
NAME
PZ
NO.
PN
Seg.
NO.
DESCRIPTION
Seg.
General-purpose digital I/O
P5.5/UCA1SOMI/UCA1RXD/
Sx
USCI_A1: Slave out, master in (SPI mode)
88
S11
USCI_A1: Receive data (UART mode)
LCD segment output (segment number is package specific)
General-purpose digital I/O
P5.6/UCA1CLK/Sx
89
USCI_A1: Clock signal input (SPI slave mode), Clock signal output (SPI
master mode)
S10
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_A1: Slave transmit enable (SPI mode)
P5.7/UCA1STE/TB0CLK/Sx
90
S9
Timer_B TB0 clock signal TB0CLK input
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_B1: Slave transmit enable (SPI mode)
P4.4/UCB1STE/TA1CLK/Sx
91
S8
72
S9
Timer_A TA1 clock signal TA1CLK input
LCD segment output (segment number is package specific)
General-purpose digital I/O
P4.5/UCB1CLK/TA1.0/Sx
92
S7
73
S8
USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI
master mode)
Timer_A TA1 CCR0 capture: CCI0A input, compare: Out0 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_B1: Slave in, master out (SPI mode)
P4.6/UCB1SIMO/UCB1SDA/
TA1.1/Sx
93
S6
74
S7
USCI_B1: I2C data (I2C mode)
Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_B1: Slave out, master in (SPI mode)
P4.7/UCB1SOMI/UCB1SCL/
TA1.2/Sx
94
S5
75
S6
USCI_B1: I2C clock (I2C mode)
Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
P10.0/SMCLK/Sx
95
S4
SMCLK output
LCD segment output (segment number is package specific)
General-purpose digital I/O
USCI_B1: Slave in, master out (SPI mode)
P4.0/UCB1SIMO/UCB1SDA/
MCLK/Sx
96
S3
76
S5
USCI_B1: I2C data (I2C mode)
MCLK output
LCD segment output (segment number is package specific)
20
Terminal Configuration and Functions
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MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
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SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Table 4-1. Signal Descriptions – MSP430FR688x and MSP430FR688x1 (continued)
TERMINAL
NAME
PZ
NO.
PN
Seg.
NO.
DESCRIPTION
Seg.
General-purpose digital I/O
USCI_B1: Slave out, master in (SPI mode)
P4.1/UCB1SOMI/UCB1SCL/
ACLK/Sx
97
S2
77
S4
USCI_B1: I2C clock (I2C mode)
ACLK output
LCD segment output (segment number is package specific)
DVSS3
98
78
Digital ground supply
DVCC3
99
79
Digital power supply
General-purpose digital I/O
USCI_A0: Slave in, master out (SPI mode)
P4.2/UCA0SIMO/UCA0TXD/
UCB1CLK
100
80
USCI_A0: Transmit data (UART mode)
USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI
master mode)
Terminal Configuration and Functions
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Copyright © 2014–2018, Texas Instruments Incorporated
21
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
www.ti.com
Table 4-2. Signal Descriptions – MSP430FR588x and MSP430FR588x1
TERMINAL
NAME
PM
RGC
DESCRIPTION
NO.
General-purpose digital I/O
P4.3/UCA0SOMI/
UCA0RXD/UCB1STE
1
USCI_A0: Slave out, master in (SPI mode), Receive data (UART mode)
USCI_B1: Slave transmit enable (SPI mode)
General-purpose digital I/O
USCI_B0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
P1.4/UCB0CLK/ UCA0STE/TA1.0
2
USCI_A0: Slave transmit enable (SPI mode)
Timer_A TA1 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O
USCI_B0: Slave transmit enable (SPI mode)
P1.5/UCB0STE/ UCA0CLK/TA0.0
3
USCI_A0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
Timer_A TA0 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O
USCI_B0: Slave in, master out (SPI mode), I2C data (I2C mode)
P1.6/UCB0SIMO/ UCB0SDA/TA0.1
4
BSL Data (I2C BSL)
Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O
USCI_B0: Slave out, master in (SPI mode), I2C clock (I2C mode)
P1.7/UCB0SOMI/ UCB0SCL/TA0.2
5
BSL Clock (I2C BSL)
Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O
P2.4/TB0.3
6
Timer_B TB0 CCR3 capture: CCI3A input, compare: Out3 output
General-purpose digital I/O
P2.5/TB0.4
7
Timer_B TB0 CCR4 capture: CCI4A input, compare: Out4 output
General-purpose digital I/O
P2.6/TB0.5/ESIC1OUT
8
Timer_B TB0 CCR5 capture: CCI5A input, compare: Out5 output
ESI Comparator 1 output
General-purpose digital I/O
P2.7/TB0.6/ESIC2OUT
9
Timer_B TB0 CCR6 capture: CCI6A input, compare: Out6 output
ESI Comparator 2 output
General-purpose digital I/O
P5.0/TA1.1/MCLK
10
Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output
MCLK output
General-purpose digital I/O
P5.1/TA1.2
11
Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O
Timer_A TA1 CCR0 capture: CCI0B input, compare: Out0 output
P5.2/TA1.0/TA1CLK/ACLK
12
Timer_A TA1 clock signal TA0CLK input
ACLK output
General-purpose digital I/O
P5.3/UCB1STE
13
USCI_B1: Slave transmit enable (SPI mode)
22
Terminal Configuration and Functions
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MSP430FR58891 MSP430FR5888 MSP430FR5887
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
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SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Table 4-2. Signal Descriptions – MSP430FR588x and MSP430FR588x1 (continued)
TERMINAL
NAME
PM
RGC
DESCRIPTION
NO.
General-purpose digital I/O
P3.0/UCB1CLK
14
USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
General-purpose digital I/O
P3.1/UCB1SIMO/UCB1SDA
15
USCI_B1: Slave in, master out (SPI mode)
USCI_B1: I2C data (I2C mode)
General-purpose digital I/O
P3.2/UCB1SOMI/UCB1SCL
16
USCI_B1: Slave out, master in (SPI mode)
USCI_B1: I2C clock (I2C mode)
DVSS1
17
Digital ground supply
DVCC1
18
Digital power supply
TEST/SBWTCK
19
Test mode pin - select digital I/O on JTAG pins
Spy-Bi-Wire input clock
Reset input, active low
RST/NMI/SBWTDIO
20
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
General-purpose digital I/O
Test data output port
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1
21
Switch all PWM outputs high impedance input - Timer_B TB0
SMCLK output
Low-power debug: CPU Status register SCG1
General-purpose digital I/O
Test data input or test clock input
PJ.1/TDI/TCLK/MCLK/SRSCG0
22
MCLK output
Low-power debug: CPU Status register SCG0
General-purpose digital I/O
Test mode select
PJ.2/TMS/ACLK/SROSCOFF
23
ACLK output
Low-power debug: CPU Status register OSCOFF
General-purpose digital I/O
Test clock
PJ.3/TCK/COUT/SRCPUOFF
24
Comparator output
Low-power debug: CPU Status register CPUOFF
General-purpose digital I/O
P3.3/TA1.1/TB0CLK
25
Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output
Timer_B TB0 clock signal TB0CLK input
General-purpose digital I/O
USCI_A1: Slave in, master out (SPI mode)
P3.4/UCA1SIMO/UCA1TXD/TB0.0
26
USCI_A1: Transmit data (UART mode)
Timer_B TB0 CCR0 capture: CCI0A input, compare: Out0 output
Terminal Configuration and Functions
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MSP430FR58891 MSP430FR5888 MSP430FR5887
Copyright © 2014–2018, Texas Instruments Incorporated
23
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
www.ti.com
Table 4-2. Signal Descriptions – MSP430FR588x and MSP430FR588x1 (continued)
TERMINAL
NAME
PM
RGC
DESCRIPTION
NO.
General-purpose digital I/O
USCI_A1: Slave out, master in (SPI mode)
P3.5/UCA1SOMI/UCA1RXD/TB0.1
27
USCI_A1: Receive data (UART mode)
Timer_B TB0 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O
P3.6/UCA1CLK/TB0.2
28
USCI_A1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
Timer_B TB0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O
P3.7/UCA1STE/TB0.3
29
USCI_A1: Slave transmit enable (SPI mode)
Timer_B TB0 CCR3 capture: CCI3B input, compare: Out3 output
General-purpose digital I/O
P2.3/UCA0STE/TB0OUTH
30
USCI_A0: Slave transmit enable (SPI mode)
Switch all PWM outputs high impedance input - Timer_B TB0
General-purpose digital I/O
USCI_A0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
P2.2/UCA0CLK/TB0.4/RTCCLK
31
Timer_B TB0 CCR4 capture: CCI4B input, compare: Out4 output
RTC clock output for calibration
General-purpose digital I/O
USCI_A0: Slave out, master in (SPI mode)
P2.1/UCA0SOMI/UCA0RXD/TB0.5/
DMAE0
USCI_A0: Receive data (UART mode)
32
BSL receive (UART BSL)
Timer_B TB0 CCR5 capture: CCI5B input, compare: Out5 output
DMA external trigger input
General-purpose digital I/O
USCI_A0: Slave in, master out (SPI mode)
P2.0/UCA0SIMO/UCA0TXD/TB0.6/
TB0CLK
USCI_A0: Transmit data (UART mode)
33
BSL transmit (UART BSL)
Timer_B TB0 CCR6 capture: CCI6B input, compare: Out6 output
Timer_B TB0 clock signal TB0CLK input
DVSS2
34
Digital ground supply
DVCC2
35
Digital power supply
General-purpose digital I/O
ESI test signal 4
P1.3/ESITEST4/TA1.2/A3/C3
36
Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output
Analog input A3
Comparator input C3
24
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions – MSP430FR588x and MSP430FR588x1 (continued)
TERMINAL
NAME
PM
RGC
DESCRIPTION
NO.
General-purpose digital I/O
Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output
Timer_A TA0 clock signal TA0CLK input
P1.2/TA1.1/TA0CLK/COUT/A2/C2
37
Comparator output
Analog input A2
Comparator input C2
General-purpose digital I/O
Timer_A TA0 CCR2 capture: CCI2A input, compare: Out2 output
Timer_A TA1 clock signal TA1CLK input
P1.1/TA0.2/TA1CLK/
COUT/A1/C1/VREF+/ VeREF+
Comparator output
38
Analog input A1
Comparator input C1
Output of positive reference voltage
Input for an external positive reference voltage to the ADC
General-purpose digital I/O
Timer_A TA0 CCR1 capture: CCI1A input, compare: Out1 output
DMA external trigger input
P1.0/TA0.1/DMAE0/ RTCCLK/A0/C0/
VREF-/VeREF-
RTC clock output for calibration
39
Analog input A0
Comparator input C0
Output of negative reference voltage
Input for an external negative reference voltage to the ADC
General-purpose digital I/O
P9.0/ESICH0/ESITEST0/ A8/C8
40
ESI channel 0 sensor excitation output and signal input
ESI test signal 0
Analog input A8; comparator input C8
General-purpose digital I/O
ESI channel 1 sensor excitation output and signal input
P9.1/ESICH1/ESITEST1/ A9/C9
41
ESI test signal 1
Analog input A9
Comparator input C9
General-purpose digital I/O
ESI channel 2 sensor excitation output and signal input
P9.2/ESICH2/ESITEST2/ A10/C10
42
ESI test signal 2
Analog input A10
Comparator input C10
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions – MSP430FR588x and MSP430FR588x1 (continued)
TERMINAL
NAME
PM
RGC
DESCRIPTION
NO.
General-purpose digital I/O
ESI channel 3 sensor excitation output and signal input
P9.3/ESICH3/ESITEST3/ A11/C11
43
ESI test signal 3
Analog input A11
Comparator input C11
General-purpose digital I/O
ESI channel 0 signal input to comparator
P9.4/ESICI0/A12/C12
44
Analog input A12
Comparator input C12
General-purpose digital I/O
ESI channel 1 signal input to comparator
P9.5/ESICI1/A13/C13
45
Analog input A13
Comparator input C13
General-purpose digital I/O
ESI channel 2 signal input to comparator
P9.6/ESICI2/A14/C14
46
Analog input A14
Comparator input C14
General-purpose digital I/O
ESI channel 3 signal input to comparator
P9.7/ESICI3/A15/C15
47
Analog input A15
Comparator input C15
ESIDVCC
48
ESI Power supply
ESIDVSS
49
ESI Ground supply
ESICI
50
ESI Scan IF input to Comparator
ESICOM
51
ESI Common termination for Scan IF sensors
AVCC1
52
Analog power supply
AVSS3
53
Analog ground supply
PJ.7/HFXOUT
54
General-purpose digital I/O
Output terminal of crystal oscillator XT2
General-purpose digital I/O
PJ.6/HFXIN
55
Input terminal for crystal oscillator XT2
AVSS1
56
PJ.4/LFXIN
57
Analog ground supply
General-purpose digital I/O
Input terminal for crystal oscillator XT1
General-purpose digital I/O
PJ.5/LFXOUT
58
AVSS2
59
Output terminal of crystal oscillator XT1
Analog ground supply
General-purpose digital I/O
USCI_B1: Slave in, master out (SPI mode)
P4.0/UCB1SIMO/UCB1SDA/MCLK
60
USCI_B1: I2C data (I2C mode)
MCLK output
26
Terminal Configuration and Functions
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SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Table 4-2. Signal Descriptions – MSP430FR588x and MSP430FR588x1 (continued)
TERMINAL
NAME
PM
RGC
DESCRIPTION
NO.
General-purpose digital I/O
USCI_B1: Slave out, master in (SPI mode)
P4.1/UCB1SOMI/UCB1SCL/ACLK
61
DVSS3
62
Digital ground supply
DVCC3
63
Digital power supply
USCI_B1: I2C clock (I2C mode)
ACLK output
General-purpose digital I/O
P4.2/UCA0SIMO/UCA0TXD/
UCB1CLK
USCI_A0: Slave in, master out (SPI mode)
64
USCI_A0: Transmit data (UART mode)
USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
Thermal pad
Pad
RGC package only. QFN package exposed thermal pad. TI recommends connection to
VSS.
Terminal Configuration and Functions
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Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and diagrams of the
multiplexed ports, see Section 6.11.23.
4.4
Connection of Unused Pins
Table 4-3 lists the correct termination of all unused pins.
Table 4-3. Connection of Unused Pins (1)
(1)
(2)
28
PIN
POTENTIAL
AVCC
DVCC
COMMENT
AVSS
DVSS
Px.0 to Px.7
Open
Set to port function, output direction (PxDIR.n = 1)
R33/LCDCAP
DVSS or DVCC
If the pin is not used, it can be tied to either supply.
ESIDVCC
DVCC
ESIDVSS
DVSS
ESICOM
Open
ESICI
Open
RST/NMI
DVCC or VCC
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
Open
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not used as JTAG pins,
these pins should be switched to port function, output direction. When used as JTAG pins, these
pins should remain open.
TEST
Open
This pin always has an internal pulldown enabled.
47-kΩ pullup or internal pullup selected with 2.2-nF (10-nF (2)) pulldown
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
The pulldown capacitor should not exceed 2.2 nF when using devices in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like
FET interfaces or GANG programmers. If JTAG or Spy-Bi-Wire access is not needed, up to a 10-nF pulldown capacitor may be used.
Terminal Configuration and Functions
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5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to VSS
Voltage difference between DVCC and AVCC pins
Voltage applied to any pin
MIN
MAX
–0.3
4.1
V
±0.3
V
–0.3
VCC + 0.3 V
(4.1 Max)
V
(2)
(3)
Diode current at any device pin
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(4)
–40
UNIT
±2
mA
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3
Recommended Operating Conditions
Typical data are based on VCC = 3.0 V, TA = 25°C unless otherwise noted.
MIN
UNIT
VSS
Supply voltage applied at all DVSS, AVSS, and ESIDVSS pins
TA
Operating free-air temperature
TJ
Operating junction temperature
CDVCC
Capacitor value at DVCC and ESIDVCC
fSYSTEM
Processor frequency (maximum MCLK
frequency) (6)
fACLK
Maximum ACLK frequency
50
kHz
Maximum SMCLK frequency
(9)
MHz
fSMCLK
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
1.8 (4)
MAX
Supply voltage range applied at all DVCC, AVCC, and ESIDVCC pins (1)
(1)
(2) (3)
NOM
VCC
3.6
V
–40
85
°C
–40
85
0
(5)
V
1–20%
No FRAM wait states (NWAITSx = 0)
With FRAM wait states (NWAITSx = 1)
(8)
°C
µF
0
8 (7)
0
16 (9)
16
MHz
TI recommends powering the DVCC, AVCC, and ESIDVCC pins from the same source. At a minimum, during power up, power down,
and device operation, the voltage difference between DVCC, AVCC, and ESIDVCC must not exceed the limits specified in Absolute
Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
See Table 5-1 for additional important information.
Modules may have a different supply voltage range specification. See the specification of each module in this data sheet.
The minimum supply voltage is defined by the supervisor SVS levels. See Table 5-2 for the exact values.
Connect a low-ESR capacitor with at least the value specified and a maximum tolerance of 20% as close as possible to the DVCC and
ESIDVCC pins.
Modules may have a different maximum input clock specification. See the specification of each module in this data sheet.
DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted.
Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always executed
without wait states.
DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted. If a clock sources with a
larger typical value is used, the clock must be divided in the clock system.
Specifications
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Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2)
FREQUENCY (fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
VCC
1 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
IAM, FRAM_UNI
(Unified memory) (3)
(4) (5)
MAX
4 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
MAX
8 MHz
0 WAIT
STATES
(NWAITSx = 0)
TYP
MAX
12 MHz
1 WAIT STATE
(NWAITSx = 1)
TYP
MAX
16 MHz
1 WAIT STATE
(NWAITSx = 1)
TYP
UNIT
MAX
FRAM
3.0 V
210
640
1220
1475
1845
µA
FRAM
0% cache hit
ratio
3.0 V
375
1290
2525
2100
2675
µA
IAM,
FRAM(0%)
IAM,
FRAM(50%)
(4) (5)
FRAM
50% cache hit
ratio
3.0 V
240
745
1440
1575
1990
µA
IAM,
FRAM(66%)
(4) (5)
FRAM
66% cache hit
ratio
3.0 V
200
560
1070
1300
1620
µA
IAM,
FRAM(75%)
(4) (5)
FRAM
75% cache hit
ratio
3.0 V
170
480
890
IAM,
FRAM(100%
FRAM
100% cache hit
ratio
3.0 V
110
235
420
640
730
IAM,
RAM
RAM
3.0 V
130
320
585
890
1070
RAM
3.0 V
100
290
555
860
1040
(6) (5)
IAM, RAM only
(1)
(2)
(3)
(4)
(5)
(6)
(7)
30
(4) (5)
(7) (5)
255
180
1085
1155
1310
1420
1620
µA
µA
µA
1300
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO = 24 MHz and
fMCLK = fSMCLK = fDCO / 2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff:
fMCLK,eff = fMCLK / [wait states × (1 – cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio fMCKL,eff = fMCLK / [1 × (1 – 0.75) + 1] = fMCLK / 1.25.
Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio implies three of
every four accesses is from cache, and the remaining are FRAM accesses.
See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in Section 5.4.
Program and data reside entirely in RAM. All execution is from RAM.
Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Specifications
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5.5
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Typical Characteristics, Active Mode Supply Currents
3000
I(AM,0%)
I(AM,50%)
2500
I(AM,66%)
Active Mode Current (µA)
I(AM,75%)
2000
I(AM,100%)
I(AM,75%)[µA] = 103 × f[MHz] + 68
I(AM,RAMonly)
1500
1000
500
0
0
1
2
3
4
5
6
7
8
9
MCLK Frequency (MHz)
I(AM, cache hit ratio): Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with
cache hit-to-miss ratio as specified. Cache hit ratio represents number cache accesses divided by the total number of
FRAM accesses. For example, a 75% ratio implies three of every four accesses is from cache, and the remaining are
FRAM accesses.
I(AM, RAMonly): Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Figure 5-1. Typical Active Mode Supply Currents, No Wait States
5.6
Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted) (1)
(2)
FREQUENCY (fSMCLK)
PARAMETER
VCC
1 MHz
TYP
ILPM0
ILPM1
(1)
(2)
2.2 V
75
3.0 V
85
2.2 V
40
3.0 V
40
4 MHz
MAX
120
65
TYP
8 MHz
MAX
TYP
12 MHz
MAX
TYP
16 MHz
MAX
TYP
105
165
250
230
115
175
260
240
65
130
215
195
65
130
215
195
UNIT
MAX
275
220
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency, except for 12 MHz: here fDCO = 24 MHz and fSMCLK = fDCO / 2.
Specifications
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Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
TEMPERATURE (TA)
PARAMETER
VCC
–40°C
TYP
25°C
MAX
TYP
ILPM2,XT12
Low-power mode 2, 12-pF
crystal (2) (3) (4)
2.2 V
0.6
1.2
3.0 V
0.6
1.2
ILPM2,XT3.7
Low-power mode 2, 3.7-pF
crystal (2) (5) (4)
2.2 V
0.5
3.0 V
0.5
ILPM2,VLO
Low-power mode 2, VLO,
includes SVS (6)
2.2 V
0.3
0.9
3.0 V
0.3
0.9
ILPM3,XT12
Low-power mode 3, 12-pF
crystal, excludes SVS (2) (3)
2.2 V
0.5
0.7
3.0 V
0.5
0.7
Low-power mode 3, 3.7-pF
crystal, excludes SVS (2) (5) (8)
(also see Figure 5-2)
2.2 V
0.4
ILPM3,XT3.7
3.0 V
ILPM3,VLO
Low-power mode 3,
VLO, excludes SVS
ILPM3,VLO,
RAMoff
(7)
(9)
Low-power mode 3,
VLO, excludes SVS, RAM
powered-down completely (10)
60°C
MAX
TYP
85°C
MAX
TYP
3.1
8.8
3.1
8.8
1.1
3.0
8.7
1.1
3.0
8.7
2.8
8.5
2.8
8.5
1.2
2.5
1.2
2.5
0.6
1.1
2.4
0.4
0.6
1.1
2.4
2.2 V
0.3
0.4
0.9
2.2
3.0 V
0.3
0.4
0.9
2.2
2.2 V
0.3
0.4
0.8
2.1
3.0 V
0.3
0.4
0.8
2.1
2.2
2.0
1.0
0.8
0.7
UNIT
MAX
20.8
μA
μA
20.5
6.4
μA
μA
μA
6.1
5.2
μA
μA
(1)
(2)
(3)
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5 pF load.
(4) Low-power mode 2, crystal oscillator test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
(6) Low-power mode 2, VLO test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
(7) Low-power mode 3, 12-pF crystal excluding SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =
0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(8) Low-power mode 3, 3.7-pF crystal excluding SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =
0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(9) Low-power mode 3, VLO excluding SVS test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout included. SVS disabled
(SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(10) Low-power mode 3, VLO excluding SVS test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). RAM disabled (RCCTL0 = 5A55h). Current for
brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
32
Specifications
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SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
TEMPERATURE (TA)
PARAMETER
VCC
–40°C
TYP
25°C
MAX
TYP
ILPM4,SVS
Low-power mode 4, includes
SVS (11)
2.2 V
0.4
0.5
3.0 V
0.4
0.5
ILPM4
Low-power mode 4, excludes
SVS (12)
2.2 V
0.2
0.3
3.0 V
0.2
0.3
Low-power mode 4, excludes
SVS, RAM powered-down
completely (13)
2.2 V
0.2
0.3
ILPM4,RAMoff
3.0 V
0.2
0.3
IIDLE,GroupA
Additional idle current if one or
more modules from Group A
(see Table 6-3) are activated in
LPM3 or LPM4
3.0V
IIDLE,GroupB
Additional idle current if one or
more modules from Group B
(see Table 6-3) are activated in
LPM3 or LPM4
IIDLE,GroupC
IIDLE,GroupD
60°C
MAX
TYP
85°C
MAX
TYP
UNIT
MAX
0.9
2.3
0.9
2.3
0.7
2.0
0.7
2.0
0.7
1.9
0.7
1.9
5.1
0.02
0.3
1.2
μA
3.0V
0.02
0.3
1.2
μA
Additional idle current if one or
more modules from Group C
(see Table 6-3) are activated in
LPM3 or LPM4
3.0V
0.02
0.38
1.5
μA
Additional idle current if one or
more modules from Group D
(see Table 6-3) are activated in
LPM3 or LPM4
3.0V
0.015
0.25
1.0
μA
0.8
0.6
0.6
6.2
6.0
μA
μA
μA
(11) Low-power mode 4 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(12) Low-power mode 4 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
(13) Low-power mode 4 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current. See the idle currents specified for the respective peripheral groups.
Specifications
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5.8
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Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEMPERATURE (TA)
PARAMETER
VCC
–40°C
TYP
25°C
MAX
TYP
ILPM3,XT12
LCD,
ext. bias
Low-power mode 3 (LPM3)
current,12-pF crystal, LCD 4mux mode, external biasing,
excludes SVS (1) (2)
3.0 V
0.7
0.9
ILPM3,XT12
LCD,
int. bias
Low-power mode 3 (LPM3)
current, 12-pF crystal, LCD 4mux mode, internal biasing,
charge pump disabled,
excludes SVS (1) (3)
3.0 V
2.0
2.2
Low-power mode 3 (LPM3)
current,12-pF crystal, LCD 4mux mode, internal biasing,
charge pump enabled, 1/3 bias,
excludes SVS (1) (4)
2.2 V
5.0
ILPM3,XT12
LCD,CP
3.0 V
4.5
(1)
(2)
(3)
(4)
34
60°C
MAX
TYP
85°C
MAX
TYP
1.5
3.1
2.8
4.4
5.2
5.8
7.4
4.7
5.3
6.9
2.9
UNIT
MAX
µA
9.3
µA
µA
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE =
0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution as well as due to additional
idle current - idle current of Group containing LCD module already included. See the idle currents specified for the respective peripheral
groups.
LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2, ... = 0, odd segments S1, S3, ... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ...=0, odd segments S1, S3, ... = 1. No LCD panel load.
LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD= 3 V typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2, ...=0, odd segments S1, S3, ... = 1. No LCD panel load. CLCDCAP = 10 µF
Specifications
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5.9
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
–40°C
TYP
25°C
MAX
TYP
ILPM3.5,XT12
Low-power mode 3.5, 12-pF
crystal including SVS (2) (3) (4)
2.2 V
0.4
0.45
3.0 V
0.4
0.45
ILPM3.5,XT3.7
Low-power mode 3.5, 3.7-pF
crystal excluding SVS (2) (5) (6)
2.2 V
0.3
3.0 V
0.3
ILPM4.5,SVS
Low-power mode 4.5, including
SVS (7)
2.2 V
0.2
0.2
3.0 V
0.2
0.2
ILPM4.5
Low-power mode 4.5,
excluding SVS (8)
2.2 V
0.02
3.0 V
0.02
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
60°C
MAX
TYP
85°C
MAX
TYP
0.55
0.75
0.55
0.75
0.35
0.4
0.65
0.35
0.4
0.65
0.25
0.35
0.25
0.35
0.02
0.03
0.14
0.02
0.03
0.13
0.7
0.4
MAX
1.6
UNIT
μA
μA
0.7
0.5
μA
μA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are
chosen to closely match the required 12.5 pF load.
Low-power mode 3.5, 1-pF crystal including SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
Low-power mode 3.5, 3.7-pF crystal excluding SVS test conditions:
Current for RTC clocked by XT1 included.Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Specifications
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5.10 Typical Characteristics, Low-Power Mode Supply Currents
3
3
3.0 V, SVS off
3.0 V, SVS off
2.2 V, SVS off
2.2 V, SVS off
3.0 V, SVS on
2.5
3.0 V, SVS on
2.5
2.2 V, SVS on
LPM4 Supply Current (µA)
LPM3 Supply Current (µA)
2.2 V, SVS on
2
1.5
1
0.5
2
1.5
1
0.5
0
0
-50
-25
0
25
50
75
100
-50
-25
0
25
Temperature (°C)
50
75
100
Temperature (°C)
Figure 5-2. LPM3 Supply Current vs Temperature (LPM3, XT3.7)
Figure 5-3. LPM4 Supply Current vs Temperature (LPM4, SVS)
0.7
0.7
3.0 V, SVS off
3.0 V, SVS off
2.2 V, SVS off
0.6
2.2 V, SVS off
0.6
LPM4.5 Supply Current (µA)
LPM3.5 Supply Current (µA)
3.0 V, SVS on
0.5
0.4
0.3
0.2
0.1
0.4
0.3
0.2
0.1
0
0
-50
-25
0
25
50
75
100
Temperature (°C)
Figure 5-4. LPM3.5 Supply Current vs Temperature (LPM3.5,
XT3.7)
36
2.2 V, SVS on
0.5
Specifications
-50
-25
0
25
50
75
100
Temperature (°C)
Figure 5-5. LPM4.5 Supply Current vs Temperature (LPM4.5)
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SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
5.11 Typical Characteristics, Current Consumption per Module (1)
MODULE
TEST CONDITIONS
Timer_A
REFERENCE CLOCK
MIN
TYP
Module input clock
Timer_B
MAX
UNIT
3
μA/MHz
Module input clock
5
μA/MHz
eUSCI_A
UART mode
Module input clock
5.5
μA/MHz
eUSCI_A
SPI mode
Module input clock
3.5
μA/MHz
eUSCI_B
SPI mode
Module input clock
3.5
μA/MHz
eUSCI_B
I2C mode, 100 kbaud
Module input clock
3.5
μA/MHz
32 kHz
100
nA
RTC_C
MPY
Only from start to end of operation
MCLK
25
μA/MHz
CRC16
Only from start to end of operation
MCLK
2.5
μA/MHz
CRC32
Only from start to end of operation
MCLK
2.5
μA/MHz
(1)
LCD_C: See Section 5.8. For other module currents not listed here, see the module-specific parameter sections.
Specifications
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5.12 Thermal Resistance Characteristics
THERMAL METRIC (1)
PACKAGE
VALUE (2)
UNIT
49.8
°C/W
θJA
Junction-to-ambient thermal resistance, still air (3)
θJC(TOP)
Junction-to-case (top) thermal resistance (4)
9.7
°C/W
θJB
Junction-to-board thermal resistance (5)
26.0
°C/W
ΨJB
Junction-to-board thermal characterization parameter
25.7
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.2
°C/W
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance (6)
N/A
°C/W
θJA
Junction-to-ambient thermal resistance, still air (3)
49.5
°C/W
14.7
°C/W
24.1
°C/W
23.8
°C/W
0.7
°C/W
LQFP-100 (PZ)
(4)
θJC(TOP)
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (5)
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
LQFP-80 (PN)
(6)
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
θJA
Junction-to-ambient thermal resistance, still air (3)
55.3
°C/W
θJC(TOP)
Junction-to-case (top) thermal resistance (4)
16.8
°C/W
26.8
°C/W
26.5
°C/W
0.8
°C/W
(5)
θJB
Junction-to-board thermal resistance
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
LQFP-64 (PM)
(6)
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
θJA
Junction-to-ambient thermal resistance, still air (3)
29.2
°C/W
θJC(TOP)
Junction-to-case (top) thermal resistance (4)
13.9
°C/W
θJB
Junction-to-board thermal resistance (5)
8.1
°C/W
ΨJB
Junction-to-board thermal characterization parameter
8.0
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.2
°C/W
θJC(BOTTOM)
Junction-to-case (bottom) thermal resistance (6)
1.0
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
38
VQFN-64 (RGC)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
N/A = not applicable
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Specifications
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SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
5.13 Timing and Switching Characteristics
5.13.1 Power Supply Sequencing
TI recommends powering the AVCC, DVCC, and ESIDVCC pins from the same source. At a minimum,
during power up, power down, and device operation, the voltage difference between AVCC, DVCC, and
ESIDVCC must not exceed the limits specified in Absolute Maximum Ratings. Exceeding the specified
limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
At power up, the device does not start executing code before the supply voltage reached VSVSH+ if the
supply rises monotonically to this level.
Table 5-1 lists the power ramp requirements.
Table 5-1. Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VVCC_BOR–
Brownout power-down level (1) (2)
VVCC_BOR+
Brownout power-up level (2)
(1)
(2)
(3)
(4)
| dDVCC/dt | < 3 V/s (3)
| dDVCC/dt | > 300 V/s (3)
| dDVCC/dt | < 3 V/s (4)
MIN
MAX
0.7
1.66
0
0.79
1.68
UNIT
V
V
In case of a supply voltage brownout, the device supply voltages must ramp down to the specified brownout power-down level
(VVCC_BOR-) before the voltage is ramped up again to ensure a reliable device start-up and performance according to the data sheet
including the correct operation of the on-chip SVS module.
Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor CDVCC should limit the slopes accordingly.
The brownout levels are measured with a slowly changing supply. With faster slopes, the MIN level required to reset the device properly
can decrease to 0 V. Use the graph in Figure 5-6 to estimate the VVCC_BOR- level based on the down slope of the supply voltage. After
removing VCC, the down slope can be estimated based on the current consumption and the capacitance on DVCC: dV/dt = I/C where
dV/dt = slope, I = current, C = capacitance.
The brownout levels are measured with a slowly changing supply.
2
Brownout Power-Down Level (V)
Process-Temperature Corner Case 1
1.5
Typical
1
Process-Temperature Corner Case 2
MIN Limit
0.5
V VCC_BOR- for reliable
device start-up
0
1
10
100
1000
10000
100000
Supply Voltage Power-Down Slope (V/s)
Figure 5-6. Brownout Power-Down Level vs Supply Voltage Down Slope
Specifications
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Table 5-2 lists the characteristics of the SVS.
Table 5-2. SVS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISVSH,LPM
TEST CONDITIONS
(1)
VSVSH-
SVSH power-down level
VSVSH+
SVSH power-up level (1)
VSVSH_hys
SVSH hysteresis
tPD,SVSH, AM
SVSH propagation delay, active mode
(1)
MIN
TYP
MAX
UNIT
170
300
nA
1.75
1.80
1.85
V
1.77
1.88
1.99
V
120
mV
10
µs
SVSH current consumption, low-power modes
40
dVVcc/dt = –10 mV/µs
For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference
Design.
5.13.2 Reset Timing
Table 5-11 lists the input requirements for the RST signal.
Table 5-3. Reset Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(RST)
(1)
40
External reset pulse duration on RST (1)
VCC
2.2 V, 3.0 V
MIN
2
MAX
UNIT
µs
Not applicable if RST/NMI pin configured as NMI.
Specifications
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5.13.3 Clock Specifications
Table 5-4 lists the characteristics of the LFXT.
Table 5-4. Low-Frequency Crystal Oscillator, LFXT (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF, ESR ≈ 44 kΩ
IVCC.LFXT
Current consumption
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {1},
TA = 25°C, CL,eff = 6 pF, ESR ≈ 40 kΩ
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {2},
TA = 25°C, CL,eff = 9 pF, ESR ≈ 40 kΩ
LFXT oscillator crystal frequency
LFXTBYPASS = 0
DCLFXT
LFXT oscillator duty cycle
Measured at ACLK,
fLFXT = 32768 Hz
fLFXT,SW
LFXT oscillator logic-level
square-wave input frequency
LFXTBYPASS = 1 (2)
DCLFXT, SW
LFXT oscillator logic-level
square-wave input duty cycle
LFXTBYPASS = 1
OALFXT
Oscillation allowance for
LF crystals (4)
MAX
185
3.0 V
nA
225
330
32768
30%
(3)
UNIT
180
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF, ESR ≈ 40 kΩ
fLFXT
TYP
10.5
Hz
70%
32.768
30%
50
kHz
70%
LFXTBYPASS = 0, LFXTDRIVE = {1},
fLFXT = 32768 Hz, CL,eff = 6 pF
210
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
300
kΩ
CLFXIN
Integrated load capacitance at
LFXIN terminal (5) (6)
2
pF
CLFXOUT
Integrated load capacitance at
LFXOUT terminal (5) (6)
2
pF
(1)
(2)
(3)
(4)
(5)
(6)
To improve EMI on the LFXT oscillator, observe the following guidelines.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
• Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
• For LFXTDRIVE = {1}, CL,eff = 6 pF
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 9 pF
• For LFXTDRIVE = {3}, 9 pF ≤ CL,eff ≤ 12.5 pF
This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the LFXIN and LFXOUT terminals, respectively.
Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
Specifications
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Table 5-4. Low-Frequency Crystal Oscillator, LFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tSTART,LFXT
(9)
(7)
Oscillator fault frequency (8)
fFault,LFXT
(7)
(8)
Start-up time
TEST CONDITIONS
VCC
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF
3.0 V
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
3.0 V
MIN
TYP
MAX
UNIT
800
ms
(9)
1000
0
3500
Hz
Includes start-up counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition sets the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Table 5-5 lists the characteristics of the HFXT.
Table 5-5. High-Frequency Crystal Oscillator, HFXT (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1 (2)
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
IDVCC.HFXT
HFXT oscillator
crystal current HF
mode at typical
ESR
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 1,
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 2, HFFREQ = 2,
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
fHFXT
HFXT oscillator
duty cycle
DCHFXT
HFXT oscillator
logic-level squarewave input
frequency, bypass
mode
fHFXT,SW
DCHFXT,
(1)
(2)
(3)
(4)
42
SW
HFXTBYPASS = 0, HFFREQ = 1 (2) (3)
MAX
120
3.0 V
μA
190
250
4
8
HFXTBYPASS = 0, HFFREQ = 2 (3)
8.01
16
HFXTBYPASS = 0, HFFREQ = 3 (3)
16.01
24
Measured at SMCLK, fHFXT = 16 MHz
40%
50%
0.9
4
HFXTBYPASS = 1, HFFREQ = 1 (4) (3)
4.01
8
(4) (3)
8.01
16
HFXTBYPASS = 1, HFFREQ = 3 (4) (3)
16.01
24
40%
60%
HFXTBYPASS = 1, HFFREQ = 2
HFXT oscillator
logic-level squareHFXTBYPASS = 1
wave input duty
cycle
MHz
60%
(4) (3)
HFXTBYPASS = 1, HFFREQ = 0
UNIT
75
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TA = 25°C, CL,eff = 18 pF, Typical ESR, Cshunt
HFXT oscillator
crystal frequency,
crystal mode
TYP
MHz
To improve EMI on the HFXT oscillator, observe the following guidelines.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
• Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
HFFREQ = {0} is not supported for HFXT crystal mode of operation.
Maximum frequency of operation of the entire device cannot be exceeded.
When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT, SW.
Specifications
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Table 5-5. High-Frequency Crystal Oscillator, HFXT(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tSTART,HFXT
CHFXIN
Start-up time
TEST CONDITIONS
(5)
VCC
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1,
TA = 25°C, CL,eff = 16 pF
3.0 V
fOSC = 24 MHz ,
HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,
TA = 25°C, CL,eff = 16 pF
3.0 V
MIN
TYP
MAX
UNIT
1.6
ms
0.6
Integrated load
capacitance at
HFXIN terminaI (6)
2
pF
2
pF
(7)
CHFXOUT
Integrated load
capacitance at
HFXOUT
terminaI (6) (7)
fFault,HFXT
Oscillator fault
frequency (8) (9)
(5)
(6)
(7)
(8)
(9)
0
800
kHz
Includes start-up counter of 1024 clock cycles.
This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the HFXIN and HFXOUT terminals, respectively.
Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static
condition or stuck at fault condition set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
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Table 5-6 lists the characteristics of the DCO.
Table 5-6. DCO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
1
±3.5%
MHz
fDCO1
DCO frequency range
1 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 0,
DCORSEL = 1, DCOFSEL = 0
fDCO2.7
DCO frequency range
2.7 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 1
2.667
±3.5%
MHz
fDCO3.5
DCO frequency range
3.5 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 2
3.5
±3.5%
MHz
fDCO4
DCO frequency range
4 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 3
4
±3.5%
MHz
fDCO5.3
DCO frequency range
5.3 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 4,
DCORSEL = 1, DCOFSEL = 1
5.333
±3.5%
MHz
fDCO7
DCO frequency range
7 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 5,
DCORSEL = 1, DCOFSEL = 2
7
±3.5%
MHz
fDCO8
DCO frequency range
8 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 6,
DCORSEL = 1, DCOFSEL = 3
8
±3.5%
MHz
fDCO16
DCO frequency range
16 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 1, DCOFSEL = 4
16
±3.5% (1)
MHz
fDCO21
DCO frequency range
21 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 5
21
±3.5% (1)
MHz
fDCO24
DCO frequency range
24 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 6
24
±3.5% (1)
MHz
Duty cycle
Measured at SMCLK, divide by 1,
no external divide, all
DCORSEL/DCOFSEL settings except
DCORSEL = 1, DCOFSEL = 5 and
DCORSEL = 1, DCOFSEL = 6
50%
52%
DCO jitter
Based on fsignal = 10 kHz and DCO used
for 12-bit SAR ADC sampling source.
This achieves >74 dB SNR due to jitter
(that is, it is limited by ADC
performance).
2
3
fDCO,DC
tDCO,
JITTER
dfDCO/dT
(1)
(2)
44
DCO temperature drift (2)
48%
3.0 V
0.01
ns
%/ºC
After a wakeup from LPM1, LPM2, LPM3, or LPM4, the DCO frequency fDCO might exceed the specified frequency range for a few clock
cycles by up to 5% before settling into the specified steady-state frequency range.
Calculated using the box method: (MAX(–40ºC to 85ºC) – MIN(–40ºC to 85ºC)) / MIN(–40ºC to 85ºC) / (85ºC – (–40ºC))
Specifications
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Table 5-7 lists the characteristics of the VLO.
Table 5-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IVLO
Current consumption
fVLO
VLO frequency
Measured at ACLK
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK (1)
dfVLO/dVCC
VLO frequency supply voltage drift
Measured at ACLK (2)
fVLO,DC
Duty cycle
Measured at ACLK
(1)
(2)
MIN
TYP
MAX
100
6
9.4
nA
14
0.2
50%
kHz
%/°C
0.7
40%
UNIT
%/V
60%
Calculated using the box method: (MAX(–40ºC to 85°C) – MIN(–40ºC to 85°C)) / MIN(–40ºC to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Table 5-8 lists the characteristics of the MODOSC.
Table 5-8. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IMODOSC
Current consumption
fMODOSC
MODOSC frequency
fMODOSC/dT
MODOSC frequency temperature drift (1)
fMODOSC/dVCC
MODOSC frequency supply voltage
drift (2)
DCMODOSC
Duty cycle
(1)
(2)
TEST CONDITIONS
MIN
TYP
4.0
4.8
Enabled
Measured at SMCLK, divide by 1
MAX
UNIT
5.4
MHz
25
40%
μA
0.08
%/℃
1.4
%/V
50%
60%
Calculated using the box method: (MAX(–40ºC to 85°C) – MIN(–40ºC to 85°C)) / MIN(–40ºC to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
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5.13.4 Wake-up Characteristics
Table 5-9 lists the wake-up times.
Table 5-9. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
6
10
μs
400 +
1.5 / fDCO
ns
tWAKE-UP FRAM
(Additional) wake-up time to activate the FRAM
in AM if previously disabled by the FRAM
controller or from an LPM if immediate
activation is selected for wakeup
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode (1)
2.2 V, 3.0 V
tWAKE-UP LPM1
Wake-up time from LPM1 to active mode (1)
2.2 V, 3.0 V
6
tWAKE-UP LPM2
Wake-up time from LPM2 to active mode
(1)
2.2 V, 3.0 V
6
tWAKE-UP LPM3
Wake-up time from LPM3 to active mode (1)
2.2 V, 3.0 V
7
10
μs
tWAKE-UP LPM4
Wake-up time from LPM4 to active mode (1)
2.2 V, 3.0 V
7
10
μs
μs
tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode
(2)
tWAKE-UP-BOR
(1)
(2)
μs
2.2 V, 3.0 V
250
375
SVSHE = 1
2.2 V, 3.0 V
250
375
μs
SVSHE = 0
2.2 V, 3.0 V
1
1.5
ms
Wake-up time from a RST pin triggered reset to
active mode (2)
2.2 V, 3.0 V
250
375
μs
(2)
2.2 V, 3.0 V
1
1.5
ms
tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode (2)
tWAKE-UP-RST
μs
Wake-up time from power-up to active mode
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge. MCLK is sourced by the DCO and the MCLK divider is set to divide-by-1 (DIVMx = 000b,
fMCLK = fDCO). This time includes the activation of the FRAM during wakeup.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
Table 5-10 lists the typical charge consumed during wakeup from various low-power modes.
Table 5-10. Typical Wake-up Charge (1)
also see Figure 5-7 and Figure 5-8
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QWAKE-UP FRAM
Charge used for activating the FRAM in AM or during wake-up
from LPM0 if previously disabled by the FRAM controller.
15.1
nAs
QWAKE-UP LPM0
Charge used for wake-up from LPM0 to active mode (with
FRAM active)
4.4
nAs
QWAKE-UP LPM1
Charge used for wake-up from LPM1 to active mode (with
FRAM active)
15.1
nAs
QWAKE-UP LPM2
Charge used for wake-up from LPM2 to active mode (with
FRAM active)
15.3
nAs
QWAKE-UP LPM3
Charge used for wake-up from LPM3 to active mode (with
FRAM active)
16.5
nAs
QWAKE-UP LPM4
Charge used for wake-up from LPM4 to active mode (with
FRAM active)
16.5
nAs
76
nAs
(2)
QWAKE-UP LPM3.5
Charge used for wake-up from LPM3.5 to active mode
QWAKE-UP LPM4.5
Charge used for wake-up from LPM4.5 to active mode (2)
QWAKE-UP-RESET
Charge used for reset from RST or BOR event to active mode (2)
(1)
(2)
46
SVSHE = 1
77
SVSHE = 0
77.5
75
nAs
nAs
Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active
mode (for example, for an interrupt service routine).
Charge required until start of user code. This does not include the energy required to reconfigure the device.
Specifications
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5.13.4.1 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
10000.00
LPM0
LPM1
Average Wake-up Current (µA)
1000.00
LPM2,XT12
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 5-7. Average LPM Currents vs Wake-up Frequency at 25°C
10000.00
LPM0
LPM1
Average Wake-up Current (µA)
1000.00
LPM2,XT12
LPM3,XT12
LPM3.5,XT12
100.00
10.00
1.00
0.10
0.001
0.01
0.1
1
10
100
1000
10000
100000
Wake-up Frequency (Hz)
NOTE: The average wake-up current does not include the energy required in active mode; for example, for an interrupt
service routine or to reconfigure the device.
Figure 5-8. Average LPM Currents vs Wake-up Frequency at 85°C
Specifications
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5.13.5 Peripherals
5.13.5.1 Digital I/Os
Table 5-11 lists the characteristics of the digital inputs.
Table 5-11. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2 V
1.2
TYP
MAX
1.65
3.0 V
1.65
2.25
2.2 V
0.55
1.00
3.0 V
0.75
1.35
2.2 V
0.44
0.98
3.0 V
0.60
1.30
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
3
pF
CI,ana
Input capacitance, port pins with shared analog
VIN = VSS or VCC
functions (1)
5
pF
Ilkg(Px.y)
High-impedance input leakage current
See
t(int)
External interrupt timing (external trigger pulse
duration to set interrupt flag) (4)
Ports with interrupt capability
(see Section 1.4 and
Section 4.2)
t(RST)
External reset pulse duration on RST (5)
(1)
(2)
(3)
(4)
(5)
48
20
(2) (3)
35
50
V
V
V
kΩ
2.2 V,
3.0 V
–20
2.2 V,
3.0 V
20
ns
2.2 V,
3.0 V
2
µs
+20
nA
If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in
series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN or
PJ.5/LFXOUT.
The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It might be set by trigger signals
shorter than t(int).
Not applicable if RST/NMI pin configured as NMI.
Specifications
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Table 5-12 lists the characteristics of the digital outputs.
Table 5-12. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-9,
Figure 5-10, Figure 5-11, and Figure 5-12)
PARAMETER
TEST CONDITIONS
VCC
TYP
I(OHmax) = –3 mA (2)
VCC –
0.60
VCC
I(OHmax) = –2 mA (1)
VCC –
0.25
VCC
VCC –
0.60
VCC
VSS
VSS +
0.25
I(OLmax) = 3 mA (2)
VSS
VSS +
0.60
I(OLmax) = 2 mA (1)
VSS
VSS +
0.25
VSS
VSS +
0.60
2.2 V
High-level output voltage
3.0 V
I(OHmax) = –6 mA (2)
I(OLmax) = 1 mA (1)
Low-level output voltage
3.0 V
I(OLmax) = 6 mA (2)
fPx.y
Port output frequency (with load) (3)
CL = 20 pF, RL
fPort_CLK
Clock output frequency (3)
ACLK, MCLK, or SMCLK at
configured output port,
CL = 20 pF (5)
trise,dig
Port output rise time, digital only port pins
CL = 20 pF
tfall,dig
Port output fall time, digital only port pins
CL = 20 pF
trise,ana
Port output rise time, port pins with shared
analog functions
CL = 20 pF
tfall,ana
Port output fall time, port pins with shared
analog functions
CL = 20 pF
(1)
(2)
(3)
(4)
(5)
(4) (5)
2.2 V
16
3.0 V
16
2.2 V
16
3.0 V
16
UNIT
V
2.2 V
VOL
MAX
VCC
I(OHmax) = –1 mA
VOH
MIN
VCC –
0.25
(1)
V
MHz
MHz
2.2 V
4
15
3.0 V
3
15
2.2 V
4
15
3.0 V
3
15
2.2 V
6
15
3.0 V
4
15
2.2 V
6
15
3.0 V
4
15
ns
ns
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
The port can output frequencies at least up to the specified limit - it might support higher frequencies.
A resistive divider with 2 × R1 and R1 = 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 20 pF is connected from the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Specifications
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5.13.5.1.1 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
30
25°C
85°C
Low-Level Output Current (mA)
Low-Level Output Current (mA)
15
10
5
25°C
85°C
20
10
P1.1
P1.1
0
0
0
0.5
1
1.5
2
0
0.5
1
Low-Level Output Voltage (V)
1.5
2
2.5
3
Low-Level Output Voltage (V)
C001
C001
VCC = 2.2 V
VCC = 3.0 V
Figure 5-9. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
25°C
85°C
High-Level Output Current (mA)
High-Level Output Current (mA)
0
Figure 5-10. Typical Low-Level Output Current vs Low-Level
Output Voltage
-5
-10
25°C
85°C
-10
-20
P1.1
P1.1
-15
-30
0
0.5
1
1.5
2
0
0.5
1
High-Level Output Voltage (V)
1.5
2
C001
Figure 5-11. Typical High-Level Output Current vs High-Level
Output Voltage
Specifications
3
High-Level Output Voltage (V)
VCC = 2.2 V
50
2.5
C001
VCC = 3.0 V
Figure 5-12. Typical High-Level Output Current vs High-Level
Output Voltage
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SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Table 5-13 lists the frequencies of the pin oscillator.
Table 5-13. Pin-Oscillator Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-13
and Figure 5-14)
PARAMETER
foPx.y
(1)
TEST CONDITIONS
VCC
Px.y, CL = 10 pF (1)
Pin-oscillator frequency
3.0 V
Px.y, CL = 20 pF (1)
MIN
TYP
MAX
1200
UNIT
kHz
650
CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.
1000
fitted
fitted
25°C
25°C
85°C
Pin Oscillator Frequency (kHz)
Pin Oscillator Frequency (kHz)
5.13.5.1.2 Typical Characteristics, Pin-Oscillator Frequency
1000
85°C
100
100
10
100
External Load Capacitance (pF) (Including Board)
VCC = 2.2 V
One output active at a time.
Figure 5-13. Typical Oscillation Frequency vs Load Capacitance
10
100
External Load Capacitance (pF) (Including Board)
VCC = 3.0 V
One output active at a time.
Figure 5-14. Typical Oscillation Frequency vs Load Capacitance
Specifications
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5.13.5.2 Timer_A and Timer_B
Table 5-14 lists the characteristics of the Timer_A.
Table 5-14. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
tTA,cap
Timer_A capture timing
All capture inputs, minimum pulse
duration required for capture
VCC
2.2 V,
3.0 V
2.2 V,
3.0 V
MIN
TYP
MAX
UNIT
16
MHz
20
ns
Table 5-15 lists the characteristics of the Timer_B.
Table 5-15. Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTB
Timer_B input clock frequency
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
tTB,cap
Timer_B capture timing
All capture inputs, minimum pulse
duration required for capture
52
Specifications
VCC
2.2 V,
3.0 V
2.2 V,
3.0 V
MIN
TYP
20
MAX
UNIT
16
MHz
ns
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5.13.5.3 eUSCI
Table 5-16 lists the supported clock frequencies of the eUSCI in UART mode.
Table 5-16. eUSCI (UART Mode) Clock Frequency
PARAMETER
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
TEST CONDITIONS
MIN
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
MAX
UNIT
16
MHz
4
MHz
Table 5-17 lists the characteristics of the eUSCI in UART mode.
Table 5-17. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
UCGLITx = 0
UART receive deglitch time (1)
tt
UCGLITx = 1
2.2 V, 3.0 V
UCGLITx = 2
UCGLITx = 3
(1)
TYP
5
MAX
UNIT
30
20
90
35
160
50
220
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch
time can limit the maximum useable baud rate. To ensure that pulses are correctly recognized, their duration should exceed the
maximum specification of the deglitch time.
Table 5-18 lists the supported clock frequencies of the eUSCI in SPI master mode.
Table 5-18. eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
feUSCI
eUSCI input clock frequency
TEST CONDITIONS
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
MIN
MAX
UNIT
16
MHz
Specifications
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Table 5-19 lists the characteristics of the eUSCI in SPI master mode.
Table 5-19. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time, STE active to clock
UCSTEM = 1,
UCMODEx = 01 or 10
tSTE,LAG
STE lag time, last clock to STE inactive
UCSTEM = 1,
UCMODEx = 01 or 10
tSTE,ACC
STE access time, STE active to SIMO data
out
UCSTEM = 0,
UCMODEx = 01 or 10
2.2 V, 3.0 V
60
ns
tSTE,DIS
STE disable time, STE inactive to SOMI high UCSTEM = 0,
impedance
UCMODEx = 01 or 10
2.2 V, 3.0 V
80
ns
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
54
1
UCxCLK
cycles
1
UCxCLK
cycles
2.2 V
40
3.0 V
40
2.2 V
0
3.0 V
0
ns
ns
2.2 V
10
3.0 V
10
2.2 V
0
3.0 V
0
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-15 and Figure 5-16.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 515 and Figure 5-16.
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 5-15. SPI Master Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tVALID,MO
tSTE,DIS
SIMO
Figure 5-16. SPI Master Mode, CKPH = 1
Specifications
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Table 5-20 lists the characteristics of the eUSCI in SPI slave mode.
Table 5-20. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
UCLK edge to SOMI valid,
CL = 20 pF
tHD,SO
SOMI output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
56
VCC
MIN
2.2 V
45
3.0 V
40
2.2 V
2
3.0 V
3
MAX
ns
ns
2.2 V
45
3.0 V
40
2.2 V
50
3.0 V
45
2.2 V
4
3.0 V
4
2.2 V
7
3.0 V
7
35
35
3.0 V
0
ns
ns
3.0 V
0
ns
ns
2.2 V
2.2 V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-17 and Figure 5-18.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams inFigure 5-17
and Figure 5-18.
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SI
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tSTE,ACC
tSTE,DIS
tVALID,SO
SOMI
Figure 5-17. SPI Slave Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 5-18. SPI Slave Mode, CKPH = 1
Specifications
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Table 5-21 lists the characteristics of the eUSCI in I2C mode.
Table 5-21. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-19)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
TYP
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
2.2 V, 3.0 V
fSCL = 100 kHz
UNIT
16
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3.0 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3.0 V
100
ns
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
tSU,STO
Setup time for STOP
tBUF
Bus free time between STOP and START
conditions
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
tSP
2.2 V, 3.0 V
0
MAX
2.2 V, 3.0 V
2.2 V, 3.0 V
4.7
4.0
4.7
1.3
UCGLITx = 0
50
2.2 V, 3.0 V
UCGLITx = 3
µs
0.6
fSCL > 100 kHz
UCGLITx = 2
µs
0.6
fSCL = 100 kHz
UCGLITx = 1
µs
0.6
µs
250
25
125
12.5
62.5
6.3
31.5
UCCLTOx = 1
tTIMEOUT
Clock low time-out
UCCLTOx = 2
27
2.2 V, 3.0 V
30
UCCLTOx = 3
tSU,STA
tHD,STA
ns
ms
33
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-19. I2C Mode Timing
58
Specifications
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5.13.5.4 LCD Controller
Table 5-22 lists the operating conditions of the LCD_C.
Table 5-22. LCD_C, Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VCC,LCD_C,CP en,3.6
Supply voltage range,
charge pump enabled,
VLCD ≤ 3.6 V
LCDCPEN = 1, 0000b < VLCDx ≤ 1111b
(charge pump enabled, VLCD ≤ 3.6 V)
2.2
3.6
V
VCC,LCD_C,CP en,3.3
Supply voltage range,
charge pump enabled,
VLCD ≤ 3.3 V
LCDCPEN = 1, 0000b < VLCDx ≤ 1100b
(charge pump enabled, VLCD ≤ 3.3 V)
2.0
3.6
V
VCC,LCD_C,int.
bias
Supply voltage range,
internal biasing, charge
pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_C,ext.
bias
Supply voltage range,
external biasing, charge
pump disabled
LCDCPEN = 0, VLCDEXT = 0
2.4
3.6
V
VCC,LCD_C,VLCDEXT
Supply voltage range,
external LCD voltage,
internal or external
biasing, charge pump
disabled
LCDCPEN = 0, VLCDEXT = 1
2.0
3.6
V
VLCDCAP
External LCD voltage at
LCDCAP, internal or
external biasing, charge
pump disabled
LCDCPEN = 0, VLCDEXT = 1
2.4
3.6
V
CLCDCAP
Capacitor value on
LCDCAP when charge
pump enabled
LCDCPEN = 1, VLCDx > 0000b (charge
pump enabled)
fACLK,in
ACLK input frequency
range
fLCD
LCD frequency range
fFRAME = 1/(2 × mux) × fLCD with mux = 1
(static) to 8
fFRAME,4mux
LCD frame frequency
range
fFRAME,8mux
4.7-20%
4.7
10+20%
µF
30
32.768
40
kHz
1024
Hz
fFRAME,4mux(MAX) = 1/(2 × 4) × fLCD(MAX)
= 1/(2 × 4) × 1024 Hz
128
Hz
LCD frame frequency
range
fFRAME,8mux(MAX) = 1/(2 × 4) × fLCD(MAX)
= 1/(2 × 8) × 1024 Hz
64
Hz
CPanel
Panel capacitance
fLCD = 1024 Hz, all common lines equally
loaded
10000
pF
VR33
Analog input voltage at
R33
LCDCPEN = 0, VLCDEXT = 1
VCC+0.2
V
VR23,1/3bias
Analog input voltage at
R23
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR13
VR03 + 2/3
× (VR33VR03)
VR33
V
VR13,1/3bias
Analog input voltage at
R13 with 1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR03
VR03 + 1/3
× (VR33 –
VR03)
VR23
V
VR13,1/2bias
Analog input voltage at
R13 with 1/2 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1
VR03
VR03 + 1/2
× (VR33 –
VR03)
VR33
V
VR03
Analog input voltage at
R03
R0EXT = 1
VSS
VLCD-VR03
Voltage difference
between VLCD and R03
LCDCPEN = 0, R0EXT = 1
2.4
VLCDREF
External LCD reference
voltage applied at
LCDREF
VLCDREFx = 01
0.8
0
2.4
V
1.0
VCC+0.2
V
1.2
V
Specifications
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Table 5-23 lists the characteristics of the LCD_C.
Table 5-23. LCD_C Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
VLCDx = 0000, VLCDEXT = 0
VLCD,1
LCDCPEN = 1, VLCDx = 0001b
2 V to 3.6 V
VLCD,2
LCDCPEN = 1, VLCDx = 0010b
2 V to 3.6 V
2.66
VLCD,3
LCDCPEN = 1, VLCDx = 0011b
2 V to 3.6 V
2.72
VLCD,4
LCDCPEN = 1, VLCDx = 0100b
2 V to 3.6 V
2.78
VLCD,5
LCDCPEN = 1, VLCDx = 0101b
2 V to 3.6 V
2.84
VLCD,6
LCDCPEN = 1, VLCDx = 0110b
2 V to 3.6 V
2.90
VLCD,7
LCDCPEN = 1, VLCDx = 0111b
2 V to 3.6 V
2.96
LCDCPEN = 1, VLCDx = 1000b
2 V to 3.6 V
3.02
VLCD,9
LCDCPEN = 1, VLCDx = 1001b
2 V to 3.6 V
3.08
VLCD,10
LCDCPEN = 1, VLCDx = 1010b
2 V to 3.6 V
3.14
VLCD,11
LCDCPEN = 1, VLCDx = 1011b
2 V to 3.6 V
3.20
VLCD,12
LCDCPEN = 1, VLCDx = 1100b
2 V to 3.6 V
3.26
VLCD,13
LCDCPEN = 1, VLCDx = 1101b
2.2 V to 3.6 V
3.32
VLCD,14
LCDCPEN = 1, VLCDx = 1110b
2.2 V to 3.6 V
3.38
VLCD,15
LCDCPEN = 1, VLCDx = 1111b
2.2 V to 3.6 V
VLCD,7,0.8
LCD voltage with external
reference of 0.8 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b,
VLCDREF = 0.8 V
2 V to 3.6 V
2.96 ×
0.8 V
V
VLCD,7,1.0
LCD voltage with external
reference of 1.0 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b,
VLCDREF = 1.0 V
2 V to 3.6 V
2.96 ×
1.0 V
V
VLCD,7,1.2
LCD voltage with external
reference of 1.2 V
LCDCPEN = 1, VLCDx = 0111b,
VLCDREFx = 01b,
VLCDREF = 1.2 V
2.2 V to 3.6 V
2.96 ×
1.2 V
V
ΔVLCD
Voltage difference between
consecutive VLCDx settings
ΔVLCD = VLCD,x - VLCD,x-1
with x = 0010b to 1111b
ICC,Peak,CP
Peak supply currents due to
charge pump activities
LCDCPEN = 1, VLCDx = 1111b
external, with decoupling capacitor
on DVCC supply ≥ 1 µF
2.2 V
600
tLCD,CP,on
Time to charge CLCD when
discharged
CLCD = 4.7 µF, LCDCPEN = 0→1,
VLCDx = 1111b
2.2 V
100
ICP,Load
Maximum charge pump load
current
LCDCPEN = 1, VLCDx = 1111b
2.2 V
RLCD,Seg
LCD driver output impedance,
segment lines
LCDCPEN = 0, ILOAD = ±10 µA
2.2 V
10
kΩ
RLCD,COM
LCD driver output impedance,
common lines
LCDCPEN = 0, ILOAD = ±10 µA
2.2 V
10
kΩ
LCD voltage
VLCD,8
60
Specifications
2.4 V to 3.6 V
TYP
VLCD,0
VCC
2.49
3.32
40
2.60
3.44
2.72
V
3.6
60
80
mV
µA
500
50
ms
µA
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5.13.5.5 ADC
Table 5-24 lists the input requirements of the ADC.
Table 5-24. 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(Ax)
I(ADC12_B)
single-ended
mode
I(ADC12_B)
differential
mode
TEST CONDITIONS
Analog input voltage range (1)
MIN
NOM
0
MAX
UNIT
AVCC
V
145
199
(3)
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 0,
REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
3.0 V
Operating supply current into
AVCC and DVCC terminals (2)
2.2 V
140
190
175
245
(3)
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 1,
REFON = 0, ADC12SHTx= 0,
ADC12DIV = 0
3.0 V
Operating supply current into
AVCC and DVCC terminals (2)
2.2 V
170
230
2.2 V
10
15
>2 V
0.5
4
50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz.
Clocked by external clock ≤50 kHz.
Timer_B, TBx
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Ax in
UART mode
Clocked by SMCLK
Clocked by ACLK
Waiting for first edge of START bit
eUSCI_Ax in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Ax in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Bx in I2C
master mode
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Not applicable
eUSCI_Bx in I2C
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Waiting for START condition or
clocked by external clock ≤50 kHz
eUSCI_Bx in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Bx in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
ESI
Clocked by SMCLK
Clocked by ACLK or ESIOSC
Not applicable
ADC12_B
Clocked by SMCLK or by MODOSC
Clocked by ACLK
Waiting for a trigger
REF_A
Not applicable
Not applicable
Always
COMP_E
Not applicable
Not applicable
Always
(5)
Not applicable
Not applicable
Not applicable
MPY (5)
Not applicable
Not applicable
Not applicable
DMA
CRC
(1)
(2)
(3)
(4)
(5)
76
Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz.
Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.
Peripherals are in a state that does not require or does not use an internal clock.
The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power
mode will cause a temporary transition into active mode for the time of the transfer.
Operates only during active mode and will delay the transition into a low-power mode until its operation is completed.
Detailed Description
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6.3.1.1
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Idle Currents of Peripherals in LPM3 and LPM4
Most peripherals can be activated to be operational in LPM3 if clocked by ACLK. Some modules are even
operational in LPM4 because they do not require a clock to operate (for example, the comparator).
Activating a peripheral in LPM3 or LPM4 increases the current consumption due to its active supply
current contribution but also due to an additional idle current. To limit the idle current adder certain
peripherals are group together. To achieve optimal current consumption try to use modules within one
group and to limit the number of groups with active modules. Table 6-3 lists the group for each peripheral.
Modules not listed in this table are either already included in the standard LPM3 current consumption
specifications or cannot be used in LPM3 or LPM4.
The idle current adder is very small at room temperature (25°C) but increases at high temperatures
(85°C). See the IIDLE parameters in Section 5.7 for details.
Table 6-3. Peripheral Groups
GROUP A
GROUP B
GROUP C
GROUP D
Timer TA0
Timer TA1
Timer TA2
Timer TA3
Comparator
Extended Scan Interface
(ESI)
Timer B0
LCD_C
ADC12_B
eUSCI_A0
eUSCI_A1
REF_A
eUSCI_B0
eUSCI_B1
Detailed Description
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6.4
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Interrupt Vector Table and Signatures
The interrupt vectors, the power-up start address and signatures are in the address range 0FFFFh to
0FF80h. Figure 6-1 summarizes the content of this address range.
Reset Vector
0FFFFh
BSL Password
Interrupt
Vectors
0FFE0h
JTAG Password
Reserved
Signatures
0FF88h
0FF80h
Figure 6-1. Interrupt Vectors, Signatures, and Passwords
The power-up start address or reset vector is located at 0FFFFh to 0FFFEh. It contains the 16-bit address
pointing to the start address of the application program.
The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit
address of the appropriate interrupt-handler instruction sequence. Table 6-4 shows the device-specific
interrupt vector locations.
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as the BSL password
(if enabled by the corresponding signature).
The signatures are located at 0FF80h and extend to higher addresses. Signatures are evaluated during
device start-up. Table 6-5 shows the device-specific signature locations.
A JTAG password can be programmed starting at address 0FF88h and extending to higher addresses.
The password can extend into the interrupt vector locations using the interrupt vector addresses as
additional bits for the password. The length of the JTAG password depends on the JTAG signature.
See the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide for details.
78
Detailed Description
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Table 6-4. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power up, Brownout, Supply
Supervisor
External Reset RST
Watchdog time-out (watchdog
mode)
WDT, FRCTL MPU, CS, PMM
password violation
FRAM uncorrectable bit error
detection
MPU segment violation
FRAM access time error
Software POR, BOR
SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
ACCTEIFG
PMMPORIFG, PMMBORIFG
(SYSRSTIV) (1) (2)
Reset
0FFFEh
Highest
(Non)maskable
0FFFCh
System NMI
Vacant memory access
JTAG mailbox
FRAM bit error detection
MPU segment violation
(1)
(2)
(3)
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
(SYSSNIV) (1) (3)
User NMI
External NMI
Oscillator fault
NMIIFG, OFIFG
(SYSUNIV) (1) (3)
(Non)maskable
0FFFAh
Comparator_E
Comparator_E interrupt flags
(CEIV) (1)
Maskable
0FFF8h
Timer_B TB0
TB0CCR0.CCIFG
Maskable
0FFF6h
Timer_B TB0
TB0CCR1.CCIFG to TB0CCR6.CCIFG,
TB0CTL.TBIFG
(TB0IV) (1)
Maskable
0FFF4h
Watchdog timer
(interval timer mode)
WDTIFG
Maskable
0FFF2h
Extended Scan IF
ESIIFG0 to ESIIFG8
(ESIIV) (1)
Maskable
0FFF0h
eUSCI_A0 receive or transmit
UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA0IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA0IV) (1)
Maskable
0FFEEh
eUSCI_B0 receive or transmit
UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV) (1)
Maskable
0FFECh
ADC12_B
ADC12IFG0 to ADC12IFG31
ADC12LOIFG, ADC12INIFG, ADC12HIIFG,
ADC12RDYIFG, ADC12OVIFG, ADC12TOVIFG
(ADC12IV) (1)
Maskable
0FFEAh
Timer_A TA0
TA0CCR0.CCIFG
Maskable
0FFE8h
Timer_A TA0
TA0CCR1.CCIFG to TA0CCR2.CCIFG,
TA0CTL.TAIFG
(TA0IV) (1)
Maskable
0FFE6h
eUSCI_A1 receive or transmit
UCA1IFG:UCRXIFG, UCTXIFG (SPI mode)
UCA1IFG:UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
(UCA1IV) (1)
Maskable
0FFE4h
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
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Table 6-4. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
eUSCI_B1 receive or transmit)
UCB1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB1IFG: UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1,
UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3,
UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB1IV) (1)
Maskable
0FFE2h
DMA
DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,
DMA2CTL.DMAIFG
(DMAIV) (1)
Maskable
0FFE0h
Timer_A TA1
TA1CCR0.CCIFG
Maskable
0FFDEh
Timer_A TA1
TA1CCR1.CCIFG to TA1CCR2.CCIFG,
TA1CTL.TAIFG
(TA1IV) (1)
Maskable
0FFDCh
I/O Port P1
P1IFG.0 to P1IFG.7
(P1IV) (1)
Maskable
0FFDAh
Timer_A TA2
TA2CCR0.CCIFG
Maskable
0FFD8h
Timer_A TA2
TA2CCR1.CCIFG
TA2CTL.TAIFG
(TA2IV) (1)
Maskable
0FFD6h
I/O Port P2
P2IFG.0 to P2IFG.7
(P2IV) (1)
Maskable
0FFD4h
Timer_A TA3
TA3CCR0.CCIFG
Maskable
0FFD2h
Timer_A TA3
TA3CCR1.CCIFG
TA3CTL.TAIFG
(TA3IV) (1)
Maskable
0FFD0h
I/O Port P3
P3IFG.0 to P3IFG.7
(P3IV) (1)
Maskable
0FFCEh
I/O Port P4
P4IFG.0 to P4IFG.7
(P4IV) (1)
Maskable
0FFCCh
Maskable
0FFCAh
Maskable
0FFC8h
LCD_C
(Reserved on MSP430FR5xxx)
RTC_C
LCD_C interrupt flags (LCDCIV)
(1)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG
(RTCIV) (1)
PRIORITY
Lowest
Table 6-5. Signatures
SIGNATURE
WORD ADDRESS
IP Encapsulation Signature2
IP Encapsulation Signature1
(1)
80
(1)
0FF8Ah
0FF88h
BSL Signature2
0FF86h
BSL Signature1
0FF84h
JTAG Signature2
0FF82h
JTAG Signature1
0FF80h
Must not contain 0AAAAh if used as JTAG password and IP encapsulation functionality is not desired.
Detailed Description
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6.5
SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
Bootloader (BSL)
The BSL enables programming of the FRAM or RAM using a UART serial interface (FRxxxx devices) or
an I2C interface (FRxxxx1 devices). Access to the device memory through the BSL is protected by an
user-defined password. Table 6-6 lists the BSL pin requirements. BSL entry requires a specific entry
sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the features
of the BSL and its implementation, see MSP430 Programming With the Bootloader (BSL).
Table 6-6. BSL Pin Requirements and Functions
6.6
6.6.1
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P2.0
Devices with UART BSL (FRxxxx): Data transmit
P2.1
Devices with UART BSL (FRxxxx): Data receive
P1.6
Devices with I2C BSL (FRxxxx1): Data
P1.7
Devices with I2C BSL (FRxxxx1): Clock
VCC
Power supply
VSS
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/Os. The TEST/SBWTCK pin is used
to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO signal is required to
interface with MSP430 development tools and device programmers. Table 6-7 lists the JTAG pin
requirements. For details on interfacing to development tools and device programmers, see the MSP430
Hardware Tools User's Guide. For details on the JTAG implementation in MSP MCUs, see MSP430
Programming With the JTAG Interface.
Table 6-7. JTAG Pin Requirements and Functions
6.6.2
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the 2-wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 6-8
lists the Spy-Bi-Wire interface pin requirements. For details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide. For details on the SBW implementation in
MSP MCUs, see MSP430 Programming With the JTAG Interface.
Detailed Description
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Table 6-8. Spy-Bi-Wire Pin Requirements and Functions
6.7
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
VCC
Power supply
VSS
Ground supply
FRAM
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in system by the
CPU. Features of the FRAM include:
• Ultra-low-power ultra-fast-write nonvolatile memory
• Byte and word access capability
• Programmable wait state generation
• Error correction coding (ECC)
NOTE
Wait States
For MCLK frequencies > 8 MHz, wait states must be configured following the flow described
in the "FRAM Controller (FRCTRL)" chapter, section "Wait State Control" of the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
For important software design information regarding FRAM including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the memory protection unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
MSP430 FRAM Technology – How To and Best Practices.
6.8
RAM
The RAM is made up of one sector. The sector can be completely powered down in LPM3 and LPM4 to
save leakage; however, all data is lost during shutdown.
6.9
Tiny RAM
The Tiny RAM can be used to hold data or a very small stack if the complete RAM is powered down in
LPM3 and LPM4.
6.10 Memory Protection Unit Including IP Encapsulation
The FRAM can be protected from inadvertent CPU execution, read or write access by the MPU. Features
of the MPU include:
• IP Encapsulation with programmable boundaries (prevents reads from "outside" like JTAG or non-IP
software) in steps of 1KB.
• Main memory partitioning programmable up to three segments in steps of 1KB.
• The access rights of each segment (main and information memory) can be individually selected.
• Access violation flags with interrupt capability for easy servicing of access violations.
82
Detailed Description
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MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
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SLASE32C – AUGUST 2014 – REVISED AUGUST 2018
6.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430FR58xx,
MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
6.11.1 Digital I/O
Up to eleven 8-bit I/O ports are implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all pins of
ports P1, P2, P3, and P4.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• Capacitive touch functionality is supported on all pins of ports P1 to P10 and PJ.
• No cross-currents during start-up
NOTE
Configuration of Digital I/Os After BOR Reset
To prevent any cross-currents during start-up of the device all port pins are high-impedance
with Schmitt triggers and their module functions disabled. To enable the I/O functionality after
a BOR reset the ports must be configured first and then the LOCKLPM5 bit must be cleared.
For details, see the Configuration After Reset section of the Digital I/O chapter in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide.
6.11.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch crystal oscillator XT1 (LF), an internal very-lowpower low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements
of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources.
The clock system module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (LFXT1), the internal low-frequency
oscillator (VLO), or a digital external low frequency (
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