www.ti.com
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992,
MSP430FR5962
SLASE54D –MSP430FR5964,
MARCH 2016 – REVISED
JANUARY 2021
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
MSP430FR599x, MSP430FR596x Mixed-Signal Microcontrollers
1 Features
•
•
•
•
•
Embedded microcontroller
– 16-bit RISC architecture up to 16‑MHz clock
– Up to 256KB of ferroelectric random access
memory (FRAM)
• Ultra-low-power writes
• Fast write at 125 ns per word (64KB in
4 ms)
• Flexible allocation of data and application
code in memory
• 1015 write cycle endurance
• Radiation resistant and nonmagnetic
– Wide supply voltage range from 3.6 V down to
1.8 V (minimum supply voltage is restricted by
SVS levels, see the SVS specifications)
Optimized ultra-low-power modes
– Active mode: 118 µA/MHz
– Standby with VLO (LPM3): 500 nA
– Standby with real-time clock (RTC) (LPM3.5):
350 nA (the RTC is clocked by a 3.7-pF crystal)
– Shutdown (LPM4.5): 45 nA
Low-energy accelerator (LEA) for signal
processing (MSP430FR599x only)
– Operation independent of CPU
– 4KB of RAM shared with CPU
– Efficient 256-point complex FFT:
Up to 40x faster than Arm® Cortex®-M0+ core
Intelligent digital peripherals
– 32-bit hardware multiplier (MPY)
– 6-channel internal DMA
– RTC with calendar and alarm functions
– Six 16-bit timers with up to seven capture/
compare registers each
– 32- and 16-bit cyclic redundancy check (CRC)
High-performance analog
– 16-channel analog comparator
– 12-bit analog-to-digital converter (ADC)
featuring window comparator, internal reference
and sample-and-hold, up to 20 external input
channels
•
•
•
•
•
•
Multifunction input/output ports
– All pins support capacitive-touch capability with
no need for external components
– Accessible bit-, byte-, and word-wise (in pairs)
– Edge-selectable wake from LPM on all ports
– Programmable pullup and pulldown on all ports
Code security and encryption
– 128- or 256-bit AES security encryption and
decryption coprocessor
– Random number seed for random number
generation algorithms
– IP encapsulation protects memory from
external access
Enhanced serial communication
– Up to four eUSCI_A serial communication ports
• UART with automatic baud-rate detection
• IrDA encode and decode
– Up to four eUSCI_B serial communication ports
• I2C with multiple-slave addressing
– Hardware UART or I2C bootloader (BSL)
Flexible clock system
– Fixed-frequency DCO with 10 selectable
factory-trimmed frequencies
– Low-power low-frequency internal clock source
(VLO)
– 32-kHz crystals (LFXT)
– High-frequency crystals (HFXT)
Development tools and software (also see Tools
and Software)
– Development kits (MSP-EXP430FR5994
LaunchPad™ development kit and
MSP‑TS430PN80B target socket board)
– MSP430Ware™ software for MSP430™
microcontrollers
Device Comparison summarizes the available
devices
2 Applications
•
•
•
•
•
Grid infrastructure
Factory automation & control
Building automation
Wearable fitness & activity monitor
Wearable electronics
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
Submit
Document
Feedback
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
1
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
www.ti.com
3 Description
The MSP430FR599x microcontrollers (MCUs) take low power and performance to the next level with the unique
low-energy accelerator (LEA) for digital signal processing. This accelerator delivers 40x the performance of
Arm® Cortex®-M0+ MCUs to help developers efficiently process data using complex functions such as FFT, FIR,
and matrix multiplication. Implementation requires no DSP expertise with a free optimized DSP Library available.
Additionally, with up to 256KB of unified memory with FRAM, these devices offer more space for advanced
applications and flexibility for effortless implementation of over-the-air firmware updates.
The MSP ultra-low-power (ULP) FRAM microcontroller platform combines uniquely embedded FRAM and a
holistic ultra-low-power system architecture, allowing system designers to increase performance while lowering
energy consumption. FRAM technology combines the low-energy fast writes, flexibility, and endurance of RAM
with the nonvolatile behavior of flash.
MSP430FR599x MCUs are supported by an extensive hardware and software ecosystem with reference designs
and code examples to get your design started quickly. Development kits for the MSP430FR599x include the
MSP-EXP430FR5994 LaunchPad™ development kit and the MSP-TS430PN80B 80-pin target development
board. TI also provides free MSP430Ware™ software, which is available as a component of Code Composer
Studio™ IDE desktop and cloud versions within TI Resource Explorer.
For complete module descriptions, see the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's
Guide.
Device Information
PART NUMBER (1) (2)
MSP430FR5994IZVW
BODY SIZE(3)
NFBGA (87)
6 mm × 6 mm
MSP430FR5994IPN
LQFP (80)
12 mm × 12 mm
MSP430FR5994IPM
LQFP (64)
10 mm × 10 mm
MSP430FR5994IRGZ
VQFN (48)
7 mm × 7 mm
(1)
(2)
(3)
2
PACKAGE
For the most current part, package, and ordering information for all available devices, see the
Package Option Addendum in Section 12, or see the TI website at www.ti.com.
For a comparison of all available device variants, see Section 6.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 12.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
4 Functional Block Diagram
Figure 4-1 shows the functional block diagram of the devices.
P1.x, P2.x
LFXIN,
HFXIN
2x8
LFXOUT,
HFXOUT
P3.x, P4.x
P5.x, P6.x
2x8
2x8
P7.x, P8.x
2x8
PJ.x
1x8
Capacitive Touch I/O 0, Capacitive Touch I/O 1
ADC12_B
MCLK
ACLK
Comp_E
SMCLK
(up to 16
inputs)
Clock
System
(up to 16
standard
inputs,
up to 8
differential
inputs)
DMA
Controller
REF_A
Voltage
Reference
I/O Ports
P1, P2
2x8 I/Os
I/O Ports
P3, P4
2x8 I/Os
I/O Ports
P5, P6
2x8 I/Os
I/O Ports
P7, P8
2x8 I/Os
PA
1x16 I/Os
PB
1x16 I/Os
PC
1x16 I/Os
PD
1x16 I/Os
I/O Port
PJ
1x8 I/Os
6 channels
Bus
Control
Logic
MAB
MDB
CPUXV2
with 16
registers
MPU
IP Encap
FRCTL_A
256KB
128KB
EEM
(S3+1)
:
RAM
4KB + 4KB
Tiny RAM
22B
CRC16
Power
Management
LDO
SVS
Brownout
CRC-16CCITT
TA2(int)
TA3(int)
Timer_A
2 CC
Registers
AES256
MPY32
CRC32
CRC-32ISO-3309
Security
Encryption,
Decryption
(128, 256)
Watchdog
MDB
JTAG
Interface
MAB
Spy-Bi-Wire
LEA
Subsystem
TB0
TA0
TA1
TA4
Timer_B
7 CC
Registers
(int, ext)
Timer_A
3 CC
Registers
(int, ext)
Timer_A
3 CC
Registers
(int, ext)
Timer_A
2 CC
Registers
(int, ext)
eUSCI_A0
eUSCI_A1
eUSCI_A2
eUSCI_A3
(UART,
IrDA, SPI)
eUSCI_B0
eUSCI_B1
eUSCI_B2
eUSCI_B3
RTC_C
2
(I C, SPI)
LPM3.5 Domain
A. The device has 8KB of RAM, and 4KB of the RAM is shared with the LEA subsystem. The CPU has priority over the LEA subsystem.
B. The LEA subsystem is available on the MSP430FR599x MCUs only.
Figure 4-1. Functional Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
3
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 5
6 Device Comparison......................................................... 7
6.1 Related Products........................................................ 8
7 Terminal Configuration and Functions..........................9
7.1 Pin Diagrams.............................................................. 9
7.2 Pin Attributes.............................................................14
7.3 Signal Descriptions................................................... 20
7.4 Pin Multiplexing.........................................................28
7.5 Buffer Types..............................................................28
7.6 Connection of Unused Pins...................................... 28
8 Specifications................................................................ 29
8.1 Absolute Maximum Ratings...................................... 29
8.2 ESD Ratings............................................................. 29
8.3 Recommended Operating Conditions.......................30
8.4 Active Mode Supply Current Into VCC Excluding
External Current.......................................................... 31
8.5 Typical Characteristics, Active Mode Supply
Currents.......................................................................32
8.6 Low-Power Mode (LPM0, LPM1) Supply
Currents Into VCC Excluding External Current............ 32
8.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply
Currents (Into VCC) Excluding External Current.......... 33
8.8 Low-Power Mode (LPMx.5) Supply Currents
(Into VCC) Excluding External Current......................... 35
8.9 Typical Characteristics, Low-Power Mode
Supply Currents...........................................................36
8.10 Typical Characteristics, Current Consumption
per Module.................................................................. 37
8.11 Thermal Packaging Characteristics........................ 37
8.12 Timing and Switching Characteristics..................... 38
9 Detailed Description......................................................66
4
Submit Document Feedback
9.1 Overview................................................................... 66
9.2 CPU.......................................................................... 66
9.3 Low-Energy Accelerator (LEA) for Signal
Processing (MSP430FR599x Only)............................ 66
9.4 Operating Modes...................................................... 67
9.5 Interrupt Vector Table and Signatures.......................70
9.6 Bootloader (BSL)...................................................... 73
9.7 JTAG Operation........................................................ 74
9.8 FRAM Controller A (FRCTL_A)................................ 75
9.9 RAM.......................................................................... 75
9.10 Tiny RAM................................................................ 75
9.11 Memory Protection Unit (MPU) Including IP
Encapsulation..............................................................75
9.12 Peripherals..............................................................76
9.13 Input/Output Diagrams............................................86
9.14 Device Descriptors (TLV)...................................... 124
9.15 Memory Map......................................................... 127
9.16 Identification..........................................................147
10 Applications, Implementation, and Layout............. 148
10.1 Device Connection and Layout Fundamentals..... 148
10.2 Peripheral- and Interface-Specific Design
Information................................................................ 151
11 Device and Documentation Support........................153
11.1 Getting Started...................................................... 153
11.2 Device Nomenclature............................................153
11.3 Tools and Software................................................154
11.4 Documentation Support........................................ 156
11.5 Related Links........................................................ 157
11.6 Support Resources............................................... 157
11.7 Trademarks........................................................... 157
11.8 Electrostatic Discharge Caution............................ 158
11.9 Export Control Notice............................................ 158
11.10 Glossary.............................................................. 158
12 Mechanical, Packaging, and Orderable
Information.................................................................. 159
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from revision C to revision D
Changes from August 31, 2018 to January 15, 2021
Page
• Updated the numbering format for tables, figures, and cross references throughout the document..................1
• Format updates and corrections to external links as needed............................................................................. 1
• Changed the column "FRAM Program + Information (KB)" in Section 6, Device Comparison ..........................7
• Added ball L5 to the COUT signal on the ZVW package in Section 7.3, Signal Descriptions ......................... 20
• Added the note that begins "XT1CLK and VLOCLK can be active during LPM4..." ........................................67
• Added the INTERRUPT VECTOR REGISTER column, moved register names from the INTERRUPT FLAG
column, and corrected interrupt flag names as necessary in Table 9-4, Interrupt Sources, Flags, Vectors, and
Signatures ........................................................................................................................................................70
• Corrected the interrupt flags for Port 4 to Port 8 in Table 9-4, Interrupt Sources, Flags, and Vectors .............70
• Corrected the note on the P1DIR.x column for the UCB0SOMI/UCB0SCL row (changed eUSCI_A0 to
eUSCI_B0) in Table 9-22, Port P1 (P1.6 and P1.7) Pin Functions .................................................................. 91
• Corrected the value of P5SEL1.5 (changed from 0 to 1) and P5SEL0.5 (from 1 to 0) for the N/A and DVSS
rows on P5.5 in Table 9-31, Port P5 (P5.0 to P5.7) Pin Functions ................................................................ 106
• Corrected eUSCI module in the note "Direction controlled by eUSCI_B1 module" (changed from eUSCI_B0 to
eUSCI_B1) .....................................................................................................................................................106
Changes from revision B to revision C
Changes from February 1, 2017 to August 30, 2018
Page
• Updated Section 6.1, Related Products .............................................................................................................8
• Added note (1) to Section 8.12.1.2, SVS .........................................................................................................38
• Corrected the value of P6SEL1.x (changed from 0 to 1) for the N/A and DVSS rows on P6.5, P6.6, and P6.7
in Table 9-32, Port P6 (P6.0 to P6.7) Pin Functions ...................................................................................... 108
• Changed capacitor value from 4.7 µF to 470 nF in Figure 10-5, ADC12_B Grounding and Noise
Considerations ...............................................................................................................................................151
• Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of Section 10.2.1.2, Design
Requirements ................................................................................................................................................ 151
• Updated text and figure in Section 11.2, Device Nomenclature .................................................................... 153
Changes from revision A to revision B
Changes from October 18, 2016 to January 31, 2017
Page
• Changed document status from Advance Information to Production Data.........................................................1
• Updated all electrical and timing specifications and typical characteristics graphs with production data.........29
Changes from initial release to revision A
Changes from March 17, 2016 to October 17, 2016
Page
• Changed from 35x Faster to Up to 40x Faster in the list item that starts "Efficient 256-Point Complex FFT..." in
Section 1, Features ............................................................................................................................................1
• Added Section 6.1, Related Products ................................................................................................................8
• Added second row to tSample parameter in Section 8.12.9.2, 12-Bit ADC, Timing Parameters ....................... 58
• Removed ADC12DIV from equation for the tCONVERT TYP time, because ADC12CLK is after division...........58
• Added "RS < 10 kΩ" to the note that starts "Approximately 10 Tau (τ) are needed..." on Section 8.12.9.2, 12Bit ADC, Timing Parameters ............................................................................................................................58
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
5
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
•
6
www.ti.com
Changed from "If the RST/NMI pin is unused...with a 2.2-nF pulldown capacitor" to "If the RST/NMI pin is
unused...with a 10-nF pulldown capacitor" in Section 10.1.4, Reset ............................................................. 150
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
6 Device Comparison
Table 6-1 summarizes the available family members.
Table 6-1. Device Comparison
DEVICE (1) (2)
FRAM
Program +
Information
(KB)
SRAM
(KB)
CLOCK
SYSTEM
LEA
ADC12_B
(Channels)
eUSCI_A(5)
eUSCI_B (6)
4
4
3
3
16 external,
2 internal
2
20 external,
2 internal
Comp_E
Timer_A (3)
Timer_B (4)
I/Os
PACKAGE
68
80 PN (LQFP)
87 ZVW (NFBGA)
54
64 PM (LQFP)
1
40
48 RGZ (VQFN)
4
4
68
80 PN (LQFP)
87 ZVW (NFBGA)
3
3
54
64 PM (LQFP)
16 external,
2 internal
2
1
40
48 RGZ (VQFN)
20 external,
2 internal
4
4
68
80 PN (LQFP)
87 ZVW (NFBGA)
3
3
54
64 PM (LQFP)
16 external,
2 internal
2
1
40
48 RGZ (VQFN)
20 external,
2 internal
4
4
68
80 PN (LQFP)
87 ZVW (NFBGA)
3
3
54
64 PM (LQFP)
16 external,
2 internal
2
1
40
48 RGZ (VQFN)
20 external,
2 internal
4
4
68
80 PN (LQFP)
87 ZVW (NFBGA)
3
3
54
64 PM (LQFP)
2
1
40
48 RGZ (VQFN)
20 external,
2 internal
MSP430FR5994
MSP430FR5992
MSP430FR5964
MSP430FR5962
MSP430FR59941
256 + 0.5
128 + 0.5
256 + 0.5
128 + 0.5
256 + 0.5
DCO
HFXT
LFXT
8
DCO
HFXT
LFXT
8
DCO
HFXT
LFXT
8
DCO
HFXT
LFXT
8
DCO
HFXT
LFXT
8
Yes
Yes
No
No
Yes
17 external,
2 internal
17 external,
2 internal
17 external,
2 internal
17 external,
2 internal
17 external,
2 internal
16 external,
2 internal
(1)
(2)
(3)
16 ch.
16 ch.
16 ch.
16 ch.
16 ch.
3, 3 (7)
2, 2,2 (8)
3, 3 (7)
2, 2,2 (8)
3, 3 (7)
2, 2,2 (8)
3, 3 (7)
2, 2,2 (8)
3, 3 (7)
2, 2,2 (8)
7
7
7
7
7
AES
Yes
Yes
Yes
Yes
Yes
BSL
UART
UART
UART
UART
I2C
For the most current package and ordering information, see the Package Option Addendum in Section 12, or see the TI website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 capture/compare registers and PWM output generators and the second
instantiation having 5 capture/compare registers and PWM output generators, respectively.
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
Submit Document Feedback
7
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
(4)
(5)
(6)
(7)
(8)
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 capture/compare registers and PWM output generators and the second
instantiation having 5 capture/compare registers and PWM output generators, respectively.
eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
eUSCI_B supports I2C with multiple slave addresses and SPI.
Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any). Timer TA4 provides internal and external capture/compare inputs and internal
and external PWM outputs.
Note: TA4 in the RGZ package provides only internal capture/compare inputs and only internal PWM outputs.
6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power sensing & measurement MCUs
One platform. One ecosystem. Endless possibilities.
Reference designs for MSP430FR5994
Find reference designs leveraging the best in TI technology – from analog and power management to embedded processors.
8
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
7 Terminal Configuration and Functions
7.1 Pin Diagrams
Figure 7-1 shows the bottom view of the pinout of the 87-pin ZVW package, and Figure 7-2 shows the top view
of the pinout.
DVSS1 DVCC1 DGND
DGND
P2.0
P2.1
P8.1
P3.5
P1.6
P5.0
P5.3
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
P2.2
P8.2
P3.4
P1.7
P5.1
P5.2
P4.6
DGND
P2.4
K3
K4
K5
K6
K7
K8
K9
K10
K11
P5.4
P2.3
DVCC3 DGND
K1
K2
DVSS3 RST
J1
J2
P2.6
TST
J10
J11
P8.3
P3.6
P3.7
P4.4
P4.5
P5.5
HFIN
H5
H6
H7
H8
H10
H11
H1
H2
H4
P4.2
P4.3
P2.5
P5.7
G1
G2
G4
G8
G10
G11
P4.0
P7.7
P4.1
P6.4
P6.5
F1
F2
F4
F8
F10
P2.7
F11
P7.4
P7.5
P7.6
P6.6
E1
E2
E4
E8
AVSS3 LFIN
E11
E10
P7.2
PJ.3
P7.3
P8.0
P4.7
P6.1
P6.0
AVSS2 LFOUT
D1
D2
D4
D5
D6
D7
D8
PJ.1
PJ.2
C1
C2
P5.6 HFOUT
D10
D11
P6.7 AVSS1
C10
C11
PJ.0
P1.4
P1.5
P7.1
P6.3
P3.2
P3.1
P1.2
B1
B3
B4
B5
B6
B7
B8
B9
B10
B11
P7.0
P6.2
P3.3
P3.0
P1.1
P1.0
AGND
A5
A6
A7
A8
A9
A10
A11
DGND DVSS2 DVCC2 P1.3
A1
A2
A3
A4
AGND AVCC1
On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 7-1. 87-Pin ZVW Package (Bottom View)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
9
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
DGND DVCC1 DVSS1 P5.3
L11
L10
L9
L8
P5.0
P1.6
P3.5
P8.1
P2.1
P2.0
DGND
L7
L6
L5
L4
L3
L2
L1
P8.2
P2.2
K4
K3
P2.4
DGND
P4.6
P5.2
P5.1
P1.7
P3.4
K11
K10
K9
K8
K7
K6
K5
P2.3
J11
HFIN
P5.5
H11
H10
DGND DVCC3
K2
K1
P5.4
RST
DVSS3
J10
J2
J1
TST
P2.6
HFOUT P5.6
P4.5
P4.4
P3.7
P3.6
H8
H7
H6
H5
P8.3
H4
H2
H1
P5.7
P2.5
P4.3
P4.2
G11
G10
G8
G4
G2
G1
P2.7
F11
P6.5
P6.4
P4.1
P7.7
P4.0
F10
F8
F4
F2
F1
LFIN AVSS3
E11
E10
P6.6
P7.6
P7.5
P7.4
E8
E4
E2
E1
LFOUT AVSS2
P6.0
P6.1
P4.7
P8.0
P7.3
PJ.3
P7.2
D8
D7
D6
D5
D4
D2
D1
D11
D10
AVSS1
C11
P6.7
PJ.2
PJ.1
C10
C2
C1
P1.2
P3.1
P3.2
P6.3
P7.1
P1.5
P1.4
PJ.0
B11
B10
B9
B8
B7
B6
B5
B4
B3
B1
L1
AGND
P1.0
P1.1
P3.0
P3.3
P6.2
P7.0
A11
A10
A9
A8
A7
A6
A5
AVCC1 AGND
P1.3 DVCC2 DVSS2 DGND
A4
A3
A2
A1
Figure 7-2. 87-Pin ZVW Package (Top View)
10
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
DVCC1
P2.7
P2.3/TA0.0/UCA1STE/A6/C10
P5.4/UCA2TXD/UCA2SIMO/TB0OUTH
P2.4/TA1.0/UCA1CLK/A7/C11
P5.5/UCA2RXD/UCA2SOMI/ACLK
P5.6/UCA2CLK/TA4.0/SMCLK
P6.4/UCB3SIMO/UCB3SDA
P5.7/UCA2STE/TA4.1/MCLK
P6.6/UCB3CLK
P6.5/UCB3SOMI/UCB3SCL
AVSS3
P6.7/UCB3STE
PJ.6/HFXIN
AVSS2
PJ.7/HFXOUT
PJ.4/LFXIN
AVSS1
PJ.5/LFXOUT
AVCC1
Figure 7-3 shows the pinout of the 80-pin PN package.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
1
53
P5.0/UCB1SIMO/UCB1SDA
9
52
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P6.2/UCA3CLK
10
51
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P6.3/UCA3STE
11
50
P3.7/TB0.6
P4.7
12
49
P3.6/TB0.5
P7.0/UCB2SIMO/UCB2SDA
13
48
P3.5/TB0.4/COUT
P7.1/UCB2SOMI/UCB2SCL
14
47
P3.4/TB0.3/SMCLK
P8.0
15
46
P8.3
P1.3/TA1.2/UCB0STE/A3/C3
16
45
P8.2
P1.4/TB0.1/UCA0STE/A4/C4
17
44
P8.1
P1.5/TB0.2/UCA0CLK/A5/C5
18
43
P2.2/TB0.2/UCB0CLK
DVSS2
19
42
P2.1/TB0.0/UCA0RXD/UCA0SOMI
DVCC2
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
DVCC3
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
DVSS3
8
P6.1/UCA3RXD/UCA3SOMI
RST/NMI/SBWTDIO
P5.2/UCB1CLK/TA4CLK
P5.1/UCB1SOMI/UCB1SCL
TEST/SBWTCK
54
P2.6/TB0.1/UCA1RXD/UCA1SOMI
55
7
P4.3/A11
6
P3.3/A15/C15
P6.0/UCA3TXD/UCA3SIMO
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P3.2/A14/C14
P4.1/A9
P5.3/UCB1STE
P4.2/A10
56
P4.0/A8
5
P7.7/A19
P4.4/TB0.5
P3.1/A13/C13
P7.6/A18
P4.5
57
P7.5/A17
58
4
P7.4/TA4.0/A16
3
P3.0/A12/C12
P7.3/UCB2STE/TA4.1
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P7.2/UCB2CLK
DVSS1
P4.6
PJ.3/TCK/SRCPUOFF/C9
59
PJ.2/TMS/ACLK/SROSCOFF/C8
2
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 7-3. 80-Pin PN Package (Top View)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
11
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
DVCC1
P2.7
P2.3/TA0.0/UCA1STE/A6/C10
P5.4/UCA2TXD/UCA2SIMO/TB0OUTH
P2.4/TA1.0/UCA1CLK/A7/C11
P5.5/UCA2RXD/UCA2SOMI/ACLK
P5.6/UCA2CLK/TA4.0/SMCLK
AVSS3
P5.7/UCA2STE/TA4.1/MCLK
PJ.6/HFXIN
AVSS2
PJ.7/HFXOUT
PJ.4/LFXIN
AVSS1
PJ.5/LFXOUT
AVCC1
Figure 7-4 shows the pinout of the 64-pin PM package.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
1
48
DVSS1
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
2
47
P4.6
P1.2/TA1.1/TA0CLK/COUT/A2/C2
3
46
P4.5
P3.0/A12/C12
4
45
P4.4/TB0.5
P3.1/A13/C13
5
44
P5.3/UCB1STE
P3.2/A14/C14
6
43
P5.2/UCB1CLK/TA4CLK
P3.3/A15/C15
7
42
P5.1/UCB1SOMI/UCB1SCL
36
P3.5/TB0.4/COUT
P1.5/TB0.2/UCA0CLK/A5/C5
14
35
P3.4/TB0.3/SMCLK
DVSS2
15
34
P2.2/TB0.2/UCB0CLK
DVCC2
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P2.1/TB0.0/UCA0RXD/UCA0SOMI
P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
TEST/SBWTCK
13
RST/NMI/SBWTDIO
P3.6/TB0.5
P1.4/TB0.1/UCA0STE/A4/C4
P2.6/TB0.1/UCA1RXD/UCA1SOMI
37
P2.5/TB0.0/UCA1TXD/UCA1SIMO
12
P4.3/A11
P3.7/TB0.6
P1.3/TA1.2/UCB0STE/A3/C3
P4.2/A10
38
P4.1/A9
11
P4.0/A8
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P8.0
P7.4//TA4.0/A16
39
P7.3/UCB2STE/TA4.1
10
P7.2/UCB2CLK
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P7.1/UCB2SOMI/UCB2SCL
PJ.3/TCK/SRCPUOFF/C9
P5.0/UCB1SIMO/UCB1SDA
40
PJ.2/TMS/ACLK/SROSCOFF/C8
41
9
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7
8
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
P4.7
P7.0/UCB2SIMO/UCB2SDA
On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 7-4. 64-Pin PM Package (Top View)
12
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
www.ti.com
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
DVCC1
P2.7
P2.3/TA0.0/UCA1STE/A6/C10
P2.4/TA1.0/UCA1CLK/A7/C11
AVSS
PJ.6/HFXIN
PJ.7/HFXOUT
AVSS
PJ.4/LFXIN
PJ.5/LFXOUT
AVSS1
AVCC1
Figure 7-5 shows the pinout of the 48-pin RGZ package.
48 47 46 45 44 43 42 41 40 39 38 37
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
1
36
DVSS1
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
2
35
P4.6
P1.2/TA1.1/TA0CLK/COUT/A2/C2
3
34
P4.5
P3.0/A12/C12
4
33
P4.4/TB0.5
P3.1/A13/C13
5
32
P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0
P3.2/A14/C14
6
31
P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0
P3.3/A15/C15
7
30
P3.7/TB0.6
P4.7
8
29
P3.6/TB0.5
P1.3/TA1.2/UCB0STE/A3/C3
9
28
P3.5/TB0.4/COUT
P1.4/TB0.1/UCA0STE/A4/C4
10
27
P3.4/TB0.3/SMCLK
P1.5/TB0.2/UCA0CLK/A5/C5
11
26
P2.2/TB0.2/UCB0CLK
P2.1/TB0.0/UCA0RXD/UCA0SOMI
P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.6/TB0.1/UCA1RXD/UCA1SOMI
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P4.3/A11
P4.2/A10
P4.1/A9
P4.0/A8
PJ.3/TCK/SRCPUOFF/C9
PJ.2/TMS/ACLK/SROSCOFF/C8
12
25
13 14 15 16 17 18 19 20 21 22 23 24
PJ.1/TDI/TCLK/MCLK/SRSCG0/C7
PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6
TI recommends connecting the QFN thermal pad to VSS.
On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 7-5. 48-Pin RGZ Package (Top View)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
13
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
7.2 Pin Attributes
Table 7-1 summarizes the attributes of the pins.
Table 7-1. Pin Attributes
PIN NUMBER (1)
PN
1
2
3
4
5
6
7
8
9
14
PM
1
2
3
4
5
6
7
–
–
RGZ
1
2
3
4
5
6
7
–
–
ZVW
A10
A9
B9
A8
B8
B7
A7
D8
D7
Submit Document Feedback
SIGNAL TYPE (4)
BUFFER TYPE
(5)
POWER
SOURCE (6)
RESET STATE
AFTER BOR (7)
P1.0
I/O
LVCMOS
DVCC
OFF
TA0.1
I/O
LVCMOS
DVCC
–
DMAE0
I
LVCMOS
DVCC
–
RTCCLK
O
LVCMOS
DVCC
–
A0
I
Analog
DVCC
–
C0
I
Analog
DVCC
–
VREF-
O
Analog
DVCC
–
VeREF-
I
Analog
DVCC
–
SIGNAL NAME (2) (3)
P1.1
I/O
LVCMOS
DVCC
OFF
TA0.2
I/O
LVCMOS
DVCC
–
TA1CLK
I
LVCMOS
DVCC
–
COUT
O
LVCMOS
DVCC
–
A1
I
Analog
DVCC
–
C1
I
Analog
DVCC
–
VREF+
O
Analog
DVCC
–
VeREF+
I
Analog
DVCC
–
P1.2
I/O
LVCMOS
DVCC
OFF
TA1.1
I/O
LVCMOS
DVCC
–
TA0CLK
I
LVCMOS
DVCC
–
COUT
O
LVCMOS
DVCC
–
A2
I
Analog
DVCC
–
C2
I
Analog
DVCC
–
P3.0
I/O
LVCMOS
DVCC
OFF
A12
I
Analog
DVCC
–
C12
I
Analog
DVCC
–
P3.1
I/O
LVCMOS
DVCC
–
A13
I
Analog
DVCC
–
C13
I
Analog
DVCC
–
P3.2
I/O
LVCMOS
DVCC
OFF
A14
I
Analog
DVCC
–
C14
I
Analog
DVCC
–
P3.3
I/O
LVCMOS
DVCC
OFF
A15
I
Analog
DVCC
–
C15
I
Analog
DVCC
–
P6.0
I/O
LVCMOS
DVCC
OFF
UCA3TXD
O
LVCMOS
DVCC
–
UCA3SIMO
I/O
LVCMOS
DVCC
–
P6.1
I/O
LVCMOS
DVCC
OFF
UCA3RXD
I
LVCMOS
DVCC
–
UCA3SOMI
I/O
LVCMOS
DVCC
–
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 7-1. Pin Attributes (continued)
PIN NUMBER (1)
PN
PM
RGZ
ZVW
10
–
–
A6
11
–
–
B6
12
8
8
D6
13
9
–
A5
14
10
–
B5
15
11
–
D5
16
12
9
A4
SIGNAL TYPE (4)
BUFFER TYPE
(5)
POWER
SOURCE (6)
RESET STATE
AFTER BOR (7)
P6.2
I/O
LVCMOS
DVCC
OFF
UCA3CLK
I/O
LVCMOS
DVCC
–
P6.3
I/O
LVCMOS
DVCC
OFF
UCA3STE
I/O
LVCMOS
DVCC
–
P4.7
I/O
LVCMOS
DVCC
OFF
P7.0
I/O
LVCMOS
DVCC
OFF
UCB2SIMO
I/O
LVCMOS
DVCC
–
UCB2SDA
I/O
LVCMOS
DVCC
–
P7.1
I/O
LVCMOS
DVCC
OFF
UCB2SOMI
I/O
LVCMOS
DVCC
–
UCB2SCL
I/O
LVCMOS
DVCC
–
P8.0
I/O
LVCMOS
DVCC
OFF
P1.3
I/O
LVCMOS
DVCC
OFF
TA1.2
I/O
LVCMOS
DVCC
–
UCB0STE
I/O
LVCMOS
DVCC
–
I
Analog
DVCC
–
SIGNAL NAME (2) (3)
A3
C3
17
18
13
14
10
11
B3
B4
I
Analog
DVCC
–
P1.4
I/O
LVCMOS
DVCC
OFF
TB0.1
I/O
LVCMOS
DVCC
–
UCA0STE
I/O
LVCMOS
DVCC
–
A4
I
Analog
DVCC
–
C4
I
Analog
DVCC
–
P1.5
I/O
LVCMOS
DVCC
OFF
TB0.2
I/O
LVCMOS
DVCC
–
UCA0CLK
I/O
LVCMOS
DVCC
–
I
Analog
DVCC
–
A5
C5
I
Analog
DVCC
–
19
15
–
A2
DVSS2
P
Power
–
N/A
20
16
–
A3
DVCC2
P
Power
–
N/A
PJ.0
I/O
LVCMOS
DVCC
OFF
TDO
O
LVCMOS
DVCC
–
21
22
17
18
12
13
B1
C1
TB0OUTH
I
LVCMOS
DVCC
–
SMCLK
O
LVCMOS
DVCC
–
SRSCG1
O
LVCMOS
DVCC
–
C6
I
Analog
DVCC
–
PJ.1
I/O
LVCMOS
DVCC
OFF
TDI
I
LVCMOS
DVCC
–
TCLK
I
LVCMOS
DVCC
–
MCLK
O
LVCMOS
DVCC
–
SRSCG0
O
LVCMOS
DVCC
–
C7
I
Analog
DVCC
–
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
15
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 7-1. Pin Attributes (continued)
PIN NUMBER (1)
PN
23
PM
19
RGZ
14
ZVW
C2
SIGNAL TYPE (4)
BUFFER TYPE
(5)
POWER
SOURCE (6)
RESET STATE
AFTER BOR (7)
PJ.2
I/O
LVCMOS
DVCC
OFF
TMS
I
LVCMOS
DVCC
–
ACLK
O
LVCMOS
DVCC
–
SROSCOFF
O
LVCMOS
DVCC
–
SIGNAL NAME (2) (3)
C8
I
Analog
DVCC
–
I/O
LVCMOS
DVCC
OFF
TCK
I
LVCMOS
DVCC
–
SRCPUOFF
O
LVCMOS
DVCC
–
PJ.3
24
20
15
D2
C9
25
26
27
28
29
30
31
32
21
22
23
–
–
–
24
25
–
–
–
–
–
–
16
17
D1
D4
E1
E2
E4
F2
F1
F4
33
26
18
G1
34
27
19
G2
35
36
28
29
20
21
G4
H1
37
30
22
H2
38
31
23
J2
I
Analog
DVCC
–
P7.2
I/O
LVCMOS
DVCC
OFF
UCB2CLK
I/O
LVCMOS
DVCC
–
P7.3
I/O
LVCMOS
DVCC
OFF
UCB2STE
I/O
LVCMOS
DVCC
–
TA4.1
I/O
LVCMOS
DVCC
–
P7.4
I/O
LVCMOS
DVCC
OFF
TA4.0
I/O
LVCMOS
DVCC
–
A16
I
Analog
DVCC
–
P7.5
I/O
LVCMOS
DVCC
OFF
A17
I
Analog
DVCC
–
P7.6
I/O
LVCMOS
DVCC
OFF
A18
I
Analog
DVCC
–
P7.7
I/O
LVCMOS
DVCC
OFF
A19
I
Analog
DVCC
–
P4.0
I/O
LVCMOS
DVCC
OFF
A8
P4.1
A9
Submit Document Feedback
Analog
DVCC
–
LVCMOS
DVCC
OFF
I
Analog
DVCC
–
P4.2
I/O
LVCMOS
DVCC
OFF
A10
I
Analog
DVCC
–
P4.3
I/O
LVCMOS
DVCC
OFF
A11
I
Analog
DVCC
–
P2.5
I/O
LVCMOS
DVCC
OFF
TB0.0
I/O
LVCMOS
DVCC
–
UCA1TXD
O
LVCMOS
DVCC
–
UCA1SIMO
I/O
LVCMOS
DVCC
–
P2.6
I/O
LVCMOS
DVCC
OFF
TB0.1
O
LVCMOS
DVCC
–
UCA1RXD
I
LVCMOS
DVCC
–
UCA1SOMI
I/O
LVCMOS
DVCC
–
TEST
I
LVCMOS
DVCC
OFF
SBWTCK
I
LVCMOS
DVCC
–
RST
I
LVCMOS
DVCC
OFF
NMI
I
LVCMOS
DVCC
–
I/O
LVCMOS
DVCC
–
SBWTDIO
16
I
I/O
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 7-1. Pin Attributes (continued)
PIN NUMBER (1)
PN
PM
RGZ
39
–
–
J1
40
–
–
K1
41
32
24
ZVW
L2
SIGNAL TYPE (4)
BUFFER TYPE
(5)
POWER
SOURCE (6)
RESET STATE
AFTER BOR (7)
DVSS3
P
Power
–
N/A
DVCC3
P
Power
–
N/A
P2.0
I/O
LVCMOS
DVCC
OFF
TB0.6
I/O
LVCMOS
DVCC
–
UCA0TXD
O
LVCMOS
DVCC
–
BSLTX
O
LVCMOS
DVCC
–
UCA0SIMO
I/O
LVCMOS
DVCC
–
I
LVCMOS
DVCC
–
ACLK
O
LVCMOS
DVCC
–
P2.1
I/O
LVCMOS
DVCC
OFF
TB0.0
I/O
LVCMOS
DVCC
–
I
LVCMOS
DVCC
–
SIGNAL NAME (2) (3)
TB0CLK
42
33
25
L3
UCA0RXD
BSLRX
I
LVCMOS
DVCC
–
UCA0SOMI
I/O
LVCMOS
DVCC
–
P2.2
I/O
LVCMOS
DVCC
OFF
TB0.2
O
LVCMOS
DVCC
–
43
34
26
K3
UCB0CLK
I/O
LVCMOS
DVCC
–
44
–
–
L4
P8.1
I/O
LVCMOS
DVCC
OFF
45
–
–
K4
P8.2
I/O
LVCMOS
DVCC
OFF
46
–
–
H4
P8.3
I/O
LVCMOS
DVCC
OFF
P3.4
I/O
LVCMOS
DVCC
OFF
47
35
27
K5
TB0.3
I/O
LVCMOS
DVCC
–
48
49
50
51
52
36
37
38
39
40
28
29
30
31
32
L5
H5
H6
L6
K6
SMCLK
O
LVCMOS
DVCC
–
P3.5
I/O
LVCMOS
DVCC
OFF
TB0.4
I/O
LVCMOS
DVCC
–
COUT
O
LVCMOS
DVCC
–
P3.6
I/O
LVCMOS
DVCC
OFF
TB0.5
I/O
LVCMOS
DVCC
–
P3.7
I/O
LVCMOS
DVCC
OFF
TB0.6
I/O
LVCMOS
DVCC
–
P1.6
I/O
LVCMOS
DVCC
OFF
TB0.3
I/O
LVCMOS
DVCC
–
UCB0SIMO
I/O
LVCMOS
DVCC
–
UCB0SDA
I/O
LVCMOS
DVCC
–
BSLSDA
I/O
LVCMOS
DVCC
–
TA0.0
I/O
LVCMOS
DVCC
–
P1.7
I/O
LVCMOS
DVCC
OFF
TB0.4
I/O
LVCMOS
DVCC
–
UCB0SOMI
I/O
LVCMOS
DVCC
–
UCB0SCL
I/O
LVCMOS
DVCC
–
BSLSCL
I/O
LVCMOS
DVCC
–
TA1.0
I/O
LVCMOS
DVCC
–
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
17
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 7-1. Pin Attributes (continued)
PIN NUMBER (1)
PN
PM
RGZ
ZVW
53
41
–
L7
54
55
42
43
–
–
K7
K8
SIGNAL TYPE (4)
BUFFER TYPE
(5)
POWER
SOURCE (6)
RESET STATE
AFTER BOR (7)
P5.0
I/O
LVCMOS
DVCC
OFF
UCB1SIMO
I/O
LVCMOS
DVCC
–
UCB1SDA
I/O
LVCMOS
DVCC
–
P5.1
I/O
LVCMOS
DVCC
OFF
UCB1SOMI
I/O
LVCMOS
DVCC
–
UCB1SCL
I/O
LVCMOS
DVCC
–
P5.2
I/O
LVCMOS
DVCC
OFF
UCB1CLK
I/O
LVCMOS
DVCC
–
SIGNAL NAME (2) (3)
TA4CLK
56
44
–
L8
I
LVCMOS
DVCC
–
P5.3
I/O
LVCMOS
DVCC
OFF
UCB1STE
I/O
LVCMOS
DVCC
–
P4.4
I/O
LVCMOS
DVCC
OFF
57
45
33
H7
TB0.5
I/O
LVCMOS
DVCC
–
58
46
34
H8
P4.5
I/O
LVCMOS
DVCC
OFF
59
47
35
K9
P4.6
I/O
LVCMOS
DVCC
OFF
60
48
36
L9
DVSS1
P
Power
–
N/A
61
49
37
L10
DVCC1
P
Power
–
N/A
62
50
38
F11
P2.7
I/O
LVCMOS
DVCC
OFF
P2.3
I/O
LVCMOS
DVCC
OFF
TA0.0
I/O
LVCMOS
DVCC
–
UCA1STE
I/O
LVCMOS
DVCC
–
I
Analog
DVCC
–
63
51
39
J11
A6
64
65
52
53
40
–
K11
J10
C10
I
Analog
DVCC
–
P2.4
I/O
LVCMOS
DVCC
OFF
TA1.0
I/O
LVCMOS
DVCC
–
UCA1CLK
I/O
LVCMOS
DVCC
–
–
A7
I
Analog
DVCC
C11
I
Analog
DVCC
–
P5.4
I/O
LVCMOS
DVCC
OFF
UCA2TXD
O
LVCMOS
DVCC
–
UCA2SIMO
I/O
LVCMOS
DVCC
–
TB0OUTH
I
LVCMOS
DVCC
–
I/O
LVCMOS
DVCC
OFF
UCA2RXD
I
LVCMOS
DVCC
–
UCA2SOMI
I/O
LVCMOS
DVCC
–
ACLK
O
LVCMOS
DVCC
–
P5.6
I/O
LVCMOS
DVCC
OFF
UCA2CLK
I/O
LVCMOS
DVCC
–
TA4.0
I/O
LVCMOS
DVCC
–
SMCLK
O
LVCMOS
DVCC
–
P5.7
I/O
LVCMOS
DVCC
OFF
UCA2STE
I/O
LVCMOS
DVCC
–
TA4.1
I/O
LVCMOS
DVCC
–
MCLK
O
LVCMOS
DVCC
–
P5.5
66
67
68
18
54
55
56
–
–
–
H10
G10
G8
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 7-1. Pin Attributes (continued)
PIN NUMBER (1)
PN
PM
RGZ
ZVW
69
–
–
F8
70
–
F10
71
–
–
E8
72
–
–
C10
73
57
41
E10
74
(1)
(2)
(3)
(4)
(5)
(6)
(7)
–
58
42
H11
SIGNAL TYPE (4)
BUFFER TYPE
(5)
POWER
SOURCE (6)
RESET STATE
AFTER BOR (7)
P6.4
I/O
LVCMOS
DVCC
OFF
UCB3SIMO
I/O
LVCMOS
DVCC
–
UCB3SDA
I/O
LVCMOS
DVCC
–
P6.5
I/O
LVCMOS
DVCC
OFF
UCB3SOMI
I/O
LVCMOS
DVCC
–
UCB3SCL
I/O
LVCMOS
DVCC
–
P6.6
I/O
LVCMOS
DVCC
OFF
UCB3CLK
I/O
LVCMOS
DVCC
–
P6.7
I/O
LVCMOS
DVCC
OFF
UCB3STE
I/O
LVCMOS
DVCC
–
SIGNAL NAME (2) (3)
AVSS3
PJ.6
HFXIN
P
Power
–
N/A
I/O
LVCMOS
DVCC
–
I
Analog
DVCC
–
PJ.7
I/O
LVCMOS
DVCC
OFF
HFXOUT
O
Analog
DVCC
–
AVSS2
P
Power
–
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
–
PJ.5
I/O
LVCMOS
DVCC
OFF
LFXOUT
O
Analog
DVCC
–
75
59
43
G11
76
60
44
D10
77
61
45
E11
78
62
46
D11
79
63
47
C11
AVSS1
P
Power
–
N/A
80
64
48
B11
AVCC1
P
Power
–
N/A
–
–
–
A1
DGND
P
Power
–
N/A
–
–
–
A11
AGND
P
Power
–
N/A
–
–
–
B10
AGND
P
Power
–
N/A
–
–
–
K2
DGND
P
Power
–
N/A
–
–
–
K10
DGND
P
Power
–
N/A
–
–
–
L1
DGND
P
Power
–
N/A
–
–
–
L11
DGND
P
Power
–
N/A
–
–
Pad
–
QFN Pad
P
Power
–
N/A
PJ.4
LFXIN
N/A = not available
The signal that is listed first for each pin is the reset default pin name.
Signal Types: I = Input, O = Output, I/O = Input or Output.
Buffer Types: LVCMOS, Analog, or Power (see Table 7-3 for details)
To determine the pin mux encodings for each pin, see Section 9.13.
The power source shown in this table is the I/O power source, which may differ from the module power source.
Reset States:
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
N/A = Not applicable
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
19
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
7.3 Signal Descriptions
Section 7.3 describes the signals for all device variants and package options.
Table 7-2. Signal Descriptions
FUNCTION
ADC
BSL (I2C)
BSL (UART)
Clock
20
SIGNAL NAME
PIN NO.(1)
ZVW
PN
PM
RGZ
PIN
TYPE(2)
DESCRIPTION
A0
A10
1
1
1
I
ADC analog input A0
A1
A9
2
2
2
I
ADC analog input A1
A2
B9
3
3
3
I
ADC analog input A2
A3
A4
16
12
9
I
ADC analog input A3
A4
B3
17
13
10
I
ADC analog input A4
A5
B4
18
14
11
I
ADC analog input A5
A6
J11
63
51
39
I
ADC analog input A6
A7
K11
64
52
40
I
ADC analog input A7
A8
F1
31
24
16
I
ADC analog input A8
A9
F4
32
25
17
I
ADC analog input A9
A10
G1
33
26
18
I
ADC analog input A10
A11
G2
34
27
19
I
ADC analog input A11
A12
A8
4
4
4
I
ADC analog input A12
A13
B8
5
5
5
I
ADC analog input A13
A14
B7
6
6
6
I
ADC analog input A14
A15
A7
7
7
7
I
ADC analog input A15
A16
E1
27
23
–
I
ADC analog input A16
A17
E2
28
–
–
I
ADC analog input A17
A18
E4
29
–
–
I
ADC analog input A18
A19
F2
30
–
–
I
ADC analog input A19
VREF+
A9
2
2
2
O
Output of positive reference voltage
VREF-
A10
1
1
1
O
Output of negative reference voltage
VeREF+
A9
2
2
2
I
Input for an external positive reference voltage to the ADC
VeREF-
A10
1
1
1
I
Input for an external negative reference voltage to the
ADC
BSLSCL
K6
52
40
32
I/O
I2C BSL clock
BSLSDA
L6
51
39
31
I/O
I2C BSL data
BSLRX
L3
42
33
25
I
UART BSL receive
BSLTX
L2
41
32
24
O
UART BSL transmit
ACLK
C2
H10
23
41
66
19
32
54
14
24
O
ACLK output
HFXIN
H11
74
58
42
I
Input for high-frequency crystal oscillator HFXT
HFXOUT
G11
75
59
43
O
Output for high-frequency crystal oscillator HFXT
LFXIN
E11
77
61
45
I
Input for low-frequency crystal oscillator LFXT
LFXOUT
D11
78
62
46
O
Output of low-frequency crystal oscillator LFXT
MCLK
C1
G8
22
68
18
56
13
O
MCLK output
SMCLK
B1
G10
21
47
67
17
35
55
12
27
O
SMCLK output
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 7-2. Signal Descriptions (continued)
FUNCTION
Comparator
DMA
Debug
SIGNAL NAME
PIN NO.(1)
ZVW
PN
PM
RGZ
PIN
TYPE(2)
DESCRIPTION
C0
A10
1
1
1
I
Comparator input C0
C1
A9
2
2
2
I
Comparator input C1
C2
B9
3
3
3
I
Comparator input C2
C3
A4
16
12
9
I
Comparator input C3
C4
B3
17
13
10
I
Comparator input C4
C5
B4
18
14
11
I
Comparator input C5
C6
B1
21
17
12
I
Comparator input C6
C7
C1
22
18
13
I
Comparator input C7
C8
C2
23
19
14
I
Comparator input C8
C9
D2
24
20
15
I
Comparator input C9
C10
J11
63
51
39
I
Comparator input C10
C11
K11
64
52
40
I
Comparator input C11
C12
A8
4
4
4
I
Comparator input C12
C13
B8
5
5
5
I
Comparator input C13
C14
B7
6
6
6
I
Comparator input C14
C15
A7
7
7
7
I
Comparator input C15
COUT
A9
B9
L5
2
3
48
2
3
36
2
3
28
O
Comparator output
DMAE0
A10
1
1
1
I
External DMA trigger
SBWTCK
H2
37
30
22
I
Spy-Bi-Wire input clock
SBWTDIO
J2
38
31
23
I/O
Spy-Bi-Wire data input/output
SRCPUOFF
D2
24
20
15
O
Low-power debug: CPU Status register bit CPUOFF
SROSCOFF
C2
23
19
14
O
Low-power debug: CPU Status register bit OSCOFF
SRSCG0
C1
22
18
13
O
Low-power debug: CPU Status register bit SCG0
SRSCG1
B1
21
17
12
O
Low-power debug: CPU Status register bit SCG1
TCK
D2
24
20
15
I
Test clock
TCLK
C1
22
18
13
I
Test clock input
TDI
C1
22
18
13
I
Test data input
TDO
B1
21
17
12
O
Test data output port
TEST
H2
37
30
22
I
Test mode pin – select digital I/O on JTAG pins
TMS
C2
23
19
14
I
Test mode select
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
21
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 7-2. Signal Descriptions (continued)
FUNCTION
PIN NO.(1)
ZVW
PN
PM
RGZ
PIN
TYPE(2)
P1.0
A10
1
1
1
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P1.1
A9
2
2
2
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P1.2
B9
3
3
3
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P1.3
A4
16
12
9
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P1.4
B3
17
13
10
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P1.5
B4
18
14
11
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P1.6
L6
51
39
31
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P1.7
K6
52
40
32
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P2.0
L2
41
32
24
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P2.1
L3
42
33
25
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P2.2
K3
43
34
26
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P2.3
J11
63
51
39
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P2.4
K11
64
52
40
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P2.5
G4
35
28
20
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P2.6
H1
36
29
21
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P2.7
F11
62
50
38
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P3.0
A8
4
4
4
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P3.1
B8
5
5
5
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P3.2
B7
6
6
6
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P3.3
A7
7
7
7
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P3.4
K5
47
35
27
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P3.5
L5
48
36
28
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P3.6
H5
49
37
29
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P3.7
H6
50
38
30
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
SIGNAL NAME
GPIO
GPIO
GPIO
22
Submit Document Feedback
DESCRIPTION
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 7-2. Signal Descriptions (continued)
FUNCTION
PIN NO.(1)
ZVW
PN
PM
RGZ
PIN
TYPE(2)
P4.0
F1
31
24
16
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P4.1
F4
32
25
17
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P4.2
G1
33
26
18
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P4.3
G2
34
27
19
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P4.4
H7
57
45
33
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P4.5
H8
58
46
34
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P4.6
K9
59
47
35
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P4.7
D6
12
8
8
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P5.0
L7
53
41
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P5.1
K7
54
42
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P5.2
K8
55
43
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P5.3
L8
56
44
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P5.4
J10
65
53
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P5.5
H10
66
54
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P5.6
G10
67
55
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P5.7
G8
68
56
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P6.0
D8
8
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P6.1
D7
9
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P6.2
A6
10
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P6.3
B6
11
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P6.4
F8
69
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P6.5
F10
70
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P6.6
E8
71
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P6.7
C10
72
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
SIGNAL NAME
GPIO
GPIO
GPIO
Copyright © 2021 Texas Instruments Incorporated
DESCRIPTION
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
23
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 7-2. Signal Descriptions (continued)
FUNCTION
PIN NO.(1)
ZVW
PN
PM
RGZ
PIN
TYPE(2)
P7.0
A5
13
9
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P7.1
B5
14
10
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P7.2
D1
25
21
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P7.3
D4
26
22
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P7.4
E1
27
23
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P7.5
E2
28
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P7.6
E4
29
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P7.7
F2
30
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P8.0
D5
15
11
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P8.1
L4
44
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P8.2
K4
45
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
P8.3
H4
46
–
–
I/O
General-purpose digital I/O with port interrupt and wake
up from LPMx.5
PJ.0
B1
21
17
12
I/O
General-purpose digital I/O
PJ.1
C1
22
18
13
I/O
General-purpose digital I/O
PJ.2
C2
23
19
14
I/O
General-purpose digital I/O
PJ.3
D2
24
20
15
I/O
General-purpose digital I/O
PJ.4
E11
77
61
45
I/O
General-purpose digital I/O
PJ.5
D11
78
62
46
I/O
General-purpose digital I/O
PJ.6
H11
74
58
42
I/O
General-purpose digital I/O
PJ.7
G11
75
59
43
I/O
General-purpose digital I/O
UCB0SCL
K6
52
40
32
I/O
I2C clock – eUSCI_B0 I2C mode
UCB0SDA
L6
51
39
31
I/O
I2C data – eUSCI_B0 I2C mode
UCB1SCL
K7
54
42
–
I/O
I2C clock – eUSCI_B1 I2C mode
UCB1SDA
L7
53
41
–
I/O
I2C data – eUSCI_B1 I2C mode
UCB2SCL
B5
14
10
–
I/O
I2C clock – eUSCI_B2 I2C mode
UCB2SDA
A5
13
9
–
I/O
I2C data – eUSCI_B2 I2C mode
UCB3SCL
F10
70
–
–
I/O
I2C clock – eUSCI_B3 I2C mode
UCB3SDA
F8
69
–
–
I/O
I2C data – eUSCI_B3 I2C mode
SIGNAL NAME
GPIO
GPIO
GPIO
I2C
24
Submit Document Feedback
DESCRIPTION
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 7-2. Signal Descriptions (continued)
FUNCTION
PN
PM
RGZ
PIN
TYPE(2)
B10
A11
–
–
–
P
Analog ground
AVCC1
B11
80
64
48
P
Analog power supply
AVSS1
C11
79
63
47
P
Analog ground supply
AVSS2
D10
76
60
44
P
Analog ground supply
AVSS3
E10
73
57
41
P
Analog ground supply
DGND
A1
K2
K10
L1
L11
–
–
–
P
Digital ground
AGND
Power
RTC
PIN NO.(1)
ZVW
SIGNAL NAME
DESCRIPTION
DVCC1
L10
61
49
37
P
Digital power supply
DVCC2
A3
20
16
–
P
Digital power supply
DVCC3
K1
40
–
–
P
Digital power supply
DVSS1
L9
60
48
36
P
Digital ground supply
DVSS2
A2
19
15
–
P
Digital ground supply
DVSS3
J1
39
–
–
P
Digital ground supply
QFN Pad
–
–
–
Pad
P
QFN package exposed thermal pad. TI recommends
connection to VSS.
RTCCLK
A10
1
1
1
O
RTC clock calibration output (not available on
MSP430FR5x5x devices)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
25
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 7-2. Signal Descriptions (continued)
FUNCTION
SPI
System
26
PIN NO.(1)
ZVW
PN
PM
RGZ
PIN
TYPE(2)
UCA0CLK
B4
18
14
11
I/O
Clock signal input – eUSCI_A0 SPI slave mode
Clock signal output – eUSCI_A0 SPI master mode
UCA0SIMO
L2
41
32
24
I/O
Slave in/master out – eUSCI_A0 SPI mode
UCA0SOMI
L3
42
33
25
I/O
Slave out/master in – eUSCI_A0 SPI mode
UCA0STE
B3
17
13
10
I/O
Slave transmit enable – eUSCI_A0 SPI mode
UCA1CLK
K11
64
52
40
I/O
Clock signal input – eUSCI_A1 SPI slave mode
Clock signal output – eUSCI_A1 SPI master mode
UCA1SIMO
G4
35
28
20
I/O
Slave in/master out – eUSCI_A1 SPI mode
UCA1SOMI
H1
36
29
21
I/O
Slave out/master in – eUSCI_A1 SPI mode
UCA1STE
J11
63
51
39
I/O
Slave transmit enable – eUSCI_A1 SPI mode
UCA2CLK
G10
67
55
–
I/O
Clock signal input – eUSCI_A2 SPI slave mode
Clock signal output – eUSCI_A2 SPI master mode
UCA2SIMO
J10
65
53
–
I/O
Slave in/master out – eUSCI_A2 SPI mode
UCA2SOMI
H10
66
54
–
I/O
Slave out/master in – eUSCI_A2 SPI mode
UCA2STE
G8
68
56
–
I/O
Slave transmit enable – eUSCI_A2 SPI mode
UCA3CLK
A6
10
–
–
I/O
Clock signal input – eUSCI_A3 SPI slave mode
Clock signal output – eUSCI_A3 SPI master mode
UCA3SIMO
D8
8
–
–
I/O
Slave in/master out – eUSCI_A3 SPI mode
UCA3SOMI
D7
9
–
–
I/O
Slave out/master in – eUSCI_A3 SPI mode
UCA3STE
B6
11
–
–
I/O
Slave transmit enable – eUSCI_A3 SPI mode
UCB0CLK
K3
43
34
26
I/O
Clock signal input – eUSCI_B0 SPI slave mode
Clock signal output – eUSCI_B0 SPI master mode
UCB0SIMO
L6
51
39
31
I/O
Slave in/master out – eUSCI_B0 SPI mode
UCB0SOMI
K6
52
40
32
I/O
Slave out/master in – eUSCI_B0 SPI mode
UCB0STE
A4
16
12
9
I/O
Slave transmit enable – eUSCI_B0 SPI mode
UCB1CLK
K8
55
43
–
I/O
Clock signal input – eUSCI_B1 SPI slave mode
Clock signal output – eUSCI_B1 SPI master mode
UCB1SIMO
L7
53
41
–
I/O
Slave in/master out – eUSCI_B1 SPI mode
UCB1SOMI
K7
54
42
–
I/O
Slave out/master in – eUSCI_B1 SPI mode
UCB1STE
L8
56
44
–
I/O
Slave transmit enable – eUSCI_B1 SPI mode
UCB2CLK
D1
25
21
–
I/O
Clock signal input – eUSCI_B2 SPI slave mode
Clock signal output – eUSCI_B2 SPI master mode
UCB2SIMO
A5
13
9
–
I/O
Slave in/master out – eUSCI_B2 SPI mode
UCB2SOMI
B5
14
10
–
I/O
Slave out/master in – eUSCI_B2 SPI mode
UCB2STE
D4
26
22
–
I/O
Slave transmit enable – eUSCI_B2 SPI mode
UCB3CLK
E8
71
–
–
I/O
Clock signal input – eUSCI_B3 SPI slave mode
Clock signal output – eUSCI_B3 SPI master mode
UCB3SIMO
F8
69
–
–
I/O
Slave in/master out – eUSCI_B3 SPI mode
UCB3SOMI
F10
70
–
–
I/O
Slave out/master in – eUSCI_B3 SPI mode
UCB3STE
C10
72
–
–
I/O
Slave transmit enable – eUSCI_B3 SPI mode
NMI
J2
38
31
23
I
Nonmaskable interrupt input
RST
J2
38
31
23
I
Reset input active low
SIGNAL NAME
Submit Document Feedback
DESCRIPTION
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 7-2. Signal Descriptions (continued)
FUNCTION
Timer
UART
(1)
(2)
PIN NO.(1)
ZVW
PN
PM
RGZ
PIN
TYPE(2)
TA0.0
L6
51
39
31
I/O
TA0 CCR0 capture: CCI0A input, compare: Out0
TA0.0
J11
63
51
39
I/O
TA0 CCR0 capture: CCI0B input, compare: Out0
TA0.1
A10
1
1
1
I/O
TA0 CCR1 capture: CCI1A input, compare: Out1
TA0.2
A9
2
2
2
I/O
TA0 CCR2 capture: CCI2A input, compare: Out2
SIGNAL NAME
DESCRIPTION
TA0CLK
B9
3
3
3
I
TA1.0
K6
52
40
32
I/O
TA0 input clock
TA1.0
K11
64
52
40
I/O
TA1 CCR0 capture: CCI0B input, compare: Out0
TA1.1
B9
3
3
3
I/O
TA1 CCR1 capture: CCI1A input, compare: Out1
TA1.2
A4
16
12
9
I/O
TA1CLK
A9
2
2
2
I
TA4.0
E1
27
23
–
I/O
TA4 CCR0 capture: CCI0B input, compare: Out0
TA4.0
G10
67
55
–
I/O
TA4 CCR0 capture: CCI0A input, compare: Out0
TA4.1
D4
26
22
–
I/O
TA4CCR1 capture: CCI1B input, compare: Out1
TA4.1
G8
68
56
–
I/O
TA4 CCR1 capture: CCI1A input, compare: Out1
TA4CLK
K8
55
43
–
I
TB0.0
G4
35
28
20
I/O
TB0 CCR0 capture: CCI0B input, compare: Out0
TB0.0
L3
42
33
25
I/O
TB0 CCR0 capture: CCI0A input, compare: Out0
TB0.1
B3
17
13
10
I/O
TB0 CCR1 capture: CCI1A input, compare: Out1
TB0.1
H1
36
29
21
O
TB0 CCR1 compare: Out1
TB0.2
B4
18
14
11
I/O
TB0 CCR2 capture: CCI2A input, compare: Out2
TB0.2
K3
43
34
26
O
TB0 CCR2 compare: Out2
TB0.3
K5
47
35
27
I/O
TB0 CCR3 capture: CCI3A input, compare: Out3
TB0.3
L6
51
39
31
I/O
TB0 CCR3 capture: CCI3B input, compare: Out3
TB0.4
L5
48
36
28
I/O
TB0 CCR4 capture: CCI4A input, compare: Out4
TA1 CCR0 capture: CCI0A input, compare: Out0
TA1 CCR2 capture: CCI2A input, compare: Out2
TA1 input clock
TA4 input clock
TB0.4
K6
52
40
32
I/O
TB0 CCR4 capture: CCI4B input, compare: Out4
TB0.5
H5
49
37
29
I/O
TB0 CCR5 capture: CCI5A input, compare: Out5
TB0.5
H7
57
45
33
I/O
TB0CCR5 capture: CCI5B input, compare: Out5
TB0.6
L2
41
32
24
I/O
TB0 CCR6 capture: CCI6B input, compare: Out6
TB0.6
H6
50
38
30
I/O
TB0 CCR6 capture: CCI6A input, compare: Out6
TB0CLK
L2
41
32
24
I
TB0 clock input
TB0OUTH
B1
J10
21
65
17
53
12
I
Switch all PWM outputs high impedance input – TB0
UCA0RXD
L3
42
33
25
I
Receive data – eUSCI_A0 UART mode
UCA0TXD
L2
41
32
24
O
Transmit data – eUSCI_A0 UART mode
UCA1RXD
H1
36
29
21
I
Receive data – eUSCI_A1 UART mode
UCA1TXD
G4
35
28
20
O
Transmit data – eUSCI_A1 UART mode
UCA2RXD
H10
66
54
–
I
Receive data – eUSCI_A2 UART mode
UCA2TXD
J10
65
53
–
O
Transmit data – eUSCI_A2 UART mode
UCA3RXD
D7
9
–
–
I
Receive data – eUSCI_A3 UART mode
UCA3TXD
D8
8
–
–
O
Transmit data – eUSCI_A3 UART mode
N/A = not available
I = input, O = output, P = power
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
27
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
7.4 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the
device is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see
Section 9.13.
7.5 Buffer Types
Table 7-3 describes the buffer types that are referenced in Table 7-1.
Table 7-3. Buffer Type
BUFFER TYPE
(STANDARD)
NOMINAL
PU OR PD
STRENGTH
(µA)(1)
OUTPUT DRIVE
STRENGTH
(mA)(1)
N/A
N/A
N/A
Yes(3)
Programmable
See Section
8.12.5
See Section
8.12.5.3
3.0 V
No
N/A
N/A
N/A
3.0 V
No
N/A
N/A
N/A
0V
No
N/A
N/A
N/A
NOMINAL
VOLTAGE
HYSTERESIS
Analog(2)
3.0 V
No
LVCMOS
3.0 V
Power (DVCC)(4)
Power (AVCC)(4)
Power (DVSS
and AVSS)(4)
(1)
(2)
(3)
(4)
PU OR
PD(1)
COMMENTS
See analog modules in
Section 8 for details
SVS enables hysteresis on
DVCC
N/A = not applicable
This is a switch, not a buffer.
Only for input pins
This is supply input, not a buffer.
7.6 Connection of Unused Pins
Table 7-4 lists the correct termination of all unused pins.
Table 7-4. Connection of Unused Pins
PIN (1)
POTENTIAL
AVCC
DVCC
AVSS
DVSS
Px.0 to Px.7
Open
Switched to port function, output direction (PxDIR.n = 1)
RST/NMI
DVCC or VCC
47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF(2)) pulldown
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
Open
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used, these should
be switched to port function, output direction. When used as JTAG pins, these pins should remain
open.
TEST
Open
This pin always has an internal pulldown enabled.
(1)
(2)
28
COMMENT
For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 pins.
The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire
JTAG mode with TI tools like FET interfaces or GANG programmers.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
Voltage applied at DVCC and AVCC pins to VSS
–0.3
Voltage difference between DVCC and AVCC pins(1)
Voltage applied to any pin (2)
–0.3
Diode current at any device pin
Storage temperature, Tstg
(1)
(2)
(3)
(3)
–40
MAX
UNIT
4.1
V
±0.3
V
VCC + 0.3 V
(4.1 V Max)
V
±2
mA
125
°C
Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±250 V may actually have higher performance.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
29
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.3 Recommended Operating Conditions
TYP data are based on VCC = 3.0 V and TA = 25°C, unless otherwise noted
MIN
pins(1) (2) (3)
NOM
1.8(6)
MAX
VCC
Supply voltage range applied at all DVCC and AVCC
VSS
Supply voltage applied at all DVSS and AVSS pins.
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
85
°C
CDVCC
fSYSTEM
Capacitor value at
fACLK
Maximum ACLK frequency
fSMCLK
Maximum SMCLK frequency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
30
0
DVCC(4)
Processor frequency (maximum MCLK frequency)(5)
3.6
UNIT
V
V
1–20%
µF
No FRAM wait states
(NWAITSx = 0)
0
8(8)
With FRAM wait states
(NWAITSx = 1)(7)
0
16(9)
MHz
50
kHz
16(9)
MHz
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device
operation, the voltage difference between AVCC and DVCC must not exceed the limits specified under Absolute Maximum Ratings.
Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation
for capacitor CDVCC should limit the slopes accordingly.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
For each supply pin pair (DVCC and DVSS, AVCC and AVSS), place a low-ESR ceramic capacitor of 100 nF (minimum) as close as
possible (within a few millimeters) to the respective pin pairs.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
The minimum supply voltage is defined by the supervisor SVS levels. See the PMM SVS threshold parameters for the exact values.
Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always
excecuted without wait states.
DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted.
DCO settings and HF cyrstals with a typical value less than or equal to the specified MAX value are permitted. If a clock sources with a
higher typical value is used, the clock must be divided in the clock system.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1) (2) (see Figure 8-1)
FREQUENCY (fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
VCC
1 MHz
4 MHz
8 MHz
0 WAIT STATES 0 WAIT STATES 0 WAIT STATES
(NWAITSx = 0)
(NWAITSx = 0)
(NWAITSx = 0)
TYP
MAX
TYP
MAX
TYP
MAX
12 MHz
1 WAIT STATE
(NWAITSx = 1)
TYP
MAX
16 MHz
1 WAIT STATE
(NWAITSx = 1)
TYP
UNIT
MAX
IAM, FRAM_UNI
(Unified memory)(3)
FRAM
3.0 V
225
665
1275
1550
1970
µA
IAM, FRAM(0%)(4) (5)
FRAM
0% cache hit
ratio
3.0 V
420
1455
2850
2330
3000
µA
IAM, FRAM(50%)(4) (5)
FRAM
50% cache hit
ratio
3.0 V
275
855
1650
1770
2265
µA
IAM, FRAM(66%)(4) (5)
FRAM
66% cache hit
ratio
3.0 V
220
650
1240
1490
1880
µA
IAM, FRAM(75%)(4) (5)
FRAM
75% cache hit
ratio
3.0 V
192
535
1015
IAM, FRAM(100%(4) (5)
FRAM
100% cache hit
ratio
3.0 V
125
255
450
670
790
IAM, RAM (6) (5)
RAM
3.0 V
140
325
590
880
1070
IAM, RAM only (7) (5)
RAM
3.0 V
90
280
540
830
1020
(1)
(2)
(3)
(4)
(5)
(6)
(7)
261
182
1170
1290
1490
1620
1870
µA
µA
µA
1313
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Characterized with program executing typical data processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency, except for 12 MHz. For 12 MHz, fDCO= 24 MHz and
fMCLK = fSMCLK = fDCO / 2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(fMCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute fMCLK,eff:
fMCLK,eff = fMCLK / [wait states × (1 – cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio fMCKL,eff = fMCLK / [1 × (1 – 0.75) + 1] = fMCLK / 1.25.
Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache
hit ratio represents number cache accesess divided by the total number of FRAM accesses. For example, a 75% ratio implies three of
every four accesses is from cache, and the remaining are FRAM accesses.
See Figure 8-1 for typical curves. The characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in Section 8.4.
Program and data reside entirely in RAM. All execution is from RAM.
Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
31
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.5 Typical Characteristics, Active Mode Supply Currents
3000
I(AM,0%)
I(AM,50%)
I(AM,66%)
I(AM,75%)
I(AM,100%)
I(AM,RAM)
IAM, Active Mode Current (µA)
2500
2000
I(AM,75%) [µA] = 118 × f [MHz] + 74
1500
1000
500
0
1
2
3
4
5
fMCLK, MCLK Frequency (MHz)
6
7
8
Figure 8-1. Typical Active Mode Supply Currents, No Wait States
8.6 Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1) (2)
FREQUENCY (fSMCLK)
PARAMETER
VCC
1 MHz
TYP
ILPM0
ILPM1
(1)
(2)
32
2.2 V
75
3.0 V
85
2.2 V
40
3.0 V
40
4 MHz
MAX
TYP
8 MHz
MAX
TYP
12 MHz
MAX
TYP
16 MHz
MAX
TYP
105
165
240
220
135
115
175
250
240
65
130
215
195
67
65
130
215
195
UNIT
MAX
290
222
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO at specified frequency - except for 12 MHz: here fDCO=24MHz and fSMCLK = fDCO / 2.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.7 Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External
Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see Figure 8-2
and Figure 8-3)
PARAMETER
ILPM2,XT12
ILPM2,XT3.7
Low-power mode 2, 12-pF crystal(2)
(3) (4)
Low-power mode 2, 3.7-pF crystal(2)
(5) (4)
VCC
–40°C
TYP
MAX
25°C
TYP
60°C
MAX
TYP
85°C
MAX
TYP
2.2 V
0.8
1.3
4.1
10.8
3.0 V
0.8
1.3
4.1
10.8
2.2 V
0.6
1.2
4.0
10.7
3.0 V
0.6
1.2
4.0
10.7
MAX
UNIT
μA
μA
ILPM2,VLO
Low-power mode 2, VLO, includes
SVS(6)
2.2 V
0.5
1.0
3.8
10.5
3.0 V
0.5
1.0
3.8
10.5
ILPM3,XT12
Low-power mode 3, 12-pF crystal,
includes SVS(2) (3) (7)
2.2 V
0.8
1.0
2.2
4.5
3.0 V
0.8
1.0
2.2
4.5
Low-power mode 3, 3.7-pF crystal,
excludes SVS(2) (5) (8)
(also see Figure 8-2)
2.2 V
0.5
0.7
2.1
4.4
ILPM3,XT3.7
3.0 V
0.5
0.7
2.1
4.4
ILPM3,VLO
Low-power mode 3, VLO, excludes
SVS(9)
2.2 V
0.4
0.5
1.9
4.2
3.0 V
0.4
0.5
1.9
4.2
Low-power mode 3, VLO, excludes
SVS, RAM powered down
completely(9)
2.2 V
0.36
0.47
1.4
2.6
3.0 V
0.36
0.47
1.4
2.6
ILPM4,SVS
Low-power mode 4, includes
SVS(10)
2.2 V
0.5
0.6
1.9
4.3
3.0 V
0.5
0.6
1.9
4.3
ILPM4
Low-power mode 4, excludes
SVS(11)
2.2 V
0.3
0.4
1.7
4.0
3.0 V
0.3
0.4
1.7
4.0
ILPM4,RAMoff
Low-power mode 4, excludes SVS,
RAM powered down completely(11)
2.2 V
0.3
0.37
1.2
2.5
3.0 V
0.3
0.37
1.2
2.5
IIDLE,GroupA
Additional idle current if one or more
modules from Group A (see Table
9-3) are activated in LPM3 or LPM4
3.0 V
0.02
0.3
μA
IIDLE,GroupB
Additional idle current if one or more
modules from Group B (see Table
9-3) are activated in LPM3 or LPM4
3.0 V
0.02
0.35
μA
IIDLE,GroupC
Additional idle current if one or more
modules from Group C (see Table
9-3) are activated in LPM3 or LPM4
3.0 V
0.02
0.38
μA
ILPM3,VLO,
RAMoff
(1)
(2)
(3)
(4)
(5)
(6)
(7)
μA
μA
μA
μA
μA
μA
μA
μA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance
are chosen to closely match the required 12.5 pF load.
Low-power mode 2, crystal oscillator test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
Low-power mode 2, VLO test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). Current for brownout and SVS included.
CPUOFF = 1, SCG0 = 0 SCG1 = 1, OSCOFF = 0 (LPM2),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Low-power mode 3, 12-pF crystal including SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
33
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
www.ti.com
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle
current. See the idle currents specified for the respective peripheral groups.
(8) Low-power mode 3, 3.7-pF crystal excluding SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE
= 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle
current. See the idle currents specified for the respective peripheral groups.
(9) Low-power mode 3, VLO excluding SVS test conditions:
Current for watchdog timer clocked by ACLK included. RTC disabled (RTCHOLD = 1). RAM disabled (RCCTL0 = 5A55h). Current for
brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fVLO, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle
current. See the idle currents specified for the respective peripheral groups.
(10) Low-power mode 4 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle
current. See the idle currents specified for the respective peripheral groups.
(11) Low-power mode 4 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). RAM disabled (RCCTL0 = 5A55h).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle
current. See the idle currents specified for the respective peripheral groups.
34
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.8 Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(see Figure 8-4
and Figure 8-5)
PARAMETER
VCC
–40°C
TYP
MAX
25°C
TYP
60°C
MAX
TYP
85°C
MAX
TYP
ILPM3.5,XT12
Low-power mode 3.5, 12-pF crystal
including SVS (2) (3) (4)
2.2 V
0.45
0.5
0.55
0.75
3.0 V
0.45
0.5
0.55
0.75
ILPM3.5,XT3.7
Low-power mode 3.5, 3.7-pF crystal
excluding SVS (2) (5) (6)
2.2 V
0.3
0.35
0.4
0.65
3.0 V
0.3
0.35
0.4
0.65
ILPM4.5,SVS
Low-power mode 4.5, including
SVS(7)
2.2 V
0.23
0.25
0.28
0.4
3.0 V
0.23
0.25
0.28
0.4
ILPM4.5
Low-power mode 4.5, excluding
SVS(8)
2.2 V
0.035
0.045
0.075
0.15
3.0 V
0.035
0.045
0.075
0.15
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
MAX
UNIT
μA
μA
μA
μA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current
Not applicable for devices with HF crystal oscillator only.
Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance
are chosen to closely match the required 12.5 pF load.
Low-power mode 3.5, 1-pF crystal including SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1; CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Characterized with a Seiko SSP-T7-FL (SMD) crystal with a load capacitance of 3.7 pF. The internal and external load capacitance are
chosen to closely match the required 3.7-pF load.
Low-power mode 3.5, 3.7-pF crystal excluding SVS test conditions:
Current for RTC clocked by XT1 included.Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1; CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5 including SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1; CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5 excluding SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1; CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = 0 Hz, fMCLK = fSMCLK = 0 MHz
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
35
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.9 Typical Characteristics, Low-Power Mode Supply Currents
3.5
2.5
ILPM4, LPM4 Supply Current (µA)
ILPM3, LPM3 Supply Current (µA)
3
3
3.0 V, SVS off
2.2 V, SVS off
3.0 V, SVS on
2.2 V, SVS on
2.5
2
1.5
1
0.5
-40
-20
0
20
40
Temperature (°C)
60
80
-20
0
20
40
Temperature (°C)
60
80
100
Figure 8-3. LPM4 Supply Current vs Temperature
2.2 V, SVS Off
3.0 V, SVS Off
0.45
0.55
ILPM4.5, LPM4.5 Supply Current (µA)
ILPM3.5, LPM3.5 Supply Current (µA)
1
0.5
0.5
0.45
0.4
0.35
0.3
0.25
0.4
2.2 V, SVS off
3.0 V, SVS off
2.2 V, SVS on
3.0 V, SVS on
0.35
0.3
0.25
0.2
0.15
0.1
0.05
-20
0
20
40
Temperature (°C)
60
80
Figure 8-4. LPM3.5 Supply Current vs Temperature
36
1.5
0
-40
100
Figure 8-2. LPM3 Supply Current vs Temperature
0.2
-40
2
0.5
0.65
0.6
3.0 V, SVS off
2.2 V, SVS off
3.0 V, SVS on
2.2 V, SVS on
Submit Document Feedback
100
0
-40
-20
0
20
40
Temperature (°C)
60
80
100
Figure 8-5. LPM4.5 Supply Current vs Temperature
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.10 Typical Characteristics, Current Consumption per Module
MODULE
TEST CONDITIONS (1)
REFERENCE CLOCK
MIN
TYP
MAX
UNIT
Timer_A
Module input clock
3
μA/MHz
Timer_B
Module input clock
5
μA/MHz
eUSCI_A
UART mode
Module input clock
6.3
μA/MHz
eUSCI_A
SPI mode
Module input clock
4
μA/MHz
eUSCI_B
SPI mode
Module input clock
4
μA/MHz
eUSCI_B
I2C mode, 100 kbaud
Module input clock
4
μA/MHz
RTC_C
32 kHz
100
nA
MPY
Only from start to end of operation
MCLK
28
μA/MHz
CRC16
Only from start to end of operation
MCLK
3.3
μA/MHz
CRC32
Only from start to end of operation
MCLK
3.3
μA/MHz
256 Point Complex FFT, Data = nonzero
LEA
(1)
256 Point Complex FFT, Data = zero
86
MCLK
66
µA/MHz
For other module currents not listed here, see the module-specific parameter sections.
8.11 Thermal Packaging Characteristics
THERMAL METRIC(1) (2)
PACKAGE
VALUE
UNIT
RθJA
Junction-to-ambient thermal resistance, still air
27.5
°C/W
RθJC(TOP)
Junction-to-case (top) thermal resistance
12.5
°C/W
RθJB
Junction-to-board thermal resistance
4.4
°C/W
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
QFN-48 (RGZ)
4.4
°C/W
0.2
°C/W
RθJC(BOTTOM)
Junction-to-case (bottom) thermal resistance
0.8
°C/W
RθJA
Junction-to-ambient thermal resistance, still air
53.2
°C/W
RθJC(TOP)
Junction-to-case (top) thermal resistance
14.3
°C/W
RθJB
Junction-to-board thermal resistance
24.7
°C/W
QFP-64 (PM)
ΨJB
Junction-to-board thermal characterization parameter
24.4
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.6
°C/W
RθJA
Junction-to-ambient thermal resistance, still air
47.9
°C/W
RθJC(TOP)
Junction-to-case (top) thermal resistance
13.0
°C/W
RθJB
Junction-to-board thermal resistance
22.5
°C/W
ΨJB
Junction-to-board thermal characterization parameter
22.2
°C/W
QFP-80 (PN)
ΨJT
Junction-to-top thermal characterization parameter
0.6
°C/W
RθJA
Junction-to-ambient thermal resistance, still air
60.6
°C/W
RθJC(TOP)
Junction-to-case (top) thermal resistance
18.1
°C/W
RθJB
Junction-to-board thermal resistance
31.8
°C/W
BGA-87 (ZVW)
ΨJB
Junction-to-board thermal characterization parameter
30.1
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.7
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
37
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.12 Timing and Switching Characteristics
8.12.1 Power Supply Sequencing
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power
down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits
specified in Section 8.1. Exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
Section 8.12.1.1 lists the power ramp requirements.
8.12.1.1 Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VVCC_BOR–
Brownout power-down level
VVCC_BOR+
Brownout power-up level(1)
(1)
(2)
TEST CONDITIONS
(1)
MIN
MAX
UNIT
| dDVCC/dt | < 3 V/s
0.73
1.66
V
| dDVCC/dt | < 3 V/s(2)
0.79
1.75
V
Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 volts per microsecond (±0.05 V/µs). Following the data sheet
recommendation for capacitor CDVCC should limit the slopes accordingly.
The brownout levels are measured with a slowly changing supply.
Section 8.12.1.2 lists the supply voltage supervisor characteristics.
8.12.1.2 SVS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISVSH,LPM
level(1)
VSVSH-
SVSH power-down
VSVSH+
SVSH power-up level(1)
VSVSH_hys
SVSH hysteresis
tPD,SVSH, AM
SVSH propagation delay, active mode
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
170
300
nA
1.75
1.80
1.85
V
1.77
1.88
1.99
V
150
mV
10
µs
SVSH current consumption, low power modes
40
dVVcc/dt = –10 mV/µs
For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference
Design.
8.12.2 Reset Timing
Section 8.12.2.1 lists the input requirements of the reset pin.
8.12.2.1 Reset Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
t(RST)
(1)
38
External reset pulse duration on RST (1)
2.2 V, 3.0 V
MIN
2
MAX
UNIT
µs
Not applicable if RST/NMI pin configured as NMI .
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.12.3 Clock Specifications
LFXTCLK (see Section 8.12.3.1) is a low-frequency oscillator that can be used either with low-frequency 32768Hz watch crystals, standard crystals, resonators, or external clock sources in the 50 kHz or below range. When
in bypass mode, LFXTCLK can be driven with an external square-wave signal.
8.12.3.1 Low-Frequency Crystal Oscillator, LFXT
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER (1)
IVCC.LFXT
Current consumption
TEST CONDITIONS
VCC
MIN
TYP
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF, ESR ≈ 44 kΩ
180
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {1},
TA = 25°C, CL,eff = 6 pF, ESR ≈ 40 kΩ
185
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {2},
TA = 25°C, CL,eff = 9 pF, ESR ≈ 40 kΩ
MAX UNIT
3.0 V
nA
225
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF, ESR ≈ 40 kΩ
330
fLFXT
LFXT oscillator crystal
frequency
LFXTBYPASS = 0
DCLFXT
LFXT oscillator duty cycle
Measured at ACLK,
fLFXT = 32768 Hz
30%
fLFXT,SW
LFXT oscillator logic-level
square-wave input frequency
LFXTBYPASS = 1 (2) (3)
10.5
DCLFXT, SW
LFXT oscillator logic-level
square-wave input duty cycle
LFXTBYPASS = 1
30%
OALFXT
Oscillation allowance for
LF crystals (4)
32768
Hz
70%
32.768
50
kHz
70%
LFXTBYPASS = 0, LFXTDRIVE = {1},
fLFXT = 32768 Hz, CL,eff = 6 pF
210
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
300
kΩ
CLFXIN
Integrated load capacitance at
LFXIN terminal (5) (6)
2
pF
CLFXOUT
Integrated load capacitance at
LFXOUT terminal (5) (6)
2
pF
tSTART,LFXT
fFault,LFXT
(1)
(2)
(3)
(4)
Start-up time
(7)
Oscillator fault frequency (8) (9)
fOSC = 32768 Hz
LFXTBYPASS = 0, LFXTDRIVE = {0},
TA = 25°C, CL,eff = 3.7 pF,
3.0 V
fOSC = 32768 Hz
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
3.0 V
800
ms
1000
0
3500
Hz
To improve EMI on the LFXT oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.
• Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this datasheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
39
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
(5)
(6)
(7)
(8)
(9)
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF
• For LFXTDRIVE = {1}, CL,eff = 6 pF
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 9 pF
• For LFXTDRIVE = {3}, 9 pF ≤ CL,eff ≤ 12.5 pF
This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT are
the total capacitance at the LFXIN and LFXOUT terminals, respectively.
Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers.
Recommended effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF.
The PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective
load capacitance of the selected crystal is met.
Includes startup counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition will set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
HFXTCLK (see Section 8.12.3.2) is a high-frequency oscillator that can be used with standard crystals or
resonators in the 4‑MHz to 24-MHz range. When in bypass mode, HFXTCLK can be driven with an external
square-wave signal.
8.12.3.2 High-Frequency Crystal Oscillator, HFXT
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER (1)
IDVCC.HFXT
HFXT oscillator crystal current
HF mode at typical ESR
TEST CONDITIONS
VCC
MIN
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1 (2), TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt
75
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1, TA = 25°C,
CL,eff = 18 pF, typical ESR, Cshunt
120
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 2,
HFFREQ = 2, TA = 25°C
CL,eff = 18 pF, typical ESR, Cshunt
HFXTBYPASS = 0, HFFREQ = 1 (2) (3)
fHFXT
DCHFXT
HFXT oscillator duty cycle.
190
fHFXT,SW
8
8.01
16
HFXTBYPASS = 0, HFFREQ = 3 (3)
16.01
24
Measured at SMCLK,
fHFXT = 16 MHz
40%
HFXTBYPASS = 1, HFFREQ = 1 0 (4) (3)
HFXTBYPASS = 1, HFFREQ = 20
(4) (3)
HFXTBYPASS = 1, HFFREQ = 3 0 (4) (3)
DCHFXT, SW
40
HFXT oscillator logic-level
square-wave input duty cycle
Submit Document Feedback
250
4
HFXTBYPASS = 0, HFFREQ = 2
HFXTBYPASS = 1
UNIT
μA
(3)
HFXTBYPASS = 1, HFFREQ = 0 (4) (3)
HFXT oscillator logic-level
square-wave input frequency,
bypass mode
MAX
3.0 V
fOSC = 24 MHz
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3, TA = 25°C
CL,eff = 18 pF, typical ESR, Cshunt
HFXT oscillator crystal
frequency, crystal mode
TYP
50%
MHz
60%
0.9
4
4.01
8
8.01
16
16.01
24
40%
60%
MHz
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.12.3.2 High-Frequency Crystal Oscillator, HFXT (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER (1)
OAHFXT
tSTART,HFXT
Oscillation allowance for
HFXT crystals(5)
Startup time
(6)
TEST CONDITIONS
VCC
MIN
TYP
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1 (2),
fHFXT,HF = 4 MHz, CL,eff = 16 pF
450
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1
fHFXT,HF = 8 MHz, CL,eff = 16 pF
320
HFXTBYPASS = 0, HFXTDRIVE = 2,
HFFREQ = 2
fHFXT,HF = 16 MHz, CL,eff = 16 pF
200
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3
fHFXT,HF = 24 MHz, CL,eff = 16 pF
200
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 1, TA = 25°C, CL,eff = 16 pF
1.6
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 3,
HFFREQ = 3, TA = 25°C, CL,eff = 16 pF
MAX
UNIT
Ω
3.0 V
ms
0.6
CHFXIN
Integrated load capacitance at
HFXIN terminaI (7) (8)
2
pF
CHFXOUT
Integrated load capacitance at
HFXOUT terminaI (7) (8)
2
pF
fFault,HFXT
Oscillator fault frequency (9) (10)
0
800
kHz
(1)
To improve EMI on the HFXT oscillator the following guidelines should be observed.
• Keep the traces between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.
• Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) HFFREQ = {0} is not supported for HFXT crystal mode of operation.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this datasheet. Duty cycle requirements are defined by DCHFXT, SW.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes startup counter of 1024 clock cycles.
(7) This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT is the
total capacitance at the HFXIN and HFXOUT terminals, respectively.
(8) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers.
Recommended effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The
PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load
capacitance of the selected crystal is met.
(9) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static
condition or stuck at fault condition will set the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
41
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
The DCO (see Section 8.12.3.3) is an internal digitally controlled oscillator (DCO) with selectable frequencies.
8.12.3.3 DCO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
1 ±3.5%
MHz
fDCO1
DCO frequency range
1 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 0,
DCORSEL = 1, DCOFSEL = 0
fDCO2.7
DCO frequency range
2.7 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 1
2.667 ±3.5%
MHz
fDCO3.5
DCO frequency range
3.5 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 2
3.5 ±3.5%
MHz
fDCO4
DCO frequency range
4 MHz, trimmed
Measured at SMCLK, divide by 1
DCORSEL = 0, DCOFSEL = 3
4 ±3.5%
MHz
fDCO5.3
DCO frequency range
5.3 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 4,
DCORSEL = 1, DCOFSEL = 1
5.333 ±3.5%
MHz
fDCO7
DCO frequency range
7 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 5,
DCORSEL = 1, DCOFSEL = 2
7 ±3.5%
MHz
fDCO8
DCO frequency range
8 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 0, DCOFSEL = 6,
DCORSEL = 1, DCOFSEL = 3
8 ±3.5%
MHz
fDCO16
DCO frequency range
16 MHz, trimmed
Measured at SMCLK, divide by 1,
DCORSEL = 1, DCOFSEL = 4
16 ±3.5%
MHz
fDCO21
DCO frequency range
21 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 5
21 ±3.5%
MHz
fDCO24
DCO frequency range
24 MHz, trimmed
Measured at SMCLK, divide by 2,
DCORSEL = 1, DCOFSEL = 6
24 ±3.5%
MHz
fDCO,DC
Duty cycle
Measured at SMCLK, divide by 1,
No external divide, all DCORSEL and
DCOFSEL settings except DCORSEL = 1
with DCOFSEL = 5, and DCORSEL = 1 with
DCOFSEL = 6
tDCO, JITTER
DCO jitter
Based on fsignal = 10 kHz and DCO used for
12-bit SAR ADC sampling source. This
achieves greather than 74-dB SNR due to
jitter (that is, limited by ADC performance).
dfDCO/dT
DCO temperature drift(1)
(1)
48%
3.0 V
50%
52%
2
3
0.01
ns
%/°C
Calculated using the box method: (MAX(–40°C to 85°C) - MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C - (-40°C))
8.12.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IVLO
TEST CONDITIONS
(1)
VLO frequency
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK(2)
dfVLO/dVCC
VLO frequency supply voltage drift
Measured at ACLK(3)
fVLO,DC
Duty cycle
Measured at ACLK
42
MIN
TYP
MAX
100
fVLO
(1)
(2)
(3)
VCC
Current consumption
Measured at ACLK
6
9.4
nA
14
0.2
50%
kHz
%/°C
0.7
40%
UNIT
%/V
60%
VLO frequency may decrease in LPM3 or LPM4 mode. The typical ratio of VLO freuqencies (LPM3/4 to AM) is 85%.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
The module oscillator (MODOSC) is an internal low-power oscillator with 5-MHz typical frequency (see Section
8.12.3.5).
8.12.3.5 Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IMODOSC
Current consumption
fMODOSC
MODOSC frequency
fMODOSC/dT
MODOSC frequency temperature drift(1)
fMODOSC/dVCC
MODOSC frequency supply voltage drift(2)
DCMODOSC
Duty cycle
(1)
(2)
MIN
Enabled
TYP
MAX
UNIT
25
4.0
μA
4.8
5.4
MHz
0.08
%/℃
1.4
Measured at SMCLK, divide by 1
40%
%/V
50%
60%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
8.12.4 Wake-up Characteristics
Section 8.12.4.1 lists the wake-up times.
8.12.4.1 Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8-6
and Figure 8-7)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
6
10
UNIT
tWAKE-UP FRAM
(Additional) wake-up time to activate the FRAM
in AM if previously disabled by the FRAM
controller or from an LPM if immediate
activation is selected for wakeup
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode(1)
2.2 V, 3.0 V
tWAKE-UP LPM1
Wake-up time from LPM1 to active mode(1)
2.2 V, 3.0 V
tWAKE-UP LPM2
mode(1)
2.2 V, 3.0 V
6
9.6 +
2.5 / fDCO
μs
9.6 +
2.5 / fDCO
μs
Wake-up time from LPM2 to active
μs
400 ns +
1.5 / fDCO
6
tWAKE-UP LPM3
Wake-up time from LPM3 to active mode(1)
2.2 V, 3.0 V
6.6 +
2.0 / fDCO
tWAKE-UP LPM4
Wake-up time from LPM4 to active mode(1)
2.2 V, 3.0 V
6.6 +
2.0 / fDCO
tWAKE-UP LPM3.5
Wake-up time from LPM3.5 to active mode(2)
μs
μs
2.2 V, 3.0 V
250
350
μs
SVSHE = 1
2.2 V, 3.0 V
250
350
μs
SVSHE = 0
tWAKE-UP LPM4.5
Wake-up time from LPM4.5 to active mode(2)
2.2 V, 3.0 V
0.4
0.8
ms
tWAKE-UP-RST
Wake-up time from a RST pin triggered reset to
active mode(2)
2.2 V, 3.0 V
300
403
μs
tWAKE-UP-BOR
Wake-up time from power-up to active mode (2)
2.2 V, 3.0 V
0.5
1
ms
(1)
(2)
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge with MCLKREQEN = 1. This time includes the activation of the FRAM during wake up. With
MCLKREQEN = 0, the externally observable MCLK clock is gated one additional cycle.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
43
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.12.4.2 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
5000
LPM0
LPM1
LPM2,XT12
LPM3,XT12
LPM3.5,XT12
Average Wake-up Current (µA)
1000
100
10
1
0.1
0.001
0.01
0.1
1
10
100
Wake-up Frequency (Hz)
1000
10000
100000
The average wake-up current does not include the energy required in active mode; for example, for an interrupt service routine (ISR) or
to reconfigure the device.
Figure 8-6. Average LPM Currents vs Wake-up Frequency at 25°C
5000
LPM0
LPM1
LPM2,XT12
LPM3,XT12
LPM3.5,XT12
Average Wake-up Current (µA)
1000
100
10
1
0.1
0.001
0.01
0.1
1
10
100
Wake-up Frequency (Hz)
1000
10000
100000
The average wake-up current does not include the energy required in active mode; for example, for an ISR or to reconfigure the device.
Figure 8-7. Average LPM Currents vs Wake-up Frequency at 85°C
44
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.12.4.3 Typical Wake-up Charge
Section 8.12.4.3 lists the typical charge required to wake up from LPM or reset.
PARAMETER (1)
QWAKE-UP FRAM
Charge used for activating the FRAM in AM or during wake-up
from LPM0 if previously disabled by the FRAM controller.
QWAKE-UP LPM0
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
16.5
nAs
Charge used for wake-up from LPM0 to active mode (with
FRAM active)
3.8
nAs
QWAKE-UP LPM1
Charge used for wake-up from LPM1 to active mode (with
FRAM active)
21
nAs
QWAKE-UP LPM2
Charge used for wake-up from LPM2 to active mode (with
FRAM active)
22
nAs
QWAKE-UP LPM3
Charge used for wake-up from LPM3 to active mode (with
FRAM active)
25
nAs
QWAKE-UP LPM4
Charge used for wake-up from LPM4 to active mode (with
FRAM active)
25
nAs
QWAKE-UP LPM3.5
Charge used for wake-up from LPM3.5 to active mode(2)
121
nAs
QWAKE-UP LPM4.5
Charge used for wake-up from LPM4.5 to active mode(2)
QWAKE-UP-RESET
Charge used for reset from RST or BOR event to active
mode(2)
(1)
(2)
SVSHE = 1
123
SVSHE = 0
121
102
nAs
nAs
Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in
active mode (for example, for an ISR).
Charge required until start of user code. This does not include the energy required to reconfigure the device.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
45
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.12.5 Digital I/Os
Section 8.12.5.1 lists the characteristics of the digital inputs.
8.12.5.1 Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2 V
1.2
TYP
MAX
1.65
3.0 V
1.65
2.25
2.2 V
0.55
1.00
3.0 V
0.75
1.35
2.2 V
0.44
0.98
3.0 V
0.60
1.30
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS,
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
3
pF
CI,ana
Input capacitance, port pins with shared
analog functions(1)
VIN = VSS or VCC
5
pF
Ilkg(Px.y)
High-impedance input leakage current
See (2) (3)
2.2 V,
3.0 V
–20
t(int)
External interrupt timing (external trigger
pulse duration to set interrupt flag)(4)
Ports with interrupt capability (see
the Functional Block Diagram and
Signal Descriptions)
2.2 V,
3.0 V
20
ns
t(RST)
External reset pulse duration on RST (5)
2.2 V,
3.0 V
2
µs
(1)
(2)
(3)
(4)
(5)
46
20
35
50
+20
V
V
V
kΩ
nA
If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in
series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and/or PJ.5/
LFXOUT.
The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor
is disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Not applicable if RST/NMI pin configured as NMI .
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Section 8.12.5.2 lists the characteristics of the digital outputs.
8.12.5.2 Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(1)
High-level output voltage
(see Figure 8-10 and Figure 8-11)
VOH
I(OHmax) = –3 mA(2)
I(OHmax) = –2 mA(1)
I(OHmax) = –6 mA(2)
I(OLmax) = 1 mA(1)
Low-level output voltage
(see Figure 8-8 and Figure 8-9)
VOL
I(OLmax) = 3 mA(2)
I(OLmax) = 2
mA(1)
I(OLmax) = 6 mA(2)
VCC
2.2 V
3.0 V
2.2 V
3.0 V
MIN
TYP
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
2.2 V
16
3.0 V
16
2.2 V
16
3.0 V
16
fPx.y
Port output frequency (with load)(3)
CL = 20 pF, RL (4) (5)
fPort_CLK
Clock output frequency(3)
ACLK, MCLK, or SMCLK at
configured output port,
CL = 20 pF(5)
trise,dig
Port output rise time, digital only port
CL = 20 pF
pins
2.2 V
4
15
3.0 V
3
15
tfall,dig
Port output fall time, digital only port
CL = 20 pF
pins
2.2 V
4
15
3.0 V
3
15
trise,ana
Port output rise time, port pins with
shared analog functions
CL = 20 pF
2.2 V
6
15
3.0 V
4
15
tfall,ana
Port output fall time, port pins with
shared analog functions
CL = 20 pF
2.2 V
6
15
3.0 V
4
15
(1)
(2)
(3)
(4)
(5)
UNIT
V
V
MHz
MHz
ns
ns
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
The port can output frequencies at least up to the specified limit, and it might support higher frequencies.
A resistive divider with 2 × R1 and R1 = 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 20 pF is connected from the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
47
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.12.5.3 Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
30
25°C
85°C
Low-Level Output Current (mA)
Low-Level Output Current (mA)
15
10
5
25°C
85°C
20
10
P1.1
P1.1
0
0
0
0.5
1
1.5
2
0
0.5
1
Low-Level Output Voltage (V)
1.5
2
2.5
3
Low-Level Output Voltage (V)
C001
VCC = 2.2 V
VCC = 3.0 V
Figure 8-8. Typical Low-Level Output Current vs
Low-Level Output Voltage
Figure 8-9. Typical Low-Level Output Current vs
Low-Level Output Voltage
0
0
25°C
85°C
High-Level Output Current (mA)
High-Level Output Current (mA)
C001
-5
-10
25°C
85°C
-10
-20
P1.1
P1.1
-15
-30
0
0.5
1
1.5
2
0
0.5
High-Level Output Voltage (V)
1
1.5
2
2.5
3
High-Level Output Voltage (V)
C001
VCC = 2.2 V
C001
VCC = 3.0 V
Figure 8-10. Typical High-Level Output Current vs
High-Level Output Voltage
Figure 8-11. Typical High-Level Output Current vs
High-Level Output Voltage
8.12.5.4 Pin-Oscillator Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
foPx.y
(1)
48
Pin-oscillator frequency
(see Figure 8-12 and Figure 8-13)
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
pF(1)
3.0 V
1200
kHz
Px.y, CL = 20 pF(1)
3.0 V
650
kHz
Px.y, CL = 10
CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.12.5.5 Typical Characteristics, Pin-Oscillator Frequency
2000
2000
Best Fit
25°C
85°C
Best Fit
25°C
85°C
1000
Pin Oscillator Frequency (kHz)
Pin Oscillator Frequency (kHz)
1000
800
700
600
500
400
300
200
800
700
600
500
400
300
200
100
10
20
VCC = 2.2 V
30 40 50 60 7080 100
CL, Load Capacitance (pF)
200
One output active at a time.
Figure 8-12. Typical Oscillation Frequency vs
Load Capacitance
Copyright © 2021 Texas Instruments Incorporated
100
10
VCC = 3.0 V
20
30 40 50 60 7080 100
CL, Load Capacitance (pF)
200
One output active at a time.
Figure 8-13. Typical Oscillation Frequency vs
Load Capacitance
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
49
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.12.6 LEA (Low-Energy Accelerator) (MSP430FR599x Only)
The LEA module is a hardware engine designed for operations that involve vector-based signal processing.
Section 8.12.6.1 lists the performance characteristics of the LEA module.
8.12.6.1 Low Energy Accelerator Performance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLEA
Frequency for specified
performance
MCLK
W_LEA_FFT
LEA subsystem energy on
fast Fourier transform
Complex FFT 128-point Q.15 with
random data in LEA-RAM
W_LEA_FIR
LEA subsystem energy on
finite impulse response
W_LEA_ADD
LEA subsystem energy on
additions
MIN
TYP
MAX
UNIT
16
MHz
VCore = 3 V,
MCLK = 16 MHz
350
nJ
Real FIR on random Q.31 data with
128 taps on 24 points
VCore = 3 V,
MCLK = 16 MHz
2.6
µJ
On 32 Q.31 elements with random
value out of LEA-RAM with linear
address increment
VCore = 3 V,
MCLK = 16 MHz
6.6
nJ
8.12.7 Timer_A and Timer_B
Timer_A and Timer_B are 16-bit timers and counters with multiple capture/compare registers. Section 8.12.7.1
lists the Timer_A characteristics, and Section 8.12.7.2 lists the Timer_B characteristics.
8.12.7.1 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTA
Timer_A input clock frequency
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
2.2 V, 3.0 V
tTA,cap
Timer_A capture timing
All capture inputs, minimum pulse duration required
for capture
2.2 V, 3.0 V
MIN
MAX
UNIT
16
MHz
20
ns
8.12.7.2 Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTB
Timer_B input clock frequency
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
2.2 V, 3.0 V
tTB,cap
Timer_B capture timing
All capture inputs, minimum pulse duration required
for capture
2.2 V, 3.0 V
50
Submit Document Feedback
MIN
20
MAX
UNIT
16
MHz
ns
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.12.8 eUSCI
The enhanced universal serial communication interface (eUSCI) supports multiple serial communication modes
with one hardware module. The eUSCI_A module supports UART and SPI modes. The eUSCI_B module
supports I2C and SPI modes.
Section 8.12.8.1 lists the UART clock frequencies.
8.12.8.1 eUSCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
16
MHz
4
MHz
MIN
MAX
UNIT
UCGLITx = 0
5
30
UCGLITx = 1
20
90
35
160
50
220
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency (equals baud rate in MBaud)
Section 8.12.8.2 lists the UART operating characteristics.
8.12.8.2 eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tt
UART receive deglitch time(1)
TEST CONDITIONS
UCGLITx = 2
UCGLITx = 3
(1)
VCC
2.2 V, 3.0 V
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch
time can limit the maximum useable baud rate. To ensure that pulses are correctly recognized, their duration should exceed the
maximum specification of the deglitch time.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
51
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Section 8.12.8.3 lists the SPI master mode clock frequencies.
8.12.8.3 eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
feUSCI
TEST CONDITIONS
MIN
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
eUSCI input clock frequency
MAX
UNIT
16
MHz
Section 8.12.8.4 lists the SPI master mode operating characteristics.
8.12.8.4 eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time, STE active to clock
UCSTEM = 1, UCMODEx = 01 or 10
1
tSTE,LAG
STE lag time, Last clock to STE
inactive
UCSTEM = 1, UCMODEx = 01 or 10
1
tSTE,ACC
STE access time, STE active to
SIMO data out
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V,
3.0 V
60
ns
tSTE,DIS
STE disable time, STE inactive to
SOMI high impedance
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V,
3.0 V
80
ns
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time(2)
UCLK edge to SIMO valid,
CL = 20 pF
tHD,MO
SIMO output data hold time(3)
CL = 20 pF
(1)
(2)
(3)
52
2.2 V
40
3.0 V
40
2.2 V
0
3.0 V
0
UCxCLK
cycles
ns
ns
2.2 V
11
3.0 V
10
2.2 V
0
3.0 V
0
ns
ns
fUCxCLK = 1/2 tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8-14 and Figure 8-15.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure
8-14 and Figure 8-15.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 8-14. SPI Master Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tVALID,MO
tSTE,DIS
SIMO
Figure 8-15. SPI Master Mode, CKPH = 1
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
53
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Section 8.12.8.5 lists the SPI slave mode operating characteristics.
8.12.8.5 eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time(2)
UCLK edge to SOMI valid,
CL = 20 pF
tHD,SO
SOMI output data hold time(3)
CL = 20 pF
(1)
(2)
(3)
54
VCC
MIN
2.2 V
45
3.0 V
40
2.2 V
2
3.0 V
3
MAX
ns
ns
2.2 V
45
3.0 V
40
2.2 V
50
3.0 V
45
2.2 V
4
3.0 V
4
2.2 V
7
3.0 V
7
35
35
0
0
ns
ns
2.2 V
2.2 V
ns
ns
3.0 V
3.0 V
UNIT
ns
ns
fUCxCLK = 1/2 tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8-16 and Figure 8-17.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure
8-16 and Figure 8-17.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SI
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tSTE,ACC
tSTE,DIS
tVALID,SO
SOMI
Figure 8-16. SPI Slave Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 8-17. SPI Slave Mode, CKPH = 1
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
55
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Section 8.12.8.6 lists the I2C mode operating characteristics.
8.12.8.6 eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8-18)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
MAX
UNIT
16
MHz
400
kHz
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.2 V, 3.0 V
0
ns
tSU,DAT
Data setup time
2.2 V, 3.0 V
100
ns
tSU,STO
Setup time for STOP
2.2 V, 3.0 V
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
tSP
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
0
4.0
4.7
4.0
µs
0.6
50
250
UCGLITx = 1
25
125
12.5
62.5
6.3
31.5
UCGLITx = 2
2.2 V, 3.0 V
UCCLTOx = 1
UCCLTOx = 2
Clock low time-out
µs
0.6
UCGLITx = 0
UCGLITx = 3
tTIMEOUT
µs
0.6
27
30
2.2 V, 3.0 V
UCCLTOx = 3
tSU,STA
tHD,STA
ns
ms
33
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 8-18. I2C Mode Timing
56
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
8.12.9 ADC12_B
The ADC12_B module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, and up to 32 independent conversion-and-control buffers. The conversion-andcontrol buffer allows up to 32 independent analog-to-digital converter (ADC) samples to be converted and stored
without any CPU intervention.
Section 8.12.9.1 lists the power supply and input range conditions.
8.12.9.1 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(Ax)
Analog input voltage
TEST CONDITIONS
range(1)
VCC
All ADC12 analog input pins Ax
MIN
NOM
0
MAX UNIT
AVCC
3.0 V
145
199
Operating supply current into
AVCC plus DVCC terminals(2) (3)
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 0,
REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
2.2 V
140
190
fADC12CLK = MODCLK, ADC12ON = 1,
ADC12PWRMD = 0, ADC12DIF = 1,
REFON = 0, ADC12SHTx= 0,
ADC12DIV = 0
3.0 V
175
245
Operating supply current into
AVCC plus DVCC terminals(2) (3)
2.2 V
170
230
fADC12CLK = MODCLK / 4, ADC12ON = 1,
ADC12PWRMD = 1, ADC12DIF = 0,
REFON = 0, ADC12SHTx = 0,
ADC12DIV = 0
3.0 V
85
125
Operating supply current into
AVCC plus DVCC terminals(2) (3)
2.2 V
83
120
fADC12CLK = MODCLK / 4, ADC12ON = 1,
ADC12PWRMD = 1, ADC12DIF = 1,
REFON = 0, ADC12SHTx= 0,
ADC12DIV = 0
3.0 V
110
165
Operating supply current into
AVCC plus DVCC terminals(2) (3)
2.2 V
109
160
CI
Input capacitance
Only one terminal Ax can be selected at
one time
2.2 V
10
15
RI
Input MUX ON-resistance
0 V ≤ V(Ax) ≤ AVCC
>2 V
0.5
4
50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Timer_B TBx
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Ax in
UART mode
Clocked by SMCLK
Clocked by ACLK
Waiting for first edge of START bit.
eUSCI_Ax in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Ax in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Bx in I2C
master mode
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Not applicable
eUSCI_Bx in I2C
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Waiting for START condition or
clocked by external clock ≤50 kHz
eUSCI_Bx in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Bx in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Clocked by SMCLK or by MODOSC
Clocked by ACLK
Waiting for a trigger
REF_A
Not applicable
Not applicable
Always
COMP_E
Not applicable
Not applicable
Always
CRC(5)
Not applicable
Not applicable
Not applicable
MPY(5)
Not applicable
Not applicable
Not applicable
AES(5)
Not applicable
Not applicable
Not applicable
ADC12_B
(1)
(2)
(3)
(4)
(5)
Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz
Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.
Peripherals are in a state that does not require or does not use an internal clock.
The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power
mode causes a temporary transition into active mode for the time of the transfer.
This peripheral operates during active mode only and will delay the transition into a low-power mode until its operation is completed.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
69
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
www.ti.com
9.4.2 Idle Currents of Peripherals in LPM3 and LPM4
Most peripherals can be operational in LPM3 if clocked by ACLK. Some modules are operational in LPM4,
because they do not require a clock to operate (for example, the comparator). Activating a peripheral in LPM3 or
LPM4 increases the current consumption due to its active supply current contribution but also due to an
additional idle current. To reduce the idle current adder, certain peripherals are grouped together (see Table 9-3).
To achieve optimal current consumption, use modules within one group and limit the number of groups with
active modules. Modules not listed in Table 9-3 are either already included in the standard LPM3 current
consumption or cannot be used in LPM3 or LPM4.
The idle current adder is very small at room temperature (25°C) but increases at high temperatures (85°C). See
the IIDLE current parameters in Section 8 for details.
Table 9-3. Peripheral Groups
GROUP A
GROUP B
GROUP C
Timer TA1
Timer TA0
Timer TA4
Timer TA2
Timer TA3
eUSCI_A2
Timer TB0
Comparator
eUSCI_A3
eUSCI_A0
ADC12_B
eUSCI_B1
eUSCI_A1
REF_A
eUSCI_B2
eUSCI_B0
eUSCI_B3
9.5 Interrupt Vector Table and Signatures
The interrupt vectors, the power-up start address and signatures are in the address range 0FFFFh to 0FF80h.
Figure 9-1 summarizes the content of this address range.
Reset Vector
0FFFFh
BSL Password
Interrupt
Vectors
0FFE0h
JTAG Password
Reserved
Signatures
0FF88h
0FF80h
Figure 9-1. Interrupt Vectors, Signatures and Passwords
The power-up start address or reset vector is at 0FFFFh to 0FFFEh. This location contains a 16-bit address
pointing to the start address of the application program.
The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit address of
the appropriate interrupt-handler instruction sequence. Table 9-4 shows the device specific interrupt vector
locations.
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if enabled
by the corresponding signature).
The signatures are at 0FF80h and extend to higher addresses. Signatures are evaluated during device start-up.
Table 9-5 lists the device-specific signature locations.
70
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
A JTAG password can be programmed starting at address 0FF88h and extending to higher addresses. The
password can extend into the interrupt vector locations using the interrupt vector addresses as additional bits for
the password. The length of the JTAG password depends on the JTAG signature.
See the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.
Table 9-4. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
INTERRUPT
VECTOR
REGISTER
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
SYSRSTIV(1)
Reset
0FFFEh
Highest
SYSSNIV(1)
(Non)maskable(3)
0FFFCh
SYSUNIV(1)
(Non)maskable(3)
0FFFAh
System Reset
Power up, brownout,
supply supervisor
SVSHIFG
External reset, RST
PMMRSTIFG
Watchdog time-out
(watchdog mode)
WDTIFG
WDT, FRCTL MPU, CS,
PMM password violation
WDTPW, FRCTLPW, MPUPW, CSPW,
PMMPW
FRAM uncorrectable bit
error detection
UBDIFG
MPU segment violation
MPUSEGIIFG, MPUSEG1IFG,
MPUSEG2IFG, MPUSEG3IFG
Software POR, BOR
PMMPORIFG, PMMBORIFG
System NMI
Vacant memory access(2)
VMAIFG
JTAG mailbox
JMBINIFG, JMBOUTIFG
FRAM access time error
ACCTEIFG
FRAM write protection
error
WPIFG
FRAM bit error detection
CBDIFG, UBDIFG
MPU segment violation
MPUSEGIIFG, MPUSEG1IFG,
MPUSEG2IFG, MPUSEG3IFG
User NMI
External NMI
NMIIFG
Oscillator fault
OFIFG
Comparator_E
CEIFG, CEIIFG
TB0
TB0CCR0 CCIFG
TB0
TB0CCR1 CCIFG to TB0CCR6 CCIFG,
TB0CTL.TBIFG
Watchdog timer (interval
timer mode)
WDTIFG
eUSCI_A0 receive or
transmit
CEIV(1)
Maskable
0FFF8h
Maskable
0FFF6h
Maskable
0FFF4h
Maskable
0FFF2h
UCA0IV(1)
Maskable
0FFF0h
UCB0IV(1)
Maskable
0FFEEh
ADC12IV(1)
Maskable
0FFECh
TB0IV(1)
UCRXIFG, UCTXIFG (SPI mode)
UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
eUSCI_B0 receive or
transmit
ADC12_B(4)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I2C mode)
ADC12IFG0 to ADC12IFG31,
ADC12LOIFG, ADC12INIFG,
ADC12HIIFG, ADC12RDYIFG,
ADC21OVIFG, ADC12TOVIFG
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
71
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 9-4. Interrupt Sources, Flags, and Vectors (continued)
WORD
ADDRESS
Maskable
0FFEAh
TA0IV(1)
Maskable
0FFE8h
UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCA1IV(1)
Maskable
0FFE6h
DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,
DMA2CTL.DMAIFG
DMAIV(1)
Maskable
0FFE4h
Maskable
0FFE2h
INTERRUPT FLAG
TA0
TA0CCR0 CCIFG
TA0
TA0CCR1 CCIFG, TA0CCR2 CCIFG,
TA0CTL.TAIFG
eUSCI_A1 receive or
transmit
DMA
INTERRUPT
VECTOR
REGISTER
SYSTEM
INTERRUPT
INTERRUPT SOURCE
UCRXIFG, UCTXIFG (SPI mode)
TA1
TA1CCR0 CCIFG
TA1
TA1CCR1 CCIFG, TA1CCR2 CCIFG,
TA1CTL.TAIFG
TA1IV(1)
Maskable
0FFE0h
I/O port P1
P1IFG.0 to P1IFG.7
P1IV(1)
Maskable
0FFDEh
Maskable
0FFDCh
Maskable
0FFDAh
TA2
TA2CCR0 CCIFG
TA2
TA2CCR1 CCIFG, TA2CTL.TAIFG
TA2IV(1)
I/O port P2
P2IFG.0 to P2IFG.7
P2IV(1)
TA3
TA3CCR0 CCIFG
Maskable
0FFD8h
Maskable
0FFD6h
TA3
TA3CCR1 CCIFG, TA3CTL.TAIFG
TA3IV(1)
Maskable
0FFD4h
I/O port P3
P3IFG.0 to P3IFG.7
P3IV(1)
Maskable
0FFD2h
I/O port P4
P4IFG.0 to P4IFG.7
P4IV(1)
Maskable
0FFD0h
RTC_C
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG
RTCIV(1)
Maskable
0FFCEh
AES
AESRDYIFG
Maskable
0FFCCh
TA4
TA4CCR0 CCIFG
Maskable
0FFCAh
TA4
TA4CCR1 CCIFG, TA4CTL.TAIFG
TA4IV(1)
Maskable
0FFC8h
I/O port P5
P5IFG.0 to P5IFG.7
P5IV(1)
Maskable
0FFC6h
P6IFG.0 to P6IFG.7
P6IV(1)
Maskable
0FFC4h
UCA2IV(1)
Maskable
0FFC2h
UCA3IV(1)
Maskable
0FFC0h
UCB1IV(1)
Maskable
0FFBEh
UCB2IV(1)
Maskable
0FFBCh
UCB3IV(1)
Maskable
0FFBAh
I/O port P6
eUSCI_A2 receive or
transmit
eUSCI_A3 receive or
transmit
PRIORITY
UCRXIFG, UCTXIFG (SPI mode)
UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
eUSCI_B1 receive or
transmit
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I2C mode)
UCRXIFG, UCTXIFG (SPI mode)
eUSCI_B2 receive or
transmit
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I2C mode)
UCRXIFG, UCTXIFG (SPI mode)
eUSCI_B3 receive or
transmit
72
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I2C mode)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
Table 9-4. Interrupt Sources, Flags, and Vectors (continued)
(1)
(2)
(3)
(4)
INTERRUPT SOURCE
INTERRUPT FLAG
INTERRUPT
VECTOR
REGISTER
SYSTEM
INTERRUPT
WORD
ADDRESS
I/O port P7
P7IFG.0 to P7IFG.7
P7IV(1)
Maskable
0FFB8h
I/O port P8
P8IFG.0 to P8IFG.7
P8IV(1)
Maskable
0FFB6h
LEA (MSP430FR599x
only)
CMDIFG, SDIIFG, OORIFG,TIFG,
COVLIFG
LEAIV(1)
Maskable
0FFB4h
PRIORITY
Lowest
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from peripheral space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
Only on devices with ADC, otherwise reserved.
Table 9-5. Signatures
SIGNATURE
WORD ADDRESS
IP Encapsulation Signature 2
IP Encapsulation Signature
0FF8Ah
1(1)
0FF88h
BSL Signature 2
(1)
0FF86h
BSL Signature 1
0FF84h
JTAG Signature 2
0FF82h
JTAG Signature 1
0FF80h
Must not contain 0AAAAh if used as the JTAG password.
9.6 Bootloader (BSL)
The BSL can program the FRAM or RAM using a UART serial interface (FRxxxx devices) or an I2C interface
(FRxxxx1 devices). Access to the device memory through the BSL is protected by an user-defined password.
Table 9-6 lists the pins that are required to use the BSL. BSL entry requires a specific entry sequence on the
RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the features of the BSL and its
implementation, see the MSP430 FRAM Devices Bootloader (BSL) User's Guide. Visit Bootloader (BSL) for
MSP low-power microcontrollers for more information.
Table 9-6. BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P2.0
Devices with UART BSL (FRxxxx): Data transmit
P2.1
Devices with UART BSL (FRxxxx): Data receive
P1.6
Devices with I2C BSL (FRxxxx1): Data
P1.7
Devices with I2C BSL (FRxxxx1): Clock
DVCC
Power supply
DVSS
Ground supply
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
73
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
www.ti.com
9.7 JTAG Operation
9.7.1 JTAG Standard Interface
The MSP family supports the standard JTAG interface, which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP
development tools and device programmers. Table 9-7 lists the JTAG pin requirements. For further details on
interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a
complete description of the features of the JTAG interface and its implementation, see MSP430 Programming
With the JTAG Interface.
Table 9-7. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
DVCC
Power supply
DVSS
Ground supply
9.7.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP family supports the two wire Spy-Bi-Wire interface. Spy-BiWire can be used to interface with MSP development tools and device programmers. The Spy-Bi-Wire interface
pin requirements are shown in Table 9-8. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the
JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface.
Table 9-8. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
74
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
Submit Document Feedback
DVCC
Power supply
DVSS
Ground supply
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
www.ti.com
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
9.8 FRAM Controller A (FRCTL_A)
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in system by the CPU
(also see Table 9-45 for control and configuration registers). Features of the FRAM include:
•
•
•
•
Ultra-low-power ultra-fast-write nonvolatile memory
Byte and word access capability
Programmable wait state generation
Error correction coding (ECC)
Note
Wait States
For MCLK frequencies > 8 MHz, wait states must be configured following the flow described in the
"Wait State Control" section of the FRAM Controller A (FRCTRL_A) chapter in the MSP430FR58xx,
MSP430FR59xx, and MSP430FR6xx Family User's Guide.
For important software design information regarding FRAM including but not limited to partitioning the memory
layout according to application-specific code, constant, and data space requirements, the use of FRAM to
optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to maximize
application robustness by protecting the program code against unintended write accesses, see MSP430™
FRAM Technology – How To and Best Practices.
9.9 RAM
The RAM is made up of three sectors: Sector 0 = 2KB, Sector 1 = 2KB, and Sector 2 = 4KB (shared with the
LEA module). Each sector can be individually powered down in LPM3 and LPM4 to save leakage. Data is lost
when sectors are powered down in LPM3 and LPM4. See Table 9-47 for control and configuration registers.
9.10 Tiny RAM
Tiny RAM provides 22 bytes of RAM in addition to the complete RAM (see Table 9-41). This memory is always
available, even in LPM3 and LPM4, while the complete RAM can be powered down in LPM3 and LPM4. Tiny
RAM can be used to hold data or a very small stack when the complete RAM is powered down in LPM3 and
LPM4. No memory is available in LPMx.5.
9.11 Memory Protection Unit (MPU) Including IP Encapsulation
The FRAM can be protected by the MPU from inadvertent CPU execution, read access, or write access. See
Table 9-67 for control and configuration registers. Features of the MPU include:
•
•
•
•
IP encapsulation with programmable boundaries in steps of 1KB (prevents reads from "outside"; for example,
through JTAG or by non-IP software).
Main memory partitioning is programmable up to three segments in steps of 1KB.
Access rights of each segment can be individually selected (main and information memory).
Access violation flags with interrupt capability for easy servicing of access violations.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: MSP430FR5994 MSP430FR59941 MSP430FR5992 MSP430FR5964 MSP430FR5962
75
MSP430FR5994, MSP430FR59941, MSP430FR5992, MSP430FR5964, MSP430FR5962
SLASE54D – MARCH 2016 – REVISED JANUARY 2021
www.ti.com
9.12 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430FR58xx, MSP430FR59xx,
and MSP430FR6xx Family User's Guide.
9.12.1 Digital I/O
Up to nine 8-bit I/O ports are implemented (see Table 9-52 through Table 9-56 for control and configuration
registers):
•
•
•
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all pins of ports
P1 to P8.
Read and write access to port control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise in pairs.
All pins of ports P1 to P8, and PJ support capacitive touch functionality.
No cross-currents during start-up.
Note
Configuration of Digital I/Os After BOR Reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance with
Schmitt triggers and their module functions disabled. To enable the I/O functionality after a BOR reset,
first configure the ports and then clear the LOCKLPM5 bit. For details, see the Configuration After
Reset section of the Digital I/O chapter in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx
Family User's Guide.
9.12.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch-crystal oscillator XT1 (LF), an internal very-low-power
low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency
crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements of both low system
cost and low power consumption. A fail-safe mechanism exists for all crystal sources. See Table 9-49 for control
and configuration registers.
The clock system module provides the following clock signals:
•
•
•
Auxiliary clock (ACLK). ACLK can be sourced from a 32-kHz watch crystal (LFXT1), the internal VLO, or a
digital external low-frequency (
工商网监
湘ICP备2023018690号
