MSP430FR6005IPZ

MSP430FR6007, MSP430FR6005 MSP430FR6007, MSP430FR6005 SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 www.ti.com MSP430FR600x Ultrasonic Sensing MSP430™ Microcontrollers for Water‑Metering Applications 1 Features • • • • • • • Best-in-class ultrasonic water-flow measurement with ultra-low power consumption – 74-dB SNR due to jitter; that is, limited by ADC performance. 2 3 dfDCO/dT DCO temperature drift(1) (1) (2) 40 48% 3.0 V 0.01 ns %/°C Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) After a wakeup from LPM1, LPM2, LPM3, or LPM4, the DCO frequency fDCO might exceed the specified frequency range for a few clock cycles by up to 5% before settling to the specified steady state frequency range. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS IVLO Current consumption fVLO VLO frequency Measured at ACLK MIN TYP MAX 100 6 UNIT nA 9.4 14 kHz dfVLO/dT VLO frequency temperature drift Measured at ACLK(1) 0.2 %/°C dfVLO/dVCC VLO frequency supply voltage drift Measured at ACLK(2) 0.7 %/V fVLO,DC Duty cycle Measured at ACLK (1) (2) 40% 50% 60% Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) 8.13.3.5 Module Oscillator (MODOSC) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS IMODOSC Current consumption fMODOSC MODOSC frequency fMODOSC/dT MODOSC frequency temperature drift(1) fMODOSC/dVCC MODOSC frequency supply voltage drift(2) DCMODOSC (1) (2) MIN Enabled Duty cycle MAX 25 4.0 Measured at SMCLK, divide by 1 TYP 40% 4.8 UNIT μA 5.4 MHz 0.08 %/℃ 1.4 %/V 50% 60% Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 Submit Document Feedback 41 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.4 Wake-up Characteristics 8.13.4.1 Wake-up Times From Low-Power Modes and Reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 6 10 μs 400 + 1.5/fDCO ns tWAKE-UP FRAM (Additional) wake-up time to activate the FRAM in AM if previously disabled by the FRAM controller or from an LPM if immediate activation is selected for wakeup tWAKE-UP LPM0 Wake-up time from LPM0 to active mode(1) 2.2 V, 3.0 V tWAKE-UP LPM1 Wake-up time from LPM1 to active mode(1) 2.2 V, 3.0 V 6 μs tWAKE-UP LPM2 Wake-up time from LPM2 to active mode(1) 2.2 V, 3.0 V 6 μs tWAKE-UP LPM3 Wake-up time from LPM3 to active mode(1) 2.2 V, 3.0 V 6.6 + 9.6 + 2.0/fDCO 2.5/fDCO tWAKE-UP LPM4 Wake-up time from LPM4 to active mode(1) 2.2 V, 3.0 V 6.6 + 9.6 + 2.0/fDCO 2.5/fDCO tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode(2) μs μs 2.2 V, 3.0 V 350 450 SVSHE = 1 2.2 V, 3.0 V 350 450 μs μs SVSHE = 0 2.2 V, 3.0 V 0.4 0.8 ms tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode(2) tWAKE-UP-RST Wake-up time from a RST pin triggered reset to active mode(2) 2.2 V, 3.0 V 480 596 μs tWAKE-UP-BOR Wake-up time from power-up to active mode (2) 2.2 V, 3.0 V 0.5 1 ms (1) (2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first externally observable MCLK clock edge with MCLKREQEN = 1. This time includes the activation of the FRAM during wakeup. With MCLKREQEN = 0, the externally observable MCLK clock is gated one additional cycle. The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first instruction of the user program is executed. 8.13.4.2 Typical Wake-up Charges over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) PARAMETER QWAKE-UP FRAM Charge used for activating the FRAM in AM or during wakeup from LPM0 if previously disabled by the FRAM controller. TEST CONDITIONS MIN TYP MAX UNIT 16.5 nAs QWAKE-UP LPM0 Charge used to wake up from LPM0 to active mode (with FRAM active) 3.8 nAs QWAKE-UP LPM1 Charge used to wake up from LPM1 to active mode (with FRAM active) 21 nAs QWAKE-UP LPM2 Charge used to wake up from LPM2 to active mode (with FRAM active) 22 nAs QWAKE-UP LPM3 Charge used to wake up from LPM3 to active mode (with FRAM active) 28 nAs QWAKE-UP LPM4 Charge used to wake up from LPM4 to active mode (with FRAM active) QWAKE-UP LPM3.5 Charge used to wake up from LPM3.5 to active mode(2) QWAKE-UP LPM4.5 Charge used to wake up from LPM4.5 to active mode(2) QWAKE-UP-RESET Charge used for reset from RST or BOR event to active mode(2) (1) (2) 42 28 nAs 170 nAs SVSHE = 1 173 SVSHE = 0 171 148 nAs nAs Charge used during the wake-up time from a given low-power mode to active mode. This does not include the energy required in active mode (for example, for an interrupt service routine). Charge required until start of user code. This does not include the energy required to reconfigure the device. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.4.3 Typical Characteristics, Average LPM Currents vs Wake-up Frequency Figure 8-6 shows the average LPM currents vs wake-up frequency at 25°C. 10000.00 LPM0 LPM1 Average Wake-up Current (µA) 1000.00 LPM2,XT12 LPM3,XT12 LPM3.5,XT12 100.00 10.00 1.00 0.10 0.001 0.01 0.1 1 10 100 1000 10000 100000 Wake-up Frequency (Hz) The average wake-up current does not include the energy required in active mode; for example, for an interrupt service routine or to reconfigure the device. Figure 8-6. Average LPM Currents vs Wake-up Frequency at 25°C Figure 8-7 shows the average LPM currents vs wake-up frequency at 85°C. 10000.00 LPM0 LPM1 Average Wake-up Current (µA) 1000.00 LPM2,XT12 LPM3,XT12 LPM3.5,XT12 100.00 10.00 1.00 0.10 0.001 0.01 0.1 1 10 100 1000 10000 100000 Wake-up Frequency (Hz) The average wake-up current does not include the energy required in active mode; for example, for an interrupt service routine or to reconfigure the device. Figure 8-7. Average LPM Currents vs Wake-up Frequency at 85°C Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 Submit Document Feedback 43 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.5 Digital I/Os 8.13.5.1 Digital Inputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX 2.2 V 1.2 1.65 3.0 V 1.65 2.25 UNIT VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) RPull Pullup or pulldown resistor For pullup: VIN = VSS For pulldown: VIN = VCC CI,dig Input capacitance, digital only port pins VIN = VSS or VCC 3 pF CI,ana Input capacitance, port pins with shared analog functions(1) VIN = VSS or VCC 5 pF Ilkg(Px.y) High-impedance input leakage current See (2) (3) 2.2 V, 3.0 V –20 t(int) External interrupt timing (external trigger pulse duration to set interrupt flag)(4) Ports with interrupt capability (see Section 7.3) 2.2 V, 3.0 V 20 ns t(RST) External reset pulse duration on RST (5) 2.2 V, 3.0 V 2 µs (1) (2) (3) (4) (5) 44 2.2 V 0.55 1.00 3.0 V 0.75 1.35 2.2 V 0.44 0.98 3.0 V 0.60 1.30 20 35 50 +20 V V V kΩ nA If the port pins PJ.4/LFXIN and PJ.5/LFXOUT are used as digital I/Os, they are connected by a 4-pF capacitor and a 35-MΩ resistor in series. At frequencies of approximately 1 kHz and lower, the 4-pF capacitor can add to the pin capacitance of PJ.4/LFXIN and/or PJ.5/ LFXOUT. The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted. The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It might be set by trigger signals shorter than t(int). Not applicable if RST/NMI pin configured as NMI Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.5.2 Digital Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VCC – 0.60 VCC I(OHmax) = –2 mA(1) VCC – 0.25 VCC VCC – 0.60 VCC VSS VSS + 0.25 I(OLmax) = 3 mA(2) VSS VSS + 0.60 I(OLmax) = 2 mA(1) VSS VSS + 0.25 VSS VSS + 0.60 3.0 V I(OHmax) = –6 mA(2) I(OLmax) = 1 mA(1) VOL 3.0 V I(OLmax) = 6 mA(2) fPx.y Port output frequency (with load)(5) CL = 20 pF, RL (3) (4) fPort_CLK Clock output frequency(5) ACLK, MCLK, or SMCLK at configured output port, CL = 20 pF(4) trise,dig Port output rise time, digital only port pins CL = 20 pF tfall,dig Port output fall time, digital only port pins CL = 20 pF trise,ana Port output rise time, port pins with shared analog functions CL = 20 pF tfall,ana Port output fall time, port pins with shared analog functions CL = 20 pF (1) (2) (3) (4) (5) 2.2 V 16 3.0 V 16 2.2 V 16 3.0 V 16 UNIT V 2.2 V Low-level output voltage (see Figure 8-8 and Figure 8-9) MAX I(OHmax) = –3 mA(2) 2.2 V VOH TYP VCC I(OHmax) = –1 mA(1) High-level output voltage (see Figure 8-10 and Figure 8-11) MIN VCC – 0.25 V MHz MHz 2.2 V 4 15 3.0 V 3 15 2.2 V 4 15 3.0 V 3 15 2.2 V 6 15 3.0 V 4 15 2.2 V 6 15 3.0 V 4 15 ns ns ns ns The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified. The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified. A resistive divider with 2 × R1 and R1 = 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider. CL = 20 pF is connected from the output to VSS. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. The port can output frequencies at least up to the specified limit, and the port might support higher frequencies. Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 Submit Document Feedback 45 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.5.3 Typical Characteristics, Digital Outputs 30 25°C 85°C Low-Level Output Current (mA) Low-Level Output Current (mA) 15 10 5 25°C 85°C 20 10 P1.1 P1.1 0 0 0 0.5 1 1.5 2 0 0.5 1 Low-Level Output Voltage (V) 1.5 2 2.5 3 Low-Level Output Voltage (V) C001 VCC = 2.2 V VCC = 3.0 V Figure 8-8. Typical Low-Level Output Current vs Low-Level Output Voltage Figure 8-9. Typical Low-Level Output Current vs Low-Level Output Voltage 0 0 25°C 85°C High-Level Output Current (mA) High-Level Output Current (mA) C001 -5 -10 25°C 85°C -10 -20 P1.1 P1.1 -15 -30 0 0.5 1 1.5 2 0 0.5 High-Level Output Voltage (V) 1 1.5 2 2.5 C001 VCC = 2.2 V C001 VCC = 3.0 V Figure 8-10. Typical High-Level Output Current vs High-Level Output Voltage 46 3 High-Level Output Voltage (V) Figure 8-11. Typical High-Level Output Current vs High-Level Output Voltage Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.6 LEA 8.13.6.1 Low-Energy Accelerator (LEA) Performance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fLEA Frequency for specified performance MCLK W_LEA_FFT LEA subsystem energy on fast Fourier transform Complex FFT 128 pt. Q.15 with random data in LEA-RAM W_LEA_FIR LEA subsystem energy on finite impulse response W_LEA_ADD LEA subsystem energy on additions MIN TYP MAX UNIT 16 MHz VCORE = 3 V, MCLK = 16 MHz 350 nJ Real FIR on random Q.31 data with 128 taps on 24 points VCORE = 3 V, MCLK = 16 MHz 2.6 µJ On 32 Q.31 elements with random value out of LEA-RAM with linear address increment VCORE = 3 V, MCLK = 16 MHz 6.6 nJ 8.13.7 Timer_A and Timer_B 8.13.7.1 Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTA Timer_A input clock frequency Internal: SMCLK or ACLK, External: TACLK, Duty cycle = 50% ±10% tTA,cap Timer_A capture timing All capture inputs, minimum pulse duration required for capture VCC 2.2 V, 3.0 V 2.2 V, 3.0 V MIN TYP MAX UNIT 16 MHz 20 ns 8.13.7.2 Timer_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTB Timer_B input clock frequency Internal: SMCLK or ACLK, External: TBCLK, Duty cycle = 50% ±10% tTB,cap Timer_B capture timing All capture inputs, minimum pulse duration required for capture VCC 2.2 V, 3.0 V 2.2 V, 3.0 V Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 MIN 20 TYP MAX UNIT 16 MHz ns Submit Document Feedback 47 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.8 eUSCI 8.13.8.1 eUSCI (UART Mode) Clock Frequency PARAMETER feUSCI eUSCI input clock frequency fBITCLK BITCLK clock frequency (equals baud rate in MBaud) CONDITIONS MIN Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10% MAX UNIT 16 MHz 4 MHz 8.13.8.2 eUSCI (UART Mode) Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN UCGLITx = 0 UCGLITx = 1 UART receive deglitch time(1) tt 2.2 V, 3.0 V UCGLITx = 2 UCGLITx = 3 (1) TYP MAX 5 UNIT 30 20 90 35 160 50 220 ns Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch time can limit the maximum useable baud rate. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time. 8.13.8.3 eUSCI (SPI Master Mode) Clock Frequency TEST CONDITIONS PARAMETER feUSCI MIN Internal: SMCLK or ACLK, Duty cycle = 50% ±10% eUSCI input clock frequency MAX UNIT 16 MHz MAX UNIT 8.13.8.4 eUSCI (SPI Master Mode) Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) PARAMETER TEST CONDITIONS VCC MIN TYP tSTE,LEAD STE lead time, STE active to clock UCSTEM = 1, UCMODEx = 01 or 10 1 tSTE,LAG STE lag time, Last clock to STE inactive UCSTEM = 1, UCMODEx = 01 or 10 1 tSTE,ACC STE access time, STE active to SIMO data out UCSTEM = 0, UCMODEx = 01 or 10 2.2 V, 3.0 V 60 ns tSTE,DIS STE disable time, STE inactive to SOMI high impedance UCSTEM = 0, UCMODEx = 01 or 10 2.2 V, 3.0 V 80 ns tSU,MI SOMI input data setup time tHD,MI SOMI input data hold time tVALID,MO SIMO output data valid time(2) UCLK edge to SIMO valid, CL = 20 pF tHD,MO SIMO output data hold time(3) CL = 20 pF (1) (2) (3) 48 2.2 V 40 3.0 V 40 2.2 V 0 3.0 V 0 UCxCLK cycles ns ns 2.2 V 11 3.0 V 10 2.2 V 0 3.0 V 0 ns ns fUCxCLK = 1/2 tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)). For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave. Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 8-12 and Figure 8-13. Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 8-12 and Figure 8-13. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.8.5 eUSCI (SPI Master Mode) Timing Diagrams UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tHD,MO tSTE,ACC tSTE,DIS tVALID,MO SIMO Figure 8-12. SPI Master Mode, CKPH = 0 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tHD,MO tSTE,ACC tVALID,MO tSTE,DIS SIMO Figure 8-13. SPI Master Mode, CKPH = 1 Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 Submit Document Feedback 49 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) PARAMETER TEST CONDITIONS tSTE,LEAD STE lead time, STE active to clock tSTE,LAG STE lag time, Last clock to STE inactive tSTE,ACC STE access time, STE active to SOMI data out tSTE,DIS STE disable time, STE inactive to SOMI high impedance tSU,SI SIMO input data setup time tHD,SI SIMO input data hold time tVALID,SO SOMI output data valid time(2) UCLK edge to SOMI valid, CL = 20 pF tHD,SO SOMI output data hold time(3) CL = 20 pF (1) (2) (3) 50 VCC MIN 2.2 V 45 3.0 V 40 2.2 V 2 3.0 V 3 MAX ns ns 2.2 V 45 3.0 V 40 2.2 V 50 3.0 V 45 2.2 V 4 3.0 V 4 2.2 V 7 3.0 V 7 35 35 3.0 V 0 ns ns 3.0 V 0 ns ns 2.2 V 2.2 V UNIT ns ns fUCxCLK = 1/2 tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)) For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master. Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 8-14 and Figure 8-15. Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 8-14 and Figure 8-15. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.8.7 eUSCI (SPI Slave Mode) Timing Diagrams UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tSU,SI tLOW/HIGH tHD,SI SIMO tHD,SO tSTE,ACC tSTE,DIS tVALID,SO SOMI Figure 8-14. SPI Slave Mode, CKPH = 0 UCMODEx = 01 tSTE,LEAD STE tSTE,LAG UCMODEx = 10 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLOW/HIGH tLOW/HIGH tHD,SI tSU,SI SIMO tHD,SO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 8-15. SPI Slave Mode, CKPH = 1 Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 Submit Document Feedback 51 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.8.8 eUSCI (I2C Mode) Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8-16) PARAMETER TEST CONDITIONS feUSCI eUSCI input clock frequency fSCL SCL clock frequency VCC MIN TYP Internal: SMCLK or ACLK, External: UCLK, Duty cycle = 50% ±10% 2.2 V, 3.0 V fSCL = 100 kHz 0 MAX UNIT 16 MHz 400 kHz 4.0 tHD,STA Hold time (repeated) START tSU,STA Setup time for a repeated START tHD,DAT Data hold time 2.2 V, 3.0 V 0 ns tSU,DAT Data setup time 2.2 V, 3.0 V 100 ns tSU,STO Setup time for STOP tBUF Bus free time between a STOP and START condition fSCL > 100 kHz fSCL = 100 kHz fSCL > 100 kHz fSCL = 100 kHz fSCL > 100 kHz Pulse duration of spikes suppressed by input filter tSP 2.2 V, 3.0 V 4.7 2.2 V, 3.0 V 4.0 2.2 V, 3.0 V µs 0.6 fSCL = 100 kHz 4.7 fSCL > 100 kHz 1.3 UCGLITx = 0 50 250 UCGLITx = 1 25 125 12.5 62.5 UCGLITx = 2 2.2 V, 3.0 V UCCLTOx = 2 us 6.3 UCCLTOx = 1 Clock low time-out µs 0.6 UCGLITx = 3 tTIMEOUT µs 0.6 ns 31.5 27 2.2 V, 3.0 V 30 UCCLTOx = 3 ms 33 8.13.8.9 eUSCI (I2C Mode) Timing Diagram tSU,STA tHD,STA tHD,STA tBUF SDA tLOW tHIGH tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 8-16. I2C Mode Timing 52 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.9 Segment LCD Controller 8.13.9.1 LCD_C Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) PARAMETER CONDITIONS MIN NOM MAX UNIT VCC,LCD_C,CP en,3.6 Supply voltage range, charge pump enabled, VLCD ≤ 3.6 V LCDCPEN = 1, 0000b < VLCDx ≤ 1111b (charge pump enabled, VLCD ≤ 3.6 V) 2.2 3.6 V VCC,LCD_C,CP en,3.3 Supply voltage range, charge pump enabled, VLCD ≤ 3.3 V LCDCPEN = 1, 0000b < VLCDx ≤ 1100b (charge pump enabled, VLCD ≤ 3.3 V) 2.0 3.6 V VCC,LCD_C,int. bias Supply voltage range, internal biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V VCC,LCD_C,ext. bias Supply voltage range, external biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V VCC,LCD_C,VLCDEXT Supply voltage range, external LCD voltage, internal or external biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 1 2.0 3.6 V VLCDCAP External LCD voltage at LCDCAP, internal or external biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 1 2.4 3.6 V CLCDCAP Capacitor value on LCDCAP when charge pump enabled LCDCPEN = 1, VLCDx > 0000b (charge pump enabled) fACLK,in ACLK input frequency range fLCD LCD frequency range fFRAME = (1 / (2 × mux)) × fLCD with mux = 1 (static) to 8 fFRAME,4mux LCD frame frequency range fFRAME,4mux(MAX) = (1 / (2 × 4)) × fLCD(MAX) = (1 / (2 × 4)) × 1024 Hz CPanel Panel capacitance fLCD = 1024 Hz, all common lines equally loaded VR33 Analog input voltage at R33 LCDCPEN = 0, VLCDEXT = 1 4.7–20% 4.7 10+20% µF 30 32.768 40 kHz 1024 Hz 128 Hz 10000 pF 0 2.4 VCC + 0.2 V VR33 V VR23,1/3bias Analog input voltage at R23 LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 VR13 VR03 + 2/3 × (VR33 – VR03) VR13,1/3bias Analog input voltage at R13 with 1/3 biasing LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 VR03 VR03 + 1/3 × (VR33 – VR03) VR23 V VR13,1/2bias Analog input voltage at R13 with 1/2 biasing LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 1 VR03 VR03 + 1/2 × (VR33 – VR03) VR33 V VR03 Analog input voltage at R03 R0EXT = 1 VLCD – VR03 Voltage difference between VLCD and LCDCPEN = 0, R0EXT = 1 R03 2.4 VLCDREF External LCD reference voltage applied at LCDREF 0.8 VLCDREFx = 01 Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 VSS V 1.0 VCC + 0.2 V 1.2 V Submit Document Feedback 53 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.9.2 LCD_C Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VLCD,0 VLCDx = 0000, VLCDEXT = 0 VCC MIN 2.4 V to 3.6 V TYP VLCD,1 LCDCPEN = 1, VLCDx = 0001b 2 V to 3.6 V VLCD,2 LCDCPEN = 1, VLCDx = 0010b 2 V to 3.6 V 2.66 VLCD,3 LCDCPEN = 1, VLCDx = 0011b 2 V to 3.6 V 2.72 2.49 2.60 VLCD,4 LCDCPEN = 1, VLCDx = 0100b 2 V to 3.6 V 2.78 VLCD,5 LCDCPEN = 1, VLCDx = 0101b 2 V to 3.6 V 2.84 VLCD,6 LCDCPEN = 1, VLCDx = 0110b 2 V to 3.6 V 2.90 VLCD,7 LCDCPEN = 1, VLCDx = 0111b 2 V to 3.6 V 2.96 LCDCPEN = 1, VLCDx = 1000b 2 V to 3.6 V 3.02 VLCD,9 LCDCPEN = 1, VLCDx = 1001b 2 V to 3.6 V 3.08 3.14 LCD voltage VLCD,8 VLCD,10 LCDCPEN = 1, VLCDx = 1010b 2 V to 3.6 V VLCD,11 LCDCPEN = 1, VLCDx = 1011b 2 V to 3.6 V 3.20 VLCD,12 LCDCPEN = 1, VLCDx = 1100b 2 V to 3.6 V 3.26 VLCD,13 LCDCPEN = 1, VLCDx = 1101b 2.2 V to 3.6 V 3.32 VLCD,14 LCDCPEN = 1, VLCDx = 1110b 2.2 V to 3.6 V 3.38 LCDCPEN = 1, VLCDx = 1111b 2.2 V to 3.6 V VLCD,15 VLCD,7,0.8 LCD voltage with external reference of 0.8 V LCDCPEN = 1, VLCDx = 0111b, VLCDREFx = 01b, VLCDREF = 0.8 V VLCD,7,1.0 LCD voltage with external reference of 1.0 V VLCD,7,1.2 MAX UNIT VCC 3.32 3.44 2.72 V 3.6 2 V to 3.6 V 2.96 × 0.8 V V LCDCPEN = 1, VLCDx = 0111b, VLCDREFx = 01b, VLCDREF = 1.0 V 2 V to 3.6 V 2.96 × 1.0 V V LCD voltage with external reference of 1.2 V LCDCPEN = 1, VLCDx = 0111b, VLCDREFx = 01b, VLCDREF = 1.2 V 2.2 V to 3.6 V 2.96 × 1.2 V V ΔVLCD Voltage difference between consecutive VLCDx settings ΔVLCD = VLCD,x – VLCD,x–1 with x = 0010b to 1111b ICC,Peak,CP Peak supply currents due to charge pump activities LCDCPEN = 1, VLCDx = 1111b external, with decoupling capacitor on DVCC supply ≥1 µF 2.2 V 600 tLCD,CP,on Time to charge CLCD when discharged CLCD = 4.7 µF, LCDCPEN = 0→1, VLCDx = 1111b 2.2 V 100 ICP,Load Maximum charge pump load current LCDCPEN = 1, VLCDx = 1111b 2.2 V RLCD,Seg LCD driver output impedance, segment LCDCPEN = 0, ILOAD = ±10 µA lines 2.2 V 10 kΩ RLCD,COM LCD driver output impedance, common LCDCPEN = 0, ILOAD = ±10 µA lines 2.2 V 10 kΩ 54 40 Submit Document Feedback 60 80 mV µA 500 50 ms µA Copyright © 2020 Texas Instruments Incorporated Product Folder Links: MSP430FR6007 MSP430FR6005 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3A – MARCH 2020 – REVISED DECEMBER 2020 8.13.10 ADC12_B 8.13.10.1 12-Bit ADC, Power Supply and Input Range Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER I(ADC12_B) single-ended mode I(ADC12_B) differential mode I(ADC12_B) single-ended low-power mode I(ADC12_B) differential lowpower mode CI RI (1) (2) (3) TEST CONDITIONS Analog input voltage range(1) V(Ax) VCC All ADC12 analog input pins Ax Operating supply current into AVCC and DVCC terminals(2) (3) Operating supply current into AVCC and DVCC terminals(2) (3) Operating supply current into AVCC and DVCC terminals(2) (3) MIN NOM 0 MAX UNIT AVCC V fADC12CLK = MODCLK, ADC12ON = 1, ADC12PWRMD = 0, ADC12DIF = 0, REFON = 0, ADC12SHTx = 0, ADC12DIV = 0 3.0 V fADC12CLK = MODCLK, ADC12ON = 1, ADC12PWRMD = 0, ADC12DIF = 0, REFON = 0, ADC12SHTx = 0, ADC12DIV = 0 2.2 V 140 190 3.0 V 175 245 2.2 V 170 230 fADC12CLK = MODCLK/4, ADC12ON = 1, ADC12PWRMD = 1, ADC12DIF = 0, REFON = 0, ADC12SHTx = 0, ADC12DIV = 0 3.0 V 85 125 fADC12CLK = MODCLK/4, ADC12ON = 1, ADC12PWRMD = 1, ADC12DIF = 0, REFON = 0, ADC12SHTx = 0, ADC12DIV = 0 2.2 V 83 120 3.0 V 110 165 2.2 V 109 160 fADC12CLK = MODCLK, ADC12ON = 1, ADC12PWRMD = 0, ADC12DIF = 1, REFON = 0, ADC12SHTx= 0, ADC12DIV = 0 145 199 µA µA Operating supply current into AVCC and DVCC terminals(2) (3) fADC12CLK = MODCLK/4, ADC12ON = 1, ADC12PWRMD = 1, ADC12DIF = 1, REFON = 0, ADC12SHTx= 0, ADC12DIV = 0 Input capacitance Only one terminal Ax can be selected at one time 2.2 V 10 15 >2 V 0.5 4