MSP430FR6043, MSP430FR60431, MSP430FR6041
MSP430FR5043, MSP430FR50431, MSP430FR5041
SLASEF5B – JANUARY 2019 – REVISED DECEMBER 2021
MSP430FR604x, MSP430FR504x 16-MHz MCU up to 64KB FRAM, 12-Bit High-Speed
8-MSPS Sigma-Delta ADC, and Integrated Sensor AFE
1 Features
•
•
•
•
Best-in-class ultrasonic water and gas flow
measurement with ultra-low power consumption
– Water
• ±12.5-ps differential time of flight (dToF)
accuracy at low to high flow rates and
across operating temperature
• Achieves ±1% accuracy for a wide dynamic
range of 500:1
• Ability to measure a maximum flow rate
of 8800 liters/hour (40 gallons/minute) on
25‑mm diameter pipe
• Ability to detect a minimum flow rate of
VR–
0
1.2
V
VR+ – VR– Differential external reference voltage input VR+ > VR–
1.2
VR+
Positive external reference voltage
input VeREF+ or VeREF- based on
ADC12VRSEL bit
VR+ > VR–
VR–
Negative external reference voltage
input VeREF+ or VeREF- based on
ADC12VRSEL bit
IVeREF+,
IVeREF-
IVeREF+,
IVeREF-
Static input current singled-ended input
mode
Static input current differential input mode
MIN
TYP
AVCC
V
1.2 V ≤ VeREF+≤ VAVCC, VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 0, ADC12PWRMD = 0
±10
µA
1.2 V ≤ VeREF+≤ VAVCC , VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 0, ADC12PWRMD = 01
±2.5
µA
1.2 V ≤ VeREF+≤ VAVCC, VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
ADC12DIF = 1, ADC12PWRMD = 0
±20
µA
1.2 V ≤ VeREF+≤ VAVCC , VeREF- = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h,
ADC12DIF = 1, ADC12PWRMD = 1
±5
µA
IVeREF+
Peak input current with single-ended input
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 0
1.5
mA
IVeREF+
Peak input current with differential input
0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 1
3
mA
CVeREF+/-
Capacitance at VeREF+ or VeREFterminal
See (2)
(1)
(2)
10
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance (CI) is
also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
Connect two decoupling capacitors, 10 µF and 470 nF, to VeREF to decouple the dynamic current required for an external reference
source if it is used for the ADC12_B. Also see the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.
8.13.10.8 Temperature Sensor Typical Characteristics
Typical Temperature Sensor Voltage (mV)
950
900
850
800
750
700
650
600
550
500
–40
–20
0
20
40
60
80
Ambient Temperature (°C)
Figure 8-17. Typical Temperature Sensor Voltage
62
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8.13.11 Reference
8.13.11.1 REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Positive built-in reference
voltage output
VREF+
TEST CONDITIONS
TYP
MAX
2.5 ±1.5%
REFVSEL = {1} for 2.0 V, REFON = 1
2.2 V
2.0 ±1.5%
REFVSEL = {0} for 1.2 V, REFON = 1
1.8 V
1.2 ±1.8%
RMS noise at VREF (3)
From 0.1 Hz to 10 Hz, REFVSEL = {0}
VOS_BUF_INT
VREF ADC BUF_INT buffer
offset(5)
TA = 25°C, ADC on, REFVSEL = {0},
REFON = 1, REFOUT = 0
VOS_BUF_EXT
VREF ADC BUF_EXT buffer TA = 25°C, REFVSEL = {0} , REFOUT = 1,
offset(4)
REFON = 1 or ADC on
AVCC(min)
AVCC minimum voltage,
Positive built-in reference
active
IREF+
Operating supply current
into AVCC terminal(1)
IREF+_ADC_BUF
MIN
2.7 V
Noise
Operating supply current
into AVCC terminal(1)
VCC
REFVSEL = {2} for 2.5 V, REFON = 1
30
UNIT
V
130
µV
–16
+16
mV
–16
+16
mV
REFVSEL = {0} for 1.2 V
1.8
REFVSEL = {1} for 2.0 V
2.2
REFVSEL = {2} for 2.5 V
2.7
V
REFON = 1
3V
19
26
ADC ON, REFOUT = 0,
REFVSEL = {0, 1, or 2},
ADC12PWRMD = 0
3V
247
400
ADC ON, REFOUT = 1,
REFVSEL = {0, 1, 2}, ADC12PWRMD = 0
3V
1053
1820
ADC ON, REFOUT = 0,
REFVSEL = {0, 1, 2}, ADC12PWRMD = 1
3V
153
240
ADC ON, REFOUT = 1,
REFVSEL = {0, 1, 2}, ADC12PWRMD = 1
3V
581
1030
ADC OFF, REFON = 1, REFOUT = 1,
REFVSEL = {0, 1, 2}
3V
1105
1890
µA
µA
IO(VREF+)
VREF maximum load
current, VREF+ terminal
REFVSEL = {0, 1, 2}, AVCC = AVCC(min) for
each reference level,
REFON = REFOUT = 1
ΔVout/ ΔIo(VREF+)
Load-current regulation,
VREF+ terminal
REFVSEL = {0, 1, 2},
IO(VREF+) = +10 µA or –1000 µA,
AVCC = AVCC(min) for each reference level,
REFON = REFOUT = 1
CVREF+/-
Capacitance at VREF+ and
VREF- terminals
REFON = REFOUT = 1
TCREF+
Temperature coefficient of
built-in reference
REFVSEL = {0, 1, 2},
REFON = REFOUT = 1,
TA = –40°C to 85°C(6)
PSRR_DC
Power supply rejection ratio
(DC)
AVCC = AVCC (min) to AVCC(max),
TA = 25°C, REFVSEL = {0, 1, 2},
REFON = REFOUT = 1
100
PSRR_AC
Power supply rejection ratio
(AC)
dAVCC= 0.1 V at 1 kHz
3.0
tSETTLE
Settling time of reference
voltage(2)
AVCC = AVCC (min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 0 → 1
40
80
µs
Tbuf_settle
Settling time of ADC
reference voltage buffer(2)
AVCC = AVCC (min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 1
0.4
2
µs
(1)
(2)
(3)
(4)
–1000
+10
µA
1500 µV/mA
0
100
24
pF
50 ppm/K
400
µV/V
mV/V
The internal reference current is supplied through the AVCC terminal.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
Internal reference noise affects ADC performance when ADC uses the internal reference. See Designing With the MSP430FR59xx
and MSP430FR58xx ADC for details on optimizing ADC performance for your application with the choice of internal or external
reference.
Buffer offset affects ADC gain error and thus total unadjusted error.
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(5)
(6)
Buffer offset affects ADC gain error and thus total unadjusted error.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
8.13.12 Comparator
8.13.12.1 Comparator_E
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
12
16
10
14
0.1
0.3
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TA = 85°C
0.3
1.3
CEREFLx = 01, CERSx = 10,
REFON = 0, CEON = 1,
CEREFACC = 0
31
38
CEPWRMD = 00, CEON = 1,
CERSx = 00 (fast)
Comparator operating
supply current into AVCC,
excludes reference resistor
ladder
IAVCC_COMP
IAVCC_COMP_REF
VREF
Quiescent current of
resistor ladder into AVCC,
including REF module
current
Reference voltage level
VIC
Common-mode input range
VOFFSET
Input offset voltage
CIN
RSIN
tPD
64
Input capacitance
Series input resistance
Propagation delay,
response time
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CEPWRMD = 01, CEON = 1,
CERSx = 00 (medium)
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TA = 30°C
CEREFLx = 01, CERSx = 10,
REFON = 0, CEON = 1,
CEREFACC = 1
2.2 V, 3.0 V
µA
2.2 V, 3.0 V
µA
16
19
CERSx = 11, CEREFLx = 01,
CEREFACC = 0
1.8 V
1.152
1.2
1.248
CERSx = 11, CEREFLx = 10,
CEREFACC = 0
2.2 V
1.92
2.0
2.08
CERSx = 11, CEREFLx = 11,
CEREFACC = 0
2.7 V
2.40
2.5
2.60
CERSx = 11, CEREFLx = 01,
CEREFACC = 1
1.8 V
1.10
1.2
1.245
CERSx = 11, CEREFLx = 10,
CEREFACC = 1
2.2 V
1.90
2.0
2.08
CERSx = 11, CEREFLx = 11,
CEREFACC = 1
2.7 V
2.35
2.5
2.60
V
0
VCC – 1
CEPWRMD = 00
–16
16
CEPWRMD = 01
–12
12
CEPWRMD = 10
–37
37
CEPWRMD = 00 or
CEPWRMD = 01
10
CEPWRMD = 10
10
ON (switch closed)
OFF (switch open)
UNIT
1
V
mV
pF
3
50
kΩ
MΩ
CEPWRMD = 00, CEF = 0,
Overdrive ≥ 20 mV
193
330
CEPWRMD = 01, CEF = 0,
Overdrive ≥ 20 mV
230
400
CEPWRMD = 10, CEF = 0,
Overdrive ≥ 20 mV
5
15
ns
µs
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SLASEF5B – JANUARY 2019 – REVISED DECEMBER 2021
8.13.12.1 Comparator_E (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Propagation delay with
filter active
tPD,filter
tEN_CMP
Comparator enable time
TYP
MAX
UNIT
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 00
VCC
MIN
700
1000
ns
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 01
1.0
1.9
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 10
2.0
3.7
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 11
4.0
7.7
CEON = 0 → 1, VIN+,
VIN- from pins,
Overdrive ≥ 20 mV,
CEPWRMD = 00
0.9
1.5
CEON = 0 → 1, VIN+,
VIN- from pins,
Overdrive ≥ 20 mV,
CEPWRMD = 01
0.9
1.5
CEON = 0 → 1,
VIN+, VIN- from pins,
Overdrive ≥ 20 mV,
CEPWRMD = 10
15
65
220
Comparator and reference
ladder and reference
voltage enable time
CEON = 0 → 1, CEREFLX = 10,
CERSx = 10 or 11,
CEREF0 = CEREF1 = 0x0F,
REFON = 0
120
tEN_CMP_RL
Comparator and reference
ladder enable time
CEON = 0 → 1, CEREFLX = 10,
CERSx = 10, REFON = 1,
CEREF0 = CEREF1 = 0x0F
10
VCE_REF
Reference voltage for a
given tap
VIN = reference into resistor ladder,
n = 0 to 31
tEN_CMP_VREF
µs
µs
µs
30
VIN ×
VIN ×
VIN ×
(n + 0.5) (n + 1) / (n + 1.5) /
/ 32
32
32
V
8.13.13 FRAM
8.13.13.1 FRAM Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
tRetention
Data retention duration
IWRITE
Current to write into FRAM(1)
Erase
tWRITE
Write time(4)
tREAD
Read time(5)
(1)
(2)
(3)
(4)
(5)
TYP
25°C
100
70°C
40
85°C
10
MAX
UNIT
cycles
years
IREAD
nA
N/A(3)
nA
tREAD
ns
NWAITSx = 0
1 / fSYSTEM
ns
NWAITSx = 1
2 / fSYSTEM
ns
current(2)
IERASE
MIN
1015
Read and write endurance
Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption, IAM,FRAM.
FRAM does not require a special erase sequence.
N/A = Not applicable
Writing into FRAM is as fast as reading.
The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
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8.13.14 USS
8.13.14.1 USS Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PVCC
Analog supply voltage at PVCC pins for LDO operation
2.2
3.6
V
PVCC
Analog supply voltage at PVCC pins for USS operation
2.2
3.6
V
8.13.14.2 USS LDO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC_ldo
Analog supply voltage at PVCC pins
Vuss
USS voltage
Tholdoff
Ttimeout
TYP
MAX
2.2
0 ≤ ILOAD ≤ ILOAD,MAX
Hold off delay on power up
MIN
1.52
1.6
LBHDEL = 0
0
LBHDEL = 1
100
LBHDEL = 2
200
LBHDEL = 3
300
Time-out on transition OFF to READY
UNIT
3.6
V
1.65
V
µs
160 +
Tholdoff
µs
8.13.14.3 USSXTAL
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Nphase_osc
Integrated phase noise
FRQXTAL
Resonator frequency
DCosc
Duty cycle
Iosc
OSC supply current
Aosc
Oscillation allowance
Tstart_osc
66
Startup time (gate)
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TEST CONDITIONS
MIN
MAX
UNIT
4
8
MHz
35
65
%
fosc = 4 MHz or 8 MHz, range = 10 kHz to 4 MHz
TYP
–74
fosc = 4 MHz or 8 MHz, CL = 18 pF, CS = 4 pF, fully
settled, ceramic resonator
180
fosc = 4 MHz or 8 MHz, CL = 12 pF (4 MHz) or
16 pF(8 MHz), CS = 7 pF, fully settled, crystal
resonator
240
fosc = 4 MHz, CL = 18 pF, CS = 4 pF, ceramic
resonator
1500
fosc = 4 MHz, CL = 12 pF, CS = 7 pF, crystal
resonator
1000
dBc
µA
Ω
fosc = 8 MHz, CL = 18 pF, CS = 4 pF, ceramic
resonator
500
fosc = 8 MHz, CL = 16 pF, CS = 7 pF, crystal
resonator
350
fosc = 4 MHz, crystal resonator
2.8
4.6
fosc = 8 MHz, crystal resonator
1
1.9
fosc = 4 MHz, ceramic resonator
0.14
0.17
fosc = 8 MHz, ceramic resonator
0.08
0.12
ms
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SLASEF5B – JANUARY 2019 – REVISED DECEMBER 2021
8.13.14.4 USS HSPLL
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
PLL_CLKin
Input clock to HSPLL
PLL_CLKout
Output clock from HSPLL
LOCKpwr
TEST CONDITIONS
Lock time from PLL power up
MIN
MAX
UNIT
4
TYP
8
MHz
68
80
MHz
64
cycles
Reference clock = PLL_CLKin,
Sequence: Set USS.CTL.USSPWRUP bit = 1,
then measure the time between PSQ_PLLUP
(internal control signal) is set to 1 and
HSPLL.CTL.PLL_LOCK is set to 1
8.13.14.5 USS SDHS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Vsdhs
SDHS power domain
supply voltage
Vsdhs = Vuss
Isdhs_product
Operating supply current
into AVCC and DVCC
Includes PLL, PGA, SDHS, and DTC,
modulator clock = 80 MHz, output data rate = 8 Msps
Fm
Modulator clock(1)
BWmod
Frequency at -3dB SNR
Signal-to-noise ratio(2)
SNR
SDHS settling time (PGA
+ Modulator)
DROUTsdhs
Output data rate
(1)
(2)
TYP
MAX
UNIT
1.52
1.6
1.65
V
5.2
68
Modulator clock = 80 MHz, modulator only (no filter is
enabled)
mA
80
1.5
Bandwidth from 200 kHz
to 1.5 MHz, PGA gain: a Input signal level = 1000 mVpp,
gain from the PGA gain PVCC = 3.0 V, Fm = 80 MHz,
table for the maximum
OSR = 20
SNR
58.5
62.5
Bandwidth from 200 kHz
to 1.5 MHz, PGA gain: a Input signal level = 760 mVpp,
gain from the PGA gain PVCC = 2.5 V, Fm = 80 MHz,
table for the maximum
OSR = 20
SNR
57.5
62
Bandwidth from 200 kHz
to 1.5 MHz, PGA gain: a Input signal level = 200 mVpp,
gain from the PGA gain PVCC = 2.5 V, Fm = 80 MHz,
table for the maximum
OSR = 20
SNR
54.5
57
Bandwidth from 200 kHz
to 1.5 MHz, PGA gain: a Input signal level = 100 mVpp,
gain from the PGA gain PVCC = 2.5 V, Fm = 80 MHz,
table for the maximum
OSR = 20
SNR
49
53
38.5
43
Bandwidth from 200 kHz
to 1.5 MHz, PGA gain: a Input signal level = 30 mVpp,
gain from the PGA gain PVCC = 2.5 V, Fm = 80 MHz,
table for the maximum
OSR = 20
SNR
TMOD_Settle
MIN
MHz
MHz
dB
TM2 - TM1, AUTOSSDIS = 0, 1% of settled DC level
40
TM2 - TM1, AUTOSSDIS = 1, 1% of settled DC level
40
8
µs
Msps
Informative parameter, not characterized
SNR as specified, SINAD and THD not specified over complete signal chain
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8.13.14.6 USS PHY Output Stage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
PVCC = VCC, PVSS = VSS
MIN
TYP
MAX
2.2
3.6
UNIT
PVCC
PHY supply voltage
V
RDSonT
Output impedance of CH0OUT and CH1OUT for
PVCC ≥ 2.5 V
high and low side (trimmed at 3-V PVDD)
3
Ω
RTerm
Termination impedance of CH0OUT and
CH1OUT towards PVSS (trimmed)
PVCC ≥ 2.5 V
3
Ω
DrvM
High side to low side drive mismatch (trimmed)
PVCC ≥ 2.5 V
5%
12.5%
TermM
Termination to drive mismatch (trimmed)
PVCC ≥ 2.5 V
5%
12.5%
fMAX
Maximum output frequency
PVCC = VCC (2.5 V to 3.6 V)
4.5
CSUPP
Supply buffering capacitance (low ESR type)
PVCC = VCC
22
RSUPP
Series resistance to CSUPP
PVCC = VCC
MHz
100
µF
22
Ω
8.13.14.7 USS PHY Input Stage, Multiplexer
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VIN
TEST CONDITIONS
Input voltage on CH0IN or CH1IN
PVCC = VCC, PVSS = VSS
MIN
TYP
MAX
PVSS –
0.3
1.8
UNIT
V
8.13.14.8 USS_PGA
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PVcc
Supply voltage
GN
Gain(1)
Vinr1
Input range
2.2 V ≤ PVCC
Vinr2
Input range
2.5 V ≤ PVCC
Gtol
Gain tolerance
Full PGA gain range, VOUT = 600 mV
GTdrift
Gain drift over
temperature
Full PGA gain range, VOUT = 600 mV
0.0019
GVdrift
Gain drift over voltage
Full PGA gain range, VOUT = 600 mV
0.15
TSET
Gain settling time
Gain setting: from 0 dB to 6 dB, to ±5%
0.65
DCoffset
DC offset (PGA and
SDHS)
Full PGA gain range, measured at SDHS output
5.5
mV
DCdrift
DC offset drift (PGA and
Full PGA gain range, measured at SDHS output
SDHS)
4.7
µV/℃
AC power supply
PSRR_AC
rejection ratio
(1)
68
VCC = 3 V + 50 mVpp × sin (2π ×
fC) where fC = 1 MHz, VIN = ground,
PSRR_AC = 20log(VOUT / 50 mV)
2.2
3.6
–6.5
30.8
dB
30
800
mVpp
30
1000
mVpp
–1.5
1.5
PGA gain = 0 dB
-41
PGA gain = 10 dB
-37
PGA gain = 30 dB
-19
V
dB
dB/℃
dB/V
1.4
µs
dB
See PGA Gain Table in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide.
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8.13.14.9 USS Bias Voltage Generator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Vexc_bias
RVBE
TSBE
Vpga_bias
RVBA
Excitation bias voltage
(coupling capacitors)
Impedance of excitation bias
generator
Excitation bias settling time
PGA bias voltage (coupling
caps)
Impedance of acquisition bias
generator
TEST CONDITIONS
TYP
200
PVCC = VCC (2.2 V to 3.6 V), EXCBIAS = 1
300
PVCC = VCC (2.2 V to 3.6 V), EXCBIAS = 2
400
PVCC = VCC (2.2 V to 3.6 V), EXCBIAS = 3
600
PVCC = VCC (2.2 V to 3.6 V), BIMP = 0
450
PVCC = VCC (2.2 V to 3.6 V), BIMP = 1
850
PVCC = VCC (2.2 V to 3.6 V), BIMP = 2
1450
PVCC = VCC (2.2 V to 3.6 V), BIMP = 3
2900
PVCC = VCC (2.2 V to 3.6 V) to 0.1% end value
RET = 200 Ω, CK + C0P = 1 nF, BIMP = 2
750
PVCC = VCC (2.2 V to 3.6 V), PGABIAS = 1
800
PVCC = VCC (2.2 V to 3.6 V), PGABIAS = 2
900
PVCC = VCC (2.2 V to 3.6 V), PGABIAS = 3
950
PVCC = VCC (2.2 V to 3.6 V), BIMP = 0
500
PVCC = VCC (2.2 V to 3.6 V), BIMP = 1
900
PVCC = VCC (2.2 V to 3.6 V), BIMP = 2
1500
PVCC = VCC (2.2 V to 3.6 V), BIMP = 3
2950
TSBA
Acquisition bias settling time
RVBX
Impedance of bias switches
on XPB0/1 terminals on top of
RVBA
PVCC = VCC (2.2 V to 3.6 V), PGABIAS = 0;1;2;3 ,
BIMP = 0;1;2;3
MAX
20
PVCC = VCC (2.2 V to 3.6 V), PGABIAS = 0
PVCC = VCC (2.2 V to 3.6 V)to 0.1% end value
RET = 200 Ω, CK + C0P = 1 nF, BIMP = 2
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MIN
PVCC = VCC (2.2 V to 3.6 V), EXCBIAS = 0
UNIT
mV
Ω
µs
mV
Ω
22
µs
1000
Ω
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8.13.15 Emulation and Debug
8.13.15.1 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
40
100
μA
0
10
MHz
0.04
15
μs
110
μs
15
100
μs
2.2 V
0
16
3.0 V
0
16
2.2 V, 3.0 V
20
IJTAG
Supply current adder when JTAG active (but not clocked)
2.2 V, 3.0 V
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3.0 V
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3.0 V
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge)(1)
2.2 V, 3.0 V
tSBW,Rst
Spy-Bi-Wire return to normal operation time
fTCK
TCK input frequency, 4-wire JTAG(2)
Rinternal
Internal pulldown resistance on TEST
fTCLK
TCLK/MCLK frequency during JTAG access, no FRAM access
(limited by fSYSTEM)
tTCLK,Low/High
fTCLK,FRAM
35
TCLK low or high clock pulse duration, no FRAM access
TCLK/MCLK frequency during JTAG access, including FRAM access
(limited by fSYSTEM with no FRAM wait states)
tTCLK,FRAM, Low/ TCLK low or high clock pulse duration, including FRAM accesses
(1)
(2)
70
50
kΩ
16
MHz
25
ns
4
MHz
100
High
MHz
ns
Tools that access the Spy-Bi-Wire and the BSL interfaces must wait for the tSBW,En time after the first transition of the TEST/SBWTCK
pin (low to high), before the second transition of the pin (high to low) during the entry sequence.
fTCK may be restricted to meet the timing requirements of the module selected.
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9 Detailed Description
9.1 Overview
The MSP430FR604x and MSP430FR504x ultra-low-power microcontrollers feature different sets of peripherals.
The architecture, combined with seven low-power modes, is optimized to achieve extended battery life for
example in portable measurement applications. The devices features a powerful 16-bit RISC CPU, 16-bit
registers, and constant generators that contribute to maximum code efficiency.
The MSP430FR604x and MSP430FR504x MCUs feature an ultrasonic sensing solution (USS) module, a
low-energy accelerator (LEA), up to six 16-bit timers, up to six eUSCIs that support UART, SPI, and I2C,
a comparator, a hardware multiplier, an AES accelerator, a 6-channel DMA, an RTC module with alarm
capabilities, up to 57 I/O pins, and a high-performance 12-bit ADC. The MSP430FR604x MCUs also include
an LCD controller module with contrast control for displays with up to 248 segments.
9.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations
other than program-flow instructions are performed as register operations in conjunction with seven addressing
modes for the source operand and four addressing modes for the destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant
generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be managed with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
9.3 Ultrasonic Sensing Solution (USS_A)
The USS_A module provides a high-precision ultrasonic-sensing solution. The USS_A module is a sophisticated
system that consists of six submodules:
•
•
•
•
•
•
•
UUPS (universal USS power supply)
HSPLL (high-speed PLL) with oscillator
ASQ (acquisition sequencer)
PHY (physical interface)
PPG_A (programmable pulse generator "A") with low output impedance driver
PGA (programmable gain amplifier)
SDHS (sigma-delta high-speed ADC) with DTC (data transfer controller)
The submodules have different roles, and together the enable high-precision data acquisition in ultrasonic
applications. See the dedicated chapter for each submodule in the MSP430FR58xx, MSP430FR59xx, and
MSP430FR6xx Family User's Guide.
The USS module performs complete measurement sequence without CPU involvement to achieve ultra-low
power consumption for ultrasonic metrology. Section 7.1 shows the USS subsystem block diagram. The USS
module has dedicated I/O pins without secondary functions. See the Ultrasonic Sensing Solution (USS) chapter
in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.
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USS_A Module
SAPH_A
CH0_OUT
CH1_OUT
USSXT
USSXTIN USSXTOUT
PHY
PPG_A
USSXT_BOUT
OSC
ASQ
PLL_CLK
PVSS
PLL
PVCC
UUPS
VOUT
HSPLL
PVSS
SDHS
CH1_IN
CH0_IN
PGA
RAM
(shared with LEA)
MOD Filter
DTC
Optional external
signal handling
Bias
Generator
GPIOs
(software
control)
MSP430FRxxxx
Figure 9-1. USS_A Subsystem Block Diagram
9.4 Low-Energy Accelerator (LEA) for Signal Processing
The LEA is a hardware engine designed for operations that involve vector-based signal processing, such as
FIR, IIR, and FFT. The LEA offers fast performance and low energy consumption when performing vector-based
digital signal processing computations. For performance benchmarks comparing LEA to using the CPU or other
processors, see Benchmarking the Signal-Processing Capabilities of the Low-Energy Accelerator.
The LEA requires MCLK to be operational; therefore, LEA runs only in active mode or LPM0. While the LEA is
running, the LEA data operations are performed on a shared 8KB of RAM out of the 12KB of total RAM (see
Table 9-52). This shared RAM can also be used by the regular application. The MSP CPU and the LEA can run
simultaneously and independently unless they access the same system RAM.
Direct access to LEA registers is not supported, and TI recommends using the optimized Digital Signal
Processing (DSP) Library for MSP Microcontrollers for the operations that the LEA module supports.
72
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9.5 Operating Modes
The MCU has one active mode and seven software selectable low-power modes of operation. An interrupt event can wake up the device from low-power
modes LPM0 through LPM4, service the request, and restore back to the low-power mode on return from the interrupt program. Low-power modes
LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.
Note
XT1CLK and VLOCLK can be active during LPM4 if requested by low-frequency peripherals such as RTC or WDT.
Table 9-1. Operating Modes
AM
MODE
Typical current consumption,
TA = 25°C
ACTIVE,
FRAM OFF(1)
ACTIVE
Maximum system clock
LPM0
16 MHz
103 µA/MHz
Typical wake-up time
65 µA/MHz
N/A
LPM1
LPM2
LPM3
LPM4
LPM3.5
LPM4.5
SHUTDOWN
WITH SVS
SHUTDOWN
WITHOUT SVS
CPU OFF(2)
CPU OFF
STANDBY
STANDBY
OFF
RTC ONLY
16 MHz
16 MHz
50 kHz
50 kHz
0(3)
50 kHz
70 µA at 1 MHz
35 µA at 1 MHz
0.7 µA
0.4 µA
0.3 µA
0.25 µA
0.2 µA
0.02 µA
instant
6 µs
6 µs
7 µs
7 µs
250 µs
250 µs
1000 µs
LF, RTC, I/O,
Comp
I/O, Comp
RTC, I/O
I/O
0(3)
Wake-up events
N/A
all
all
LF, RTC, I/O,
Comp
CPU
on
off
off
off
off
off
reset
reset
USS_A
on
off
off
off
off
reset
reset
LEA
on
off
off
off
off
reset
reset
standby
(or off(1))
off
off
off
off
off
off
available
available
off
off
off
reset
reset
off
RTC
MTIF
reset
FRAM
Low-frequency peripherals
Unclocked
off(1)
on
High-frequency peripherals
peripherals(5)
MCLK
on
on(10)
available
available
available
on
off
available
available
on(10)
off
available
available (4)
available
available
(4)
reset
reset
off
off
off
off
off
off
off
available
available
available
(4)
optional(6)
optional(6)
optional(6)
off
off
off
off
ACLK
on
on
on
on
on
off
off
off
Full retention
yes
yes
yes
yes
yes
yes
no
no
SVS
always
always
always
optional(7)
optional(7)
optional(7)
optional(7)
Brownout
always
always
always
always
always
always
always
SMCLK
(1)
(2)
(3)
(4)
(5)
(6)
on(8)
off(9)
always
FRAM is disabled in the FRAM controller A (FRCTL_A).
Disabling the FRAM through the FRAM controller A (FRCTL_A) allows the application to lower the LPM current consumption but the wake-up time increases as soon as FRAM is
accessed (for example, to fetch an interrupt vector). For a non-FRAM wake-up (for example, DMA transfer to RAM) the wake-up is not delayed.
All clocks are disabled.
See Section 9.5.2, which describes the use of peripherals in LPM3 and LPM4.
"Unclocked peripherals" are peripherals that do not require a clock source to operate; for example, the comparator and REF, or the eUSCI when operated as an SPI slave.
Controlled by SMCLKOFF.
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(7)
(8)
(9)
(10)
74
Activated SVS (SVSHE = 1) results in higher current consumption. SVS is not included in typical current consumption.
SVSHE = 1
SVSHE = 0
Only while LEA is performing the task enabled by CPU during AM. LEA cannot be enabled in LPM0.
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9.5.1 Peripherals in Low-Power Modes
Peripherals can be in different states that impact the achievable power modes of the device. The states depend
on the operational modes of the peripherals (see Table 9-2). The states are:
•
•
•
A peripheral is in a "high-frequency state" if it requires or uses a clock with a "high" frequency of more than
50 kHz.
A peripheral is in a "low-frequency state" if it requires or uses a clock with a "low" frequency of 50 kHz or less.
A peripheral is in an "unclocked state" if it does not require or use an internal clock.
If the CPU requests a power mode that does not support the current state of all active peripherals, the device
does not enter the requested power mode, but it does enter a power mode that still supports the current state
of the peripherals, except if an external clock is used. If an external clock is used, the application must use the
correct frequency range for the requested power mode.
Table 9-2. Peripheral States
PERIPHERAL
WDT
IN HIGH-FREQUENCY STATE (1)
IN LOW-FREQUENCY STATE (2)
IN UNCLOCKED STATE (3)
Clocked by SMCLK
Clocked by ACLK
Not applicable
DMA(4)
Not applicable
Not applicable
Waiting for a trigger.
RTC_C
Not applicable
Clocked by LFXT.
Not applicable
LCD_C
Not applicable
Clocked by ACLK or VLOCLK.
Not applicable
Timer_A TAx
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Timer_B TBx
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Ax in
UART mode
Clocked by SMCLK
Clocked by ACLK
Waiting for first edge of START bit.
eUSCI_Ax in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Ax in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
eUSCI_Bx in I2C
master mode
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Not applicable
eUSCI_Bx in I2C
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Waiting for START condition or
clocked by external clock ≤50 kHz
eUSCI_Bx in SPI
master mode
Clocked by SMCLK
Clocked by ACLK
Not applicable
eUSCI_Bx in SPI
slave mode
Clocked by external clock >50 kHz
Clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Clocked by SMCLK or by MODOSC
Clocked by ACLK
Waiting for a trigger
REF_A
Not applicable
Not applicable
Always
COMP_E
Not applicable
Not applicable
Always
CRC(5)
Not applicable
Not applicable
Not applicable
MPY(5)
Not applicable
Not applicable
Not applicable
AES(5)
Not applicable
Not applicable
Not applicable
ADC12_B
(1)
(2)
(3)
(4)
(5)
Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz.
Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.
Peripherals are in a state that does not require or does not use an internal clock.
The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power
mode causes a temporary transition into active mode for the time of the transfer.
This peripheral operates during active mode only and will delay the transition into a low-power mode until its operation is completed.
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9.5.2 Idle Currents of Peripherals in LPM3 and LPM4
Most peripherals can be operational in LPM3 if clocked by ACLK. Some modules are operational in LPM4,
because they do not require a clock to operate (for example, the comparator). Activating a peripheral in LPM3
or LPM4 increases the current consumption due to its active supply current contribution but also due to an
additional idle current. To reduce the idle current adder, certain peripherals are grouped together. To achieve
optimal current consumption, use modules within one group and limit the number of groups with active modules.
Table 9-3 lists the groups. Modules not listed in this table are either already included in the standard LPM3
current consumption or cannot be used in LPM3 or LPM4.
The idle current adder is very small at room temperature (25°C) but increases at high temperatures (85°C). See
the IIDLE current parameters in Section 8 for details.
Table 9-3. Peripheral Groups
GROUP A
GROUP B
GROUP C
Timer TA1
Timer TA0
Timer TA4
Timer TA2
Timer TA3
eUSCI_A2
Timer TB0
Comparator
eUSCI_A3
eUSCI_A0
ADC12_B
eUSCI_B1
eUSCI_A1
REF_A
LCD_C
eUSCI_B0
9.6 Interrupt Vector Table and Signatures
The interrupt vectors, the power-up start address and signatures are in the address range 0FFFFh to 0FF80h.
Figure 9-2 summarizes the content of this address range.
Reset Vector
0FFFFh
BSL Password
Interrupt
Vectors
0FFE0h
JTAG Password
Reserved
Signatures
0FF88h
0FF80h
Figure 9-2. Interrupt Vectors, Signatures and Passwords
The power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains the 16-bit address pointing to the
start address of the application program.
The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit address
of the appropriate interrupt-handler instruction sequence. Table 9-4 shows the device specific interrupt vector
locations.
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if enabled
by the corresponding signature).
The signatures are located at 0FF80h and extend to higher addresses. Signatures are evaluated during device
start-up. Table 9-5 shows the device specific signature locations.
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A JTAG password can be programmed starting from address 0FF88h and extending to higher addresses. The
password can extend into the interrupt vector locations using the interrupt vector addresses as additional bits for
the password. The length of the JTAG password depends on the JTAG signature.
Refer to the chapter "System Resets, Interrupts, and Operating Modes, System Control Module (SYS)" in the
MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.
Table 9-4. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
INTERRUPT
VECTOR
REGISTER
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
SYSRSTIV(1)
Reset
0FFFEh
Highest
SYSSNIV(1)
(Non)maskable(3)
0FFFCh
SYSUNIV(1)
(Non)maskable(3)
0FFFAh
CEIV(1)
Maskable
0FFF8h
Maskable
0FFF6h
Maskable
0FFF4h
Maskable
0FFF2h
UCA0IV(1)
Maskable
0FFF0h
UCB0IV(1)
Maskable
0FFEEh
System Reset
Power up, brownout,
supply supervisor
SVSHIFG
External reset, RST
PMMRSTIFG
Watchdog time-out
(watchdog mode)
WDTIFG
WDT, FRCTL MPU, CS,
PMM password violation
WDTPW, FRCTLPW, MPUPW, CSPW,
PMMPW
FRAM uncorrectable bit
error detection
UBDIFG
MPU segment violation
MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
Software POR, BOR
PMMPORIFG, PMMBORIFG
System NMI
Vacant memory access(2)
VMAIFG
JTAG mailbox
JMBINIFG, JMBOUTIFG
FRAM access time error
ACCTEIFG
FRAM write protection
error
WPIFG
FRAM bit error detection
CBDIFG, UBDIFG
MPU segment violation
MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
User NMI
External NMI
NMIIFG
Oscillator fault
OFIFG
LEA RAM access conflict
DACCESSIFG
Comparator_E
CEIFG, CEIIFG
TB0
TB0CCR0 CCIFG
TB0
TB0CCR1 CCIFG to TB0CCR6 CCIFG,
TB0CTL.TBIFG
Watchdog timer (interval
timer mode)
WDTIFG
eUSCI_A0 receive or
transmit
TB0IV(1)
UCRXIFG, UCTXIFG (SPI mode)
UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
eUSCI_B0 receive or
transmit
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I2C mode)
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Table 9-4. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
INTERRUPT FLAG
INTERRUPT
VECTOR
REGISTER
SYSTEM
INTERRUPT
WORD
ADDRESS
ADC12_B(4)
ADC12IFG0 to ADC12IFG31,
ADC12LOIFG, ADC12INIFG,
ADC12HIIFG, ADC12RDYIFG,
ADC21OVIFG, ADC12TOVIFG
ADC12IV(1)
Maskable
0FFECh
Maskable
0FFEAh
TA0IV(1)
Maskable
0FFE8h
UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCA1IV(1)
Maskable
0FFE6h
DMA
DMA0CTL.DMAIFG, DMA1CTL.DMAIFG,
DMA2CTL.DMAIFG
DMAIV(1)
Maskable
0FFE4h
TA1
TA1CCR0 CCIFG
Maskable
0FFE2h
TA1
TA1CCR1 CCIFG, TA1CCR2 CCIFG,
TA1CTL.TAIFG
TA1IV(1)
Maskable
0FFE0h
I/O port P1
P1IFG.0 to P1IFG.7
P1IV(1)
Maskable
0FFDEh
TA2
TA2CCR0 CCIFG
Maskable
0FFDCh
TA2
TA2CCR1 CCIFG, TA2CTL.TAIFG
TA2IV(1)
Maskable
0FFDAh
I/O port P2
P2IFG.0 to P2IFG.7
P2IV(1)
Maskable
0FFD8h
TA0
TA0CCR0 CCIFG
TA0
TA0CCR1 CCIFG, TA0CCR2 CCIFG,
TA0CTL.TAIFG
eUSCI_A1 receive or
transmit
UCRXIFG, UCTXIFG (SPI mode)
TA3
TA3CCR0 CCIFG
Maskable
0FFD6h
TA3
TA3CCR1 CCIFG, TA3CTL.TAIFG
TA3IV(1)
Maskable
0FFD4h
I/O port P3
P3IFG.0 to P3IFG.7
P3IV(1)
Maskable
0FFD2h
I/O port P4
P4IFG.0 to P4IFG.7
P4IV(1)
Maskable
0FFD0h
LCD_C
LCDNOCAPIFG, LCDBLKOFFIFG,
LCDBLKONIFG, LCDFRMIFG
LCDCIV(1)
Maskable
0FFCEh
RTC_C
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG
RTCIV(1)
Maskable
0FFCCh
AES
AESRDYIFG
Maskable
0FFCAh
TA4
TA4CCR0 CCIFG
Maskable
0FFC8h
TA4
TA4CCR1 CCIFG, TA4CTL.TAIFG
TA4IV(1)
Maskable
0FFC6h
I/O port P5
P5IFG.0 to P5IFG.7
P5IV(1)
Maskable
0FFC4h
I/O port P6
P6IFG.0 to P6IFG.7
P6IV(1)
Maskable
0FFC2h
UCA2IV(1)
Maskable
0FFC0h
UCA3IV(1)
Maskable
0FFBEh
UCB1IV(1)
Maskable
0FFBCh
eUSCI_A2 receive or
transmit
eUSCI_A3 receive or
transmit
PRIORITY
UCRXIFG, UCTXIFG (SPI mode)
UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
UCSTTIFG, UCTXCPTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
eUSCI_B1 receive or
transmit
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I2C mode)
I/O port P7
P7IFG.0 to P7IFG.7
P7IV(1)
Maskable
0FFBAh
LEA
CMDIFG, SDIIFG, OORIFG, TIFG,
COVLIFG
LEAIV(1)
Maskable
0FFB8h
UUPS
PTMOUT, PREQIG
IIDX(1)
Maskable
0FFB6h
PLLUNLOCK
IIDX(1)
Maskable
0FFB4h
HSPLL
78
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Table 9-4. Interrupt Sources, Flags, and Vectors (continued)
(1)
(2)
(3)
(4)
INTERRUPT SOURCE
INTERRUPT FLAG
INTERRUPT
VECTOR
REGISTER
SYSTEM
INTERRUPT
WORD
ADDRESS
SAPH_A
DATAERR, TAMTO, SEQDN, PNGDN
IIDX(1)
Maskable
0FFB2h
SDHS
OVF, ACQDONE, SSTRG, DTRDY,
WINHI, WINLO
IIDX(1)
Maskable
0FFB0h
PRIORITY
Lowest
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
Only on devices with ADC, otherwise reserved.
Table 9-5. Signatures
SIGNATURE
WORD ADDRESS
IP Encapsulation Signature2
0FF8Ah
IP Encapsulation
(1)
Signature1(1)
0FF88h
BSL Signature2
0FF86h
BSL Signature1
0FF84h
JTAG Signature2
0FF82h
JTAG Signature1
0FF80h
Must not contain 0AAAAh if used as the JTAG password.
9.7 Bootloader (BSL)
The BSL can program the FRAM or RAM using a UART serial interface (FRxxxx devices) or an I2C interface
(FRxxxx1 devices). Access to the device memory through the BSL is protected by an user-defined password.
Table 9-6 lists the pins that are required for use of the BSL. BSL entry requires a specific entry sequence on
the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the features of the BSL and
its implementation, see the MSP430™ FRAM Devices Bootloader (BSL) User's Guide. More information on the
BSL can be found at www.ti.com/tool/mspbsl.
Table 9-6. BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P2.0
Devices with UART BSL (FRxxxx): Data transmit
P2.1
Devices with UART BSL (FRxxxx): Data receive
P1.6
Devices with I2C BSL (FRxxxx1): Data
P1.7
Devices with I2C BSL (FRxxxx1): Clock
DVCC, AVCC
Power supply
DVSS, AVSS
Ground supply
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9.8 JTAG Operation
9.8.1 JTAG Standard Interface
The MSP family supports the standard JTAG interface, which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable
the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP
development tools and device programmers. Table 9-7 lists the JTAG pin requirements. For further details on
interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For
a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming
With the JTAG Interface.
Table 9-7. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
DVCC, AVCC
–
Power supply
DVSS, AVSS
–
Ground supply
9.8.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP family supports the two wire Spy-Bi-Wire interface. Spy-BiWire can be used to interface with MSP development tools and device programmers. The Spy-Bi-Wire interface
pin requirements are shown in Table 9-8. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the
JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface.
Table 9-8. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
80
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
DVCC, AVCC
–
Power supply
DVSS, AVSS
–
Ground supply
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9.9 FRAM Controller A (FRCTL_A)
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU.
Features of the FRAM include:
•
•
•
•
Ultra-low-power ultra-fast-write nonvolatile memory
Byte and word access capability
Programmable wait state generation
Error correction coding (ECC)
Note
Wait States
For MCLK frequencies >8 MHz, wait states must be configured as described in the Wait State Control
section of the FRAM Controller A (FRCTRL_A) chapter in the MSP430FR58xx, MSP430FR59xx, and
MSP430FR6xx Family User's Guide.
For important software design information regarding FRAM including but not limited to partitioning the memory
layout according to application-specific code, constant, and data space requirements, the use of FRAM to
optimize application energy consumption, and the use of the memory protection unit (MPU) to maximize
application robustness by protecting the program code against unintended write accesses, see MSP430™
FRAM Technology – How to and Best Practices.
9.10 RAM
The RAM is made up of three sectors. Sector 0 = 2KB, Sector 1 = 2KB, Sector 2 = 8KB (shared with LEA).
Each sector can be individually powered down in LPM3 and LPM4 to save leakage. Data is lost when sectors
are powered down in LPM3 and LPM4.
9.11 Tiny RAM
22 bytes of Tiny RAM are provided in addition to the complete RAM (see Table 9-52). This memory is always
available, even in LPM3 and LPM4, while the complete RAM can be powered down in LPM3 and LPM4. Tiny
RAM can be used to hold data or a very small stack when the complete RAM is powered down in LPM3 and
LPM4. No memory is available in LPMx.5.
9.12 Memory Protection Unit (MPU) Including IP Encapsulation
The FRAM can be protected by the MPU from inadvertent CPU execution, read access, or write access.
Features of the MPU include:
•
•
•
•
IP encapsulation with programmable boundaries in steps of 1KB (prevents reads from "outside"; for example,
through JTAG or by non-IP software).
Main memory partitioning is programmable up to three segments in steps of 1KB.
Access rights of each segment can be individually selected (main and information memory).
Access violation flags with interrupt capability for easy servicing of access violations.
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9.13 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be controlled
using all instructions. For complete module descriptions, see the MSP430FR58xx, MSP430FR59xx, and
MSP430FR6xx Family User's Guide.
9.13.1 Digital I/O
Up to eight 8-bit I/O ports are implemented:
•
•
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Edge-selectable interrupt and LPM3.5 and LPM4.5 wakeup input capability is available for all pins of ports
P1, P2, P3, P4, P5, P6, and P7.
Read and write access to port control registers is supported by all instructions.
Ports P1/P2, P3/P4, P5/P6, P7/(P8) can be accessed byte-wise or word-wise in pairs.
No cross-currents during start-up.
Note
Configuration of Digital I/Os After BOR Reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance with
Schmitt triggers and their module functions disabled. To enable the I/O functionality after a BOR
reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For details,
refer to the "Configuration After Reset" section of the Digital I/O chapter in the MSP430FR58xx,
MSP430FR59xx, and MSP430FR6xx Family User's Guide.
9.13.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch-crystal oscillator XT1 (LF), an internal very-low-power
low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency
crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements of both low system
cost and low power consumption. A fail-safe mechanism exists for all crystal sources. The clock system module
provides the following clock signals:
•
•
•
•
Auxiliary clock (ACLK). ACLK can be sourced from a 32-kHz watch crystal (LFXT1), the internal VLO, or a
digital external low-frequency (
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