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MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
MSP430G2x33, MSP430G2x03 Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Low Supply-Voltage Range: 1.8 V to 3.6 V
• Ultra-Low Power Consumption
– Active Mode: 230 µA at 1 MHz, 2.2 V
– Standby Mode: 0.5 µA
– Off Mode (RAM Retention): 0.1 µA
• Five Power-Saving Modes
• Ultra-Fast Wake up From Standby Mode in Less
Than 1 µs
• 16-Bit RISC Architecture, 62.5-ns Instruction Cycle
Time
• Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With Four
Calibrated Frequencies
– Internal Very-Low-Power Low-Frequency (LF)
Oscillator
– 32-kHz Crystal
– External Digital Clock Source
• Two 16-Bit Timer_A With Three Capture/Compare
Registers
• Up to 24 Capacitive-Touch Enabled I/O Pins
1.2
•
•
Applications
Power Management
Sensor Interface
1.3
• Universal Serial Communication Interface (USCI)
– Enhanced UART Supports Automatic BaudRate Detection (LIN)
– IrDA Encoder and Decoder
– Synchronous SPI
– I2C
• 10-Bit 200-ksps Analog-to-Digital Converter (ADC)
With Internal Reference, Sample-and-Hold, and
Autoscan (See Table 3-1)
• Brownout Detector
• Serial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security Fuse
• On-Chip Emulation Logic With Spy-Bi-Wire
Interface
• Section 3 Summarizes Available Family Members
• Package Options
– TSSOP: 20 Pin, 28 Pin
– PDIP: 20 Pin
– QFN: 32 Pin
• For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide (SLAU144)
•
Capacitive Touch
Description
The TI MSP family of ultra-low-power microcontrollers consists of several devices that feature different
sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to
maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from lowpower modes to active mode in less than 1 µs.
The MSP430G2x03 and MSP430G2x33 devices are ultra-low-power mixed-signal microcontrollers with
built-in 16-bit timers, up to 24 I/O capacitive-touch enabled pins, and built-in communication capability
using the USCI. In addition, the MSP430G2x33 family members have a 10-bit ADC. See Section 3 for
configuration details.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital
values, and then process the data for display or for transmission to a host system.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
Device Information (1)
PART NUMBER
MSP430G2533IRHB
MSP430G2533IPW
MSP430G2533IN
(1)
(2)
1.4
PACKAGE
BODY SIZE (2)
VQFN (32)
5 mm × 5 mm
TSSOP (28)
9.7 mm × 4.4 mm
TSSOP (20)
6.5 mm × 4.4 mm
PDIP (20)
24.33 mm × 6.35 mm
For the most current part, package, and ordering information, see the Package Option Addendum in
Section 8, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 8.
Functional Block Diagrams
Figure 1-1 shows the functional block diagram of the MSP430G2x33 MCUs.
XIN XOUT
DVCC
DVSS
P1.x
8
P2.x
8
P3.x
8
ACLK
Clock
System
SMCLK
MCLK
16-MHz
CPU
including
16 registers
Emulation
2BP
Flash
RAM
ADC
Port P1
Port P2
Port P3
16KB
8KB
4KB
2KB
512B
256B
10 bit,
8 channel,
autoscan,
1-channel
DMA
8 I/Os,
interrupt
capability,
pullup or
pulldown
resistors
8 I/Os,
interrupt
capability,
pullup or
pulldown
resistors
8 I/Os,
pullup or
pulldown
resistors
Watchdog
WDT+
Timer0_A3
Timer1_A3
3 CC
registers
3 CC
registers
MAB
MDB
Brownout
Protection
15-Bit
JTAG
interface
USCI A0
UART,
LIN, IrDA,
SPI
USCI B0
SPI, I2C
Spy-BiWire
RST/NMI
Copyright © 2016, Texas Instruments Incorporated
NOTE: Port P3 is available on 28-pin and 32-pin devices only.
Figure 1-1. Functional Block Diagram, MSP430G2x33
2
Device Overview
Copyright © 2011–2016, Texas Instruments Incorporated
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MSP430G2203
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Figure 1-2 shows the functional block diagram of the MSP430G2x03 MCUs.
DVCC
XIN XOUT
DVSS
P1.x
8
P2.x
8
P3.x
8
ACLK
Clock
System
SMCLK
Flash
RAM
Port P1
Port P2
Port P3
8KB
4KB
2KB
256B
8 I/Os,
interrupt
capability,
pullup or
pulldown
resistors
8 I/Os,
interrupt
capability,
pullup or
pulldown
resistors
8 I/Os,
pullup or
pulldown
resistors
MCLK
16-MHz
CPU
including
16 registers
Emulation
2BP
MAB
MDB
Brownout
Protection
Watchdog
WDT+
15-Bit
JTAG
interface
Timer0_A3
Timer1_A3
3 CC
registers
3 CC
registers
USCI A0
UART,
LIN, IrDA,
SPI
USCI B0
2
SPI, I C
Spy-BiWire
RST/NMI
Copyright © 2016, Texas Instruments Incorporated
NOTE: Port P3 is available on 28-pin and 32-pin devices only.
Figure 1-2. Functional Block Diagram, MSP430G2x03
Device Overview
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MSP430G2203
Copyright © 2011–2016, Texas Instruments Incorporated
3
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
Device Overview ......................................... 1
5.25
USCI (UART Mode) ................................. 28
1.1
Features .............................................. 1
5.26
USCI (SPI Master Mode)............................ 28
1.2
Applications ........................................... 1
5.27
USCI (SPI Slave Mode) ............................. 29
1.3
Description ............................................ 1
1.4
Functional Block Diagrams ........................... 2
5.28
5.29
USCI (I2C Mode) ....................................
10-Bit ADC, Power Supply and Input Range
Conditions (MSP430G2x33 Only) ...................
10-Bit ADC, Built-In Voltage Reference
(MSP430G2x33 Only) ...............................
10-Bit ADC, External Reference (MSP430G2x33
Only) .................................................
10-Bit ADC, Timing Parameters (MSP430G2x33
Only) .................................................
10-Bit ADC, Linearity Parameters (MSP430G2x33
Only) .................................................
10-Bit ADC, Temperature Sensor and Built-In VMID
(MSP430G2x33 Only) ...............................
Revision History ......................................... 5
Device Comparison ..................................... 6
Related Products ..................................... 7
3.1
4
5
5.31
Terminal Configuration and Functions .............. 8
4.1
Pin Diagrams ......................................... 8
4.2
Signal Descriptions .................................. 10
5.32
Specifications ........................................... 13
........................
ESD Ratings ........................................
Recommended Operating Conditions ...............
5.1
Absolute Maximum Ratings
5.2
5.3
5.4
Active Mode Supply Current Into VCC Excluding
External Current .....................................
Typical Characteristics, Active Mode Supply Current
(Into VCC) ............................................
Low-Power Mode Supply Currents (Into VCC)
Excluding External Current..........................
Typical Characteristics, Low-Power Mode Supply
Currents .............................................
5.5
5.6
5.7
13
14
15
6
16
17
5.9
Schmitt-Trigger Inputs, Ports Px .................... 19
5.10
Leakage Current, Ports Px .......................... 19
5.11
Outputs, Ports Px
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.34
13
Thermal Resistance Characteristics ................ 18
...................................
Output Frequency, Ports Px ........................
Typical Characteristics – Outputs ...................
Pin-Oscillator Frequency – Ports Px ................
Typical Characteristics – Pin-Oscillator Frequency .
POR, BOR ..........................................
Main DCO Characteristics ..........................
DCO Frequency .....................................
Calibrated DCO Frequencies, Tolerance ...........
5.33
13
5.8
5.12
4
5.30
19
19
20
21
21
22
7
24
24
25
Wake-up Times From Lower-Power Modes (LPM3,
LPM4) .............................................. 26
Typical Characteristics, DCO Clock Wake-up Time
From LPM3 or LPM4 ................................ 26
5.22
5.23
Crystal Oscillator, XT1, Low-Frequency Mode ..... 27
Internal Very-Low-Power Low-Frequency Oscillator
(VLO) ................................................ 27
5.24
Timer_A
.............................................
Table of Contents
27
8
30
31
32
33
33
33
34
5.35
Flash Memory ....................................... 34
5.36
RAM ................................................. 35
5.37
JTAG and Spy-Bi-Wire Interface .................... 35
5.38
JTAG Fuse .......................................... 35
Detailed Description ................................... 36
.................................................
6.1
CPU
6.2
Instruction Set ....................................... 37
6.3
Operating Modes .................................... 38
6.4
Interrupt Vector Addresses.......................... 39
6.5
Special Function Registers (SFRs) ................. 40
6.6
Memory Organization ............................... 41
6.7
Bootloader (BSL) .................................... 41
6.8
Flash Memory ....................................... 42
..........................................
36
6.9
Peripherals
6.10
I/O Port Diagrams ................................... 48
42
Device and Documentation Support ............... 64
7.1
Getting Started and Next Steps ..................... 64
7.2
Device Nomenclature ............................... 64
7.3
Tools and Software
7.4
Documentation Support ............................. 68
7.5
Related Links ........................................ 70
7.6
Community Resources .............................. 71
7.7
Trademarks.......................................... 71
7.8
Electrostatic Discharge Caution ..................... 71
7.9
Glossary ............................................. 71
.................................
66
Mechanical, Packaging, and Orderable
Information .............................................. 72
Copyright © 2011–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
SLAS734G – APRIL 2011 – REVISED APRIL 2016
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from May 2, 2013 to April 27, 2016
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Page
Document format and organization changes throughout, including addition of section numbering........................ 1
Added Device Information table .................................................................................................... 2
Added Section 3.1, Related Products ............................................................................................. 7
Moved Section 5, Specifications .................................................................................................. 13
Added Section 5.2, ESD Ratings.................................................................................................. 13
Added Section 5.8, Thermal Resistance Characteristics ...................................................................... 18
Throughout document, changed all instances of "bootstrap loader" to "bootloader" ....................................... 39
Changed all instances of "INCHx = 0x1010" to "INCHx = 1010b" in Table 6-11, Labels Used by the ADC
Calibration Tags ..................................................................................................................... 43
Moved and renamed Section 6.10, I/O Port Diagrams ......................................................................... 48
Added notes to UCB0STE and UCA0CLK in Table 6-18 ...................................................................... 53
Added notes to UCB0CLK and UCA0STE in Table 6-19 ...................................................................... 55
Added "and PW28" to title of Section 6.10.8 .................................................................................... 62
Added "and PW28" to title of Table 6-23 ......................................................................................... 63
Added Section 7, Device and Documentation Support......................................................................... 64
Added Section 8, Mechanical, Packaging, and Orderable Information ...................................................... 72
Revision History
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Copyright © 2011–2016, Texas Instruments Incorporated
5
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
3 Device Comparison
Table 3-1 compares the available family members.
Table 3-1. Device Comparison (1) (2)
DEVICE
MSP430G2533
MSP430G2433
MSP430G2333
MSP430G2233
MSP430G2403
MSP430G2303
MSP430G2203
(1)
(2)
6
BSL
1
1
1
1
1
1
1
EEM
1
1
1
1
1
1
1
FLASH
(KB)
16
8
4
2
8
4
2
RAM
(B)
512
512
256
256
512
256
256
Timer_A
2x TA3
2x TA3
2x TA3
2x TA3
2x TA3
2x TA3
2x TA3
ADC10
CHANNELS
8
8
8
8
–
–
–
USCI_A0,
USCI_B0
1
1
1
1
1
1
1
CLOCK
LF, DCO,
VLO
LF, DCO,
VLO
LF, DCO,
VLO
LF, DCO,
VLO
LF, DCO,
VLO
LF, DCO,
VLO
LF, DCO,
VLO
I/O
PACKAGE
24
32-QFN
24
28-TSSOP
16
20-TSSOP
16
20-PDIP
24
32-QFN
24
28-TSSOP
16
20-TSSOP
16
20-PDIP
24
32-QFN
24
28-TSSOP
16
20-TSSOP
16
20-PDIP
24
32-QFN
24
28-TSSOP
16
20-TSSOP
16
20-PDIP
24
32-QFN
24
28-TSSOP
16
20-TSSOP
16
20-PDIP
24
32-QFN
24
28-TSSOP
16
20-TSSOP
16
20-PDIP
24
32-QFN
24
28-TSSOP
16
20-TSSOP
16
20-PDIP
For the most current device, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website
at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Device Comparison
Copyright © 2011–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
3.1
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Related Products
For information about other devices in this family of products or related products, see the following links.
Products for MSP 16-Bit and 32-Bit MCUs Low-power mixed-signal processors with smart analog and
digital peripherals for a wide range of industrial and consumer applications.
Products for Ultra-low Power MCUs MSP Ultra-Low-Power microcontrollers (MCUs) from Texas
Instruments (TI) offer the lowest power consumption and the perfect mix of integrated
peripherals for a wide range of low-power and portable applications.
Products for MSP430G2x/i2x Low-Cost Industrial MCUs MSP430G2x microcontrollers (MCUs) from
the MSP ultra-low-power MCU series, offers the low power and performance of 16-bit MSP
microcontrollers with a feature set targeted at cost sensitive applications.
Companion Products for MSP430G2533 Review products that are frequently purchased or used in
conjunction with this product.
Reference Designs for MSP430G2533 TI Designs Reference Design Library is a robust reference
design library that spans analog, embedded processor, and connectivity. Created by TI
experts to help you jump start your system design, all TI Designs include schematic or block
diagrams, BOMs, and design files to speed your time to market. Search and download
designs at ti.com/tidesigns.
Device Comparison
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Copyright © 2011–2016, Texas Instruments Incorporated
7
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
4 Terminal Configuration and Functions
4.1
Pin Diagrams
Figure 4-1 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 20-pin N or PW
package.
DVCC
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1
1
20
2
19
3
18
P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2
P1.3/ADC10CLK/VREF-/VEREF-/A3
P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/TCK
P1.5/TA0.0/UCB0CLK/UCA0STE/A5/TMS
P2.0/TA1.0
P2.1/TA1.1
P2.2/TA1.1
4
5
6
17
N20
PW20
(TOP VIEW)
16
15
7
14
8
13
9
12
10
11
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/UCB0SIMO/UCB0SDA/A7/TDO/TDI
P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/TDI/TCLK
P2.5/TA1.2
P2.4/TA1.2
P2.3/TA1.0
NOTE: ADC10 is available on MSP430G2x33 devices only.
NOTE: The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1.
Figure 4-1. 20-Pin N or PW Package (Top View), MSP430G2x03 and MSP430G2x33
Figure 4-2 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 28-pin PW
package.
DVCC
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1
1
28
2
27
3
26
P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2
P1.3/ADC10CLK/VREF-/VEREF-/A3
P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/TCK
P1.5/TA0.0/UCB0CLK/UCA0STE/A5/TMS
P3.1/TA1.0
4
25
5
24
P3.0/TA0.2
P2.0/TA1.0
P2.1/TA1.1
P2.2/TA1.1
P3.2/TA1.1
P3.3/TA1.2
9
20
10
19
11
18
12
17
13
16
14
15
6
7
8
23
PW28
(TOP VIEW)
22
21
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/UCB0SIMO/UCB0SDA/A7/TDO/TDI
P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/TDI/TCLK
P3.7/TA1CLK
P3.6/TA0.2
P3.5/TA0.1
P2.5/TA1.2
P2.4/TA1.2
P2.3/TA1.0
P3.4/TA0.0
NOTE: ADC10 is available on MSP430G2x33 devices only.
Figure 4-2. 28-Pin PW Package (Top View), MSP430G2x03 and MSP430G2x33
8
Terminal Configuration and Functions
Copyright © 2011–2016, Texas Instruments Incorporated
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MSP430G2203
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
SLAS734G – APRIL 2011 – REVISED APRIL 2016
NC
P1.0/TA0CLK/ACLK/A0/CA0
DVCC
AVCC
DVSS
AVSS
XIN/P2.6/TA0.1
XOUT/P2.7
Figure 4-3 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 32-pin RHB
package.
32 31 30 29 28 27 26 25
P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1
P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2
P1.3/ADC10CLK/VREF-/VEREF-/A3
P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/TCK
P1.5/TA0.0/UCB0CLK/UCA0STE/A5/TMS
1
24
2
23
P3.1/TA1.0
P3.0/TA0.2
NC
6
19
7
18
3
4
5
22
RHB32
(TOP VIEW)
8
21
20
17
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/UCB0SIMO/UCB0SDA/A7/TDO/TDI
P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/TDI/TCLK
P3.7/TA1CLK
P3.6/TA0.2
P3.5/TA0.1
P2.5/TA1.2
P3.2/TA1.1
P3.3/TA1.2
P3.4/TA0.0
P2.3/TA1.0
P2.4/TA1.2
P2.0/TA1.0
P2.1/TA1.1
P2.2/TA1.1
9 10 11 12 13 14 15 16
NOTE: ADC10 is available on MSP430G2x33 devices only.
Figure 4-3. 32-Pin RHB Package (Top View), MSP430G2x03 and MSP430G2x33
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Copyright © 2011–2016, Texas Instruments Incorporated
9
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
4.2
www.ti.com
Signal Descriptions
Table 4-1 describes the signals.
Table 4-1. Terminal Functions
TERMINAL
NO.
NAME
PW20,
N20
PW28
I/O
DESCRIPTION
RHB32
P1.0/
General-purpose digital I/O pin
TA0CLK/
2
ACLK/
2
31
I/O
Timer0_A, clock signal TACLK input
ACLK signal output
A0
ADC10 analog input A0 (1)
P1.1/
General-purpose digital I/O pin
TA0.0/
Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit
UCA0RXD/
3
3
1
I/O
USCI_A0 receive data input in UART mode
UCA0SOMI/
USCI_A0 slave data out/master in SPI mode
A1
ADC10 analog input A1 (1)
P1.2/
General-purpose digital I/O pin
TA0.1/
Timer0_A, capture: CCI1A input, compare: Out1 output
UCA0TXD/
4
4
2
I/O
USCI_A0 transmit data output in UART mode
UCA0SIMO/
USCI_A0 slave data in/master out in SPI mode
A2
ADC10 analog input A2 (1)
P1.3/
General-purpose digital I/O pin
ADC10CLK/
A3/
5
5
3
I/O
ADC10, conversion clock output (1)
ADC10 analog input A3 (1)
VREF-/VEREF-
ADC10 negative reference voltage
P1.4/
General-purpose digital I/O pin
SMCLK/
SMCLK signal output
UCB0STE/
USCI_B0 slave transmit enable
UCA0CLK/
6
6
4
I/O
(1)
USCI_A0 clock input/output
A4/
ADC10 analog input A4 (1)
VREF+/VEREF+
ADC10 positive reference voltage (1)
TCK
JTAG test clock, input terminal for device programming and test
P1.5/
General-purpose digital I/O pin
TA0.0/
Timer0_A, compare: Out0 output / BSL receive
UCB0CLK/
UCA0STE/
7
7
5
I/O
USCI_B0 clock input/output
USCI_A0 slave transmit enable
A5/
ADC10 analog input A5 (1)
TMS
JTAG test mode select, input terminal for device programming and test
P1.6/
General-purpose digital I/O pin
TA0.1/
Timer0_A, compare: Out1 output
A6/
UCB0SOMI/
14
22
21
I/O
ADC10 analog input A6 (1)
USCI_B0 slave out/master in SPI mode,
UCB0SCL/
USCI_B0 SCL I2C clock in I2C mode
TDI/TCLK
JTAG test data input or test clock input during programming and test
(1)
10
MSP430G2x33 devices only
Terminal Configuration and Functions
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SLAS734G – APRIL 2011 – REVISED APRIL 2016
Table 4-1. Terminal Functions (continued)
TERMINAL
NO.
NAME
PW20,
N20
PW28
I/O
DESCRIPTION
RHB32
P1.7/
General-purpose digital I/O pin
A7/
ADC10 analog input A7 (1)
UCB0SIMO/
15
23
22
I/O
USCI_B0 slave in/master out in SPI mode
UCB0SDA/
USCI_B0 SDA I2C data in I2C mode
TDO/TDI
JTAG test data output terminal or test data input during programming and
test (2)
P2.0/
TA1.0
P2.1/
TA1.1
P2.2/
TA1.1
P2.3/
TA1.0
P2.4/
TA1.2
P2.5/
TA1.2
8
10
9
I/O
9
11
10
I/O
10
12
11
I/O
11
16
15
I/O
12
17
16
I/O
13
18
17
I/O
19
27
26
I/O
XIN/
Timer1_A, capture: CCI0A input, compare: Out0 output
General-purpose digital I/O pin
Timer1_A, capture: CCI1A input, compare: Out1 output
General-purpose digital I/O pin
Timer1_A, capture: CCI1B input, compare: Out1 output
General-purpose digital I/O pin
Timer1_A, capture: CCI0B input, compare: Out0 output
General-purpose digital I/O pin
Timer1_A, capture: CCI2A input, compare: Out2 output
General-purpose digital I/O pin
Timer1_A, capture: CCI2B input, compare: Out2 output
Input terminal of crystal oscillator
P2.6/
TA0.1
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
XOUT/
P2.7
P3.0/
TA0.2
P3.1/
TA1.0
P3.2/
TA1.1
P3.3/
TA1.2
P3.4/
TA0.0
P3.5/
TA0.1
P3.6/
TA0.2
P3.7/
TA1CLK
18
26
25
I/O
-
9
7
I/O
-
8
6
I/O
-
13
12
I/O
-
14
13
I/O
-
15
14
I/O
-
19
18
I/O
-
20
19
I/O
-
21
20
I/O
16
24
23
I
RST/
Output terminal of crystal oscillator (3)
General-purpose digital I/O pin
General-purpose digital I/O pin
Timer0_A, capture: CCI2A input, compare: Out2 output
General-purpose digital I/O pin
Timer1_A, compare: Out0 output
General-purpose digital I/O pin
Timer1_A, compare: Out1 output
General-purpose digital I/O
Timer1_A, compare: Out2 output
General-purpose digital I/O
Timer0_A, compare: Out0 output
General-purpose digital I/O
Timer0_A, compare: Out1 output
General-purpose digital I/O
Timer0_A, compare: Out2 output
General-purpose digital I/O
Timer1_A, clock signal TACLK input
Reset
NMI/
SBWTDIO
(2)
(3)
General-purpose digital I/O pin
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TDO or TDI is selected by JTAG instruction.
If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
Terminal Configuration and Functions
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Table 4-1. Terminal Functions (continued)
TERMINAL
NO.
NAME
I/O
DESCRIPTION
PW20,
N20
PW28
RHB32
17
25
24
I
AVCC
NA
NA
29
NA
Analog supply voltage
DVCC
1
1
30
NA
Digital supply voltage
TEST/
SBWTCK
Selects test mode for JTAG pins on Port 1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DVSS
20
28
27, 28
NA
Ground reference
NC
NA
NA
8, 32
NA
Not connected
QFN Pad
NA
NA
Pad
NA
QFN package pad connection to VSS recommended.
12
Terminal Configuration and Functions
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SLAS734G – APRIL 2011 – REVISED APRIL 2016
5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS
Voltage applied to any pin
(2)
MIN
MAX
–0.3
4.1
–0.3
VCC + 0.3
Diode current at any device pin
(2)
(3)
Unprogrammed device
–55
150
Programmed device
–55
150
°C
ESD Ratings
VALUE
V(ESD)
(2)
V
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
(1)
V
±2
Storage temperature, Tstg (3)
(1)
UNIT
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3
Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
VCC
Supply voltage
VSS
Supply voltage
TA
Operating free-air temperature
fSYSTEM
(1)
(2)
Processor frequency (maximum MCLK frequency
using the USART module) (1) (2)
NOM
MAX
During program execution
1.8
3.6
During flash programming or erase
2.2
3.6
0
UNIT
V
V
–40
85
VCC = 1.8 V,
Duty cycle = 50% ±10%
DC
6
VCC = 2.7 V,
Duty cycle = 50% ±10%
DC
12
VCC = 3.3 V,
Duty cycle = 50% ±10%
DC
16
°C
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Specifications
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Legend :
System Frequency - MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
1.8 V
Note:
2.7 V
2.2 V
Supply Voltage - V
3.3 V 3.6 V
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 5-1. Safe Operating Area
5.4
Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
PARAMETER
IAM,1MHz
(1)
(2)
14
Active mode (AM)
current at 1 MHz
TEST CONDITIONS
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 0 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
VCC
MIN
TYP
2.2 V
230
3V
330
MAX
420
UNIT
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Specifications
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5.5
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Typical Characteristics, Active Mode Supply Current (Into VCC)
5.0
4.0
Active Mode Current − mA
Active Mode Current − mA
f DCO = 16 MHz
4.0
3.0
f DCO = 12 MHz
2.0
1.0
f DCO = 8 MHz
TA = 25 °C
2.0
2.0
2.5
3.0
3.5
VCC − Supply Voltage − V
Figure 5-2. Active Mode Current vs VCC, TA = 25°C
VCC = 3 V
TA = 85 °C
TA = 25 °C
1.0
f DCO = 1 MHz
0.0
1.5
TA = 85 °C
3.0
VCC = 2.2 V
4.0
0.0
0.0
4.0
8.0
12.0
Specifications
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16.0
f DCO − DCO Frequency − MHz
Figure 5-3. Active Mode Current vs DCO Frequency
15
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5.6
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TA
VCC
Low-power mode 0
(LPM0) current (3)
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
25°C
2.2 V
56
µA
ILPM2
Low-power mode 2
(LPM2) current (4)
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
22
µA
ILPM3,LFXT1
Low-power mode 3
(LPM3) current (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
0.7
1.5
µA
ILPM3,VLO
Low-power mode 3
current, (LPM3) (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
0.5
0.7
µA
0.5
ILPM4
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
0.1
Low-power mode 4
(LPM4) current (5)
0.8
1.7
ILPM0,1MHz
(1)
(2)
(3)
(4)
(5)
16
TEST CONDITIONS
25°C
85°C
2.2 V
MIN
(2)
TYP
MAX
UNIT
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
Specifications
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5.7
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Typical Characteristics, Low-Power Mode Supply Currents
3.00
2.50
2.75
2.25
ILPM4 – Low-Power Mode Current – µA
ILPM3 – Low-Power Mode Current – µA
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
2.50
2.25
2.00
1.75
1.50
VCC = 3.6 V
1.25
VCC = 3 V
1.00
VCC = 2.2 V
0.75
0.50
VCC = 1.8 V
0.25
0.00
-40
-20
0
20
40
60
TA – Temperature – °C
Figure 5-4. LPM3 Current vs Temperature
80
2.00
1.75
1.50
1.25
VCC = 3.6 V
1.00
VCC = 3 V
0.75
VCC = 2.2 V
0.50
0.25
0.00
-40
VCC = 1.8 V
-20
0
20
40
60
80
TA – Temperature – °C
Figure 5-5. LPM4 Current vs Temperature
Specifications
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5.8
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Thermal Resistance Characteristics
PARAMETER
RθJA
Junction-to-ambient thermal resistance, still air
RθJC(TOP)
Junction-to-case (top) thermal resistance
RθJC(BOTTOM)
θJB
ΨJT
ΨJB
(1)
(2)
(3)
(4)
18
VALUE
(2)
(3)
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
(4)
Junction-to-package-top characterization parameter
Junction-to-board characterization parameter
VQFN (RHB-32)
32.1
TSSOP (PW-28)
72.2
TSSOP (PW-20)
86.5
PDIP (N-20)
49.3
VQFN (RHB-32)
22.3
TSSOP (PW-28)
18.3
TSSOP (PW-20)
20.8
PDIP (N-20)
41
VQFN (RHB-32)
1.4
TSSOP (PW-28)
N/A
TSSOP (PW-20)
N/A
PDIP (N-20)
N/A
VQFN (RHB-32)
6.1
TSSOP (PW-28)
30.4
TSSOP (PW-20)
39
PDIP (N-20)
30.2
VQFN (RHB-32)
0.3
TSSOP (PW-28)
0.7
TSSOP (PW-20)
0.8
PDIP (N-20)
18.1
VQFN (RHB-32)
6.1
TSSOP (PW-28)
29.9
TSSOP (PW-20)
38.1
PDIP (N-20)
30.1
(1)
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
Specifications
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5.9
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Schmitt-Trigger Inputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
VCC
MIN
RPull
Pullup or pulldown resistor
CI
Input capacitance
VIN = VSS or VCC
MAX
0.45 VCC
0.75 VCC
1.35
2.25
3V
For pullup: VIN = VSS
For pulldown: VIN = VCC
TYP
UNIT
V
0.25 VCC
0.55 VCC
3V
0.75
1.65
3V
0.3
1
V
3V
20
50
kΩ
35
V
5
pF
5.10 Leakage Current, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
TEST CONDITIONS
High-impedance leakage current
See
VCC
(1) (2)
MIN
3V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
5.11 Outputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
I(OHmax) = –6 mA
VOL
Low-level output voltage
I(OLmax) = 6 mA (1)
(1)
VCC
(1)
MIN
TYP
MAX
UNIT
3V
VCC – 0.3
V
3V
VSS + 0.3
V
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
5.12 Output Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fPx.y
Port output frequency (with load)
fPort_CLK Clock output frequency
(1)
(2)
TEST CONDITIONS
Px.y, CL = 20 pF, RL = 1 kΩ (1)
Px.y, CL = 20 pF (2)
(2)
VCC
MIN
TYP
MAX
UNIT
3V
12
MHz
3V
16
MHz
A resistive divider with two 50-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Specifications
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5.13 Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
50
VCC = 2.2 V
P1.7
TA = 25°C
25
TA = 85°C
20
15
10
5
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
30
0
0.5
1
1.5
2
40
TA = 85°C
30
20
10
2.5
VOL − Low-Level Output Voltage − V
Figure 5-6. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
0.5
1
1.5
2
2.5
3
3.5
VOL − Low-Level Output Voltage − V
Figure 5-7. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
0
VCC = 2.2 V
P1.7
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
TA = 25°C
0
0
−5
−10
−15
TA = 85°C
−20
TA = 25°C
−25
0
0.5
Specifications
VCC = 3 V
P1.7
−10
−20
−30
TA = 85°C
−40
TA = 25°C
−50
1
1.5
2
2.5
VOH − High-Level Output Voltage − V
Figure 5-8. Typical High-Level Output Current vs High-Level
Output Voltage
20
VCC = 3 V
P1.7
0
0.5
1
1.5
2
2.5
3
3.5
VOH − High-Level Output Voltage − V
Figure 5-9. Typical High-Level Output Current vs High-Level
Output Voltage
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SLAS734G – APRIL 2011 – REVISED APRIL 2016
5.14 Pin-Oscillator Frequency – Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
foP1.x
Port output oscillation frequency
foP2.x
Port output oscillation frequency
foP2.6/7
Port output oscillation frequency
foP3.x
(1)
(2)
Port output oscillation frequency
TEST CONDITIONS
P1.y, CL = 10 pF, RL = 100 kΩ
VCC
MIN
(1) (2)
P1.y, CL = 20 pF, RL = 100 kΩ (1) (2)
P2.0 to P2.5, CL = 10 pF, RL = 100 kΩ (1) (2)
P2.0 to P2.5, CL = 20 pF, RL = 100 kΩ (1) (2)
P2.6 and P2.7, CL = 20 pF, RL = 100
kΩ (1) (2)
P3.y, CL = 10 pF, RL = 100 kΩ
(1) (2)
P3.y, CL = 20 pF, RL = 100 kΩ
(1) (2)
3V
3V
3V
3V
TYP
MAX
UNIT
1400
kHz
900
1800
kHz
1000
700
kHz
1800
kHz
1000
A resistive divider with two 50-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of the
divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
5.15 Typical Characteristics – Pin-Oscillator Frequency
1.50
VCC = 2.2 V
VCC = 3.0 V
1.35
fosc − Typical Oscillation Frequency − MHz
fosc − Typical Oscillation Frequency − MHz
1.50
1.20
1.05
P1.y
0.90
P2.0 to P2.5
0.75
P2.6, P2.7
0.60
0.45
0.30
0.15
1.35
1.20
1.05
P1.y
0.90
P2.0 to P2.5
0.75
P2.6, P2.7
0.60
0.45
0.30
0.15
0.00
0.00
10
50
100
CLOAD − External Capacitance − pF
One output active at a time.
Figure 5-10. Typical Oscillating Frequency vs Load Capacitance
10
50
100
CLOAD − External Capacitance − pF
One output active at a time.
Figure 5-11. Typical Oscillating Frequency vs Load Capacitance
Specifications
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5.16 POR, BOR (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
VCC(start)
See Figure 5-12
dVCC/dt ≤ 3 V/s
0.7 V(B_IT--)
V(B_IT–)
See Figure 5-12 through Figure 5-14
dVCC/dt ≤ 3 V/s
1.35
V
Vhys(B_IT–)
See Figure 5-12
dVCC/dt ≤ 3 V/s
140
mV
td(BOR)
See Figure 5-12
2000
µs
t(reset)
Pulse duration needed at RST/NMI pin to accepted
reset internally
(1)
(2)
2.2 V
2
V
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) +
Vhys(B_IT–) is ≤ 1.8 V.
During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT–) + Vhys(B_IT–). The default DCO settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(star t)
1
0
t d(BOR)
Figure 5-12. POR and BOR vs Supply Voltage
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
t pw − Pulse Width − µs
1000
1 ns
1 ns
t pw − Pulse Width − µs
Figure 5-13. VCC(drop) Level With a Square Voltage Drop to Generate a POR or BOR Signal
22
Specifications
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VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
t f = tr
1
t pw − Pulse Width − µs
1000
tf
tr
t pw − Pulse Width − µs
Figure 5-14. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR or BOR Signal
Specifications
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5.17 Main DCO Characteristics
•
•
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency
fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
faverage =
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
5.18 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
Supply voltage
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
RSELx = 15
3
3.6
0.14
MHz
0.17
MHz
V
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
3V
0.06
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
3V
0.07
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
3V
0.15
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
3V
0.21
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
3V
0.30
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
3V
0.41
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
3V
0.58
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
3V
0.54
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
3V
0.80
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
3V
1.6
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
3V
2.3
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
3V
3.4
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
3V
4.25
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
3V
4.30
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
3V
6.00
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
3V
8.60
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3V
1.35
ratio
SDCO
Frequency step between
tap DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
3V
1.08
ratio
Measured at SMCLK output
3V
50%
Duty cycle
24
Specifications
MHz
1.06
MHz
1.50
MHz
MHz
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5.19 Calibrated DCO Frequencies, Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
–3% ±0.5%
+3%
1-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
1-MHz tolerance over VCC
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
30°C
1.8 V to 3.6 V
–3%
±2%
+3%
1-MHz tolerance overall
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
–40°C to 85°C
1.8 V to 3.6 V
–6%
±3%
+6%
8-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
–3% ±0.5%
+3%
8-MHz tolerance over VCC
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
30°C
2.2 V to 3.6 V
–3%
±2%
+3%
8-MHz tolerance overall
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
–40°C to 85°C
2.2 V to 3.6 V
–6%
±3%
+6%
12-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
–3% ±0.5%
+3%
12-MHz tolerance over VCC
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
30°C
2.7 V to 3.6 V
–3%
±2%
+3%
12-MHz tolerance overall
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
–40°C to 85°C
2.7 V to 3.6 V
–6%
±3%
+6%
16-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
–3% ±0.5%
+3%
16-MHz tolerance over VCC
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
30°C
3.3 V to 3.6 V
–3%
±2%
+3%
16-MHz tolerance overall
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
–40°C to 85°C
3.3 V to 3.6 V
–6%
±3%
+6%
(1)
UNIT
This is the frequency change from the measured frequency at 30°C over temperature.
Specifications
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5.20 Wake-up Times From Lower-Power Modes (LPM3, LPM4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
tDCO,LPM3/4
DCO clock wake-up time from LPM3 or BCSCTL1 = CALBC1_1MHz,
LPM4 (1)
DCOCTL = CALDCO_1MHz
tCPU,LPM3/4
CPU wake-up time from LPM3 or
LPM4 (2)
(1)
(2)
MIN
TYP
3V
MAX
1.5
UNIT
µs
1/fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
5.21 Typical Characteristics, DCO Clock Wake-up Time From LPM3 or LPM4
DCO Wake Time − µs
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 5-15. DCO Wake-up Time From LPM3 vs DCO Frequency
26
Specifications
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5.22 Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
fLFXT1,LF,logic
LFXT1 oscillator logic level
square-wave input frequency,
LF mode
XTS = 0, XCAPx = 0, LFXT1Sx = 3
1.8 V to 3.6 V
OALF
Oscillation allowance for
LF crystals
CL,eff
fFault,LF
(1)
(2)
(3)
(4)
Integrated effective load
capacitance, LF mode (2)
MIN
TYP
MAX
32768
10000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
UNIT
Hz
50000
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle, LF mode
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
2.2 V
30%
Oscillator fault frequency,
LF mode (3)
XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4)
2.2 V
10
50%
pF
70%
10000
Hz
To
•
•
•
•
•
•
•
improve EMI on the XT1 oscillator, the following guidelines should be observed.
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TA
VCC
MIN
TYP
MAX
fVLO
VLO frequency
PARAMETER
–40°C to 85°C
3V
4
12
20
dfVLO/dT
VLO frequency temperature drift
–40°C to 85°C
3V
25°C
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
UNIT
kHz
0.5
%/°C
4
%/V
5.24 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
SMCLK, duty cycle = 50% ±10%
tTA,cap
Timer_A capture timing
TA0, TA1
VCC
MIN
3V
20
TYP
MAX
fSYSTEM
Specifications
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UNIT
MHz
ns
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5.25 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fUSCI
USCI input clock frequency
fmax,BITCLK
Maximum BITCLK clock frequency
(equals baud rate in MBaud) (1)
3V
2
tτ
UART receive deglitch time (2)
3V
50
(1)
(2)
SMCLK, duty cycle = 50% ±10%
TYP
MAX
fSYSTEM
UNIT
MHz
MHz
100
600
ns
The DCO wake-up time must be considered in LPM3 and LPM4 for baud rates above 1 MHz.
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
5.26 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16
and Figure 5-17)
PARAMETER
TEST CONDITIONS
VCC
MIN
fUSCI
USCI input clock frequency
SMCLK, duty cycle = 50% ±10%
tSU,MI
SOMI input data setup time
3V
75
tHD,MI
SOMI input data hold time
3V
0
tVALID,MO
SIMO output data valid time
UCLK edge to SIMO valid, CL = 20 pF
3V
MAX
UNIT
fSYSTEM
MHz
ns
ns
20
ns
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-16. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 5-17. SPI Master Mode, CKPH = 1
28
Specifications
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5.27 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18
and Figure 5-19)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
STE lead time, STE low to clock
3V
tSTE,LAG
STE lag time, Last clock to STE high
3V
tSTE,ACC
STE access time, STE low to SOMI data out
3V
50
ns
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
3V
50
ns
tSU,SI
SIMO input data setup time
3V
15
ns
tHD,SI
SIMO input data hold time
3V
10
ns
tVALID,SO
UCLK edge to SOMI valid,
CL = 20 pF
SOMI output data valid time
tSTE,LEAD
3V
50
UNIT
tSTE,LEAD
ns
10
ns
50
75
ns
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tSU,SI
tLO/HI
tHD,SI
SIMO
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
SOMI
Figure 5-18. SPI Slave Mode, CKPH = 0
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
tSTE,ACC
tHD,MO
tVALID,SO
tSTE,DIS
SOMI
Figure 5-19. SPI Slave Mode, CKPH = 1
Specifications
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5.28 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-20)
PARAMETER
TEST CONDITIONS
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
3V
0
TYP
SMCLK, duty cycle = 50% ±10%
fSCL ≤ 100 kHz
MAX
UNIT
fSYSTEM
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
3V
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
3V
0
tSU,DAT
Data setup time
3V
250
ns
tSU,STO
Setup time for STOP
3V
4.0
µs
tSP
Pulse duration of spikes suppressed by
input filter
3V
50
fSCL > 100 kHz
fSCL ≤ 100 kHz
tSU,STA
tHD,STA
4.7
3V
fSCL > 100 kHz
µs
0.6
µs
0.6
tHD,STA
ns
100
600
ns
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-20. I2C Mode Timing
30
Specifications
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SLAS734G – APRIL 2011 – REVISED APRIL 2016
5.29 10-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x33 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
TEST CONDITIONS
Analog supply voltage
VAx
Analog input voltage
IADC10
IREF+
VCC
VSS = 0 V
(2)
ADC10 supply current
TA
(3)
Reference supply current,
reference buffer disabled (4)
All Ax terminals, Analog inputs
selected in ADC10AE register
fADC10CLK = 5.0 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
3V
25°C
3V
MIN
TYP
MAX
UNIT
2.2
3.6
V
0
VCC
V
0.6
mA
0.25
25°C
3V
mA
0.25
IREFB,0
Reference buffer supply current
with ADC10SR = 0 (4)
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
25°C
3V
1.1
mA
IREFB,1
Reference buffer supply current
with ADC10SR = 1 (4)
fADC10CLK = 5.0 MHz,
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
25°C
3V
0.5
mA
CI
Input capacitance
Only one terminal Ax can be selected
at one time
25°C
3V
Input MUX ON resistance
0 V ≤ VAx ≤ VCC
25°C
3V
RI
(1)
(2)
(3)
(4)
27
1000
pF
Ω
The leakage current is defined in the leakage current table with Px.y/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied through terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
Specifications
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5.30 10-Bit ADC, Built-In Voltage Reference (MSP430G2x33 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VCC,REF+
Positive built-in reference
analog supply voltage range
IVREF+ ≤ 1 mA, REF2_5V = 0
2.2
IVREF+ ≤ 1 mA, REF2_5V = 1
2.9
VREF+
Positive built-in reference
voltage
IVREF+ ≤ IVREF+max, REF2_5V = 0
ILD,VREF+
Maximum VREF+ load current
VREF+ load regulation
IVREF+ ≤ IVREF+max, REF2_5V = 1
3V
3V
IVREF+ = 500 µA ±100 µA,
Analog input voltage VAx ≈ 0.75 V,
REF2_5V = 0
IVREF+ = 500 µA ±100 µA,
Analog input voltage VAx ≈ 1.25 V,
REF2_5V = 1
TYP
MAX
UNIT
V
1.41
1.5
1.59
2.35
2.5
2.65
±1
V
mA
±2
3V
LSB
±2
VREF+ load regulation response
time
IVREF+ = 100 µA → 900 µA,
VAx ≈ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB,
ADC10SR = 0
3V
400
ns
CVREF+
Maximum capacitance at pin
VREF+
IVREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1
3V
100
pF
TCREF+
Temperature coefficient
IVREF+ = const with 0 mA ≤ IVREF+ ≤ 1 mA
3V
±100
ppm/
°C
tREFON
Settling time of internal
reference voltage to 99.9%
VREF
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 → 1
3.6 V
30
µs
tREFBURST
Settling time of reference buffer
to 99.9% VREF
IVREF+ = 0.5 mA,
REF2_5V = 1, REFON = 1,
REFBURST = 1, ADC10SR = 0
3V
2
µs
32
Specifications
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SLAS734G – APRIL 2011 – REVISED APRIL 2016
5.31 10-Bit ADC, External Reference (1) (MSP430G2x33 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VEREF+
TEST CONDITIONS
Positive external reference input
voltage range (2)
(1)
(2)
(3)
(4)
(5)
UNIT
VEREF– ≤ VEREF+ ≤ VCC – 0.15 V,
SREF1 = 1, SREF0 = 1 (3)
1.4
3
0
1.2
V
1.4
VCC
V
Differential external reference input
voltage range,
VEREF+ > VEREF–
ΔVEREF = VEREF+ – VEREF–
Static input current into VEREF–
MAX
VCC
ΔVEREF
IVEREF–
TYP
1.4
Negative external reference input
voltage range (4)
Static input current into VEREF+
MIN
VEREF+ > VEREF–,
SREF1 = 1, SREF0 = 0
VEREF–
IVEREF+
VCC
V
VEREF+ > VEREF–
(5)
0 V ≤ VEREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
3V
±1
0 V ≤ VEREF+ ≤ VCC – 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1 (3)
3V
0
0 V ≤ VEREF– ≤ VCC
3V
±1
µA
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
5.32 10-Bit ADC, Timing Parameters (MSP430G2x33 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC10SR = 0
VCC
MIN
TYP
MAX
0.45
6.3
0.45
1.5
fADC10CLK
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10OSC
ADC10 built-in
oscillator frequency
ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
3V
3.7
6.3
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
3V
2.06
3.51
tCONVERT
Conversion time
tADC10ON
Turnon settling time
of the ADC
(1)
ADC10SR = 1
3V
UNIT
MHz
MHz
µs
13 ×
ADC10DIV ×
1 / fADC10CLK
fADC10CLK from ACLK, MCLK, or SMCLK:
ADC10SSELx ≠ 0
(1)
100
ns
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
5.33 10-Bit ADC, Linearity Parameters (MSP430G2x33 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
EI
Integral linearity error
PARAMETER
TEST CONDITIONS
3V
±1
LSB
ED
Differential linearity error
3V
±1
LSB
EO
Offset error
3V
±1
LSB
EG
Gain error
3V
±1.1
±2
LSB
ET
Total unadjusted error
3V
±2
±5
LSB
Source impedance RS < 100 Ω
VCC
MIN
TYP
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5.34 10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x33 Only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Temperature sensor supply
current (1)
ISENSOR
TCSENSOR
TEST CONDITIONS
VCC
REFON = 0, INCHx = 0Ah, TA = 25°C
ADC10ON = 1, INCHx = 0Ah
(2)
60
3V
3.55
tSensor(sample)
3V
IVMID
Current into divider at channel 11
ADC10ON = 1, INCHx = 0Bh
3V
VMID
VCC divider at channel 11
ADC10ON = 1, INCHx = 0Bh,
VMID ≈ 0.5 × VCC
3V
tVMID(sample)
Sample time required if channel 11 ADC10ON = 1, INCHx = 0Bh,
is selected (5)
Error of conversion result ≤ 1 LSB
(2)
(3)
(4)
(5)
TYP
3V
Sample time required if channel 10 ADC10ON = 1, INCHx = 0Ah,
is selected (3)
Error of conversion result ≤ 1 LSB
(1)
MIN
3V
MAX
UNIT
µA
mV/°C
30
µs
(4)
1.5
µA
V
1220
ns
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor (273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
No additional current is needed. The VMID is used during sampling.
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
5.35 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.2 V, 3.6 V
1
5
mA
IERASE
Supply current from VCC during erase
2.2 V, 3.6 V
1
7
mA
tCPT
Cumulative program time (1)
2.2 V, 3.6 V
10
ms
tCMErase
Cumulative mass erase time
2.2 V, 3.6 V
20
4
Program and erase endurance
10
ms
5
10
100
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
See
(2)
30
years
tFTG
See
(2)
25
tFTG
tBlock, 1-63
Block program time for each additional byte or
word
See
(2)
18
tFTG
tBlock,
Block program end-sequence wait time
See
(2)
6
tFTG
10593
tFTG
4819
tFTG
tBlock,
Block program time for first byte or word
0
End
tMass Erase
Mass erase time
See
(2)
tSeg
Segment erase time
See
(2)
(1)
(2)
34
Erase
Do not exceed the cumulative program time when writing to a 64-byte flash block. This parameter applies to all programming methods:
individual word or byte write and block write modes.
These values are hardwired into the state machine of the flash controller (tFTG = 1/fFTG).
Specifications
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SLAS734G – APRIL 2011 – REVISED APRIL 2016
5.36 RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
(1)
TEST CONDITIONS
MIN
CPU halted
MAX
UNIT
1.6
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
5.37 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2.2 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V
0.025
15
µs
tSBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge (1))
2.2 V
1
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V
15
100
fTCK
TCK input frequency (2)
2.2 V
0
5
MHz
RInternal
Internal pulldown resistance on TEST
2.2 V
25
90
kΩ
(1)
(2)
VCC
MIN
TYP
60
µs
Tools that access the Spy-Bi-Wire interface must wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before
applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
5.38 JTAG Fuse (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
TEST CONDITIONS
TA = 25°C
MIN
MAX
UNIT
2.5
6
V
7
V
100
mA
1
ms
After the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation features is possible, and JTAG is switched to
bypass mode.
Specifications
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6 Detailed Description
6.1
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are
dedicated as program counter, stack pointer, status register, and constant generator, respectively. The
remaining registers are general-purpose registers (see Figure 6-1).
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Figure 6-1. Integrated CPU Registers
36
Detailed Description
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6.2
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Instruction Set
The instruction set consists of 51 instructions with three formats and seven address modes. Each
instruction can operate on word and byte data. Table 6-1 lists examples of the three types of instruction
formats. Table 6-2 lists the address modes.
Table 6-1. Instruction Word Formats
EXAMPLE
OPERATION
Dual operands, source-destination
INSTRUCTION FORMAT
ADD R4,R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC → (TOS), R8 → PC
JNE
Jump-on-equal bit = 0
Relative jump, unconditional or conditional
Table 6-2. Address Mode Descriptions
(1)
ADDRESS MODE
S (1)
D
SYNTAX
EXAMPLE
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
Absolute
✓
✓
MOV &MEM,&TCDAT
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
S = source, D = destination
Detailed Description
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SLAS734G – APRIL 2011 – REVISED APRIL 2016
6.3
www.ti.com
Operating Modes
These microcontrollers have one active mode and five software-selectable low-power modes of operation.
An interrupt event can wake the device from any of the low-power modes, service the request, and restore
back to the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– DC generator of the DCO is disabled if DCO not used in active mode
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and SMCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK and SMCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK and SMCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
38
Detailed Description
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6.4
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are in the address range 0FFFFh to 0FFC0h (see
Table 6-3). The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
If the reset vector (at address 0FFFEh) contains 0FFFFh (for example, if the flash is not programmed), the
CPU goes into LPM4 immediately after power-up.
Table 6-3. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Power up
External reset
Watchdog Timer+
Flash key violation
PC out of range (1)
PORIFG
RSTIFG
WDTIFG
KEYV (2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (2)
(non)-maskable (3)
(non)-maskable
(non)-maskable
0FFFCh
30
Timer1_A3
TACCR0 CCIFG (4)
maskable
0FFFAh
29
Timer1_A3
TACCR2 TACCR1 CCIFG, TAIFG (2) (4)
maskable
0FFF8h
28
0FFF6h
27
Watchdog Timer+
WDTIFG
maskable
0FFF4h
26
Timer0_A3
TACCR0 CCIFG (4)
maskable
0FFF2h
25
(5) (4)
maskable
0FFF0h
24
USCI_A0, USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG (2) (5)
maskable
0FFEEh
23
USCI_A0, USCI_B0 transmit
USCI_B0 I2C receive or transmit
UCA0TXIFG, UCB0TXIFG (2) (6)
maskable
0FFECh
22
ADC10
(MSP430G2x33 only)
ADC10IFG (4)
maskable
0FFEAh
21
0FFE8h
20
I/O Port P2 (up to eight flags)
P2IFG.0 to P2IFG.7 (2) (4)
maskable
0FFE6h
19
I/O Port P1 (up to eight flags)
P1IFG.0 to P1IFG.7 (2) (4)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
(7)
0FFDEh
15
(8)
0FFDEh to
0FFC0h
14 to 0, lowest
Timer0_A3
See
See
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
TACCR2 TACCR1 CCIFG, TAIFG
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
Multiple source flags
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Interrupt flags are in the module.
In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
In UART or SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
This location is used as bootloader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h)
disables the erasure of the flash if an invalid password is supplied.
The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
Detailed Description
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6.5
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Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function
register bits not allocated to a functional purpose are not physically present in the device. Simple software
access is provided with this arrangement.
Legend
rw
rw-0, rw-1
rw-(0), rw-(1)
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Figure 6-2. Interrupt Enable Register 1 (Address = 00h)
7
6
5
ACCVIE
rw-0
4
NMIIE
rw-0
3
2
1
OFIE
rw-0
0
WDTIE
rw-0
Table 6-4. Interrupt Enable Register 1 Description
Bit
Field
Type
Reset
Description
5
ACCVIE
RW
0h
Flash access violation interrupt enable
4
NMIIE
RW
0h
(Non)maskable interrupt enable
1
OFIE
RW
0h
Oscillator fault interrupt enable
0
WDTIE
RW
0h
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if
Watchdog Timer is configured in interval timer mode.
Figure 6-3. Interrupt Enable Register 2 (Address = 01h)
7
6
5
4
3
UCB0TXIE
rw-0
2
UCB0RXIE
rw-0
1
UCA0TXIE
rw-0
0
UCA0RXIE
rw-0
Table 6-5. Interrupt Enable Register 2 Description
Bit
Field
Type
Reset
Description
3
UCB0TXIE
RW
0h
USCI_B0 transmit interrupt enable
2
UCB0RXIE
RW
0h
USCI_B0 receive interrupt enable
1
UCA0TXIE
RW
0h
USCI_A0 transmit interrupt enable
0
UCA0RXIE
RW
0h
USCI_A0 receive interrupt enable
Figure 6-4. Interrupt Flag Register 1 (Address = 02h)
7
6
5
4
NMIIFG
rw-0
3
RSTIFG
rw-(0)
2
PORIFG
rw-(1)
1
OFIFG
rw-1
0
WDTIFG
rw-(0)
Table 6-6. Interrupt Flag Register 1 Description
Bit
Field
Type
Reset
Description
4
NMIIFG
RW
0h
Set by the RST/NMI pin
3
RSTIFG
RW
0h
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset
mode. Reset on VCC power-up.
2
PORIFG
RW
1h
Power-On Reset interrupt flag. Set on VCC power-up.
1
OFIFG
RW
1h
Flag set on oscillator fault.
0
WDTIFG
RW
0h
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
40
Detailed Description
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SLAS734G – APRIL 2011 – REVISED APRIL 2016
Figure 6-5. Interrupt Flag Register 2 (Address = 03h)
7
6
5
4
3
UCB0TXIFG
rw-1
2
UCB0RXIFG
rw-0
1
UCA0TXIFG
rw-1
0
UCA0RXIFG
rw-0
Table 6-7. Interrupt Flag Register 2 Description
Bit
Field
Type
Reset
Description
3
UCB0TXIFG
RW
0h
USCI_B0 transmit interrupt flag
2
UCB0RXIFG
RW
1h
USCI_B0 receive interrupt flag
1
UCA0TXIFG
RW
1h
USCI_A0 transmit interrupt flag
0
UCA0RXIFG
RW
0h
USCI_A0 receive interrupt flag
6.6
Memory Organization
Table 6-8 summarizes the memory map.
Table 6-8. Memory Organization
MSP430G2233
MSP430G2203
MSP430G2333
MSP430G2303
MSP430G2433
MSP430G2403
MSP430G2533
Size
2KB
4KB
8KB
16KB
Main: interrupt vector
Flash
FFFFh to FFC0h
FFFFh to FFC0h
FFFFh to FFC0h
FFFFh to FFC0h
Main: code memory
Flash
FFFFh to F800h
FFFFh to F000h
FFFFh to E000h
FFFFh to C000h
Information memory
Size
256 byte
256 byte
256 byte
256 byte
Flash
010FFh to 01000h
010FFh to 01000h
010FFh to 01000h
010FFh to 01000h
Size
256 byte
256 byte
512 byte
512 byte
02FFh to 0200h
02FFh to 0200h
03FFh to 0200h
03FFh to 0200h
16-bit
01FFh to 0100h
01FFh to 0100h
01FFh to 0100h
01FFh to 0100h
8-bit
0FFh to 010h
0FFh to 010h
0FFh to 010h
0FFh to 010h
0Fh to 00h
0Fh to 00h
0Fh to 00h
0Fh to 00h
Memory
RAM
Peripherals
8-bit SFR
6.7
Bootloader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface.
Access to the MSP430 memory through the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Programming With the
Bootloader User's Guide (SLAU319). Table 6-9 lists the BSL function pins.
Table 6-9. BSL Function Pins
BSL FUNCTION
20-PIN PW PACKAGE
20-PIN N PACKAGE
28-PIN PW PACKAGE
32-PIN RHB PACKAGE
Data transmit
3 - P1.1
3 - P1.1
1 - P1.1
Data receive
7 - P1.5
7 - P1.5
5 - P1.5
Detailed Description
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6.8
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Flash Memory
The flash memory can be programmed through the Spy-Bi-Wire/JTAG port or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory
include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are
also called information memory.
• Segment A contains calibration data. After reset segment A is protected against programming and
erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific
calibration data is required.
6.9
Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430x2xx Family User's
Guide (SLAU144).
6.9.1
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch
crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled
oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost
and low power consumption. The internal DCO provides a fast turnon clock source and stabilizes in less
than 1 µs. The basic clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
42
Detailed Description
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6.9.2
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Calibration Data Stored in Information Memory Segment A
Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure (see
Table 6-10 and Table 6-11).
Table 6-10. Tags Used by the ADC Calibration Tags
NAME
ADDRESS
VALUE
TAG_DCO_30
0x10F6
0x01
DCO frequency calibration at VCC = 3 V and TA = 30°C
DESCRIPTION
TAG_ADC10_1
0x10DA
0x10
ADC10_1 calibration tag
TAG_EMPTY
–
0xFE
Identifier for empty memory areas
Table 6-11. Labels Used by the ADC Calibration Tags
ADDRESS
OFFSET
SIZE
CAL_ADC_25T85
0x0010
word
INCHx = 1010b, REF2_5 = 1, TA = 85°C
CAL_ADC_25T30
0x000E
word
INCHx = 1010b, REF2_5 = 1, TA = 30°C
CAL_ADC_25VREF_FACTOR
0x000C
word
REF2_5 = 1, TA = 30°C, IVREF+ = 1 mA
CAL_ADC_15T85
0x000A
word
INCHx = 1010b, REF2_5 = 0, TA = 85°C
CAL_ADC_15T30
0x0008
word
INCHx = 1010b, REF2_5 = 0, TA = 30°C
CAL_ADC_15VREF_FACTOR
0x0006
word
REF2_5 = 0, TA = 30°C, IVREF+ = 0.5 mA
CAL_ADC_OFFSET
0x0004
word
External VREF = 1.5 V, fADC10CLK = 5 MHz
CAL_ADC_GAIN_FACTOR
0x0002
word
External VREF = 1.5 V, fADC10CLK = 5 MHz
LABEL
6.9.3
CONDITION AT CALIBRATION
CAL_BC1_1MHZ
0x0009
byte
–
CAL_DCO_1MHZ
0x0008
byte
–
CAL_BC1_8MHZ
0x0007
byte
–
CAL_DCO_8MHZ
0x0006
byte
–
CAL_BC1_12MHZ
0x0005
byte
–
CAL_DCO_12MHZ
0x0004
byte
–
CAL_BC1_16MHZ
0x0003
byte
–
CAL_DCO_16MHZ
0x0002
byte
–
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power
on and power off.
6.9.4
Digital I/O
Up to three 8-bit I/O ports are implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition (port P1 and port P2 only) is possible.
• Edge-selectable interrupt input capability for all bits of port P1 and port P2 (if available).
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup or pulldown resistor.
• Each I/O has an individually programmable pin oscillator enable bit to enable low-cost capacitive touch
detection.
Detailed Description
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WDT+ Watchdog Timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after
a software problem occurs. If the selected time interval expires, a system reset is generated. If the
watchdog function is not needed in an application, the module can be disabled or configured as an interval
timer and can generate interrupts at selected time intervals.
6.9.6
Timer_A3 (TA0, TA1)
Timer0_A3 and Timer1_A3 are 16-bit timers/counters with three capture/compare registers. Timer_A3 can
support multiple capture/compares, PWM outputs, and interval timing (see Table 6-12 and Table 6-13).
Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on
overflow conditions and from each of the capture/compare registers.
Table 6-12. Timer0_A3 Signal Connections
INPUT PIN NUMBER
PW20, N20
PW28
RHB32
DEVICE
INPUT
SIGNAL
P1.0-2
P1.0-2
P1.0-31
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
PW20, N20
PW28
RHB32
PinOsc
PinOsc
PinOsc
TACLK
INCLK
P1.1-3
P1.1-3
P1.1-1
TA0.0
CCI0A
P1.1-3
P1.1-3
P1.1-1
ACLK
CCI0B
P1.5-7
P1.5-7
P1.5-5
–
P3.4-15
P3.4-14
P1.2-4
44
MODULE
INPUT
NAME
P1.2-4
P1.2-2
VSS
GND
VCC
VCC
TA0
TA0.1
CCI1A
P1.2-4
P1.2-4
P1.2-2
CAOUT
CCI1B
P1.6-14
P1.6-22
P1.6-21
VSS
GND
P2.6-19
P2.6-27
P2.6-26
VCC
VCC
–
P3.5-19
P3.5-18
–
P3.0-9
P3.0-7
–
P3.6-20
P3.6-19
–
P3.0-9
P3.0-7
TA0.2
CCI2A
PinOsc
PinOsc
PinOsc
TA0.2
CCI2B
VSS
GND
VCC
VCC
Detailed Description
CCR0
CCR1
CCR2
TA1
TA2
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SLAS734G – APRIL 2011 – REVISED APRIL 2016
Table 6-13. Timer1_A3 Signal Connections
PW20, N20
INPUT PIN NUMBER
PW28
RHB32
DEVICE
INPUT
SIGNAL
MODULE
INPUT
NAME
–
P3.7-21
P3.7-20
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
P3.7-20
TACLK
INCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
PW20, N20
PW28
RHB32
–
P3.7-21
P2.0-8
P2.0-10
P2.0-9
TA1.0
CCI0A
P2.0-8
P2.0-10
P2.0-9
P2.3-11
P2.3-16
P2.3-12
TA1.0
CCI0B
P2.3-11
P2.3-16
P2.3-15
VSS
GND
P3.1-8
P3.1-6
VCC
VCC
CCR0
TA0
P2.1-9
P2.1-11
P2.1-10
TA1.1
CCI1A
P2.1-9
P2.1-11
P2.1-10
P2.2-10
P2.2-12
P2.2-11
TA1.1
CCI1B
P2.2-10
P2.2-12
P2.2-11
VSS
GND
P3.2-13
P3.2-12
CCR1
TA1
VCC
VCC
P2.4-12
P2.4-17
P2.4-16
TA1.2
CCI2A
P2.4-12
P2.4-17
P2.4-16
P2.5-13
P2.5-18
P2.5-17
TA1.2
CCI2B
P2.5-13
P2.5-18
P2.5-17
VSS
GND
P3.3-14
P3.3-13
VCC
VCC
6.9.7
CCR2
TA2
Universal Serial Communications Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication
protocols such as UART, enhanced UART with automatic baud rate detection (LIN), and IrDA. Not all
packages support the USCI functionality.
USCI_A0 provides support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3-pin or 4-pin) and I2C.
6.9.8
ADC10 (MSP430G2x33 Only)
The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit
SAR core, sample select control, reference generator, and data transfer controller (DTC) for automatic
conversion result handling, allowing ADC samples to be converted and stored without any CPU
intervention.
Detailed Description
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6.9.9
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Peripheral File Map
Table 6-14 lists the registers that support word access. Table 6-15 that support byte access.
Table 6-14. Peripherals With Word Access
MODULE
REGISTER DESCRIPTION
ACRONYM
OFFSET
ADC10SA
1BCh
ADC memory
ADC10MEM
1B4h
ADC control register 1
ADC10CTL1
1B2h
ADC control register 0
ADC10CTL0
1B0h
Capture/compare register
TA1CCR2
0196h
Capture/compare register
TA1CCR1
0194h
Capture/compare register
TA1CCR0
0192h
TA1R
0190h
Capture/compare control
TA1CCTL2
0186h
Capture/compare control
TA1CCTL1
0184h
Capture/compare control
TA1CCTL0
0182h
TA1CTL
0180h
Timer_A interrupt vector
TA1IV
011Eh
Capture/compare register
TA0CCR2
0176h
Capture/compare register
TA0CCR1
0174h
Capture/compare register
TA0CCR0
0172h
TA0R
0170h
Capture/compare control
TA0CCTL2
0166h
Capture/compare control
TA0CCTL1
0164h
Capture/compare control
TA0CCTL0
0162h
ADC data transfer start address
ADC10 (MSP430G2x33 only)
Timer_A register
Timer1_A3
Timer_A control
Timer_A register
Timer0_A3
Timer_A control
Flash Memory
Watchdog Timer+
TA0CTL
0160h
Timer_A interrupt vector
TA0IV
012Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
WDTCTL
0120h
ACRONYM
OFFSET
Watchdog timer control
Table 6-15. Peripherals With Byte Access
MODULE
REGISTER DESCRIPTION
USCI_B0 transmit buffer
UCB0TXBUF
06Fh
USCI_B0 receive buffer
UCB0RXBUF
06Eh
UCB0STAT
06Dh
USCI B0 I C Interrupt enable
UCB0CIE
06Ch
USCI_B0 bit rate control 1
UCB0BR1
06Bh
USCI_B0 bit rate control 0
UCB0BR0
06Ah
USCI_B0 control 1
UCB0CTL1
069h
USCI_B0 control 0
UCB0CTL0
068h
USCI_B0 I2C slave address
UCB0SA
011Ah
USCI_B0 I2C own address
UCB0OA
0118h
USCI_B0 status
2
USCI_B0
46
Detailed Description
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SLAS734G – APRIL 2011 – REVISED APRIL 2016
Table 6-15. Peripherals With Byte Access (continued)
MODULE
USCI_A0
ACRONYM
OFFSET
USCI_A0 transmit buffer
REGISTER DESCRIPTION
UCA0TXBUF
067h
USCI_A0 receive buffer
UCA0RXBUF
066h
USCI_A0 status
UCA0STAT
065h
USCI_A0 modulation control
UCA0MCTL
064h
USCI_A0 baud rate control 1
UCA0BR1
063h
USCI_A0 baud rate control 0
UCA0BR0
062h
USCI_A0 control 1
UCA0CTL1
061h
USCI_A0 control 0
ADC10 (MSP430G2x33 only)
Basic Clock System+
Port P3
(28-pin PW and 32-pin RHB only)
UCA0CTL0
060h
USCI_A0 IrDA receive control
UCA0IRRCTL
05Fh
USCI_A0 IrDA transmit control
UCA0IRTCTL
05Eh
USCI_A0 auto baud rate control
UCA0ABCTL
05Dh
ADC analog enable 0
ADC10AE0
04Ah
ADC analog enable 1
ADC10AE1
04Bh
ADC data transfer control register 1
ADC10DTC1
049h
ADC data transfer control register 0
ADC10DTC0
048h
Basic clock system control 3
BCSCTL3
053h
Basic clock system control 2
BCSCTL2
058h
Basic clock system control 1
BCSCTL1
057h
DCO clock frequency control
DCOCTL
056h
Port P3 selection 2. pin
P3SEL2
043h
Port P3 resistor enable
P3REN
010h
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
P3IN
018h
Port P3 input
Port P2 selection 2
P2SEL2
042h
Port P2 resistor enable
P2REN
02Fh
Port P2 selection
P2SEL
02Eh
P2IE
02Dh
Port P2 interrupt edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
P2IN
028h
Port P1 selection 2
P1SEL2
041h
Port P1 resistor enable
P1REN
027h
Port P1 selection
P1SEL
026h
Port P2 interrupt enable
Port P2
Port P2 input
Port P1 interrupt enable
Port P1
Special Function
P1IE
025h
Port P1 interrupt edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
Detailed Description
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MSP430G2203
Copyright © 2011–2016, Texas Instruments Incorporated
47
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
6.10 I/O Port Diagrams
6.10.1 Port P1 Pin Diagram: P1.0 to P1.2, Input/Output With Schmitt Trigger
Figure 6-6 shows the port diagram. Table 6-16 summarizes the selection of the pin functions.
To ADC10 *
INCHx = y *
ADC10AE0.y *
PxSEL2.y
PxSEL.y
PxDIR.y
0
From Timer
1
1
2
Direction
0: Input
1: Output
3
From USCI
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Timer
1
0
3
0
1
1
2
P1.0/TA0CLK/ ACLK/A0*
P1.1/TA0.0/
UCA0RXD/UCA0SOMI/A1*
P1.2/TA0.1/
UCA0TXD/UCA0SIMO/A2*
Bus
Keeper
EN
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
* Note: MSP430G2x33 devices only. MSP430G2x03 devices have no ADC10.
Figure 6-6. Port P1 (P1.0 to P1.2) Diagram
48
Detailed Description
Copyright © 2011–2016, Texas Instruments Incorporated
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MSP430G2203
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Table 6-16. Port P1 (P1.0 to P1.2) Pin Functions
PIN NAME
(P1.x)
CONTROL BITS OR SIGNALS (1)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
ADC10AE.x
(INCH.y = 1) (2)
I: 0; O: 1
0
0
0
TA0.TACLK
0
1
0
0
ACLK
1
1
0
0
A0 (2)/
A0
X
X
X
1 (y = 0)
Pin Osc
Capacitive sensing
P1.1/
P1.x (I/O)
TA0.0/
P1.0/
P1.x (I/O)
TA0CLK/
ACLK/
0
UCA0RXD/
1
X
0
1
0
I: 0; O: 1
0
0
0
TA0.0
1
1
0
0
TA0.CCI0A
0
1
0
0
0
UCA0RXD
from USCI
1
1
UCA0SOMI/
UCA0SOMI
from USCI
1
1
0
A1 (2)/
A1
X
X
X
1 (y = 1)
Pin Osc
Capacitive sensing
P1.2/
P1.x (I/O)
TA0.1/
TA0.1
X
0
1
0
I: 0; O: 1
0
0
0
1
1
0
0
TA0.CCI1A
0
1
0
0
UCA0TXD
from USCI
1
1
0
UCA0SIMO/
UCA0SIMO
from USCI
1
1
0
A2 (2)/
A2
X
X
X
1 (y = 2)
Pin Osc
Capacitive sensing
X
0
1
0
UCA0TXD/
(1)
(2)
2
X = don't care
MSP430G2x33 devices only
Detailed Description
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MSP430G2203
Copyright © 2011–2016, Texas Instruments Incorporated
49
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
6.10.2 Port P1 Pin Diagram: P1.3, Input/Output With Schmitt Trigger
Figure 6-7 shows the port diagram. Table 6-17 summarizes the selection of the pin functions.
SREF2 *
VSS
0
1
To ADC10 VREF- *
To ADC10 *
INCHx = y *
ADC10AE0.y *
PxSEL2.y PxSEL.y
PxDIR.y
0,2,3
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
PxOUT.y
From ADC10 *
DVSS
DVCC
0
1
1
0
1
2
P1.3/ADC10CLK*/
A3*/VREF-*/VEREF-*
Bus
Keeper
EN
3
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
EN
Set
Interrupt
Edge
Select
* Note: MSP430G2x33 devices only. MSP430G2x03 devices have no ADC10.
Figure 6-7. Port P1 (P1.3) Diagram
50
Detailed Description
Copyright © 2011–2016, Texas Instruments Incorporated
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MSP430G2203
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Table 6-17. Port P1 (P1.3) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME
(P1.x)
x
P1.3/
P1.x (I/O)
ADC10CLK
A3 (2)/
Pin Osc
(1)
(2)
(2)
/
3
VREF- (2)/
VEREF-
FUNCTION
(2)
/
P1DIR.x
P1SEL.x
P1SEL2.x
ADC10AE.x
(INCH.y = 1) (2)
I: 0; O: 1
0
0
0
ADC10CLK
1
1
0
0
A3
X
X
X
1 (y = 3)
VREF-
X
X
X
1
VEREF-
X
X
X
1
Capacitive sensing
X
0
1
0
X = don't care
MSP430G2x33 devices only
Detailed Description
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MSP430G2203
Copyright © 2011–2016, Texas Instruments Incorporated
51
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
6.10.3 Port P1 Pin Diagram: P1.4, Input/Output With Schmitt Trigger
Figure 6-8 shows the port diagram. Table 6-18 summarizes the selection of the pin functions.
From/To ADC10 Ref+ *
To ADC10 *
INCHx = y *
ADC10AE0.y *
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
0
1
DVCC
PxOUT.y
SMCLK
0
1
from Module
2
3
1
Bus
Keeper
EN
P1.4/SMCLK/UCB0STE/UCA0CLK/
VREF+/VEREF+/A4/TCK
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
From JTAG
To JTAG
* Note: MSP430G2x33 devices only. MSP430G2x03 devices have no ADC10.
Figure 6-8. Port P1 (P1.4) Diagram
52
Detailed Description
Copyright © 2011–2016, Texas Instruments Incorporated
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MSP430G2203
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Table 6-18. Port P1 (P1.4) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME
(P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
ADC10AE.x
(INCH.y =
1) (2)
JTAG Mode
I: 0; O: 1
0
0
0
0
1
1
0
0
0
1
1
0
0
P1.4/
P1.x (I/O)
SMCLK/
SMCLK
UCB0STE/
UCB0STE (3) (4)
from USCI
UCA0CLK/
(3) (4)
from USCI
1
1
0
0
VREF+
X
X
X
1
0
VEREF+ (2)/
VEREF+
X
X
X
1
0
A4 (2)/
A4
X
X
X
1 (y = 4)
0
TCK/
TCK
X
X
X
0
1
Pin Osc
Capacitive sensing
X
0
1
0
0
VREF+ (2)/
(1)
(2)
(3)
(4)
UCA0CLK
4
X = don't care
MSP430G2x33 devices only
The pin direction is controlled by the USCI module.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
Detailed Description
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MSP430G2203
Copyright © 2011–2016, Texas Instruments Incorporated
53
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
6.10.4 Port P1 Pin Diagram: P1.5 to P1.7, Input/Output With Schmitt Trigger
Figure 6-9 shows the port diagram. Table 6-19 summarizes the selection of the pin functions.
To ADC10 *
INCHx = y *
ADC10AE0.y *
PxSEL2.y
PxSEL.y
PxDIR.y
0
From Module
1
Direction
0: Input
1: Output
2
From Module
3
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Module
1
From Module
3
0
1
1
2
Bus
Keeper
EN
P1.5/TA0.0/UCB0CLK/
UCA0STE/A5*/TMS
P1.6/TA0.1/UCB0SOMI/
UCB0SCL/A6*/TDI/TCLK
P1.7/CAOUT/UCB0SIMO/
UCB0SDA/A7*/TDO/TDI
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
From JTAG
To JTAG
* Note: MSP430G2x33 devices only. MSP430G2x03 devices have no ADC10.
Figure 6-9. Port P1 (P1.5 to P1.7) Diagram
54
Detailed Description
Copyright © 2011–2016, Texas Instruments Incorporated
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MSP430G2203
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Table 6-19. Port P1 (P1.5 to P1.7) Pin Functions
CONTROL BITS OR SIGNALS (1)
PIN NAME
(P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
ADC10AE.x
(INCH.y =
1) (2)
JTAG Mode
I: 0; O: 1
0
0
0
0
1
1
0
0
0
1
1
0
0
P1.5/
P1.x (I/O)
TA0.0/
TA0.0
UCB0CLK/
UCB0CLK (3) (4)
from USCI
UCA0STE/
(3) (4)
from USCI
1
1
0
0
A5 (2)/
A5
X
X
X
1 (y = 5)
0
TMS
TMS
X
X
X
0
1
Pin Osc
Capacitive sensing
X
0
1
0
0
P1.6/
P1.x (I/O)
I: 0; O: 1
0
0
0
0
TA0.1/
TA0.1
1
1
0
0
0
UCB0SOMI/
UCB0SOMI
from USCI
1
1
0
0
UCB0SCL
UCB0SCL/
5
from USCI
1
1
0
0
A6 (2)/
A6
X
X
X
1 (y = 6)
0
TDI/TCLK/
TDI/TCLK
X
X
X
0
1
Pin Osc
Capacitive sensing
P1.7/
P1.x (I/O)
UCB0SIMO/
UCB0SDA/
(2)
A7 /
6
UCA0STE
7
X
0
1
0
0
I: 0; O: 1
0
0
0
0
UCB0SIMO
from USCI
1
1
0
0
UCB0SDA
from USCI
1
1
0
0
A7
X
X
X
1 (y = 7)
0
TDO/TDI/
TDO/TDI
X
X
X
0
1
Pin Osc
Capacitive sensing
X
0
1
0
0
(1)
(2)
(3)
(4)
X = don't care
MSP430G2x33 devices only
The pin direction is controlled by the USCI module.
UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
Detailed Description
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MSP430G2203
Copyright © 2011–2016, Texas Instruments Incorporated
55
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
6.10.5 Port P2 Pin Diagram: P2.0 to P2.5, Input/Output With Schmitt Trigger
Figure 6-10 shows the port diagram. Table 6-20 summarizes the selection of the pin functions.
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
PxSEL2.y
PxSEL.y
PxOUT.y
0
From Timer
1
1
DVSS
0
DVCC
1
1
2
0
P2.0/TA1.0
P2.1/TA1.1
P2.2/TA1.1
P2.3/TA1.0
P2.4/TA1.2
P2.5/TA1.2
3
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
Figure 6-10. Port P2 (P2.0 to P2.5) Diagram
56
Detailed Description
Copyright © 2011–2016, Texas Instruments Incorporated
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MSP430G2203
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Table 6-20. Port P2 (P2.0 to P2.5) Pin Functions
PIN NAME
(P2.x)
x
FUNCTION
P2.0/
P2.x (I/O)
TA1.0/
Timer1_A3.CCI0A
0
CONTROL BITS OR SIGNALS (1)
P2DIR.x
P2SEL.x
P2SEL2.x
I: 0; O: 1
0
0
0
1
0
Timer1_A3.TA0
1
1
0
Pin Osc
Capacitive sensing
X
0
1
P2.1/
P2.x (I/O)
I: 0; O: 1
0
0
Timer1_A3.CCI1A
0
1
0
Timer1_A3.TA1
1
1
0
Pin Osc
Capacitive sensing
X
0
1
P2.2/
P2.x (I/O)
I: 0; O: 1
0
0
TA1.1/
Timer1_A3.CCI1B
0
1
0
Timer1_A3.TA1
1
1
0
Pin Osc
Capacitive sensing
X
0
1
P2.3/
P2.x (I/O)
I: 0; O: 1
0
0
TA1.0/
Timer1_A3.CCI0B
0
1
0
Timer1_A3.TA0
1
1
0
TA1.1/
1
2
3
Pin Osc
Capacitive sensing
P2.4/
P2.x (I/O)
TA1.2/
Timer1_A3.CCI2A
4
X
0
1
I: 0; O: 1
0
0
0
1
0
Timer1_A3.TA2
1
1
0
Pin Osc
Capacitive sensing
X
0
1
P2.5/
P2.x (I/O)
I: 0; O: 1
0
0
TA1.2/
Timer1_A3.CCI2B
0
1
0
Timer1_A3.TA2
1
1
0
Capacitive sensing
X
0
1
5
Pin Osc
(1)
X = don't care
Detailed Description
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Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Copyright © 2011–2016, Texas Instruments Incorporated
57
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
6.10.6 Port P2 Pin Diagram: P2.6, Input/Output With Schmitt Trigger
Figure 6-11 shows the port diagram. Table 6-21 summarizes the selection of the pin functions.
XOUT/P2.7
LF off
PxSEL.6, PxSEL.7
BCSCTL3.LFXT1Sx = 11
0
1
LFXT1CLK
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
DVCC
PxOUT.y
0
From Module
1
0
1
1
2
XIN/P2.6/TA0.1
3
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
Figure 6-11. Port P2 (P2.6) Diagram
58
Detailed Description
Copyright © 2011–2016, Texas Instruments Incorporated
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Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Table 6-21. Port P2 (P2.6) Pin Functions
PIN NAME
(P2.x)
CONTROL BITS OR SIGNALS (1)
x
FUNCTION
XIN
XIN
P2.6
P2.x (I/O)
P2DIR.x
P2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
0
1
1
0
0
I: 0; O: 1
0
X
0
0
6
TA0.1
Timer0_A3.TA1
1
1
0
0
0
Pin Osc
Capacitive sensing
X
0
X
1
X
(1)
X = don't care
Detailed Description
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Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Copyright © 2011–2016, Texas Instruments Incorporated
59
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
6.10.7 Port P2 Pin Diagram: P2.7, Input/Output With Schmitt Trigger
Figure 6-12 shows the port diagram. Table 6-22 summarizes the selection of the pin functions.
XIN
LF off
PxSEL.6, PxSEL.7
BCSCTL3.LFXT1Sx = 11
0
1
LFXT1CLK
from P2.6
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
0
1
PxSEL2.y
PxSEL.y
DVSS
0
1
DVCC
PxOUT.y
0
From Module
1
1
2
XOUT/P2.7
3
TAx.y
TAxCLK
PxIN.y
EN
To Module
D
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
Figure 6-12. Port P2 (P2.7) Diagram
60
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MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Table 6-22. Port P2 (P2.7) Pin Functions
PIN NAME
(P2.x)
CONTROL BITS OR SIGNALS (1)
x
XOUT/
XOUT
P2.7/
7
Pin Osc
(1)
FUNCTION
P2.x (I/O)
Capacitive sensing
P2DIR.x
P2SEL.6
P2SEL.7
P2SEL2.6
P2SEL2.7
1
1
1
0
0
I: 0; O: 1
0
X
0
0
X
0
X
1
X
X = don't care
Detailed Description
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61
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
6.10.8 Port P3 Pin Diagram: P3.0 to P3.7, Input/Output With Schmitt Trigger (RHB and
PW28 Package Only)
Figure 6-13 shows the port diagram. Table 6-23 summarizes the selection of the pin functions.
PxSEL.y
PxDIR.y
0
1
Direction
0: Input
1: Output
PxSEL2.y
PxSEL.y
PxREN.y
0
1
1
PxSEL2.y
PxSEL.y
0
1
DVSS
DVCC
PxOUT.y
0
1
1
0
1
From Module
2
P3.0/TA0.2
P3.1/TA1.0
P3.2/TA1.1
P3.3/TA1.2
P3.4/TA0.0
P3.5/TA0.1
P3.6/TA0.2
P3.7/TA1CLK/CAOUT
3
TAx.y
TAxCLK
PxIN.y
EN
D
To Module
Figure 6-13. Port P3 (P3.0 to P3.7) Diagram (RHB and PW28 Package Only)
62
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MSP430G2203
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MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Table 6-23. Port P3 (P3.0 to P3.7) Pin Functions (RHB and PW28 Package Only)
PIN NAME
(P3.x)
x
FUNCTION
P3.0/
P3.x (I/O)
TA0.2/
Timer0_A3.CCI2A
0
CONTROL BITS OR SIGNALS (1)
P3DIR.x
P3SEL.x
P3SEL2.x
I: 0; O: 1
0
0
0
1
0
Timer0_A3.TA2
1
1
0
Pin Osc
Capacitive sensing
X
0
1
P3.1/
P3.x (I/O)
I: 0; O: 1
0
0
TA1.0/
Timer1_A3.TA0
1
1
0
Pin Osc
1
Capacitive sensing
X
0
1
P3.2/
P3.x (I/O)
I: 0; O: 1
0
0
TA1.1/
Timer1_A3.TA1
1
1
0
Pin Osc
2
Capacitive sensing
X
0
1
P3.3/
P3.x (I/O)
I: 0; O: 1
0
0
1
1
0
TA1.2/
3
Timer1_A3.TA2
Pin Osc
Capacitive sensing
P3.4/
P3.x (I/O)
TA0.0/
4
Timer0_A3.TA0
Pin Osc
Capacitive sensing
P3.5/
P3.x (I/O)
TA0.1/
5
Timer0_A3.TA1
Pin Osc
Capacitive sensing
P3.6/
P3.x (I/O)
TA0.2/
6
Pin Osc
P3.7/
7
Pin Osc
(1)
0
1
0
0
1
1
0
X
0
1
I: 0; O: 1
0
0
1
1
0
X
0
1
I: 0; O: 1
0
0
Timer0_A3.TA2
1
1
0
Capacitive sensing
X
0
1
P3.x (I/O)
TA1CLK/
X
I: 0; O: 1
I: 0; O: 1
0
0
Timer1_A3.TACLK
0
1
0
Capacitive sensing
X
0
1
X = don't care
Detailed Description
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MSP430G2403, MSP430G2303, MSP430G2203
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www.ti.com
7 Device and Documentation Support
7.1
Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
7.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP430F5438A). TI recommends two of three possible
prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the electrical specifications for the
final device
PMS – Final silicon die that conforms to the electrical specifications for the device but has not completed
quality and reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI's internal qualification testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard
production devices. TI recommends that these devices not be used in any production system because
their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PZP) and temperature range (for example, T). Figure 7-1 provides a legend
for reading the complete device name for any family member.
64
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MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
SLAS734G – APRIL 2011 – REVISED APRIL 2016
MSP 430 F 5 438 A I ZQW T -EP
Processor Family
Optional: Additional Features
MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 = MSP430 low-power microcontroller platform
MCU Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Series
1 Series = Up to 8 MHz
2 Series = Up to 16 MHz
3 Series = Legacy
4 Series = Up to 16 MHz with LCD
Feature Set
Various Levels of Integration Within a Series
Optional: A = Revision
N/A
Specialized Application
AFE = Analog Front End
BT = Preprogrammed with Bluetooth
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
5 Series = Up to 25 MHz
6 Series = Up to 25 MHz with LCD
0 = Low-Voltage Series
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel
R = Large Reel
No Markings = Tube or Tray
Optional: Additional Features -EP = Enhanced Product (–40°C to 105°C)
-HT = Extreme Temperature Parts (–55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 7-1. Device Nomenclature
Device and Documentation Support
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65
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MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
7.3
www.ti.com
Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at MSP Tools.
Table 7-1 lists the debug features of these devices. See the Code Composer Studio for MSP430 User's
Guide (SLAU157) for details on the available features.
Table 7-1. Hardware Features
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMx.5
DEBUGGING
SUPPORT
MSP430
Yes
Yes
2
No
Yes
No
No
No
Design Kits and Evaluation Modules
28-Pin Target Development Board and MSP-FET USB Programmer Bundle for MSP430F2x and
MSP430G2x MCUs The MSP-FET430U28A kit includes all of the hardware and software
required to quickly begin application development on the MSP430 MCU. This kit includes a
ZIF socket target board (MSP-TS430PW28A) that accepts some MSP430 devices in 20- or
28-pin TSSOP packages (TI Package Code: PW). It is also bundled with a USB flash
emulation tool (MSP-FET) that interfaces the target board to a PC, allowing developers to
program and debug their MSP430 devices through in-system emulation through the JTAG
interface or the pin-saving Spy Bi-Wire (2-wire JTAG) protocol.
MSP430 LaunchPad™ Value Line Development Kit The MSP-EXP430G2 LaunchPad Development Kit
is an easy-to-use microcontroller development board for the low-power and low-cost
MSP430G2x MCUs. It has on-board emulation for programming and debugging and features
a 14- or 20-pin DIP socket, on-board buttons and LEDs and BoosterPack Plug-in Module
pinouts that support a wide range of modules for added functionality such as wireless,
displays, and more.
MSP430 Capacitive Touch BoosterPack™ Plug-in Module The Capacitive Touch BoosterPack
(430BOOST-SENSE1) is a plug-in module for MCU LaunchPad Development Kits. This
BoosterPack also includes a preprogrammed MSP430G2452IN20 Value Line device for the
MSP-EXP430G2 LaunchPad. Developers can use this BoosterPack as a solution for adding
capacitive touch differentiation in many applications such as consumer electronics, point of
sales machines, and other devices with a physical button.
Software
MSP430G2x53, MSP430G2x33, MSP430G2x13, MSP430G2x03 Code Examples C Code examples are
available for every MSP device that configures each of the integrated peripherals for various
application needs.
MSPWare™ Software MSPWare software is a collection of code examples, data sheets, and other
design resources for all MSP devices delivered in a convenient package. In addition to
providing a complete collection of existing MSP design resources, MSPWare software also
includes a high-level API called MSP Driver Library. This library makes it easy to program
MSP hardware. MSPWare software is available as a component of CCS or as a stand-alone
package.
MSP Driver Library Driver Library's abstracted API keeps you above the bits and bytes of the MSP430
hardware by providing easy-to-use function calls. Thorough documentation is delivered
through a helpful API Guide, which includes details on each function call and the recognized
parameters. Developers can use Driver Library functions to write complete projects with
minimal overhead.
66
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MSP430G2403, MSP430G2303, MSP430G2203
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SLAS734G – APRIL 2011 – REVISED APRIL 2016
Capacitive Touch Software Library Free C libraries for enabling capacitive touch capabilities on
MSP430 MCUs and MSP432 MCUs. The MSP430 MCU version of the library features
several capacitive touch implementations including the RO and RC method.
MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the application’s energy profile and
helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more
efficient code to fully utilize the unique ultra-low power features of MSP and MSP432
microcontrollers. Aimed at both experienced and new microcontroller developers, ULP
Advisor checks your code against a thorough ULP checklist to squeeze every last nano amp
out of your application. At build time, ULP Advisor will provide notifications and remarks to
highlight areas of your code that can be further optimized for lower power.
IEC60730 Software Package The IEC60730 MSP430 software package was developed to be useful in
assisting customers in complying with IEC 60730-1:2010 (Automatic Electrical Controls for
Household and Similar Use – Part 1: General Requirements) for up to Class B products,
which includes home appliances, arc detectors, power converters, power tools, e-bikes, and
many others. The IEC60730 MSP430 software package can be embedded in customer
applications running on MSP430s to help simplify the customer’s certification efforts of
functional safety-compliant consumer devices to IEC 60730-1:2010 Class B.
Fixed-Point Math Library for MSP The MSP IQmath and Qmath Libraries are a collection of highly
optimized and high-precision mathematical functions for C programmers to seamlessly port a
floating-point algorithm into fixed-point code on MSP430 and MSP432 devices. These
routines are typically used in computationally intensive real-time applications where optimal
execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and
Qmath libraries, it is possible to achieve execution speeds considerably faster and energy
consumption considerably lower than equivalent code written using floating-point math.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code
Composer Studio is an integrated development environment (IDE) that supports all MSP
microcontroller devices. Code Composer Studio comprises a suite of embedded software
utilities used to develop and debug embedded applications. It includes an optimizing C/C++
compiler, source code editor, project build environment, debugger, profiler, and many other
features. The intuitive IDE provides a single user interface taking you through each step of
the application development flow. Familiar utilities and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse
software framework with advanced embedded debug capabilities from TI resulting in a
compelling feature-rich development environment for embedded developers. When using
CCS with an MSP MCU, a unique and powerful set of plugins and embedded software
utilities are made available to fully leverage the MSP microcontroller.
Grace – Graphical Peripheral Configuration Tool Enable and configure ADCs, DACs, timers, clocks,
serial communication interfaces, and more, by interacting with buttons, drop-down menus,
and text fields. Navigate through the MSP430 MCUs highly integrated peripheral set with
ease.
MSP Flasher - Command Line Programmer MSP Flasher is an open-source shell-based interface for
programming MSP microcontrollers through a FET programmer or eZ430 using JTAG or
Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary files (.txt or .hex) files
directly to the MSP microcontroller without an IDE.
Device and Documentation Support
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www.ti.com
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which allows users to quickly begin application development on MSP
low-power microcontrollers (MCU). Creating MCU software usually requires downloading the
resulting binary program to the MSP device for validation and debugging. The MSP-FET
provides a debug communication pathway between a host computer and the target MSP.
Furthermore, the MSP-FET also provides a Backchannel UART connection between the
computer's USB interface and the MSP UART. This affords the MSP programmer a
convenient method for communicating serially between the MSP and a terminal running on
the computer. It also supports loading programs (often called firmware) to the MSP target
using the BSL (bootloader) through the UART and I2C communication protocols.
MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 or MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 Flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that allow
the user to fully customize the process. The MSP Gang Programmer is provided with an
expansion board, called the Gang Splitter, that implements the interconnections between the
MSP Gang Programmer and multiple target devices. Eight cables are provided that connect
the expansion board to eight target devices (through JTAG or Spy-Bi-Wire connectors). The
programming can be done with a PC or as a stand-alone device. A PC-side graphical user
interface is also available and is DLL-based.
7.4
Documentation Support
The following documents describe the MSP430G2x33 and MSP430G2x03 devices. Copies of these
documents are available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (for example, MSP430G2533). In the upper right corner, click the "Alert me" button.
This registers you to receive a weekly digest of product information that has changed (if any). For change
details, check the revision history of any revised document.
Errata
MSP430G2533 Device Erratasheet Describes the known exceptions to the functional specifications for
the MSP430G2533 device.
MSP430G2433 Device Erratasheet Describes the known exceptions to the functional specifications for
the MSP430G2433 device.
MSP430G2333 Device Erratasheet Describes the known exceptions to the functional specifications for
the MSP430G2333 device.
MSP430G2233 Device Erratasheet Describes the known exceptions to the functional specifications for
the MSP430G2233 device.
MSP430G2403 Device Erratasheet Describes the known exceptions to the functional specifications for
the MSP430G2403 device.
MSP430G2303 Device Erratasheet Describes the known exceptions to the functional specifications for
the MSP430G2303 device.
MSP430G2203 Device Erratasheet Describes the known exceptions to the functional specifications for
the MSP430G2203 device.
68
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MSP430G2203
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
SLAS734G – APRIL 2011 – REVISED APRIL 2016
User's Guides
MSP430x2xx Family User's Guide Detailed information on the modules and peripherals available in this
device family.
Code Composer Studio v6.1 for MSP430 User's Guide This manual describes the use of TI Code
Composer Studio IDE v6.1 (CCS v6.1) with the MSP430 ultra-low-power microcontrollers.
This document applies only for the Windows version of the Code Composer Studio IDE. The
Linux version is similar and, therefore, is not described separately.
IAR Embedded Workbench Version 3+ for MSP430 User's Guide This manual describes the use of
IAR Embedded Workbench (EW430) with the MSP430 ultra-low-power microcontrollers.
MSP430 Programming With the Bootloader (BSL) The MSP430 bootloader (BSL, formerly known as
the bootstrap loader) allows users to communicate with embedded memory in the MSP430
microcontroller during the prototyping phase, final production, and in service. Both the
programmable memory (flash memory) and the data memory (RAM) can be modified as
required. Do not confuse the bootloader with the bootstrap loader programs found in some
digital signal processors (DSPs) that automatically load program code (and data) from
external memory to the internal memory of the DSP.
MSP430 Programming Via the JTAG Interface This document describes the functions that are required
to erase, program, and verify the memory module of the MSP430 flash-based and FRAMbased microcontroller families using the JTAG communication port. In addition, it describes
how to program the JTAG access security fuse that is available on all MSP430 devices. This
document describes device access using both the standard 4-wire JTAG interface and the 2wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide This manual describes the hardware of the TI MSP-FET430
Flash Emulation Tool (FET). The FET is the program development tool for the MSP430 ultralow-power microcontroller. Both available interface types, the parallel port interface and the
USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators Selection of the right crystal, correct load circuit, and proper board
layout are important for a stable crystal oscillator. This application report summarizes crystal
oscillator function and explains the parameters to select the correct crystal for MSP430 ultralow-power operation. In addition, hints and examples for correct board layout are given. The
document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations System-Level ESD has become increasingly demanding
with silicon technology scaling towards lower voltages and the need for designing costeffective and ultra-low-power components. This application report addresses three different
ESD topics to help board designers and OEMs understand and design robust system-level
designs: (1) Component-level ESD testing and system-level ESD testing, their differences
and why component-level ESD rating does not ensure system-level robustness. (2) General
design guidelines for system-level ESD protection at different levels including enclosures,
cables, PCB layout, and on-board ESD protection devices. (3) Introduction to System
Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip ESD
protection to achieve system-level ESD robustness, with example simulations and test
results. A few real-world system-level ESD protection design examples and their results are
also discussed.
Device and Documentation Support
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MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
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SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
General Oversampling of MSP ADCs for Higher Resolution
Multiple
MSP
ultra-low-power
microcontrollers offer analog-to-digital converters (ADCs) to convert physical quantities into
digital numbers, a function that is widely used across numerous applications. There are
times, however, when a customer design demands a higher resolution than the ADC of the
selected MSP can offer. This application report, which is based on the previously-published
Oversampling the ADC12 for Higher Resolution (SLAA323), therefore describes how an
oversampling method can be incorporated to increase ADC resolution past the currently
available number of bits.
Capacitive Touch Hardware Design Guide Capacitive touch detection is sometimes considered more
art than science. This often results in multiple design iterations before the optimum
performance is achieved. There are, however, good design practices for circuit layout and
principles of materials that need to be understood to keep the number of iterations to a
minimum. This design guide describes a process for creating and designing capacitive touch
solutions, starting with the schematic, working through the mechanicals, and finally designing
the electrodes for the application.
Capacitive Touch Sensing, MSP430 Slider and Wheel Tuning Guide This application report provides
guidelines on how to tune capacitive touch sliders and wheels running on the MSP430™
microcontrollers. It identifies the hardware and software parameters as well as explains the
steps used in tuning sliders and wheels. The slider and wheel tuning is based on the APIs
defined in the Capacitive Touch Sense Library (CAPSENSELIBRARY).
Capacitive Touch Sensing, MSP430 Button Gate Time Optimization and Tuning Guide
MSP430™
microcontroller based capacitive touch buttons can offer increased performance when
properly optimized and tuned for their specific application. Performance benefits that result
from button optimization can include, but are not limited to, decreased power consumption,
improved response time, and the ability to grow a design to include more buttons. This
application report provides the reader with a starting point for button design at the system
and software level.
7.5
Related Links
Table 7-2 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7-2. Related Links
70
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430G2533
Click here
Click here
Click here
Click here
Click here
MSP430G2433
Click here
Click here
Click here
Click here
Click here
MSP430G2333
Click here
Click here
Click here
Click here
Click here
MSP430G2233
Click here
Click here
Click here
Click here
Click here
MSP430G2403
Click here
Click here
Click here
Click here
Click here
MSP430G2303
Click here
Click here
Click here
Click here
Click here
MSP430G2203
Click here
Click here
Click here
Click here
Click here
Device and Documentation Support
Copyright © 2011–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
www.ti.com
7.6
SLAS734G – APRIL 2011 – REVISED APRIL 2016
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
7.7
Trademarks
MSP430, LaunchPad, BoosterPack, MSPWare, EnergyTrace, ULP Advisor, Code Composer Studio, E2E
are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
7.8
Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
7.9
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
Copyright © 2011–2016, Texas Instruments Incorporated
71
MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233
MSP430G2403, MSP430G2303, MSP430G2203
SLAS734G – APRIL 2011 – REVISED APRIL 2016
www.ti.com
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
72
Mechanical, Packaging, and Orderable Information
Copyright © 2011–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303
MSP430G2203
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430G2203IN20
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430G2203
MSP430G2203IPW20
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2203
MSP430G2203IPW20R
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2203
MSP430G2203IPW28
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2203
MSP430G2203IPW28R
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2203
MSP430G2203IRHB32R
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
G2203
MSP430G2233IN20
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430G2233
MSP430G2233IPW20
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2233
MSP430G2233IPW20R
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2233
MSP430G2233IPW28
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2233
MSP430G2233IPW28R
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2233
MSP430G2233IRHB32R
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
G2233
MSP430G2233IRHB32T
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
G2233
MSP430G2303IPW20
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2303
MSP430G2303IPW20R
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2303
MSP430G2303IPW28
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2303
MSP430G2303IPW28R
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2303
MSP430G2303IRHB32R
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
G2303
MSP430G2303IRHB32T
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
G2303
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Sep-2021
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430G2333IN20
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430G2333
MSP430G2333IPW20
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2333
MSP430G2333IPW20R
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2333
MSP430G2333IPW28
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2333
MSP430G2333IPW28R
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2333
MSP430G2333IRHB32R
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
G2333
MSP430G2333IRHB32T
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
G2333
MSP430G2403IN20
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430G2403
MSP430G2403IPW20
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2403
MSP430G2403IPW20R
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2403
MSP430G2403IPW28
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2403
MSP430G2403IPW28R
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2403
MSP430G2403IRHB32R
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
G2403
MSP430G2403IRHB32T
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
G2403
MSP430G2433IN20
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430G2433
MSP430G2433IPW20
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2433
MSP430G2433IPW20R
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2433
MSP430G2433IPW28
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2433
MSP430G2433IPW28R
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2433
MSP430G2433IRHB32R
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
G2433
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Sep-2021
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MSP430G2433IRHB32T
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
G2433
MSP430G2533IN20
ACTIVE
PDIP
N
20
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
M430G2533
MSP430G2533IPW20
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2533
MSP430G2533IPW20R
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2533
MSP430G2533IPW28
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2533
MSP430G2533IPW28R
ACTIVE
TSSOP
PW
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
430G2533
MSP430G2533IRHB32R
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
G2533
MSP430G2533IRHB32T
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
MSP430
G2533
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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