MSP432E401YTPDTR

Product Folder Order Now Technical Documents Tools & Software Support & Community MSP432E401Y SLASEN5 – OCTOBER 2017 MSP432E401Y SimpleLink™ Ethernet Microcontroller 1 Device Overview 1.1 Features 1 • Core – 120-MHz Arm® Cortex®-M4F Processor Core With Floating-Point Unit (FPU) • Connectivity – Ethernet MAC: 10/100 Ethernet MAC With Integrated Ethernet PHY – Ethernet PHY: PHY With IEEE 1588 PTP Hardware Support – Universal Serial Bus (USB): USB 2.0 OTG, Host, or Device With ULPI Interface Option and Link Power Management (LPM) – Eight Universal Asynchronous Receivers/Transmitters (UARTs), Each With Independently Clocked Transmitter and Receiver – Four Quad Synchronous Serial Interface (QSSI): With Bi-, Quad-, and Advanced-SSI Support – Ten Inter-Integrated Circuit (I2C) Modules With High-Speed Mode Support – Two CAN 2.0 A and B Controllers: Multicast Shared Serial-Bus Standard • Memories – 1024KB of Flash Memory With 4-Bank Configuration Supports an Independent Code Protection for Each Bank – 256KB of SRAM With Single-Cycle Access, Provides Nearly 2-GB/s Memory Bandwidth at 120-MHz Clock Frequency – 6KB EEPROM: 500-kwrite per 2 Page Block, Leveling, Lock Protection – Internal ROM: Loaded With SimpleLink™ SDK Software – Peripheral Driver Library – Bootloader – External Peripheral Interface (EPI): 8-, 16-, or 32-Bit Dedicated Parallel Interface to Access External Devices and Memory (SDRAM, Flash, or SRAM) • Security – Advanced Encryption Standard (AES): Hardware Accelerated Data Encryption and Decryption Based on 128-, 192-, and 256-Bit Keys – Data Encryption Standard (DES): Hardware Accelerated Data Encryption and Decryption Supported by Block Cipher Implementation With 168-Bit Effective Key Length – Secure Hash Algorithm/Message Digest Algorithm (SHA/MD5): Advanced Hash Engine That Supports SHA-1, SHA-2, and MD5 Hash Computation – Cyclical Redundancy Check (CRC) Hardware – Tamper: Support for Four Tamper Inputs and Configurable Tamper Event Response • Analog – Two 12-Bit SAR-Based ADC Modules, Each Supports Up to 2 Million Samples per Second (2 Msps) – Three Independent Analog Comparator Controllers – 16 Digital Comparators • System Management – JTAG and Serial Wire Debug (SWD): One JTAG Module With Integrated Arm SWD Provides a Means of Accessing and Controlling Design-forTest Features Such as I/O Pin Observation and Control, Scan Testing, and Debugging. • Development Kits and Software (See Tools and Software) – SimpleLink™ MSP-EXP432E401Y LaunchPad™ Development Kit – SimpleLink MSP432E4 Software Development Kit (SDK) • Package Information – Package: 128-Pin TQFP (PDT) – Extended Operating Temperature (Ambient) Range: –40°C to 105°C 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. MSP432E401Y SLASEN5 – OCTOBER 2017 1.2 • • • • • • www.ti.com Applications Industrial Ethernet Gateway Industrial Smart Gateway Zone Controllers for Building Automation Factory Automation Data Collectors and Gateway Data Concentrators for Grid Infrastructure Wireless to Ethernet Gateway 1.3 Description The SimpleLink MSP432E401Y Arm® Cortex®-M4F microcontrollers provide top performance and advanced integration. The product family is positioned for cost-effective applications requiring significant control processing and connectivity capabilities. The MSP432E401Y microcontrollers integrate a large variety of rich communication features to enable a new class of highly connected designs with the ability to allow critical real-time control between performance and power. The microcontrollers feature integrated communication peripherals along with other high-performance analog and digital functions to offer a strong foundation for many different target uses, spanning from human-machine interface (HMI) to networked system management controllers. In addition, the MSP432E401Y microcontrollers offer the advantages of widely available development tools, system-on-chip (SoC) infrastructure, and a large user community for Arm-based microcontrollers. Additionally, these microcontrollers use the Arm Thumb®-compatible Thumb-2® instruction set to reduce memory requirements and, thereby, cost. When using the SimpleLink MSP432™ SDK, the MSP432E401Y microcontroller is code compatible with all members of the extensive SimpleLink family, providing flexibility to fit precise needs. The MSP432E401Y device is part of the SimpleLink microcontroller (MCU) platform, which consists of WiFi®, Bluetooth® low energy, Sub-1 GHz, Ethernet, Zigbee, Thread, and host MCUs, which all share a common, easy-to-use development environment with a single core software development kit (SDK) and rich tool set. A one-time integration of the SimpleLink platform enables you to add any combination of the portfolio's devices into your design, allowing 100 percent code reuse when your design requirements change. For more information, visit www.ti.com/simplelink. Device Information (1) PART NUMBER MSP432E401YTPDT (1) 2 PACKAGE BODY SIZE TQFP (128) 14 mm × 14 mm For more information, see Section 9, Mechanical, Packaging, and Orderable Information. Device Overview Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com 1.4 SLASEN5 – OCTOBER 2017 Functional Block Diagram Figure 1-1 shows the functional block diagram. JTAG, SWD Arm Cortex-M4F ROM (120 MHz) System Control and Clocks (with Precision Oscillator) ETM FPU Flash Bootloader DriverLib AES and CRC Ethernet Bootloater DCode bus (1024KB) NVIC MPU ICode bus System Bus Bus Matrix SRAM (256KB) SYSTEM PERIPHERALS DMA Watchdog Timer (2 Units) EEPROM (6K) Hibernation Module GPIOs (90) GeneralPurpose Timer (8 Units) CRC Module External Peripheral Interface DES Module AES Module SSI (4 Units) Ethernet MAC, PHY, MII SHA/MD5 Module Advanced Peripheral Bus (APB) USB OTG (FS PHY or ULPI) Advanced High-Performance Bus (AHB) Tamper SERIAL PERIPHERALS UART (8 Units) I2C (10 Units) CAN Controller (2 Units) ANALOG PERIPHERALS Analog Comparator (3 Units) 12-Bit ADC (2 Units, 20 Channels) MOTION CONTROL PERIPHERALS PWM (1 Unit, 8 Signals) QEI (1 Unit) Copyright © 2017, Texas Instruments Incorporated Figure 1-1. MSP432E401Y Functional Block Diagram Device Overview Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 3 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table of Contents 1 2 3 Device Overview ......................................... 1 5.11 Peripheral Current Consumption .................... 41 1.1 Features .............................................. 1 5.12 LDO Regulator Characteristics...................... 41 1.2 Applications ........................................... 2 1.3 Description ............................................ 2 5.13 5.14 1.4 Functional Block Diagram ............................ 3 Power Dissipation ................................... 42 Thermal Resistance Characteristics, 128-Pin PDT (TQFP) Package .................................... 42 5.15 Timing and Switching Characteristics ............... 43 Revision History ......................................... 5 Device Characteristics .................................. 6 Overview Terminal Configuration and Functions .............. 8 6.2 Functional Block Diagram ........................... 95 .......................................... 8 4.2 Pin Attributes ......................................... 9 4.3 Signal Descriptions .................................. 19 4.4 GPIO Pin Multiplexing ............................... 30 4.5 Buffer Type .......................................... 33 4.6 Connections for Unused Pins ....................... 33 Specifications ........................................... 35 5.1 Absolute Maximum Ratings ......................... 35 5.2 ESD Ratings ........................................ 35 5.3 Recommended Operating Conditions ............... 35 5.4 Recommended DC Operating Conditions .......... 35 5.5 Recommended GPIO Operating Characteristics ... 35 6.3 Arm Cortex-M4F Processor Core ................... 96 6.4 On-Chip Memory ................................... 100 6.5 Peripherals ......................................... 102 6.6 Identification........................................ 144 6.7 Boot Modes ........................................ 144 Pin Diagram 5.6 .......................... 5.8 GPIO Current Restrictions 5.9 I/O Reliability ........................................ 37 5.10 Current Consumption ............................... Applications, Implementation, and Layout ...... 146 8 Device and Documentation Support .............. 147 7.1 37 38 94 7 Recommended Fast GPIO Pad Operating Conditions ........................................... 36 Recommended Slow GPIO Pad Operating Conditions ........................................... 36 5.7 4 ............................................ 6.1 4.1 5 Detailed Description ................................... 94 Related Products ..................................... 7 3.1 4 6 9 System Design Guidelines ......................... 146 ................... 8.1 Getting Started and Next Steps 8.2 Device Nomenclature .............................. 147 8.3 Tools and Software ................................ 149 8.4 Documentation Support ............................ 150 8.5 Community Resources............................. 151 8.6 Trademarks ........................................ 151 8.7 Electrostatic Discharge Caution 8.8 Export Control Notice .............................. 151 8.9 Glossary............................................ 151 ................... 147 151 Mechanical, Packaging, and Orderable Information ............................................. 152 Table of Contents Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES October 2017 * Initial Release Revision History Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 5 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com 3 Device Characteristics Table 3-1 lists the characteristics of the MSP432E401Y MCU. Table 3-1. Device Characteristics Feature Description Performance Core Arm Cortex-M4F processor core Performance 120-MHz operation, 150-DMIPS performance Flash 1024KB of flash memory System SRAM 256KB of single-cycle system SRAM EEPROM 6KB of EEPROM Internal ROM Internal ROM loaded with SimpleLink SDK software External Peripheral Interface (EPI) 8-, 16-, or 32-bit dedicated interface for peripherals and memory Security Cyclical Redundancy Check (CRC) 16- or 32-bit hash function that supports four CRC forms Advanced Encryption Standard (AES) Hardware accelerated data encryption and decryption based on 128-, 192-, and 256-bit keys Data Encryption Standard (DES) Block cipher implementation with 168-bit effective key length Hardware Accelerated Hash (SHA/MD5) Advanced hash engine that supports SHA-1, SHA-2, or MD5 hash computation Tamper Support for four tamper inputs and configurable tamper event response Communication Interfaces Universal Asynchronous Receiver/Transmitter (UART) Eight UARTs Quad Synchronous Serial Interface (QSSI) Four SSI modules with bi-, quad-, and advanced-SSI support 2 Inter-Integrated Circuit (I C) Ten I2C modules with four transmission speeds including high-speed mode Controller Area Network (CAN) Two CAN 2.0 A/B controllers Ethernet MAC 10/100 Ethernet MAC Ethernet PHY PHY with IEEE 1588 PTP hardware support Universal Serial Bus (USB) USB 2.0 OTG, Host, and Device with ULPI interface option and Link Power Management (LPM) support System Integration Micro Direct Memory Access (µDMA) Arm PrimeCell® 32-channel configurable µDMA controller General-Purpose Timer (GPTM) Eight 16- or 32-bit GPTM blocks Watchdog Timer (WDT) Two watchdog timers Hibernation Module (HIB) Low-power battery-backed Hibernation module General-Purpose Input/Output (GPIO) 15 physical GPIO blocks Advanced Motion Control Pulse Width Modulator (PWM) One PWM module, with four PWM generator blocks and a control block, for a total of 8 PWM outputs Quadrature Encoder Interface (QEI) One QEI module Analog Support Analog-to-Digital Converter (ADC) Two 12-bit ADC modules, each with a maximum sample rate of 2 Msps Analog Comparator Controller Three independent integrated analog comparators Digital Comparator 16 digital comparators System Management JTAG and Serial Wire Debug (SWD) One JTAG module with integrated Arm SWD Package Information Package 128-pin TQFP (PDT) Operating Range (Ambient) Extended temperature range (–40°C to 105°C) 6 Device Characteristics Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com 3.1 SLASEN5 – OCTOBER 2017 Related Products For information about other devices in this family of products or related products, see the following links. Products for TI Microcontrollers connectivity options. Low-power and high-performance MCUs, with wired and wireless Products for SimpleLink MSP432 MCUs SimpleLink MSP432 MCUs with an ultra-low-power Arm Cortex-M4 core are optimized for Internet-of-Things sensor node applications. With an integrated ADC, the family enables acquisition and processing of high-precision signals without sacrificing power and is an optimal host MCU for TI's SimpleLink wireless connectivity solutions. Companion Products for MSP432E401Y Review products that are frequently purchased or used with this product. Reference Designs The TI Designs Reference Design Library is a robust reference design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Device Characteristics Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 7 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagram Figure 4-1 shows the pinout of the 128-pin TQFP (PDT) package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PB1 PB0 PL6 PL7 PB3 PB2 VDD OSC1 OSC0 VDDC PL5 PL4 PL3 PL2 PL1 PL0 GND VDD PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 RST VDD VBAT XOSC1 XOSC0 HIB PA0 PA1 PA2 PA3 PA4 PA5 VDD PA6 PA7 PF0 PF1 PF2 PF3 PF4 VDD GND PG0 PG1 VDD VDD EN0RXIN EN0RXIP GND EN0TXON EN0TXOP GND RBIAS PK7 PK6 PK5 PK4 WAKE 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PD0 PD1 PD2 PD3 PQ0 PQ1 VDD VDDA VREFA+ GNDA PQ2 PE3 PE2 PE1 PE0 VDD GND PK0 PK1 PK2 PK3 PC7 PC6 PC5 PC4 VDD PQ3 VDD PH0 PH1 PH2 PH3 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 PD7 PD6 PD5 PD4 PE5 PE4 VDD PB4 PB5 PP1 PP0 PJ1 PJ0 VDDC GND VDD PN5 PN4 PN3 PN2 PN1 PN0 PP5 PP4 PP3 PP2 PQ4 VDD PC0/TCK/SWCLK PC1/TMS/SWDIO PC2/TDI PC3/TDO/SWO Each GPIO signal is identified by its GPIO port unless it defaults to an alternate function on reset. In this case, the GPIO port name is followed by the default alternate function. For a complete list of functions for each pin, see Table 4-2. Figure 4-1. 128-Pin PDT Package (Top View) 8 Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com 4.2 SLASEN5 – OCTOBER 2017 Pin Attributes Table 4-1 lists GPIO pins with special considerations. Most GPIO pins are configured as GPIOs and are high-impedance by default (GPIOAFSEL = 0, GPIODEN = 0, GPIOPDR = 0, GPIOPUR = 0, and GPIOPCTL = 0). Special consideration pins may be programed to a non-GPIO function or may have special commit controls out of reset. In addition, a POR returns these GPIOs to their original special consideration state. Table 4-1. GPIO Pins With Special Considerations (1) GPIO PINS DEFAULT RESET STATE GPIOAFSEL GPIODEN GPIOPDR GPIOPUR GPIOPCTL GPIOCR PC[3:0] JTAG/SWD 1 1 0 1 0x1 0 PD[7] GPIO (1) 0 0 0 0 0x0 0 PE[7] GPIO (1) 0 0 0 0 0x0 0 This pin is configured as a GPIO by default but is locked and can only be reprogrammed by unlocking the pin in the GPIOLOCK register and uncommitting it by setting the GPIOCR register. Table 4-2 describes the pin attributes. Table 4-2. Pin Attributes BUFFER TYPE (2) I/O LVCMOS – OFF I Analog PD0 N/A C0o O LVCMOS PD0 (5) I2C7SCL I/O LVCMOS PD0 (2) SSI2XDAT1 I/O LVCMOS PD0 (15) T0CCP0 I/O LVCMOS PD0 (3) N/A PD1 I/O LVCMOS – OFF I Analog PD1 N/A C1o O LVCMOS PD1 (5) I2C7SDA I/O LVCMOS PD1 (2) SSI2XDAT0 I/O LVCMOS PD1 (15) N/A T0CCP1 I/O LVCMOS PD1 (3) N/A PD2 SIGNAL NAME PD0 AIN15 1 AIN14 2 3 5 (1) (2) (3) (4) POWER SOURCE (3) VDD N/A N/A N/A VDD N/A N/A I/O LVCMOS – OFF AIN13 I Analog PD2 N/A C2o O LVCMOS PD2 (5) I2C8SCL I/O LVCMOS PD2 (2) SSI2Fss I/O LVCMOS PD2 (15) N/A T1CCP0 I/O LVCMOS PD2 (3) N/A PD3 I/O LVCMOS – OFF I Analog PD3 I2C8SDA I/O LVCMOS PD3 (2) SSI2Clk I/O LVCMOS PD3 (15) T1CCP1 I/O LVCMOS PD3 (3) N/A PQ0 I/O LVCMOS – OFF EPI0S20 I/O LVCMOS PQ0 (15) SSI3Clk I/O LVCMOS PQ0 (14) AIN12 4 PIN MUX ENCODING STATE AFTER RESET RELEASE (4) SIGNAL TYPE (1) PIN NUMBER VDD N/A N/A N/A VDD N/A N/A VDD N/A N/A Signal Types: I = Input, O = Output, I/O = Input or Output. For details on buffer types, see Table 4-5. N/A = Not applicable State after reset release: PU = High impedance with an active pullup resistor, OFF = High impedance, N/A = not applicable Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 9 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 4-2. Pin Attributes (continued) SIGNAL TYPE (1) BUFFER TYPE (2) PQ1 I/O LVCMOS – EPI0S21 I/O LVCMOS PQ1 (15) SSI3Fss PIN NUMBER 6 SIGNAL NAME POWER SOURCE (3) STATE AFTER RESET RELEASE (4) OFF VDD N/A I/O LVCMOS PQ1 (14) 7 VDD – Power Fixed N/A N/A 8 VDDA – Power Fixed N/A N/A 9 VREFA+ – Analog Fixed N/A N/A 10 GNDA N/A N/A – Power Fixed PQ2 I/O LVCMOS – EPI0S22 I/O LVCMOS PQ2 (15) SSI3XDAT0 I/O LVCMOS PQ2 (14) N/A PE3 I/O LVCMOS – OFF AIN0 I Analog PE3 U1DTR O LVCMOS PE3 (1) N/A PE2 I/O LVCMOS – OFF AIN1 I Analog PE2 U1DCD I LVCMOS PE2 (1) PE1 I/O LVCMOS – AIN2 I Analog PE1 U1DSR I LVCMOS PE1 (1) PE0 I/O LVCMOS – AIN3 I Analog PE0 U1RTS O LVCMOS PE0 (1) 16 VDD – Power Fixed N/A 17 GND – Power Fixed N/A PK0 I/O LVCMOS – I Analog PK0 I/O LVCMOS PK0 (15) I LVCMOS PK0 (1) N/A I/O LVCMOS – OFF 11 12 13 14 15 18 AIN16 EPI0S0 U4Rx PK1 19 20 21 AIN17 22 N/A OFF VDD VDD VDD N/A N/A N/A N/A OFF VDD N/A N/A OFF VDD N/A N/A N/A N/A OFF VDD N/A N/A I Analog PK1 EPI0S1 I/O LVCMOS PK1 (15) U4Tx O LVCMOS PK1 (1) N/A PK2 I/O LVCMOS – OFF I Analog PK2 EPI0S2 I/O LVCMOS PK2 (15) U4RTS O LVCMOS PK2 (1) N/A PK3 I/O LVCMOS – OFF I Analog PK3 I/O LVCMOS PK3 (15) AIN18 AIN19 EPI0S3 U4CTS 10 PIN MUX ENCODING VDD VDD VDD N/A N/A N/A N/A N/A N/A I LVCMOS PK3 (1) N/A PC7 I/O LVCMOS – OFF C0- I Analog PC7 EPI0S4 I/O LVCMOS PC7 (15) U5Tx O LVCMOS PC7 (1) Terminal Configuration and Functions VDD N/A N/A N/A Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Table 4-2. Pin Attributes (continued) SIGNAL TYPE (1) BUFFER TYPE (2) PC6 I/O LVCMOS – C0+ I Analog PC6 PIN NUMBER 23 24 25 26 27 28 29 30 31 SIGNAL NAME EPI0S5 VDD N/A LVCMOS PC6 (15) LVCMOS PC6 (1) N/A PC5 I/O LVCMOS – OFF C1+ I Analog PC5 N/A EPI0S6 I/O LVCMOS PC5 (15) RTCCLK O LVCMOS PC5 (7) N/A U7Tx O LVCMOS PC5 (1) N/A PC4 I/O LVCMOS – OFF C1- I Analog PC4 I/O LVCMOS PC4 (15) U7Rx I LVCMOS PC4 (1) VDD – Power Fixed PQ3 I/O LVCMOS – EPI0S23 I/O LVCMOS PQ3 (15) SSI3XDAT1 EPI0S7 VDD VDD N/A N/A N/A N/A N/A N/A N/A OFF VDD N/A I/O LVCMOS PQ3 (14) VDD – Power Fixed PH0 I/O LVCMOS – EPI0S0 I/O LVCMOS PH0 (15) U0RTS O LVCMOS PH0 (1) N/A PH1 I/O LVCMOS – OFF EPI0S1 I/O LVCMOS PH1 (15) U0CTS I LVCMOS PH1 (1) N/A PH2 I/O LVCMOS – OFF EPI0S2 I/O LVCMOS PH2 (15) N/A N/A N/A OFF VDD VDD VDD N/A N/A N/A I LVCMOS PH2 (1) N/A PH3 I/O LVCMOS – OFF EPI0S3 I/O LVCMOS PH3 (15) VDD N/A I LVCMOS PH3 (1) N/A I/O LVCMOS – OFF CAN0Rx I LVCMOS PA0 (7) N/A I2C9SCL I/O LVCMOS PA0 (2) T0CCP0 I/O LVCMOS PA0 (3) I LVCMOS PA0 (1) N/A I/O LVCMOS – OFF CAN0Tx O LVCMOS PA1 (7) I2C9SDA I/O LVCMOS PA1 (2) T0CCP1 I/O LVCMOS PA1 (3) U0Tx O LVCMOS PA1 (1) N/A PA2 I/O LVCMOS – OFF I2C8SCL I/O LVCMOS PA2 (2) N/A SSI0Clk I/O LVCMOS PA2 (15) T1CCP0 I/O LVCMOS PA2 (3) N/A I LVCMOS PA2 (1) N/A U0Rx PA1 35 OFF I PA0 34 STATE AFTER RESET RELEASE (4) I/O U0DSR 33 POWER SOURCE (3) U5Rx U0DCD 32 PIN MUX ENCODING U4Rx VDD N/A N/A N/A VDD N/A N/A VDD N/A Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 11 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 4-2. Pin Attributes (continued) BUFFER TYPE (2) PA3 I/O LVCMOS – OFF I2C8SDA I/O LVCMOS PA3 (2) N/A 36 SSI0Fss I/O LVCMOS PA3 (15) T1CCP1 I/O LVCMOS PA3 (3) U4Tx O LVCMOS PA3 (1) N/A PA4 I/O LVCMOS – OFF 37 I2C7SCL I/O LVCMOS PA4 (2) SSI0XDAT0 I/O LVCMOS PA4 (15) T2CCP0 I/O LVCMOS PA4 (3) SIGNAL NAME U3Rx 38 39 40 42 43 44 12 POWER SOURCE (3) VDD N/A N/A N/A VDD N/A N/A I LVCMOS PA4 (1) N/A PA5 I/O LVCMOS – OFF I2C7SDA I/O LVCMOS PA5 (2) N/A SSI0XDAT1 I/O LVCMOS PA5 (15) T2CCP1 I/O LVCMOS PA5 (3) U3Tx O LVCMOS PA5 (1) VDD – Power Fixed PA6 I/O LVCMOS – OFF EPI0S8 I/O LVCMOS PA6 (15) N/A I2C6SCL I/O LVCMOS PA6 (2) N/A SSI0XDAT2 I/O LVCMOS PA6 (13) T3CCP0 I/O LVCMOS PA6 (3) N/A I LVCMOS PA6 (1) N/A USB0EPEN O LVCMOS PA6 (5) N/A PA7 I/O LVCMOS – OFF EPI0S9 I/O LVCMOS PA7 (15) N/A I2C6SDA I/O LVCMOS PA7 (2) N/A SSI0XDAT3 I/O LVCMOS PA7 (13) T3CCP1 I/O LVCMOS PA7 (3) U2Tx O LVCMOS PA7 (1) N/A USB0EPEN O LVCMOS PA7 (11) N/A USB0PFLT I LVCMOS PA7 (5) N/A PF0 I/O LVCMOS – OFF EN0LED0 O LVCMOS PF0 (5) M0PWM0 O LVCMOS PF0 (6) SSI3XDAT1 I/O LVCMOS PF0 (14) N/A TRD2 O LVCMOS PF0 (15) N/A PF1 I/O LVCMOS – OFF EN0LED2 O LVCMOS PF1 (5) M0PWM1 O LVCMOS PF1 (6) SSI3XDAT0 I/O LVCMOS PF1 (14) TRD1 O LVCMOS PF1 (15) N/A PF2 I/O LVCMOS – OFF M0PWM2 O LVCMOS PF2 (6) SSI3Fss I/O LVCMOS PF2 (14) TRD0 O LVCMOS PF2 (15) U2Rx 41 PIN MUX ENCODING STATE AFTER RESET RELEASE (4) SIGNAL TYPE (1) PIN NUMBER Terminal Configuration and Functions VDD N/A N/A N/A N/A VDD VDD N/A N/A N/A N/A N/A VDD N/A N/A VDD N/A N/A VDD N/A N/A N/A Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Table 4-2. Pin Attributes (continued) BUFFER TYPE (2) PF3 I/O LVCMOS – M0PWM3 O LVCMOS PF3 (6) SSI3Clk I/O LVCMOS PF3 (14) TRCLK O LVCMOS PF3 (15) N/A PF4 I/O LVCMOS – OFF EN0LED1 O LVCMOS PF4 (5) N/A M0FAULT0 I LVCMOS PF4 (6) SSI3XDAT2 I/O LVCMOS PF4 (14) N/A TRD3 O LVCMOS PF4 (15) N/A 47 VDD – Power Fixed N/A 48 GND – Power Fixed N/A PG0 I/O LVCMOS – EN0PPS O LVCMOS PG0 (5) EPI0S11 I/O LVCMOS PG0 (15) I2C1SCL I/O LVCMOS PG0 (2) N/A M0PWM4 O LVCMOS PG0 (6) N/A PG1 I/O LVCMOS – OFF EPI0S10 I/O LVCMOS PG1 (15) I2C1SDA I/O LVCMOS PG1 (2) 45 46 49 50 SIGNAL NAME PIN MUX ENCODING POWER SOURCE (3) STATE AFTER RESET RELEASE (4) SIGNAL TYPE (1) PIN NUMBER OFF VDD VDD N/A N/A N/A N/A N/A OFF N/A VDD VDD N/A N/A N/A M0PWM5 O LVCMOS PG1 (6) 51 VDD – Power Fixed N/A N/A 52 VDD – Power Fixed N/A N/A 53 EN0RXIN I/O LVCMOS Fixed VDD N/A 54 EN0RXIP I/O LVCMOS Fixed VDD N/A 55 GND – Power Fixed N/A N/A 56 EN0TXON I/O LVCMOS Fixed VDD N/A 57 EN0TXOP I/O LVCMOS Fixed VDD N/A 58 GND – Power Fixed N/A N/A 59 RBIAS O Analog Fixed VDD N/A PK7 I/O LVCMOS – OFF EPI0S24 I/O LVCMOS PK7 (15) N/A I2C4SDA I/O LVCMOS PK7 (2) M0FAULT2 I LVCMOS PK7 (6) RTCCLK O LVCMOS PK7 (5) U0RI I LVCMOS PK7 (1) N/A PK6 I/O LVCMOS – OFF EN0LED1 O LVCMOS PK6 (5) EPI0S25 I/O LVCMOS PK6 (15) I2C4SCL I/O LVCMOS PK6 (2) 60 61 M0FAULT1 62 N/A VDD N/A N/A N/A N/A VDD N/A N/A I LVCMOS PK6 (6) N/A PK5 I/O LVCMOS – OFF EN0LED2 O LVCMOS PK5 (5) N/A EPI0S31 I/O LVCMOS PK5 (15) I2C3SDA I/O LVCMOS PK5 (2) N/A M0PWM7 O LVCMOS PK5 (6) N/A VDD N/A Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 13 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 4-2. Pin Attributes (continued) BUFFER TYPE (2) PK4 I/O LVCMOS – OFF EN0LED0 O LVCMOS PK4 (5) N/A EPI0S32 I/O LVCMOS PK4 (15) I2C3SCL I/O LVCMOS PK4 (2) M0PWM6 O LVCMOS PK4 (6) 64 WAKE I LVCMOS Fixed VBAT N/A 65 HIB O LVCMOS Fixed VBAT N/A 66 XOSC0 I Analog Fixed VBAT N/A 67 XOSC1 O Analog Fixed VBAT N/A 68 VBAT – Power Fixed N/A N/A 69 VDD – Power Fixed N/A N/A 70 RST I LVCMOS Fixed VDD N/A PM7 I/O LVCMOS – T5CCP1 I/O LVCMOS PM7 (3) TMPR0 I/O LVCMOS PM7 U0RI I LVCMOS PM7 (1) N/A PM6 I/O LVCMOS – OFF T5CCP0 I/O LVCMOS PM6 (3) TMPR1 I/O LVCMOS PM6 63 71 72 SIGNAL NAME U0DSR 73 74 75 76 77 78 14 PIN MUX ENCODING POWER SOURCE (3) STATE AFTER RESET RELEASE (4) SIGNAL TYPE (1) PIN NUMBER VDD N/A N/A N/A OFF VDD VDD N/A N/A N/A N/A I LVCMOS PM6 (1) N/A PM5 I/O LVCMOS – OFF T4CCP1 I/O LVCMOS PM5 (3) TMPR2 I/O LVCMOS PM5 U0DCD I LVCMOS PM5 (1) N/A PM4 I/O LVCMOS – OFF T4CCP0 I/O LVCMOS PM4 (3) TMPR3 I/O LVCMOS PM4 U0CTS I LVCMOS PM4 (1) N/A PM3 I/O LVCMOS – OFF EPI0S12 I/O LVCMOS PM3 (15) T3CCP1 I/O LVCMOS PM3 (3) N/A PM2 I/O LVCMOS – OFF EPI0S13 I/O LVCMOS PM2 (15) T3CCP0 I/O LVCMOS PM2 (3) N/A PM1 I/O LVCMOS – OFF EPI0S14 I/O LVCMOS PM1 (15) T2CCP1 I/O LVCMOS PM1 (3) N/A PM0 I/O LVCMOS – OFF EPI0S15 I/O LVCMOS PM0 (15) T2CCP0 VDD VDD VDD VDD VDD VDD N/A N/A N/A N/A N/A N/A N/A N/A I/O LVCMOS PM0 (3) 79 VDD – Power Fixed N/A N/A 80 GND – Power Fixed N/A N/A Terminal Configuration and Functions N/A Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Table 4-2. Pin Attributes (continued) BUFFER TYPE (2) PL0 I/O LVCMOS – OFF EPI0S16 I/O LVCMOS PL0 (15) N/A 81 I2C2SDA I/O LVCMOS PL0 (2) I LVCMOS PL0 (6) USB0D0 I/O LVCMOS PL0 (14) N/A PL1 I/O LVCMOS – OFF EPI0S17 I/O LVCMOS PL1 (15) I2C2SCL I/O LVCMOS PL1 (2) I LVCMOS PL1 (6) USB0D1 I/O LVCMOS PL1 (14) N/A PL2 I/O LVCMOS – OFF C0o O LVCMOS PL2 (5) N/A EPI0S18 I/O LVCMOS PL2 (15) I LVCMOS PL2 (6) USB0D2 I/O LVCMOS PL2 (14) N/A PL3 I/O LVCMOS – OFF C1o O LVCMOS PL3 (5) EPI0S19 I/O LVCMOS PL3 (15) I LVCMOS PL3 (6) USB0D3 I/O LVCMOS PL3 (14) N/A PL4 I/O LVCMOS – OFF EPI0S26 I/O LVCMOS PL4 (15) T0CCP0 I/O LVCMOS PL4 (3) USB0D4 I/O LVCMOS PL4 (14) N/A PL5 I/O LVCMOS – OFF EPI0S33 I/O LVCMOS PL5 (15) T0CCP1 I/O LVCMOS PL5 (3) USB0D5 I/O LVCMOS PL5 (14) – Power Fixed N/A N/A SIGNAL NAME M0FAULT3 82 PhA0 83 PhB0 84 IDX0 85 86 PIN MUX ENCODING POWER SOURCE (3) STATE AFTER RESET RELEASE (4) SIGNAL TYPE (1) PIN NUMBER VDD N/A N/A N/A VDD N/A N/A VDD N/A N/A N/A VDD N/A N/A VDD VDD N/A N/A N/A N/A N/A 87 VDDC 88 OSC0 I Analog Fixed VDD N/A 89 OSC1 O Analog Fixed VDD N/A 90 VDD – Power Fixed N/A N/A PB2 I/O LVCMOS – EPI0S27 I/O LVCMOS PB2 (15) I2C0SCL I/O LVCMOS PB2 (2) T5CCP0 I/O LVCMOS PB2 (3) USB0STP O LVCMOS PB2 (14) N/A PB3 I/O LVCMOS – OFF EPI0S28 I/O LVCMOS PB3 (15) N/A I2C0SDA I/O LVCMOS PB3 (2) T5CCP1 I/O LVCMOS PB3 (3) N/A USB0CLK O LVCMOS PB3 (14) N/A PL7 I/O LVCMOS – T1CCP1 I/O LVCMOS PL7 (3) USB0DM I/O Analog PL7 91 92 93 OFF N/A VDD N/A N/A VDD N/A OFF VDD N/A N/A Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 15 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 4-2. Pin Attributes (continued) BUFFER TYPE (2) 94 PL6 I/O LVCMOS – T1CCP0 I/O LVCMOS PL6 (3) USB0DP I/O Analog PL6 N/A PB0 I/O LVCMOS – OFF CAN1Rx I LVCMOS PB0 (7) N/A I2C5SCL I/O LVCMOS PB0 (2) 95 T4CCP0 96 97 98 99 100 101 102 SIGNAL NAME 104 105 106 OFF VDD VDD N/A N/A I/O LVCMOS PB0 (3) I LVCMOS PB0 (1) N/A USB0ID I Analog PB0 N/A PB1 I/O LVCMOS – OFF CAN1Tx O LVCMOS PB1 (7) N/A I2C5SDA I/O LVCMOS PB1 (2) T4CCP1 I/O LVCMOS PB1 (3) U1Tx O LVCMOS PB1 (1) USB0VBUS I/O Analog PB1 N/A PC3 I/O LVCMOS – OFF TDO/SWO O LVCMOS PC3 (1) PC2 I/O LVCMOS – TDI I LVCMOS PC2 (1) PC1 I/O LVCMOS – TMS/SWDIO I/O LVCMOS PC1 (1) PC0 I/O LVCMOS – TCK/SWCLK I LVCMOS PC0 (1) VDD – Power Fixed PQ4 I/O LVCMOS – DIVSCLK O LVCMOS PQ4 (7) VDD N/A N/A N/A N/A VDD VDD VDD VDD N/A PU N/A PU OFF PU OFF PU N/A OFF VDD N/A I LVCMOS PQ4 (1) N/A PP2 I/O LVCMOS – OFF EPI0S29 I/O LVCMOS PP2 (15) U0DTR O LVCMOS PP2 (1) USB0NXT O LVCMOS PP2 (14) N/A PP3 I/O LVCMOS – OFF EPI0S30 I/O LVCMOS PP3 (15) N/A RTCCLK O LVCMOS PP3 (7) U0DCD I LVCMOS PP3 (2) U1CTS I LVCMOS PP3 (1) USB0DIR O LVCMOS PP3 (14) N/A PP4 I/O LVCMOS – OFF I LVCMOS PP4 (2) U3RTS O LVCMOS PP4 (1) USB0D7 I/O LVCMOS PP4 (14) N/A PP5 I/O LVCMOS – OFF I2C2SCL I/O LVCMOS PP5 (2) I LVCMOS PP5 (1) I/O LVCMOS PP5 (14) U0DSR U3CTS USB0D6 16 POWER SOURCE (3) U1Rx U1Rx 103 PIN MUX ENCODING STATE AFTER RESET RELEASE (4) SIGNAL TYPE (1) PIN NUMBER Terminal Configuration and Functions VDD VDD N/A N/A N/A N/A N/A VDD VDD N/A N/A N/A N/A N/A Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Table 4-2. Pin Attributes (continued) BUFFER TYPE (2) 107 PN0 I/O LVCMOS – U1RTS O LVCMOS PN0 (1) 108 PN1 I/O LVCMOS – I LVCMOS PN1 (1) PN2 I/O LVCMOS – 109 EPI0S29 I/O LVCMOS PN2 (15) U1DCD I LVCMOS PN2 (1) U2RTS O LVCMOS PN2 (2) N/A PN3 I/O LVCMOS – OFF 110 EPI0S30 I/O LVCMOS PN3 (15) U1DSR I LVCMOS PN3 (1) U2CTS I LVCMOS PN3 (2) N/A PN4 I/O LVCMOS – OFF EPI0S34 I/O LVCMOS PN4 (15) 111 I2C2SDA I/O LVCMOS PN4 (3) U1DTR O LVCMOS PN4 (1) U3RTS O LVCMOS PN4 (2) N/A PN5 I/O LVCMOS – OFF EPI0S35 I/O LVCMOS PN5 (15) N/A 112 I2C2SCL SIGNAL NAME U1CTS PIN MUX ENCODING POWER SOURCE (3) STATE AFTER RESET RELEASE (4) SIGNAL TYPE (1) PIN NUMBER VDD VDD OFF N/A OFF N/A OFF VDD VDD N/A N/A N/A N/A N/A VDD N/A N/A I/O LVCMOS PN5 (3) U1RI I LVCMOS PN5 (1) N/A U3CTS I LVCMOS PN5 (2) N/A 113 VDD – Power Fixed N/A N/A 114 GND – Power Fixed N/A N/A 115 VDDC – Power Fixed N/A PJ0 I/O LVCMOS – EN0PPS O LVCMOS PJ0 (5) U3Rx I LVCMOS PJ0 (1) N/A PJ1 I/O LVCMOS – OFF U3Tx O LVCMOS PJ1 (1) PP0 I/O LVCMOS – C2+ I Analog PP0 I/O LVCMOS PP0 (15) I LVCMOS PP0 (1) N/A PP1 I/O LVCMOS – OFF C2- I Analog PP1 SSI3XDAT3 I/O LVCMOS PP1 (15) U6Tx O LVCMOS PP1 (1) N/A PB5 I/O LVCMOS – OFF 116 117 118 SSI3XDAT2 U6Rx 119 AIN11 120 VDD N/A N/A OFF VDD VDD N/A N/A OFF VDD VDD N/A N/A N/A N/A I Analog PB5 I2C5SDA I/O LVCMOS PB5 (2) N/A SSI1Clk I/O LVCMOS PB5 (15) N/A U0RTS O LVCMOS PB5 (1) N/A VDD N/A Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 17 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 4-2. Pin Attributes (continued) BUFFER TYPE (2) I/O LVCMOS – OFF I Analog PB4 N/A I2C5SCL I/O LVCMOS PB4 (2) SSI1Fss I/O LVCMOS PB4 (15) U0CTS I LVCMOS PB4 (1) VDD – Power Fixed PE4 I/O LVCMOS – AIN9 I Analog PE4 I/O LVCMOS PE4 (15) U1RI I LVCMOS PE4 (1) N/A PE5 I/O LVCMOS – OFF AIN8 I Analog PE5 SSI1XDAT1 I/O LVCMOS PE5 (15) N/A PD4 I/O LVCMOS – OFF SIGNAL NAME PB4 AIN10 121 122 123 124 SSI1XDAT0 AIN7 125 128 18 VDD N/A N/A N/A N/A VDD VDD I Analog PD4 I/O LVCMOS PD4 (15) T3CCP0 N/A N/A N/A N/A N/A VDD N/A I/O LVCMOS PD4 (3) U2Rx I LVCMOS PD4 (1) N/A PD5 I/O LVCMOS – OFF N/A I Analog PD5 SSI1XDAT3 I/O LVCMOS PD5 (15) T3CCP1 I/O LVCMOS PD5 (3) U2Tx O LVCMOS PD5 (1) N/A PD6 I/O LVCMOS – OFF N/A AIN5 127 POWER SOURCE (3) OFF SSI1XDAT2 AIN6 126 PIN MUX ENCODING STATE AFTER RESET RELEASE (4) SIGNAL TYPE (1) PIN NUMBER N/A VDD N/A N/A I Analog PD6 SSI2XDAT3 I/O LVCMOS PD6 (15) T4CCP0 I/O LVCMOS PD6 (3) U2RTS O LVCMOS PD6 (1) N/A USB0EPEN O LVCMOS PD6 (5) N/A PD7 I/O LVCMOS – OFF AIN4 I Analog PD7 N/A NMI I LVCMOS PD7 (8) N/A SSI2XDAT2 I/O LVCMOS PD7 (15) T4CCP1 I/O LVCMOS PD7 (3) N/A U2CTS I LVCMOS PD7 (1) N/A USB0PFLT I LVCMOS PD7 (5) N/A Terminal Configuration and Functions VDD VDD N/A N/A N/A Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com 4.3 SLASEN5 – OCTOBER 2017 Signal Descriptions Table 4-3 describes the signals. The signals are sorted by function. Table 4-3. Signal Descriptions FUNCTION ADC Analog Comparators Controller Area Network SIGNAL NAME PIN NO. PIN TYPE DESCRIPTION AIN0 12 I Analog-to-digital converter input 0. AIN1 13 I Analog-to-digital converter input 1 AIN2 14 I Analog-to-digital converter input 2 AIN3 15 I Analog-to-digital converter input 3 AIN4 128 I Analog-to-digital converter input 4 AIN5 127 I Analog-to-digital converter input 5 AIN6 126 I Analog-to-digital converter input 6 AIN7 125 I Analog-to-digital converter input 7 AIN8 124 I Analog-to-digital converter input 8 AIN9 123 I Analog-to-digital converter input 9 AIN10 121 I Analog-to-digital converter input 10 AIN11 120 I Analog-to-digital converter input 11 AIN12 4 I Analog-to-digital converter input 12 AIN13 3 I Analog-to-digital converter input 13 AIN14 2 I Analog-to-digital converter input 14 AIN15 1 I Analog-to-digital converter input 15 AIN16 18 I Analog-to-digital converter input 16 AIN17 19 I Analog-to-digital converter input 17 AIN18 20 I Analog-to-digital converter input 18 AIN19 21 I Analog-to-digital converter input 19 VREFA+ 9 - A reference voltage used to specify the voltage at which the ADC converts to a maximum value. This pin is used in conjunction with GNDA. The voltage that is applied to VREFA+ is the voltage with which an AINn signal is converted to 4095. The VREFA+ voltage is limited to the range specified in the ADC electrical specifications. C0+ 23 I Analog comparator 0 positive input C0- 22 I Analog comparator 0 negative input C0o 1 83 O Analog comparator 0 output C1+ 24 I Analog comparator 1 positive input C1- 25 I Analog comparator 1 negative input C1o 2 84 O Analog comparator 1 output C2+ 118 I Analog comparator 2 positive input C2- 119 I Analog comparator 2 negative input C2o 3 O Analog comparator 2 output CAN0Rx 33 I CAN module 0 receive CAN0Tx 34 O CAN module 0 transmit CAN1Rx 95 I CAN module 1 receive CAN1Tx 96 O CAN module 1 transmit Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 19 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 4-3. Signal Descriptions (continued) FUNCTION Core Ethernet 20 SIGNAL NAME PIN NO. PIN TYPE DESCRIPTION TRCLK 45 O Trace clock. TRD0 44 O Trace data 0. TRD1 43 O Trace data 1. TRD2 42 O Trace data 2. TRD3 46 O Trace data 3. EN0LED0 42 63 O Ethernet 0 LED 0 EN0LED1 46 61 O Ethernet 0 LED 1 EN0LED2 43 62 O Ethernet 0 LED 2 EN0PPS 49 116 O Ethernet 0 pulse-per-second (PPS) output EN0RXIN 53 I/O Ethernet PHY negative receive differential input EN0RXIP 54 I/O Ethernet PHY positive receive differential input EN0TXON 56 I/O Ethernet PHY negative transmit differential output EN0TXOP 57 I/O Ethernet PHY positive transmit differential output RBIAS 59 O 4.87-kΩ resistor (1% precision) for Ethernet PHY Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Table 4-3. Signal Descriptions (continued) FUNCTION External Peripheral Interface SIGNAL NAME PIN NO. PIN TYPE EPI0S0 18 29 DESCRIPTION I/O EPI module 0 signal 0 EPI0S1 19 30 I/O EPI module 0 signal 1 EPI0S2 20 31 I/O EPI module 0 signal 2 EPI0S3 21 32 I/O EPI module 0 signal 3 EPI0S4 22 I/O EPI module 0 signal 4 EPI0S5 23 I/O EPI module 0 signal 5 EPI0S6 24 I/O EPI module 0 signal 6 EPI0S7 25 I/O EPI module 0 signal 7 EPI0S8 40 I/O EPI module 0 signal 8 EPI0S9 41 I/O EPI module 0 signal 9 EPI0S10 50 I/O EPI module 0 signal 10 EPI0S11 49 I/O EPI module 0 signal 11 EPI0S12 75 I/O EPI module 0 signal 12 EPI0S13 76 I/O EPI module 0 signal 13 EPI0S14 77 I/O EPI module 0 signal 14 EPI0S15 78 I/O EPI module 0 signal 15 EPI0S16 81 I/O EPI module 0 signal 16 EPI0S17 82 I/O EPI module 0 signal 17 EPI0S18 83 I/O EPI module 0 signal 18 EPI0S19 84 I/O EPI module 0 signal 19 EPI0S20 5 I/O EPI module 0 signal 20 EPI0S21 6 I/O EPI module 0 signal 21 EPI0S22 11 I/O EPI module 0 signal 22 EPI0S23 27 I/O EPI module 0 signal 23 EPI0S24 60 I/O EPI module 0 signal 24 EPI0S25 61 I/O EPI module 0 signal 25 EPI0S26 85 I/O EPI module 0 signal 26 EPI0S27 91 I/O EPI module 0 signal 27 EPI0S28 92 I/O EPI module 0 signal 28 EPI0S29 103 109 I/O EPI module 0 signal 29 EPI0S30 104 110 I/O EPI module 0 signal 30 EPI0S31 62 I/O EPI module 0 signal 31 EPI0S32 63 I/O EPI module 0 signal 32 EPI0S33 86 I/O EPI module 0 signal 33 EPI0S34 111 I/O EPI module 0 signal 34 EPI0S35 112 I/O EPI module 0 signal 35 Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 21 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 4-3. Signal Descriptions (continued) FUNCTION General-Purpose Timers GPIO, Port A GPIO, Port B GPIO, Port C 22 SIGNAL NAME PIN NO. PIN TYPE T0CCP0 1 33 85 DESCRIPTION I/O 16/32-Bit Timer 0 Capture/Compare/PWM 0 T0CCP1 2 34 86 I/O 16/32-Bit Timer 0 Capture/Compare/PWM 1 T1CCP0 3 35 94 I/O 16/32-Bit Timer 1 Capture/Compare/PWM 0 T1CCP1 4 36 93 I/O 16/32-Bit Timer 1 Capture/Compare/PWM 1 T2CCP0 37 78 I/O 16/32-Bit Timer 2 Capture/Compare/PWM 0 T2CCP1 38 77 I/O 16/32-Bit Timer 2 Capture/Compare/PWM 1 T3CCP0 40 76 125 I/O 16/32-Bit Timer 3 Capture/Compare/PWM 0 T3CCP1 41 75 126 I/O 16/32-Bit Timer 3 Capture/Compare/PWM 1 T4CCP0 74 95 127 I/O 16/32-Bit Timer 4 Capture/Compare/PWM 0 T4CCP1 73 96 128 I/O 16/32-Bit Timer 4 Capture/Compare/PWM 1 T5CCP0 72 91 I/O 16/32-Bit Timer 5 Capture/Compare/PWM 0 T5CCP1 71 92 I/O 16/32-Bit Timer 5 Capture/Compare/PWM 1 PA0 33 I/O GPIO port A bit 0 PA1 34 I/O GPIO port A bit 1 PA2 35 I/O GPIO port A bit 2 PA3 36 I/O GPIO port A bit 3 PA4 37 I/O GPIO port A bit 4 PA5 38 I/O GPIO port A bit 5 PA6 40 I/O GPIO port A bit 6 PA7 41 I/O GPIO port A bit 7 PB0 95 I/O GPIO port B bit 0 PB1 96 I/O GPIO port B bit 1 PB2 91 I/O GPIO port B bit 2 PB3 92 I/O GPIO port B bit 3 PB4 121 I/O GPIO port B bit 4 PB5 120 I/O GPIO port B bit 5 PC0 100 I/O GPIO port C bit 0 PC1 99 I/O GPIO port C bit 1 PC2 98 I/O GPIO port C bit 2 PC3 97 I/O GPIO port C bit 3 PC4 25 I/O GPIO port C bit 4 PC5 24 I/O GPIO port C bit 5 PC6 23 I/O GPIO port C bit 6 PC7 22 I/O GPIO port C bit 7 Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Table 4-3. Signal Descriptions (continued) FUNCTION GPIO, Port D GPIO, Port E GPIO, Port F GPIO, Port G GPIO, Port H GPIO, Port J GPIO, Port K GPIO, Port L PIN NO. PIN TYPE PD0 SIGNAL NAME 1 I/O GPIO port D bit 0 DESCRIPTION PD1 2 I/O GPIO port D bit 1 PD2 3 I/O GPIO port D bit 2 PD3 4 I/O GPIO port D bit 3 PD4 125 I/O GPIO port D bit 4 PD5 126 I/O GPIO port D bit 5 PD6 127 I/O GPIO port D bit 6 PD7 128 I/O GPIO port D bit 7 PE0 15 I/O GPIO port E bit 0 PE1 14 I/O GPIO port E bit 1 PE2 13 I/O GPIO port E bit 2 PE3 12 I/O GPIO port E bit 3 PE4 123 I/O GPIO port E bit 4 PE5 124 I/O GPIO port E bit 5 PF0 42 I/O GPIO port F bit 0 PF1 43 I/O GPIO port F bit 1 PF2 44 I/O GPIO port F bit 2 PF3 45 I/O GPIO port F bit 3 PF4 46 I/O GPIO port F bit 4 PG0 49 I/O GPIO port G bit 0 PG1 50 I/O GPIO port G bit 1 PH0 29 I/O GPIO port H bit 0 PH1 30 I/O GPIO port H bit 1 PH2 31 I/O GPIO port H bit 2 PH3 32 I/O GPIO port H bit 3 PJ0 116 I/O GPIO port J bit 0 PJ1 117 I/O GPIO port J bit 1 PK0 18 I/O GPIO port K bit 0 PK1 19 I/O GPIO port K bit 1 PK2 20 I/O GPIO port K bit 2 PK3 21 I/O GPIO port K bit 3 PK4 63 I/O GPIO port K bit 4 PK5 62 I/O GPIO port K bit 5 PK6 61 I/O GPIO port K bit 6 PK7 60 I/O GPIO port K bit 7 PL0 81 I/O GPIO port L bit 0 PL1 82 I/O GPIO port L bit 1 PL2 83 I/O GPIO port L bit 2 PL3 84 I/O GPIO port L bit 3 PL4 85 I/O GPIO port L bit 4 PL5 86 I/O GPIO port L bit 5 PL6 94 I/O GPIO port L bit 6 PL7 93 I/O GPIO port L bit 7 Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 23 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 4-3. Signal Descriptions (continued) FUNCTION GPIO, Port M GPIO, Port N GPIO, Port P GPIO, Port Q PIN NO. PIN TYPE PM0 SIGNAL NAME 78 I/O GPIO port M bit 0 PM1 77 I/O GPIO port M bit 1 PM2 76 I/O GPIO port M bit 2 PM3 75 I/O GPIO port M bit 3 PM4 74 I/O GPIO port M bit 4 PM5 73 I/O GPIO port M bit 5 PM6 72 I/O GPIO port M bit 6 PM7 71 I/O GPIO port M bit 7 PN0 107 I/O GPIO port N bit 0 PN1 108 I/O GPIO port N bit 1 PN2 109 I/O GPIO port N bit 2 PN3 110 I/O GPIO port N bit 3 PN4 111 I/O GPIO port N bit 4 PN5 112 I/O GPIO port N bit 5 PP0 118 I/O GPIO port P bit 0 PP1 119 I/O GPIO port P bit 1 PP2 103 I/O GPIO port P bit 2 PP3 104 I/O GPIO port P bit 3 PP4 105 I/O GPIO port P bit 4 PP5 106 I/O GPIO port P bit 5 PQ0 5 I/O GPIO port Q bit 0 PQ1 6 I/O GPIO port Q bit 1 PQ2 11 I/O GPIO port Q bit 2 PQ3 27 I/O GPIO port Q bit 3 PQ4 102 I/O GPIO port Q bit 4 HIB 65 O An output that indicates the processor is in Hibernate mode RTCCLK 24 60 104 O Buffered version of the Hibernation module's 32.768-kHz clock. This signal is not output when the part is in Hibernate mode and before being configured after power-on reset. TMPR0 71 I/O Tamper signal 0 TMPR1 72 I/O Tamper signal 1 TMPR2 73 I/O Tamper signal 2 TMPR3 74 I/O Tamper signal 3 VBAT 68 - Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup and Hibernation module power-source supply. WAKE 64 I An external input that brings the processor out of Hibernate mode when asserted XOSC0 66 I Hibernation module oscillator crystal input or an external clock reference input. This is either a crystal or a 32.768kHz oscillator for the Hibernation module RTC. XOSC1 67 O Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. Hibernate 24 DESCRIPTION Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Table 4-3. Signal Descriptions (continued) FUNCTION I2C JTAG, SWD, SWO SIGNAL NAME PIN NO. PIN TYPE DESCRIPTION I2C0SCL 91 I/O I2C module 0 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain. I2C0SDA 92 I/O I2C module 0 data I2C1SCL 49 I/O I2C module 1 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain. I2C1SDA 50 I/O I2C module 1 data I2C2SCL 82 106 112 I/O I2C module 2 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain. I2C2SDA 81 111 I/O I2C module 2 data I2C3SCL 63 I/O I2C module 3 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain. I2C3SDA 62 I/O I2C module 3 data I2C4SCL 61 I/O I2C module 4 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain. I2C4SDA 60 I/O I2C module 4 data I2C5SCL 95 121 I/O I2C module 5 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain. I2C5SDA 96 120 I/O I2C module 5 data I2C6SCL 40 I/O I2C module 6 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain. I2C6SDA 41 I/O I2C module 6 data I2C7SCL 1 37 I/O I2C module 7 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain. I2C7SDA 2 38 I/O I2C module 7 data I2C8SCL 3 35 I/O I2C module 8 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain. I2C8SDA 4 36 I/O I2C module 8 data I2C9SCL 33 I/O I2C module 9 clock. This signal has an active pullup. The corresponding port pin should not be configured as open drain I2C9SDA 34 I/O I2C module 9 data TCK/SWCLK 100 I JTAG/SWD clock TDI 98 I JTAG TDI TDO/SWO 97 O JTAG TDO and SWO TMS/SWDIO 99 I JTAG TMS and SWDIO Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 25 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 4-3. Signal Descriptions (continued) FUNCTION PWM PIN NO. PIN TYPE M0FAULT0 SIGNAL NAME 46 I Motion Control module 0 PWM fault 0 M0FAULT1 61 I Motion Control module 0 PWM fault 1 M0FAULT2 60 I Motion Control module 0 PWM fault 2 M0FAULT3 81 I Motion Control module 0 PWM fault 3 M0PWM0 42 O Motion Control module 0 PWM 0. This signal is controlled by module 0 PWM generator 0. M0PWM1 43 O Motion Control module 0 PWM 1. This signal is controlled by module 0 PWM generator 0. M0PWM2 44 O Motion Control module 0 PWM 2. This signal is controlled by module 0 PWM generator 1. M0PWM3 45 O Motion Control module 0 PWM 3. This signal is controlled by module 0 PWM generator 1. M0PWM4 49 O Motion Control module 0 PWM 4. This signal is controlled by module 0 PWM generator 2. M0PWM5 50 O Motion Control module 0 PWM 5. This signal is controlled by module 0 PWM generator 2. M0PWM6 63 O Motion Control module 0 PWM 6. This signal is controlled by module 0 PWM generator 3. M0PWM7 62 O Motion Control module 0 PWM 7. This signal is controlled by module 0 PWM generator 3. GND 17 48 55 58 80 114 - Ground reference for logic and I/O pins GNDA 10 - The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions VDD 7 16 26 28 39 47 51 52 69 79 90 101 113 122 - Positive supply for I/O and some logic - The positive supply for the analog circuits (for example, ADC and Analog Comparators). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. VDDA pins must be supplied with a voltage that meets the specification in, regardless of system implementation Power QEI 26 DESCRIPTION VDDA 8 VDDC 87 115 - Positive supply for most of the logic function, including the processor core and most peripherals. The voltage on this pin is 1.2 V and is supplied by the on-chip LDO. The VDDC pins should only be connected to each other and an external capacitor as specified in the LDO electrical specifications. IDX0 84 I QEI module 0 index PhA0 82 I QEI module 0 phase A PhB0 83 I QEI module 0 phase B Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Table 4-3. Signal Descriptions (continued) FUNCTION SSI System Control and Clocks PIN NO. PIN TYPE SSI0Clk SIGNAL NAME 35 I/O SSI module 0 clock DESCRIPTION SSI0Fss 36 I/O SSI module 0 frame signal SSI0XDAT0 37 I/O SSI module 0 bidirectional data pin 0 (SSI0TX in Legacy SSI mode) SSI0XDAT1 38 I/O SSI module 0 bidirectional data pin 1 (SSI0RX in Legacy SSI mode) SSI0XDAT2 40 I/O SSI module 0 bidirectional data pin 2 SSI0XDAT3 41 I/O SSI module 0 bidirectional data pin 3 SSI1Clk 120 I/O SSI module 1 clock SSI1Fss 121 I/O SSI module 1 frame signal SSI1XDAT0 123 I/O SSI module 1 bidirectional data pin 0 (SSI1TX in Legacy SSI mode) SSI1XDAT1 124 I/O SSI module 1 bidirectional data pin 1 (SSI1RX in Legacy SSI mode) SSI1XDAT2 125 I/O SSI module 1 bidirectional data pin 2 SSI1XDAT3 126 I/O SSI module 1 bidirectional data pin 3 SSI2Clk 4 I/O SSI module 2 clock SSI2Fss 3 I/O SSI module 2 frame signal SSI2XDAT0 2 I/O SSI module 2 bidirectional data pin 0 (SSI2TX in Legacy SSI mode) SSI2XDAT1 1 I/O SSI module 2 bidirectional data pin 1 (SSI2RX in Legacy SSI mode) SSI2XDAT2 128 I/O SSI module 2 bidirectional data pin 2 SSI2XDAT3 127 I/O SSI module 2 bidirectional data pin 3 SSI3Clk 5 45 I/O SSI module 3 clock SSI3Fss 6 44 I/O SSI module 3 frame signal SSI3XDAT0 11 43 I/O SSI module 3 bidirectional data pin 0 (SSI3TX in Legacy SSI mode) SSI3XDAT1 27 42 I/O SSI module 3 bidirectional data pin 1 (SSI3RX in Legacy SSI mode) SSI3XDAT2 46 118 I/O SSI module 3 bidirectional data pin 2 SSI3XDAT3 119 I/O SSI module 3 bidirectional data pin 3 DIVSCLK 102 O An optionally divided reference clock output based on a selected clock source. This signal is not synchronized to the system clock. NMI 128 I Nonmaskable interrupt OSC0 88 I Main oscillator crystal input or an external clock reference input OSC1 89 O Main oscillator crystal output. Leave unconnected when using a single-ended clock source. RST 70 I System reset input Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 27 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 4-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. PIN TYPE U0CTS 30 74 121 I UART module 0 Clear To Send modem flow control input signal U0DCD 31 73 104 I UART module 0 Data Carrier Detect modem status input signal U0DSR 32 72 105 I UART module 0 Data Set Ready modem output control line U0DTR 103 O UART module 0 Data Terminal Ready modem status input signal U0RI 60 71 I UART module 0 Ring Indicator modem status input signal U0RTS 29 120 O UART module 0 Request to Send modem flow control output signal U0Rx 33 I UART module 0 receive U0Tx 34 O UART module 0 transmit U1CTS 104 108 I UART module 1 Clear To Send modem flow control input signal U1DCD 13 109 I UART module 1 Data Carrier Detect modem status input signal U1DSR 14 110 I UART module 1 Data Set Ready modem output control line U1DTR 12 111 O UART module 1 Data Terminal Ready modem status input signal U1RI 112 123 I UART module 1 Ring Indicator modem status input signal U1RTS 15 107 O UART module 1 Request to Send modem flow control output line U1Rx 95 102 I UART module 1 receive. U1Tx 96 O UART module 1 transmit U2CTS 110 128 I UART module 2 Clear To Send modem flow control input signal U2RTS 109 127 O UART module 2 Request to Send modem flow control output line U2Rx 40 125 I UART module 2 receive U2Tx 41 126 O UART module 2 transmit U3CTS 106 112 I UART module 3 Clear To Send modem flow control input signal U3RTS 105 111 O UART module 3 Request to Send modem flow control output line U3Rx 37 116 I UART module 3 receive U3Tx 38 117 O UART module 3 transmit U4CTS 21 I UART module 4 Clear To Send modem flow control input signal U4RTS 20 O UART module 4 Request to Send modem flow control output line U4Rx 18 35 I UART module 4 receive U4Tx 19 36 O UART module 4 transmit UART Module 0 UART Module 1 UART Module 2 UART Module 3 UART Module 4 28 DESCRIPTION Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Table 4-3. Signal Descriptions (continued) FUNCTION UART Module 5 UART Module 6 UART Module 7 SIGNAL NAME PIN NO. PIN TYPE 23 I UART module 5 receive U5Tx 22 O UART module 5 transmit U6Rx 118 I UART module 6 receive U6Tx 119 O UART module 6 transmit U7Rx 25 I UART module 7 receive U7Tx 24 O UART module 7 transmit USB0CLK 92 O 60-MHz clock to the external PHY USB0D0 81 I/O USB data 0 USB0D1 82 I/O USB data 1 USB0D2 83 I/O USB data 2 USB0D3 84 I/O USB data 3 USB0D4 85 I/O USB data 4 USB0D5 86 I/O USB data 5 USB0D6 106 I/O USB data 6 USB0D7 105 I/O USB data 7 USB0DIR 104 O Indicates that the external PHY is able to accept data from the USB controller USB0DM 93 I/O Bidirectional differential data pin (D– per USB specification) for USB0 USB0DP 94 I/O Bidirectional differential data pin (D+ per USB specification) for USB0 USB0EPEN 40 41 127 O Optionally used in Host mode to control an external power source to supply power to the USB bus U5Rx USB DESCRIPTION USB0ID 95 I This signal senses the state of the USB ID signal. The USB PHY enables an integrated pull-up, and an external element (USB connector) indicates the initial state of the USB controller (pulled down is the A side of the cable and pulled up is the B side). USB0NXT 103 O Asserted by the external PHY to throttle all data types USB0PFLT 41 128 I Optionally used in Host mode by an external power source to indicate an error state by that power source USB0STP 91 O Asserted by the USB controller to signal the end of a USB transmit packet or register write operation USB0VBUS 96 I/O This signal is used during the session request protocol. This signal allows the USB PHY to both sense the voltage level of VBUS, and pull up VBUS momentarily during VBUS pulsing. Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 29 MSP432E401Y SLASEN5 – OCTOBER 2017 4.4 www.ti.com GPIO Pin Multiplexing Table 4-4 lists the GPIO pins and their analog and digital alternate functions. The AINx analog signals go through an isolation circuit before reaching their circuitry. These signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN) register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL) register. Other analog signals are 3.3-V tolerant and are connected directly to their circuitry (C0-, C0+, C1 -, C1+, C2-, C2+, USB0VBUS, USB0ID). These signals are configured by clearing the DEN bit in the GPIODEN register. The digital signals are enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL) register to the numeric encoding shown in Table 4-4. Table 4-4. GPIO Pins and Alternate Functions I/O PIN ANALOG OR SPECIAL FUNCTION DIGITAL FUNCTION (GPIOPCTL PMCx BIT FIELD ENCODING) 1 2 3 4 5 6 7 8 11 13 14 15 – (1) (1) 30 PA0 33 – U0Rx I2C9SCL T0CCP0 – – – CAN0Rx – – – – PA1 34 – U0Tx I2C9SDA T0CCP1 – – – CAN0Tx – – – – – PA2 35 – U4Rx I2C8SCL T1CCP0 – – – – – – – – SSI0Clk PA3 36 – U4Tx I2C8SDA T1CCP1 – – – – – – – – SSI0Fss PA4 37 – U3Rx I2C7SCL T2CCP0 – – – – – – – – SSI0XDAT0 PA5 38 – U3Tx I2C7SDA T2CCP1 – – – – – – – – SSI0XDAT1 PA6 40 – U2Rx I2C6SCL T3CCP0 – USB0EPEN – – – – SSI0XDAT2 – EPI0S8 PA7 41 – U2Tx I2C6SDA T3CCP1 – USB0PFLT – – – USB0EPEN SSI0XDAT3 – EPI0S9 PB0 95 USB0ID U1Rx I2C5SCL T4CCP0 – – – CAN1Rx – – – – – PB1 96 USB0VBUS U1Tx I2C5SDA T4CCP1 – – – CAN1Tx – – – – – PB2 91 – – I2C0SCL T5CCP0 – – – – – – – USB0STP EPI0S27 PB3 92 – – I2C0SDA T5CCP1 – – – – – – – USB0CLK EPI0S28 PB4 121 AIN10 U0CTS I2C5SCL – – – – – – – – – SSI1Fss PB5 120 AIN11 U0RTS I2C5SDA – – – – – – – – – SSI1Clk PC0 100 – TCK SWCLK – – – – – – – – – – – PC1 99 – TMS SWDIO – – – – – – – – – – – PC2 98 – TDI – – – – – – – – – – – PC3 97 – TDO SWO – – – – – – – – – – – PC4 25 C1- U7Rx – – – – – – – – – – EPI0S7 PC5 24 C1+ U7Tx – – – – – RTCCLK – – – – EPI0S6 PC6 23 C0+ U5Rx – – – – – – – – – – EPI0S5 PC7 22 C0- U5Tx – – – – – – – – – – EPI0S4 PD0 1 AIN15 – I2C7SCL T0CCP0 – C0o – – – – – – SSI2XDAT1 PD1 2 AIN14 – I2C7SDA T0CCP1 – C1o – – – – – – SSI2XDAT0 The TMPRn signals are digital signals enabled and configured by the Hibernation module. All other signals listed in this column are analog signals. Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Table 4-4. GPIO Pins and Alternate Functions (continued) I/O PIN ANALOG OR SPECIAL FUNCTION DIGITAL FUNCTION (GPIOPCTL PMCx BIT FIELD ENCODING) 1 2 3 4 5 6 7 8 11 13 14 15 SSI2Fss (1) PD2 3 AIN13 – I2C8SCL T1CCP0 – C2o – – – – – – PD3 4 AIN12 – I2C8SDA T1CCP1 – – – – – – – – SSI2Clk PD4 125 AIN7 U2Rx – T3CCP0 – – – – – – – – SSI1XDAT2 PD5 126 AIN6 U2Tx – T3CCP1 – – – – – – – – SSI1XDAT3 PD6 127 AIN5 U2RTS – T4CCP0 – USB0EPEN – – – – – – SSI2XDAT3 PD7 128 AIN4 U2CTS – T4CCP1 – USB0PFLT – – NMI – – – SSI2XDAT2 PE0 15 AIN3 U1RTS – – – – – – – – – – – PE1 14 AIN2 U1DSR – – – – – – – – – – – PE2 13 AIN1 U1DCD – – – – – – – – – – – PE3 12 AIN0 U1DTR – – – – – – – – – – – PE4 123 AIN9 U1RI – – – – – – – – – – SSI1XDAT0 PE5 124 AIN8 – – – – – – – – – – – SSI1XDAT1 PF0 42 – – – – – EN0LED0 M0PWM0 – – – – SSI3XDAT1 TRD2 PF1 43 – – – – – EN0LED2 M0PWM1 – – – – SSI3XDAT0 TRD1 PF2 44 – – – – – – M0PWM2 – – – – SSI3Fss TRD0 PF3 45 – – – – – – M0PWM3 – – – – SSI3Clk TRCLK PF4 46 – – – – – EN0LED1 M0FAULT0 – – – – SSI3XDAT2 TRD3 PG0 49 – – I2C1SCL – – EN0PPS M0PWM4 – – – – – EPI0S11 PG1 50 – – I2C1SDA – – – M0PWM5 – – – – – EPI0S10 PH0 29 – U0RTS – – – – – – – – – – EPI0S0 PH1 30 – U0CTS – – – – – – – – – – EPI0S1 PH2 31 – U0DCD – – – – – – – – – – EPI0S2 PH3 32 – U0DSR – – – – – – – – – – EPI0S3 PJ0 116 – U3Rx – – – EN0PPS – – – – – – – PJ1 117 – U3Tx – – – – – – – – – – – PK0 18 AIN16 U4Rx – – – – – – – – – – EPI0S0 PK1 19 AIN17 U4Tx – – – – – – – – – – EPI0S1 PK2 20 AIN18 U4RTS – – – – – – – – – – EPI0S2 PK3 21 AIN19 U4CTS – – – – – – – – – – EPI0S3 PK4 63 – – I2C3SCL – – EN0LED0 M0PWM6 – – – – – EPI0S32 PK5 62 – – I2C3SDA – – EN0LED2 M0PWM7 – – – – – EPI0S31 PK6 61 – – I2C4SCL – – EN0LED1 M0FAULT1 – – – – – EPI0S25 PK7 60 – U0RI I2C4SDA – – RTCCLK M0FAULT2 – – – – – EPI0S24 PL0 81 – – I2C2SDA – – – M0FAULT3 – – – – USB0D0 EPI0S16 Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 31 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 4-4. GPIO Pins and Alternate Functions (continued) I/O PIN ANALOG OR SPECIAL FUNCTION DIGITAL FUNCTION (GPIOPCTL PMCx BIT FIELD ENCODING) 1 2 3 4 5 6 7 8 11 13 14 15 (1) 32 PL1 82 – – I2C2SCL – – – PhA0 – – – – USB0D1 EPI0S17 PL2 83 – – – – – C0o PhB0 – – – – USB0D2 EPI0S18 PL3 84 – – – – – C1o IDX0 – – – – USB0D3 EPI0S19 PL4 85 – – – T0CCP0 – – – – – – – USB0D4 EPI0S26 PL5 86 – – – T0CCP1 – – – – – – – USB0D5 EPI0S33 PL6 94 USB0DP – – T1CCP0 – – – – – – – – – PL7 93 USB0DM – – T1CCP1 – – – – – – – – – PM0 78 – – – T2CCP0 – – – – – – – – EPI0S15 PM1 77 – – – T2CCP1 – – – – – – – – EPI0S14 PM2 76 – – – T3CCP0 – – – – – – – – EPI0S13 PM3 75 – – – T3CCP1 – – – – – – – – EPI0S12 PM4 74 TMPR3 U0CTS – T4CCP0 – – – – – – – – – PM5 73 TMPR2 U0DCD – T4CCP1 – – – – – – – – – PM6 72 TMPR1 U0DSR – T5CCP0 – – – – – – – – – PM7 71 TMPR0 U0RI – T5CCP1 – – – – – – – – – PN0 107 – U1RTS – – – – – – – – – – – PN1 108 – U1CTS – – – – – – – – – – – PN2 109 – U1DCD U2RTS – – – – – – – – – EPI0S29 PN3 110 – U1DSR U2CTS – – – – – – – – – EPI0S30 PN4 111 – U1DTR U3RTS I2C2SDA – – – – – – – – EPI0S34 PN5 112 – U1RI U3CTS I2C2SCL – – – – – – – – EPI0S35 PP0 118 C2+ U6Rx – – – – – – – – – – SSI3XDAT2 PP1 119 C2- U6Tx – – – – – – – – – – SSI3XDAT3 PP2 103 – U0DTR – – – – – – – – – USB0NXT EPI0S29 PP3 104 – U1CTS U0DCD – – – – RTCCLK – – – USB0DIR EPI0S30 PP4 105 – U3RTS U0DSR – – – – – – – – USB0D7 – PP5 106 – U3CTS I2C2SCL – – – – – – – – USB0D6 – PQ0 5 – – – – – – – – – – – SSI3Clk EPI0S20 PQ1 6 – – – – – – – – – – – SSI3Fss EPI0S21 PQ2 11 – – – – – – – – – – – SSI3XDAT0 EPI0S22 PQ3 27 – – – – – – – – – – – SSI3XDAT1 EPI0S23 PQ4 102 – U1Rx – – – – – DIVSCLK – – – – – Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com 4.5 SLASEN5 – OCTOBER 2017 Buffer Type Table 4-5 describes the buffer types that are referenced in Section 4.2. Table 4-5. Buffer Type BUFFER TYPE (STANDARD) Analog (1) NOMINAL VOLTAGE HYSTERESIS PU OR PD NOMINAL PU OR PD STRENGTH (µA) OUTPUT DRIVE STRENGTH (mA) 3.3 V N N/A N/A N/A See Input/Output Programmable Pin Characteristics . See analog modules in Section 5 for details. See Typical Characteristics. LVCMOS 3.3 V Y (2) Power (VDD) (3) 3.3 V N N/A N/A N/A Power (VDDA) (3) 3.3 V N N/A N/A N/A Power (GND and GNDA) (3) 0V N N/A N/A N/A (1) (2) (3) OTHER CHARACTERISTICS This is a switch, not a buffer. Only for input pins This is supply input, not a buffer. 4.6 Connections for Unused Pins Table 4-6 lists the recommended connections for unused pins. Table 4-6 lists two options: an acceptable practice and a preferred practice for reduced power consumption and improved EMC characteristics. If a module is not used in a system, and its inputs are grounded, it is important that the clock to the module is never enabled by setting the corresponding bit in the RCGCx register. Table 4-6. Connections for Unused Pins PIN NUMBER ACCEPTABLE PRACTICE PREFERRED PRACTICE VREFA+ 9 VDDA VDDA EN0RXIN 53 NC NC EN0RXIP 54 NC NC EN0TXON 56 NC NC EN0TXOP 57 NC NC RBIAS 59 Connect to ground through 4.87-kΩ resistor. Connect to ground through 4.87-kΩ resistor. PA1 (U0Tx) 34 NC GND (1) PA4 (SSI0XDAT0) 37 NC GND (2) NC GND FUNCTION ADC Ethernet GPIO SIGNAL NAME All unused GPIOs Hibernate HIB 65 NC NC VBAT 68 NC VDD WAKE 64 NC GND XOSC0 66 NC GND NC NC XOSC1 (1) (2) 67 PA1 (U0Tx) may be enabled as an output by the ROM bootloader if no code is present in the flash and PA0 (U0Rx) receives a valid boot signature. Ensure that this condition will not occur if PA1 is to be connected directly to GND. PA4 (SSI0XDAT0) may be enabled as an output by the ROM bootloader if no code is present in the flash and the SSI0x (PA2, PA3, PA5) receives a valid boot signature. Ensure that this condition will not occur if PA4 is to be connected directly to GND. Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 33 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 4-6. Connections for Unused Pins (continued) FUNCTION System Control SIGNAL NAME PIN NUMBER ACCEPTABLE PRACTICE PREFERRED PRACTICE OSC0 88 NC GND OSC1 89 NC NC RST 70 VDD Pull up to VDD with 0 to 100-kΩ resistor. (3) USB0DM / PL7 93 NC Pull down to GND with 1-kΩ resistor. (4) USB0DP / PL6 94 NC Pull down to GND with 1-kΩ resistor. (4) USB (3) (4) 34 For details, see the System Control chapter of the SimpleLink™ MSP432E4 Microcontrollers Technical Reference Manual The ROM bootloader may configure these pins as USB pins if no code is present in the flash. Therefore, they should not be connected directly to ground. Terminal Configuration and Functions Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX VDD VDD supply voltage 0 4 V VDDA VDDA supply voltage 0 4 V VBAT VBAT battery supply voltage 0 4 VBATRMP VBAT battery supply voltage ramp time 0 0.7 VIN_GPIO Input voltage –0.3 4 V IGPIOMAX Maximum current per output pin 64 mA TS Unpowered storage temperature range –65 150 °C TJMAX Maximum junction temperature 125 °C (1) (2) (3) (3) UNIT V V/µs Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Voltages are measured with respect to GND. Applies to static and dynamic signals including overshoot. 5.2 ESD Ratings over operating free-air temperature range (unless otherwise noted) VALUE V(ESD) (1) (2) (3) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS‑001 (1) (2) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22‑C101 (3) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance. All pins are HBM compliant to ±2000 V for all combinations as per JESD22-A114F, except for the following stress combinations: • The Ethernet EN0RXIN, EN0TXON, EN0RXIP, and EN0TXOP pins to each other. • The GPIO pins PM4, PM5, PM6, and PM7 to other pins. These exceptions are compliant to 500 V and do not require any special handling beyond typical ESD control procedures during assembly operations per JEDEC publication JEP155. These pins do meet the 500-V CDM specification. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance. 5.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT TA Ambient operating temperature range Extended temperature –40 105 °C TJ Junction operating temperature range Extended temperature –40 125 °C 5.4 Recommended DC Operating Conditions over operating free-air temperature (unless otherwise noted) MIN NOM MAX UNIT 2.97 3.3 3.63 V 2.97 3.3 3.63 V VDDC supply voltage, run mode 1.14 1.2 1.32 V VDDC supply voltage, deep-sleep mode 0.85 0.95 V VDD VDD supply voltage VDDA VDDA supply voltage VDDC VDDCDS (1) 5.5 (1) To ensure proper operation, power on VDDA before VDD if sourced from different supplies, or connect VDDA to the same supply as VDD. No restriction exists for powering off. Recommended GPIO Operating Characteristics The following sections describe the recommended GPIO operating characteristics for the device. Two types of pads are provided on the device: Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 35 MSP432E401Y SLASEN5 – OCTOBER 2017 • • www.ti.com Fast GPIO pads: These pads provide variable, programmable drive strength and optimized voltage output levels. Slow GPIO pads: These pads provide 2-mA drive strength and are designed to be sensitive to voltage inputs. The PJ1 GPIOs port pins are slow GPIO pads. All other GPIOs have a fast GPIO pad type. NOTE Port pins PL6 and PL7 operate as fast GPIO pads, but have 4-mA drive capability only. GPIO register controls for drive strength, slew rate and open drain have no effect on these pins. The registers which have no effect are as follows: GPIODR2R, GPIODR4R, GPIODR8R, GPIODR12R, GPIOSLR, and GPIOODR. NOTE Port pins PM[7:4] operate as fast GPIO pads but support only 2-, 4-, 6-, and 8-mA drive capability. 10- and 12-mA drive are not supported. All standard GPIO register controls, except for the GPIODR12R register, apply to these port pins. 5.6 Recommended Fast GPIO Pad Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT 0.65 × VDD 4 V 0 VIH Fast GPIO high-level input voltage IIH Fast GPIO high-level input current 300 nA VIL Fast GPIO low-level input voltage 0.35 × VDD V IIL Fast GPIO low-level input current –200 nA VHYS Fast GPIO input hysteresis VOH Fast GPIO high-level output voltage VOL Fast GPIO low-level output voltage IOH IOL (1) (2) 5.7 (1) 0.49 V 2.4 V 0.40 Fast GPIO high-level source current, VOH = 2.4 V Fast GPIO low-level sink current, VOL = 0.4 V (2) (2) 2-mA drive 2.0 4-mA drive 4.0 8-mA drive 8.0 10-mA drive 10.0 12-mA drive 12.0 2-mA drive 2.0 4-mA drive 4.0 8-mA drive 8.0 10-mA drive 10.0 12-mA drive 12.0 12-mA drive overdriven to 18 mA 18.0 V mA mA Output, pullup, and pulldown are disabled; only input is enabled. IO specifications reflect the maximum current where the corresponding output voltage meets the VOH or VOL thresholds. IO current can exceed these limits (subject to absolute maximum ratings). Recommended Slow GPIO Pad Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIH Slow GPIO high-level input voltage IIH Slow GPIO high-level input current 36 0.65 × VDD Specifications NOM MAX UNIT 4 V 4.1 nA Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Recommended Slow GPIO Pad Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) MIN VIL Slow GPIO low-level input voltage IIL Slow GPIO low-level input current VHYS Slow GPIO input hysteresis VOH Slow GPIO high-level output voltage VOL Slow GPIO low-level output voltage IOH Slow GPIO high-level source current, VOH = 2.4 V, 2-mA drive IOL Slow GPIO low-level sink current, VOL = 0.4 V (1) (2) NOM 0 (1) MAX V –1 nA 0.49 V 2.4 V 0.4 (2) , 2-mA drive UNIT 0.35 × VDD V 2.0 mA 2.0 mA Output, pullup, and pulldown are disabled; only input is enabled. IO specifications reflect the maximum current where the corresponding output voltage meets the VOH or VOL thresholds. IO current can exceed these limits (subject to absolute maximum ratings). 5.8 GPIO Current Restrictions over operating free-air temperature range (unless otherwise noted) (1) MIN IMAXL Cumulative maximum GPIO current per side, left IMAXB Cumulative maximum GPIO current per side, bottom IMAXR Cumulative maximum GPIO current per side, right IMAXT Cumulative maximum GPIO current per side, top (1) (2) (2) (2) (2) NOM MAX UNIT 112 mA 97.6 mA 112 mA 80 mA Based on design simulations, not tested in production. Sum of sink and source current for GPIOs as listed in Table 5-1. Table 5-1. Maximum GPIO Package Side Assignments SIDE GPIOs Left PC[4-7], PD[0-3], PQ[0-3], PE[0-3], PK[0-3], PN[4-5], PH[0-3] Bottom PA[0-7], PF[0-4],PG[0-1], PK[4-7] Right PM[0-7], PL[0-7], PB[0-3] Top PC[0-3], PQ[4], PP[0-5], PN[0-5], PJ[0-1], PB[4-5], PE[4-5], PD[4-7] 5.9 I/O Reliability For typical continuous drive applications, I/O pins configured in the range from 2 mA to 12 mA and operating at –40°C to 85°C meet the standard 10-year lifetime reliability. If a continuous current sink of 18 mA is required, then operation is limited to 0 to 75°C to meet the standard 10-year reliability. At 105°C, I/O pins configured for continuous drive meet the standard 2.5-year lifetime reliability. In typical switching applications (40% switch rate) operating at –40°C to 85°C, all I/O configurations except 2 mA meet the standard 10-year lifetime reliability with 50-pF loading. By limiting the capacitive loading to 20 pF for an I/O configured to 2 mA, the 10-year lifetime reliability can be met at –40°C to 85°C. In typical switching applications (40% switch rate) operating at 105°C, all I/O configurations except 2 mA meet the standard 2.5-year lifetime reliability. By reducing the capacitive loading to 20 pF with a typical switching rate at 105°C, a 2-mA I/O configuration meets a 2.5-year lifetime reliability. Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 37 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com 5.10 Current Consumption over operating free-air temperature (unless otherwise noted) (1) SYSTEM CLOCK PARAMETER TEST CONDITIONS VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on including MAC and PHY VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on including MAC but not PHY Run mode (flash loop) VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on except MAC and PHY VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All off IDD_RUN VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on including MAC and PHY VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on including MAC but not PHY Run mode (SRAM loop) VDD = 3.3 V, VDDA = 3.3 V, Peripherals =All on except MAC and PHY VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All off (1) (2) 38 TYP MAX FREQ CLOCK SOURCE –40°C 25°C 85°C 105°C 85°C 105°C 120 MHz MOSC with PLL 96.4 105.3 107.2 108.7 129.9 140.0 60 MHz MOSC with PLL 67.4 76.6 78.6 79.9 100.3 112.5 16 MHz PIOSC 11.9 24.4 25.5 26.7 45.0 56.4 1 MHz PIOSC 5.75 10.9 12.1 13.3 31.3 42.6 120 MHz MOSC with PLL 69.9 77.8 79.6 80.8 98.8 108.4 60 MHz MOSC with PLL 40.9 49.2 50.9 52.1 69.2 80.8 16 MHz PIOSC 11.3 23.6 25.0 26.2 43.1 54.3 1 MHz PIOSC 5.10 10.1 11.5 12.7 29.3 40.5 120 MHz MOSC with PLL 68.1 76.0 77.6 78.6 96.6 106.0 60 MHz MOSC with PLL 40.0 48.2 49.8 50.8 67.9 79.2 16 MHz PIOSC 11.1 23.3 24.6 25.6 42.5 53.3 1 MHz PIOSC 5.07 10.1 11.3 12.3 29.0 39.8 120 MHz MOSC with PLL 35.2 39.1 40.4 41.5 55.8 65.3 60 MHz MOSC with PLL 23.2 29.4 30.7 31.7 45.8 55.5 16 MHz PIOSC 7.38 17.9 19.0 20.0 34.5 44.1 1 MHz PIOSC 4.12 9.13 10.3 11.4 25.7 35.5 120 MHz MOSC with PLL 93.8 103.6 111.6 113.2 133.4 144.6 60 MHz MOSC with PLL 66.9 76.7 78.7 80.0 100.0 111.9 16 MHz PIOSC 12.6 19.0 20.1 21.3 39.1 50.3 1 MHz PIOSC 5.73 10.6 11.7 12.8 30.9 42.2 120 MHz MOSC with PLL 67.2 76.1 84.0 85.4 102.3 113.0 60 MHz MOSC with PLL 40.3 49.2 50.9 52.2 68.9 80.2 16 MHz PIOSC 11.9 18.2 19.6 20.8 37.2 48.2 1 MHz PIOSC 5.08 9.79 11.2 12.3 28.9 40.1 120 MHz MOSC with PLL 65.4 74.3 82.0 83.2 100.1 110.6 60 MHz MOSC with PLL 39.4 48.2 49.8 50.9 67.6 78.6 16 MHz PIOSC 11.7 17.9 19.2 20.2 36.6 47.2 1 MHz PIOSC 5.05 9.75 11.0 11.9 28.6 39.4 120 MHz MOSC with PLL 35.4 43.3 44.7 45.8 59.8 69.0 60 MHz MOSC with PLL 23.4 29.4 30.7 31.7 45.5 54.9 16 MHz PIOSC 7.08 12.4 13.6 14.6 28.7 38.0 1 MHz PIOSC 4.60 8.78 10.0 11.0 25.3 34.9 UNIT (2) mA Section 5.11 lists the current consumption that specific peripherals contribute to the run mode current consumption in Section 5.10. If these peripherals are not powered, then the peripheral current consumption can be subtracted from the run mode consumption in Section 5.10. Applicable to extended temperature devices only. Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Current Consumption (continued) over operating free-air temperature (unless otherwise noted) (1) SYSTEM CLOCK PARAMETER TEST CONDITIONS VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on including MAC and PHY, LDO = 1.2 V Sleep mode (FLASHPM = 0x0) VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on except MAC and PHY, LDO = 1.2 V VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All off, LDO = 1.2 V IDD_SLEEP VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on including MAC and PHY, LDO = 1.2 V Sleep mode (FLASHPM = 0x2) VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on including MAC but not PHY, LDO = 1.2 V VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on except MAC and PHY, LDO = 1.2 V VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All off, LDO = 1.2 V (3) MAX FREQ –40°C 25°C 85°C 105°C 85°C 120 MHz MOSC with PLL 82.8 94.8 96.8 98.1 117.9 129.1 60 MHz MOSC with PLL 60.8 69.2 71.2 72.3 91.8 102.9 PIOSC 11.2 16.8 18.1 19.1 35.4 45.9 5.10 10.3 11.5 12.6 28.9 39.6 120 MHz MOSC with PLL 56.2 67.4 69.1 70.3 87.1 97.8 60 MHz MOSC with PLL 16 MHz 1 MHz VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on including MAC but not PHY, LDO = 1.2 V TYP CLOCK SOURCE PIOSC (3) 105°C 34.4 41.9 43.4 44.5 60.7 71.6 10.6 16.2 17.5 18.5 34.5 45.1 4.47 9.60 10.9 12.0 28.0 38.7 120 MHz MOSC with PLL 54.4 65.6 67.1 68.1 84.9 95.4 60 MHz MOSC with PLL 16 MHz PIOSC (3) 1 MHz PIOSC (3) 33.5 40.9 42.3 43.2 59.4 70.0 10.4 15.9 17.1 17.9 33.9 44.1 4.44 9.56 10.7 11.6 27.7 38.0 120 MHz MOSC with PLL 22.0 28.6 29.8 30.7 44.1 53.1 60 MHz MOSC with PLL 16.3 22.0 23.2 24.1 37.5 46.6 16 MHz PIOSC (3) 1 MHz PIOSC (3) 16 MHz PIOSC (3) 5.37 10.4 11.5 12.4 26.1 35.1 1 MHz PIOSC (3) 4.37 8.60 9.71 10.6 24.6 33.9 120 MHz MOSC with PLL 86.5 89.0 91.2 92.5 112.1 123.5 60 MHz MOSC with PLL 61.6 63.4 65.6 66.7 86.0 97.2 16 MHz PIOSC (3) 10.4 11.1 12.4 13.5 29.8 40.4 1 MHz PIOSC (3) 4.45 4.49 5.83 6.98 23.4 34.2 120 MHz MOSC with PLL 59.9 61.7 63.4 64.7 81.3 92.1 60 MHz MOSC with PLL 35.1 36.1 37.8 38.9 54.9 66.0 9.75 10.4 11.8 12.9 28.9 39.6 3.82 3.82 5.25 6.38 22.5 33.4 120 MHz MOSC with PLL 58.1 59.9 61.4 62.5 79.1 89.7 60 MHz MOSC with PLL 16 MHz PIOSC (3) 1 MHz PIOSC (3) 34.2 35.1 36.7 37.6 53.6 64.4 9.50 10.1 11.4 12.3 28.3 38.6 3.79 3.78 5.06 5.96 22.2 32.7 120 MHz MOSC with PLL 22.0 22.8 24.1 25.1 38.2 47.4 60 MHz MOSC with PLL 16 MHz PIOSC (3) 1 MHz PIOSC (3) 16 MHz PIOSC (3) 1 MHz PIOSC (3) UNIT (2) 15.7 16.2 17.5 18.5 31.7 40.9 4.50 4.60 5.80 6.80 20.5 29.8 3.00 2.80 4.10 5.20 19.1 28.7 mA If the MOSC is the source of the run-mode system clock and is powered down in sleep mode, wake time is increased by tMOSC_SETTLE. Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 39 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Current Consumption (continued) over operating free-air temperature (unless otherwise noted) (1) SYSTEM CLOCK PARAMETER IDD_DEEPSLEEP Deep-sleep mode (FLASHPM = 0x2) All run modes TEST CONDITIONS IDDA_DEEPSLEEP Deep-sleep mode (FLASHPM = 0x2) MAX FREQ –40°C 25°C 85°C 105°C 85°C VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on, LDO = 1.2 V 16 MHz PIOSC 9.74 9.78 10.8 11.6 24.1 32.1 30 kHz LFIOSC 2.60 2.83 3.83 4.60 17.1 25.3 VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All off, LDO = 1.2 V 16 MHz PIOSC 4.53 4.05 4.88 5.53 15.9 22.7 30 kHz LFIOSC 0.614 0.762 1.69 2.46 13.3 20.7 VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on, LDO = 0.9 V 16 MHz PIOSC 5.21 7.33 7.97 8.48 15.3 20.1 30 kHz LFIOSC 2.02 2.16 2.79 3.29 10.0 14.9 VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All off, LDO = 0.9 V (4) 16 MHz PIOSC 1.08 3.10 3.61 4.01 9.50 13.4 30 kHz LFIOSC 0.367 0.454 0.954 1.36 6.86 10.8 120 MHz MOSC with PLL 2.61 2.66 2.68 2.66 3.03 3.35 60 MHz MOSC with PLL 2.61 2.66 2.68 2.66 3.04 3.10 16 MHz PIOSC 2.45 2.49 2.50 2.48 2.85 2.95 1 MHz PIOSC 2.45 2.48 2.50 2.48 2.84 2.90 120 MHz MOSC with PLL 0.227 0.229 0.270 0.250 0.559 0.650 60 MHz MOSC with PLL 0.229 0.232 0.267 0.250 0.579 0.600 16 MHz PIOSC 0.228 0.229 0.265 0.251 0.545 0.575 1 MHz PIOSC 0.227 0.227 0.267 0.247 0.549 0.555 VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on, LDO = 1.2 V 16 MHz PIOSC 2.45 2.48 2.50 2.48 2.84 2.90 30 kHz LFIOSC 2.45 2.48 2.50 2.48 2.85 2.90 VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All off, LDO = 1.2 V 16 MHz PIOSC 0.226 0.227 0.265 0.249 0.558 0.635 30 kHz LFIOSC 0.228 0.227 0.272 0.247 0.558 0.600 VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on, LDO = 0.9 V (4) 16 MHz PIOSC 2.14 2.42 2.44 2.42 2.78 2.88 30 kHz LFIOSC 2.44 2.42 2.44 2.42 2.86 2.88 VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All off, LDO = 0.9 V (4) 16 MHz PIOSC 0.216 0.166 0.209 0.193 0.563 0.580 30 kHz LFIOSC 0.223 0.167 0.209 0.189 0.508 0.580 VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All on IDDA_RUN, IDDA_SLEEP All sleep modes TYP CLOCK SOURCE VDD = 3.3 V, VDDA = 3.3 V, Peripherals = All off 105°C UNIT (2) mA mA mA IHIB_NORTC Hibernate mode (external wake, RTC disabled) VBAT = 3.0 V VDD = 0 V, VDDA = 0 V, System clock = OFF, Hibernate module = 32.768 kHz 1.04 1.20 1.44 1.69 1.62 2.14 µA IHIB_RTC Hibernate mode (RTC enabled) VBAT = 3.0 V, VDD = 0 V, VDDA = 0 V, System clock = OFF, Hibernate module = 32.768 kHz 1.12 1.29 1.54 1.82 1.75 2.33 µA (4) 40 See the System Control chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual for information on lowering the LDO voltage to 0.9 V. Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Current Consumption (continued) over operating free-air temperature (unless otherwise noted) (1) SYSTEM CLOCK PARAMETER TEST CONDITIONS FREQ CLOCK SOURCE TYP –40°C 25°C 85°C 105°C 85°C 7.99 17.0 22.1 31.0 Hibernate mode (VDD3ON mode, tamper enabled) VBAT = 3.0 V, VDD = 3.3 V, VDDA = 3.3 V, System clock = OFF, Hibernate module = 32.768 kHz 6.78 Hibernate mode (VDD3ON mode, tamper disabled) VBAT = 3.0 V, VDD = 3.3 V, VDDA = 3.3 V, System clock = OFF, Hibernate module = 32.768 kHz 5.42 IHIB_VDD3ON MAX 105°C UNIT (2) 46.2 µA 6.39 15.4 17.8 28.9 32.0 5.11 Peripheral Current Consumption over operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS SYSTEM CLOCK TYP UNIT IDDUSB USB (including USB PHY) run mode current VDD = 3.3 V, VDDA = 3.3 V 120 MHz (MOSC with PLL) 4.0 mA IDDEMAC Ethernet MAC run mode current VDD = 3.3 V, VDDA = 3.3 V 120 MHz (MOSC with PLL) 1.9 mA IDDEMACPHY Ethernet MAC and PHY run mode current VDD = 3.3 V, VDDA = 3.3 V 120 MHz (MOSC with PLL) 30 mA MAX UNIT 5.12 LDO Regulator Characteristics over operating free-air temperature (unless otherwise noted) PARAMETER CLDO External filter capacitor size for internal power supply (1) ESR Filter capacitor equivalent series resistance ESL Filter capacitor equivalent series inductance VLDO LDO output voltage, run mode IINRUSH Inrush current (1) MIN TYP 2.5 4.0 µF 0 100 mΩ 0.5 nH 1.13 50 1.2 1.27 V 250 mA Connect the capacitor as close as possible to pin 115. Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 41 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com 5.13 Power Dissipation over operating free-air temperature (unless otherwise noted) PARAMETER PDE (1) (2) (1) (2) TA Extended temperature device power dissipation 105°C (extended temperature part) TJ MIN 125°C (extended temperature part) MAX UNIT 452 mW If the device exceeds the power dissipation value shown, then modifications such as heat sinks or fans must be used to conform to the limits shown. A larger power dissipation allowance can be achieved by lowering TA as long as TJMAX shown in Section 5.1 is not exceeded. 5.14 Thermal Resistance Characteristics, 128-Pin PDT (TQFP) Package over operating free-air temperature range (unless otherwise noted) THERMAL METRIC θJA Thermal resistance (junction to ambient) θJB Thermal resistance (junction to board) (1) (1) (1) VALUE UNIT 44.2 °C/W 22.4 °C/W θJC Thermal resistance (junction to case) 6.8 °C/W ΨJT Thermal metric (junction to top of package) 0.2 °C/W ΨJB Thermal metric (junction to board) 22.1 °C/W TC + (P × ΨJT) (2) TPCB + (P × ΨJB) (3) TA + (P × θJA) (4) TB + (P × θJB) (5) (6) °C TJ (1) (2) (3) (4) (5) (6) 42 Junction temperature formula Junction to ambient thermal resistance (θJA), junction to board thermal resistance (θJB), and junction to case thermal resistance (θJC) numbers are determined by a package simulator. TC is the case temperature and P is the device power consumption. TPCB is the temperature of the board acquired by following the steps listed in the EAI/JESD 51-8 standard summarized in Semiconductor and IC Package Thermal Metrics. P is the device power consumption. Because θJA is highly variable and based on factors such as board design, chip size, pad size, altitude, and external ambient temperature, TI recommends using the equations that contain ΨJT and ΨJB for best results. TB is temperature of the board. θJB is not a pure reflection of the internal resistance of the package because it includes the resistance of the testing board and environment. TI recommends using equations that contain ΨJT and ΨJB for best results. Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 5.15 Timing and Switching Characteristics 5.15.1 Load Conditions Table 5-2 shows the load conditions used for timing measurements, and Table 5-2 lists the load values for the specified signals. Pin CL Figure 5-1. Load Conditions Table 5-2. Load Conditions SIGNALS LOAD VALUE (CL) EPI0S[35:0] SDRAM interface EPI0S[35:0] general-purpose interface 30 pF EPI0S[35:0] host-bus interface EPI0S[35:0] PSRAM interface 40 pF All other digital I/O signals 50 pF 5.15.2 Power Supply Sequencing To ensure proper operation, power on VDDA before VDD if sourced from different supplies, or connect VDDA to the same supply as VDD. No restriction exists for powering off. 5.15.2.1 Power and Brownout Table 5-3. Power and Brownout Levels over operating free-air temperature (unless otherwise noted) NO. PARAMETER MIN TYP MAX UNIT P1 tVDDA_RISE Analog supply voltage (VDDA) rise time ∞ µs P2 tVDD_RISE I/O supply voltage (VDD) rise time ∞ µs P3 tVDDC_RISE Core supply voltage (VDDC) rise time 150 µs P4 VPOR 10 Power-on reset threshold (rising edge) 1.98 2.35 2.72 Power-on reset threshold (falling edge) 1.84 2.20 2.56 Power-on reset hysteresis 0.06 0.15 0.24 V P5 VDDA_POK VDDA power-OK threshold (rising edge) 2.67 2.82 2.97 V P6 VDDA_BOR0 VDDA brownout reset threshold 2.71 2.80 2.89 V VDD power-OK threshold (rising edge) 2.65 2.80 2.90 VDD power-OK threshold (falling edge) 2.67 2.76 2.85 VDD brownout reset threshold 2.77 2.86 2.95 VDDC power-OK threshold (rising edge) 0.85 0.95 1.10 VDDC power-OK threshold (falling edge) 0.71 0.80 0.85 P7 VDD_POK P8 VDD_BOR0 P9 VDDC_POK Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y V V V 43 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com 5.15.2.1.1 VDDA Levels The VDDA supply has three monitors: • Power-on reset (POR) • Power-OK (POK) • Brownout reset (BOR) The POR monitor is used to keep the analog circuitry in reset until the VDDA supply reaches the correct range for the analog circuitry to begin operating. The POK monitor is used to keep the digital circuitry in reset until the VDDA power supply is at an acceptable operational level. The digital reset is only released when the Power-On Reset has deasserted and the Power-OK monitor for each supply indicates that power levels are in operational ranges. The BOR monitor is used to generate a reset to the device or assert an interrupt if the VDDA supply drops below its operational range. NOTE VDDA BOR and VDD BOR events are a combined BOR to the system logic, such that if either BOR event occurs, the following bits are affected: • The BORRIS bit in the Raw Interrupt Status (RIS) register, System Control offset 0x050 • The BORMIS bit in the Masked Interrupt Status and Clear (MISC) register, System Control offset 0x058. This bit is set only if the BORIM bit in the Interrupt Mask Control (IMC) register has been set. • The BOR bit in the Reset Cause (RESC) register, System Control offset 0x05C. This bit is set only if either of the BOR events have been configured to initiate a reset. In addition, the following bits control both BOR events: • The BORIM bit in the Interrupt Mask Control (IMC) register, System Control offset 0x054 • The VDDA_UBOR0 and VDD_UBOR0 bits in the Power-Temperature Cause (PWRTC) register See the System Control chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual for more information on how to configure these registers. Figure 5-2 shows the relationship between VDDA, POK, POR, and a BOR event. P1 VDDAMIN VDDA P5RISE P6 P4 P4 BOR POK POR 1 0 1 0 1 0 Figure 5-2. Power and Brownout Assertions vs VDDA Levels 44 Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 5.15.2.1.2 VDD Levels The VDD supply has two monitors: • Power-OK (POK) • Brownout reset (BOR) The POK monitor is used to keep the digital circuitry in reset until the VDD power supply reaches an acceptable operational level. The digital reset is only released when the POR has deasserted and the POK monitor for each supply indicates that power levels are in operational ranges. The BOR monitor is used to generate a reset to the device or assert an interrupt if the VDD supply drops below its operational range. NOTE VDDA BOR and VDD BOR events are a combined BOR to the system logic, such that if either BOR event occurs, the following bits are affected: • The BORRIS bit in the Raw Interrupt Status (RIS) register, System Control offset 0x050 • The BORMIS bit in the Masked Interrupt Status and Clear (MISC) register, System Control offset 0x058. This bit is set only if the BORIM bit in the Interrupt Mask Control (IMC) register has been set. • The BOR bit in the Reset Cause (RESC) register, System Control offset 0x05C. This bit is set only if either of the BOR events have been configured to initiate a reset. In addition, the following bits control both BOR events: • The BORIM bit in the Interrupt Mask Control (IMC) register, System Control offset 0x054 • The VDDA_UBOR0 and VDD_UBOR0 bits in the Power-Temperature Cause (PWRTC) register See the System Control chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual for more information on how to configure these registers. Figure 5-3 shows the relationship between VDD, POK, POR, and a BOR event. P2 VDDMIN P8 POK 1 BOR VDD P7RISE 1 P7FALL 0 0 Figure 5-3. Power and Brownout Assertions vs VDD Levels Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 45 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com 5.15.2.1.3 VDDC Levels The VDDC supply has one monitor, the Power-OK (POK). The POK monitor is used to keep the digital circuitry in reset until the VDDC power supply reaches an acceptable operational level. The digital reset is only released when the power-on reset has deasserted and the POK monitor for each supply indicates that power levels are in operational ranges. Figure 5-4 shows the relationship between POK and VDDC. P3 1.2V POK VDDC P9RISE P9FALL 1 0 Figure 5-4. POK Assertion vs VDDC 5.15.2.1.4 VDD Glitch Response Figure 5-5 shows the response of the BOR and the POR circuit to glitches on the VDD supply. Figure 5-5. POR-BOR VDD Glitch Response 5.15.2.1.5 VDD Droop Response Figure 5-6 shows the response of the BOR and the POR monitors to a drop on the VDD supply. Figure 5-6. POR-BOR VDD Droop Response 5.15.3 Reset Timing Table 5-4 lists the reset characteristics. 46 Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Table 5-4. Reset Characteristics over operating free-air temperature (unless otherwise noted) NO. tDPORDLY R2 tIRTOUT R3 tBOR0DLY (4) (5) (6) (7) MIN Digital POR to internal reset assertion delay (see Figure 5-7) (1) (2) Standard internal reset time 14 Internal reset time with recovery code repair (program or erase) (3) (1) BOR0 to internal reset assertion delay TYP 0.44 (5) (see Figure 5-8) MAX UNIT 126 µs 16 6400 (4) 24.4 0.44 125 ms µs 0.25 (6) or 100 (7) µs R4 tRSTMIN Minimum RST pulse duration R5 tIRHWDLY RST to internal reset assertion delay (see Figure 5-9) 0.85 µs (1) Internal reset time-out after software-initiated system reset (see Figure 5-10) 2.44 µs R6 tIRSWR R7 tIRWDR (1) Internal reset time-out after watchdog reset (see Figure 5-11) 2.44 µs tIRMFR (1) Internal reset time-out after MOSC failure reset (see Figure 5-12) 2.44 µs R8 (1) (2) (3) PARAMETER R1 These values are based on simulation. This is the delay from the time POR is released until the reset vector is fetched. This parameter applies only in situations where a power-loss or brownout event occurs during an EEPROM program or erase operation, and EEPROM must be repaired (which is a rare case). For all other sequences, there is no change to normal POR timing. This delay is in addition to other POR delays. This value represents the maximum internal reset time when the EEPROM reaches its endurance limit. Timing values depend on the VDD power-down ramp rate. Standard operation Deep-sleep operation with PIOSC powered down Digital POR R1 R2 Reset (Internal) Figure 5-7. Digital Power-On Reset Timing The digital power-on reset is released only when the analog power-on reset has deasserted and the Power-OK monitor for each supply indicates that power levels are in operational ranges. BOR R3 R2 Reset (Internal) Figure 5-8. Brownout Reset Timing Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 47 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com R4 RST (Package Pin) R5 R2 Reset (Internal) Figure 5-9. External Reset Timing (RST) Software Reset R6 Reset (Internal) Figure 5-10. Software Reset Timing Watchdog Reset R7 Reset (Internal) Figure 5-11. Watchdog Reset Timing MOSC Fail Reset R8 Reset (Internal) Figure 5-12. MOSC Failure Reset Timing 48 Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 5.15.4 Clock Specifications The following sections provide specifications on the various clock sources and mode. 5.15.4.1 PLL Specifications Table 5-5 lists the PLL characteristics. NOTE If the integrated Ethernet PHY is used, fREF_XTAL and fREF_EXT must be 25 MHz. Table 5-5. Phase Locked Loop (PLL) Characteristics over operating free-air temperature (unless otherwise noted) PARAMETER MIN MAX UNIT fREF_XTAL Crystal reference 5 25 MHz fREF_EXT External clock reference 5 25 MHz fPLLR PLL VCO frequency at 1.2 V (1) 100 480 MHz fPLLS PLL VCO frequency at 0.9 V (2) 100 480 MHz tREADY (1) (2) PLL lock time Enabling the PLL, when PLL is transitioning from power down to power up 512 × (reference clock period) When the PLL VCO frequency is changed (PLL is already enabled) 128 × (reference clock period) Changing the OSCSRC between MOSC and PIOSC 128 × (reference clock period) µs PLL frequency is manually calculated using the values in the PLLFREQ0 and PLLFREQ1 registers. If the LDO is dropped to 0.9 V, the system must be run 1/4 of the maximum frequency at most. The Q value in the PLLFREQ1 register must be set to 0x3 rather than using the PSYSDIV field in the RSCLKCFG register for the divisor. 5.15.4.1.1 PLL Configuration The PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency and enables the PLL to drive the output. The PLL is controlled using the PLLFREQ0, PLLFREQ1, and PLLSTAT registers. Changes made to these registers do not become active until after the NEWFREQ bit in the RSCLKCFG register is enabled. The clock source for the main PLL is selected by configuring the PLLSRC field in the Run and Sleep Clock Configuration (RSCLKCFG) register. The PLL allows for the generation of system clock frequencies in excess of the reference clock provided. The reference clocks for the PLL are the PIOSC and the MOSC. The PLL is controlled by two registers, PLLFREQ0 and PLLFREQ1. The PLL VCO frequency (fVCO) is determined through Equation 1. fVCO = fIN × MDIV where • • fIN = fXTAL / (Q+1)(N+1) or fPIOSC / (Q+1)(N+1) MDIV = MINT + (MFRAC / 1024) (1) The Q and N values are programmed in the PLLFREQ1 register. To reduce jitter, program MFRAC to 0x0. When the PLL is active, the system clock frequency (SysClk) is calculated using Equation 2. SysClk = fVCO / (1 + 1) (2) The PLL system divisor factor (PSYSDIV) must be set as 1. Table 5-6 lists examples of the system clock frequency. Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 49 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 5-6. Examples of System Clock Frequencies fVCO (MHz) Q PSYSDIV + 1 System Clock (SYSCLK) Frequency (MHz) 480 2 2 120 480 3 2 80 480 4 2 60 480 5 2 48 320 2 2 80 320 3 2 53 320 4 2 40 If the main oscillator provides the clock reference to the PLL, the translation provided by hardware and used to program the PLL is available for software in the PLL Frequency n (PLLFREQn) registers. The internal translation provides a translation within ±1% of the targeted PLL VCO frequency. Table 5-7 shows the actual PLL frequency and error for a given crystal choice. Table 5-7 provides examples of the programming expected for the PLLFREQ0 and PLLFREQ1 registers. The CRYSTAL FREQUENCY column specifies the input crystal frequency and the PLL FREQUENCY column displays the PLL frequency given the values of MINT and N, when Q = 0. Table 5-7. Actual PLL Frequency (1) (1) (2) 50 MINT DECIMAL VALUE HEXADECIMAL VALUE N REFERENCE FREQUENCY (MHz) (2) PLL FREQUENCY (MHz) 5 64 0x40 0x0 5 320 6 160 0x35 0x2 2 320 8 40 0x28 0x0 8 320 10 32 0x20 0x0 10 320 12 80 0x50 0x2 4 320 16 20 0x14 0x0 16 320 18 160 0xA0 0x8 2 320 20 16 0x10 0x0 20 320 24 40 0x28 0x2 8 320 25 64 0x40 0x4 5 320 5 96 0x60 0x0 5 480 6 80 0x50 0x0 6 480 8 60 0x3C 0x0 8 480 10 48 0x30 0x0 10 480 12 40 0x28 0x0 12 480 16 30 0x1E 0x0 16 480 18 80 0x50 0x2 6 480 20 24 0x18 0x0 20 480 24 20 0x14 0x0 24 480 25 96 0x60 0x4 5 480 CRYSTAL FREQUENCY (MHz) For all examples listed, Q = 0. For a given crystal frequency, N should be chosen such that the reference frequency is 4 to 30 MHz. Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 5.15.4.2 PIOSC Specifications Table 5-8 lists the PIOSC characteristics. Table 5-8. PIOSC Clock Characteristics PARAMETER MIN NOM Factory calibration, 0°C to 105°C: Internal 16-MHz precision oscillator frequency variance across voltage and temperature range when factory calibration is used fPIOSC Factory calibration, –40°C to 3.3 V VIH (1) (2) (3) (4) (2) Oscillator output drive level tSTART VIL Total shunt capacitance NOM 32.768 0.2 × VSupply 360 30% 960 1390 V mV 70% The Hibernation XOSC pins are not fail-safe and must follow the limits in Section 5.15.9.1.2. See the additional information about the load capacitors following this table. Crystal ESR specified by crystal manufacturer. Oscillator start-up time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation such that the internal clock is valid. Only valid for recommended supply conditions. Measured with OSCDRV bit set (high drive strength enabled, 24 pF). Specification is relative to the larger of VDD or VBAT. Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 51 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Choose the load capacitors added on the board, C1 and C2, such that Equation 3 is satisfied (see Table 510 for typical values). CL = (C1 × C2) / (C1 + C2) + CSHUNT where • • • • • • CL = load capacitance specified by crystal manufacturer CSHUNT = CPKG + CPCB + C0 (total shunt capacitance seen across XOSC0 and XOSC1) CPKG, CPCB as measured across the XOSC0 and XOSC1 pins excluding the crystal Clear the OSCDRV bit in the Hibernation Control (HIBCTL) register for C1,2 ≤ 18 pF Set the OSCDRV bit for C1,2 > 18 pF C0 = Shunt capacitance of crystal specified by the crystal manufacturer (3) Table 5-11 lists the characteristics of the Hibernation module low-frequency oscillator. Table 5-11. Hibernation Internal Low-Frequency Oscillator Clock Characteristics PARAMETER fHIBLFIOSC MIN NOM MAX 10 33 90 kHz MIN NOM Internal low-frequency hibernation oscillator frequency UNIT 5.15.4.5 Main Oscillator Specifications Table 5-12 lists the required characteristics of the main oscillator input. Table 5-12. Main Oscillator Input Characteristics over operating free-air temperature (unless otherwise noted) (1) PARAMETER fMOSC Parallel resonance frequency fREF_XTAL_BYPASS External clock reference (PLL in BYPASS mode) 4 C1, C2 External load capacitance on OSC0, OSC1 pins CPKG Device package stray shunt capacitance CPCB PCB stray shunt capacitance CSHUNT Total shunt capacitance ESR (3) MHz 12 24 pF 0.5 pF 0.5 (3) pF 4 4 MHz (4) (5) 300 6 MHz (4) (5) 200 8 MHz (4) (5) 130 12 MHz (4) (5) 120 16 MHz (4) (5) 100 25 MHz (4) (5) Oscillator start-up time, when using a crystal (7) VIL CMOS input low level, when using an external oscillator VHYS CMOS input buffer hysteresis, when using an external oscillator DCOSC_EXT External clock reference duty cycle pF Ω 50 OSCPWR CMOS input high level, when using an external oscillator 52 MHz 120 (3) VIH (7) 25 0 Oscillator output drive level (6) TSTART (6) UNIT (3) Crystal effective series resistance DL (1) (2) (3) (4) (5) MAX (2) mW 18 ms 0.65 × VDD VDD V GND 0.35 × VDD V 150 45% mV 55% See Table 5-39 and Table 5-40 for additional Ethernet crystal requirements. 5 MHz is the minimum when using the PLL. See the additional information about the load capacitors following this table. Crystal ESR specified by crystal manufacturer. Crystal vendors can be contacted to confirm these specifications are met for a specific crystal part number if the vendors generic crystal datasheet show limits outside of these specifications. OSCPWR = (2 × π × FP × CL × 2.5)2 × ESR / 2. An estimation of the typical power delivered to the crystal is based on the CL, FP and ESR parameters of the crystal in the circuit as calculated by the OSCPWR equation. Ensure that the value calculated for OSCPWR does not exceed the crystal's drive-level maximum. Oscillator start-up time is specified from the time the oscillator is enabled to when it reaches a stable point of oscillation such that the internal clock is valid. Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 The load capacitors added on the board, C1 and C2, should be chosen such that Equation 4 is satisfied (see Table 5-12 for typical values and Table 5-13 for detailed crystal parameter information). CL = (C1 × C2) / (C1 + C2) + CSHUNT where • • • • CL = load capacitance specified by crystal manufacturer CSHUNT = C0 + CPKG + CPCB (total shunt capacitance seen across OSC0 and OSC1 crystal inputs) CPKG, CPCB = Mutual capacitance as measured across the OSC0 and OSC1 pins excluding the crystal C0 = Shunt capacitance of crystal specified by the crystal manufacturer (4) Table 5-13 lists part numbers of crystals that have been simulated and confirmed to operate within the specifications in Table 5-12. Other crystals that have nearly identical crystal parameters can be expected to work as well. In Table 5-13, the crystal parameters labeled C0, C1, and L1 are values that are obtained from the crystal manufacturer. These numbers are usually a result of testing a relevant batch of crystals on a network analyzer. The parameters labeled ESR, DL, and CL are maximum numbers usually available in the data sheet for a crystal. Table 5-13 also includes three columns of Recommended Component Values. These values apply to system board components. C1 and C2 are the values in picofarads of the load capacitors that should be put on each leg of the crystal pins to ensure oscillation at the correct frequency. Rs is the value in kΩ of a resistor that is placed in series with the crystal between the OSC1 pin and the crystal pin. Rs dissipates some of the power so the Max Dl crystal parameter is not exceeded. Only use the recommended C1, C2, and Rs values with the associated crystal part. The values in the table were used in the simulation to ensure crystal start-up and to determine the worst-case drive level (WC DL). The value in the WC DL column should not be greater than the Max DL crystal parameter. The WC DL value can be used to determine if a crystal with similar parameter values but a lower Max DL value is acceptable. Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 53 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 5-13. Crystal Parameters Crystal Parameters Manufacturer Part Number Manufacturer 54 Package Size (mm × mm) Frequency (MHz) Typical Values Recommended Component Values Max Values C0 (pF) C1 (fF) L1 (mH) ESR (Ω) Max DL (µW) CL (pf) C1 (pF) C2 (pF) Rs (kΩ) WC DL (µW) NX8045GB-4.000MSTD-CJL-5 NX8045GB 8 × 4.5 4 30 / 50 ppm 1.00 2.70 598.10 300 500 8 12 12 0 132 FOX FQ1045A-4 2-SMD 10 × 4.5 4 30 / 30 ppm 1.18 4.05 396.00 150 500 10 14 14 0 103 NDK NX8045GB-5.000MSTD-CSF-4 NX8045GB 8 × 4.5 5 30 / 50 ppm 1.00 2.80 356.50 250 500 8 12 12 0 164 NDK NX8045GB-6.000MSTD-CSF-4 NX8045GB 8 × 4.5 6 30 / 50 ppm 1.30 4.10 173.20 250 500 8 12 12 0 214 FOX FQ1045A-6 2-SMD 10 × 4.5 6 30 / 30 ppm 1.37 6.26 112.30 150 500 10 14 14 0 209 NDK NX8045GB-8.000MSTD-CSF-6 NX8045GB 8 × 4.5 8 30 / 50 ppm 1.00 2.80 139.30 200 500 8 12 12 0 277 217 NDK (1) (2) Holder Crystal Specification (Tolerance / Stability) FOX FQ7050B-8 4-SMD 7×5 8 30 / 30 ppm 1.95 6.69 59.10 80 500 10 14 14 0 ECS ECS-80-16-28A-TR HC49/US 12.5 × 4.85 8 50 / 30 ppm 1.82 4.90 85.70 80 500 16 24 24 0 Abracon AABMM-12.0000MHz10-D-1-X-T ABMM 7.2 × 5.2 12 10 / 20 ppm 2.37 8.85 20.5 50 500 10 12 12 NDK NX3225GA-12.000MHZSTD-CRG-2 NX3225GA 3.2 × 2.5 12 20 / 30 ppm 0.70 2.20 81.00 100 200 8 12 12 2.5 147 NDK NX5032GA-12.000MHZLN-CD-1 NX5032GA 5 × 3.2 12 30 / 50 ppm 0.93 3.12 56.40 120 500 8 12 12 0 362 FOX FQ5032B-12 4-SMD 5 × 3.2 12 30 / 30 ppm 1.16 4.16 42.30 80 500 10 14 14 0 370 Abracon AABMM-16.0000MHz10-D-1-X-T ABMM 7.2 × 5.2 16 10 / 20 ppm 3.00 11.00 9.30 50 500 10 12 12 2.0 (1) 143 Ecliptek ECX-6595-16.000M HC-49/UP 13.3 × 4.85 16 15 / 30 ppm 3.00 12.7 8.1 50 1000 10 12 12 2.0 (1) 139 NDK NX3225GA-16.000MHZSTD-CRG-2 NX3225GA 3.2 × 2.5 16 20 / 30 ppm 1.00 2.90 33.90 80 200 8 12 12 2 188 NDK NX5032GA-16.000MHZLN-CD-1 NX5032GA 5 × 3.2 16 30 / 50 ppm 1.02 3.82 25.90 500 8 10 10 0 437 ECS ECS-160-9-42-CKM-TR ECX-42 4 × 2.5 16 10 / 10 ppm 1.47 3.90 25.84 300 9 12 12 0.5 Abracon AABMM-25.0000MHz10-D-1-X-T ABMM 7.2 × 5.2 25 10 / 20 ppm 3.00 11.00 3.70 120 60 50 (2) 500 10 12 12 2.0 298 (1) 124 289 2.0 (1) 158 (1) 159 Ecliptek ECX-6593-25.000M HC-49/UP 13.3 × 4.85 25 15 / 30 ppm 3.00 12.8 3.2 40 1000 10 12 12 1.5 NDK NX3225GA-25.000MHZSTD-CRG-2 NX3225GA 3.2 × 2.5 25 20 / 30 ppm 1.10 4.70 8.70 50 200 8 12 12 2 181 RS values as low as 0 Ω can be used. Using a lower RS value causes the WC DL to increase toward the maximum DL of the crystal. Although this ESR value is outside of the recommended crystal ESR maximum for this frequency, this crystal has been simulated to confirm proper operation and is valid for use with this device. Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Table 5-13. Crystal Parameters (continued) Crystal Parameters Manufacturer Holder Package Size (mm × mm) Frequency (MHz) Typical Values C0 (pF) C1 (fF) L1 (mH) ESR (Ω) Max DL (µW) 1.3 5.1 7.1 70 500 NX5032GA AURIS Q-25.000M-HC3225/4F-30-30-E-12-TR HC3225/4 3.2 × 2.5 25 30 / 30 ppm 1.58 5.01 8.34 50 500 FOX FQ5032B-25 4-SMD 5 × 3.2 25 30 / 30 ppm 1.69 7.92 5.13 50 500 TXC 7A2570018 NX5032GA 5 × 3.2 5 × 3.2 25 25 30 / 50 ppm 20 / 25 ppm 2.0 6.7 Recommended Component Values Max Values NX5032GA-25.000MHZLD-CD-1 NDK (3) Manufacturer Part Number Crystal Specification (Tolerance / Stability) 6.1 30 350 CL (pf) 8 C1 (pF) C2 (pF) 10 10 12 12 12 16 10 14 10 12 Rs (kΩ) 1.0 (1) 0.75 WC DL (µW) 216 (3) 269 16 1 331 14 0.5 12 2.0 (3) 433 124 RS values as low as 500 Ω can be used. Using a lower RS value causes the WC DL to increase toward the maximum DL of the crystal. Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y 55 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com 5.15.4.6 Main Oscillator Specification WIth ADC Table 5-14 lists the system clock characteristics with ADC operation. Table 5-14. System Clock Characteristics With ADC Operation PARAMETER fsysadc MIN NOM System clock frequency when the ADC module is operating (when PLL is bypassed) MAX 16 UNIT MHz 5.15.4.7 System Clock Characteristics With USB Operation Table 5-15 lists the system clock characteristics with USB operation. Table 5-15. System Clock Characteristics With USB Operation PARAMETER fsysusb MIN System clock frequency when the USB module is operating (MOSC must be the clock source, either with or without using the PLL) NOM MAX 30 UNIT MHz 5.15.5 Sleep Modes The following tables can be used to calculate the maximum wake time from sleep or deep sleep mode, depending on the specific application. Depending on the application configuration, each parameter, except for tFLASH, adds sequential latency to the wake time. Flash restoration happens in parallel to the other wake processes, and its wake time is normally absorbed by the other latencies. As an example, the wake time for a device in deep sleep mode with the PIOSC and PLL turned off and the flash and SRAM in lowpower mode is calculated by Equation 5. Wake Time = tPIOSCDS + tPLLDS + tSRAMLPDS (5) tFLASH does not contribute to this equation because the values of the other parameters are greater. In sleep mode, the wake time due to a clock source is zero because the device uses the same clock configuration in run mode; thus, there is no latency involved with respect to the clocks. Table 5-16 lists the wake-up times from sleep mode. Table 5-16. Wake From Sleep Characteristics over operating free-air temperature (unless otherwise noted) NO. 56 MAX UNIT D1 tPIOSC Time to restore PIOSC as system clock in sleep mode PARAMETER N/A µs D2 tMOSC Time to restore MOSC as system clock in sleep mode N/A µs D3 tPLL Time to restore PLL as system clock in sleep mode N/A µs D4 tLDO Time to restore LDO to 1.2 V in sleep mode 39 µs D5 tFLASH Time to restore flash to active state from low-power state in sleep mode 96 µs D6 tSRAMLP Time to restore SRAM to active state from low-power state in sleep mode 15 µs D7 tSRAMSTBY Time to restore SRAM to active state from standby state in sleep mode 15 µs Specifications MIN TYP Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 Table 5-16 lists the wake-up times from deep sleep mode. Table 5-17. Wake From Deep Sleep Characteristics over operating free-air temperature (unless otherwise noted) NO. (1) PARAMETER MIN TYP MAX UNIT D8 tPIOSCDS Time to restore PIOSC as system clock in deep sleep mode 14 deepsleep clock cycles D9 tMOSCDS Time to restore MOSC as system clock in deep sleep mode 18 ms 1 cycle of deep sleep clock + 512 cycles of PLL reference clock (1) clock cycles D10 tPLLDS Time to restore PLL as system clock in deep sleep mode D11 tLDODS Time to restore LDO to 1.2 V in deep sleep mode 39 µs D12 tFLASHLPDS Time to restore flash to active state from low-power state 96 µs D13 tSRAMLPDS Time to restore SRAM to active state from low-power state 15 µs D14 tSRAMSTBYDS Time to restore SRAM to active state from standby state 15 µs Deep sleep clock can vary. See the System Control chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual for the deep sleep clock options. 5.15.6 Hibernation Module The Hibernation module requires special system implementation considerations because it is intended to power down all other sections of its host device. See the Hibernation Module chapter of the MSP432E4 SimpleLink™ Microcontrollers Technical Reference Manual. Table 5-18 lists the required characteristics of the Hibernation module battery. Table 5-18. Hibernation Module Battery Characteristics over operating free-air temperature (unless otherwise noted) PARAMETER VBAT Battery supply voltage VBATRMP VBAT battery supply voltage ramp time VLOWBAT Low-battery detect voltage MIN NOM MAX 1.8 3.0 3.6 V 0.7 V/µs 0 VBATSEL = 0x0 1.8 1.9 2.0 VBATSEL = 0x1 2.0 2.1 2.2 VBATSEL = 0x2 2.2 2.3 2.4 VBATSEL = 0x3 2.4 2.5 2.6 Specifications Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y UNIT V 57 MSP432E401Y SLASEN5 – OCTOBER 2017 www.ti.com Table 5-19 lists the timing characteristics of the HIB module. Table 5-19. Hibernation Module Characteristics over operating free-air temperature (unless otherwise noted) (see Figure 5-13) NO. MIN tWAKE WAKE assertion time H2 tWAKE_TO_HIB WAKE assert to HIB desassert (wake-up time) H3 tVDD_RAMP VDD ramp to 3.0 V H4 tVDD_CODE VDD at 3 V to internal POR deassert; first instruction executes H5 (1) PARAMETER H1 DCRTCCLK TYP MAX UNIT 100 ns 1 See HIB module clock period (1) µs 500 Duty cycle for RTCCLK output signal, when using a 32.768‑kHz crystal 40% 60% Duty cycle for RTCCLK output signal, when using a 32.768‑kHz external single-ended (bypass) clock source 30% 70% µs Depends on characteristics of power supply. H1 WAKE H2 HIB H3 VDD H4 POR Figure 5-13. Hibernation Module Timing Table 5-20 lists the characteristics of the HIB module tamper detection. Table 5-20. Hibernation Module Tamper I/O Characteristics over operating free-air temperature (unless otherwise noted) MIN TYP MAX RTPU TMPRn pullup resistor PARAMETER 3.5 4.4 5.2 tSP TMPRn pulse duration with short glitch filter 62 µs tLP TMPRn pulse duration with long glitch filter 94 ms tNMIS TMPRn assertion to NMI (short glitch filter) tNMIL TMPRn assertion to NMI (long glitch filter) VIH 58 TMPRn high-level input voltage when operating from VBAT Specifications VBAT × 0.8 UNIT MΩ 95 µs 94 ms V Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP432E401Y MSP432E401Y www.ti.com SLASEN5 – OCTOBER 2017 5.15.7 Flash Memory Table 5-21 lists the characteristics of the flash memory. Table 5-21. Flash Memory Characteristics over operating free-air temperature (unless otherwise noted) PARAMETER MIN PECYC Number of program and erase cycles 100000 cycles tRET Data retention with 100% power-on hours at TJ = 85°C 20 years tRET_EXTEMP Data retention with 10% power-on hours at TJ = 125°C and 90% power-on hours at TJ = 100°C 11 years tPROG64 Program time for double-word-aligned (64 bits) data 30 tERASE Page erase time tME Mass erase time TYP MAX 100 300