User's Guide
SLAU780 – August 2018
MSP432E411Y-BGAEVM User's Guide
This guide provides an overview on how to get started quickly with the MSP432E411Y-BGAEVM,
including power, header pinouts and connections, communication interfaces, and programming interfaces.
1
2
3
4
5
6
7
Contents
Board Overview .............................................................................................................. 2
Power the MSP432E411Y-BGAEVM ..................................................................................... 3
2.1
Emulator Power ..................................................................................................... 3
2.2
External 3.3-V Source Only ....................................................................................... 3
2.3
External 5-V Source Only .......................................................................................... 3
2.4
External 3.3-V and 5-V Source ................................................................................... 4
2.5
Measure Current Consumption ................................................................................... 4
Header Pinouts and Connections ......................................................................................... 5
3.1
J11 – External Power Connector ................................................................................. 5
3.2
J6 – Power Rail Header............................................................................................ 5
3.3
J7 – External Peripheral Interface Header ...................................................................... 6
3.4
LCD Interface Header .............................................................................................. 7
3.5
J1, J2, J3, J4 – BoosterPack Interface Headers ............................................................... 9
3.6
J5 – Additional GPIO Pin Header ............................................................................... 10
Communication Interfaces ................................................................................................ 11
4.1
Ethernet............................................................................................................. 11
4.2
USB-OTG .......................................................................................................... 11
Programming Interfaces ................................................................................................... 12
5.1
JTAG ................................................................................................................ 12
5.2
ETM Trace ......................................................................................................... 12
5.3
BSL .................................................................................................................. 13
Software Development .................................................................................................... 14
6.1
Software Description .............................................................................................. 14
6.2
Source Code ....................................................................................................... 14
6.3
Tool Options ....................................................................................................... 14
Schematics .................................................................................................................. 15
Trademarks
SimpleLink, BoosterPack, Code Composer Studio are trademarks of Texas Instruments.
Arm, Cortex, Keil are registered trademarks of Arm Limited.
IAR Embedded Workbench is a registered trademark of IAR Systems.
All other trademarks are the property of their respective owners.
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1
Board Overview
1
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Board Overview
The SimpleLink™ Ethernet MSP432E411Y microcontroller EVM is an evaluation platform for SimpleLink
Arm® Cortex®-M4F-based Ethernet microcontrollers. The MSP432E411Y-BGAEVM demonstrates the
MSP432E411Y microcontroller with its on-chip 10/100 Ethernet MAC and PHY, USB 2.0, LCD controller,
External Peripheral Interface (EPI), hibernation module, motion control pulse-width modulation, and a
multitude of simultaneous serial connectivity. The MSP432E411Y-BGAEVM also features a fully compliant
40-pin BoosterPack™ plug-in module header, a user switch, two user LEDs, and dedicated reset and
wake switches.
The preprogrammed quick start application on the EVM is an application that performs a self-test on the
onboard SDRAM by writing and reading back values in memory using the MSP432E411Y EPI. The selftest blinks an LED to indicate that the test passes. Figure 1 shows the MSP432E411Y-BGAEVM with key
features highlighted.
Figure 1. SimpleLink Ethernet MSP432E411Y Evaluation Module
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Power the MSP432E411Y-BGAEVM
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2
Power the MSP432E411Y-BGAEVM
The MSP432E411Y-BGAEVM requires a 3.3-V power supply, which can be provided in any of several
ways:
• Provide 3.3 V from an external emulator through the 20-pin Arm JTAG interface
• Provide 3.3 V directly to the 3.3V pin on the external power header (J11)
• Provide 5 V to the 5V pin on the external power header (J11) and using the onboard LDO to generate
3.3 V
• Provide 3.3 V and 5 V both to the external power header (J11)
2.1
Emulator Power
To use an external emulator as a power source, use an emulator that supplies 3.3 V to pin 1 on the Arm
20-pin JTAG interface. When 3.3 V is supplied to the board from the emulator, disconnect the output of
the onboard 3.3-V LDO (U5) from the 3.3-V power rail by removing the jumper on JP8. Figure 2 shows the
location of JP8.
Figure 2. Power Selection
If USB host functionality is required from the onboard USB OTG connector, provide 5 V to the board
through the external power header (J11) or the BoosterPack header (J3).
2.2
External 3.3-V Source Only
To use an external 3.3-V source to power the EVM, connect the 3.3-V and GND lines of the supply to the
3.3V and GND pins of the external power header (J11). Disconnect the onboard 3.3-V LDO (U5) from the
3.3-V power rail by removing the jumper on JP8 to prevent back-powering the LDO. Figure 2 shows the
location of JP8. If USB host functionality is required from the onboard USB-OTG connector, also provide
5 V to the board. Use the external 3.3-V and 5-V power option in Section 2.4.
2.3
External 5-V Source Only
To use an external 5-V source to power the EVM, connect the 5-V and GND lines of the supply to the 5V
and GND pins of the external power header (J11) or to the 5V pin on the BoosterPack header (J3).
Connect the onboard 3.3-V LDO (U5) to the 3.3-V power rail by populating the jumper on JP8 to connect
the output of the LDO to the 3.3-V power rail. Figure 2 shows the location for JP8.
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Power the MSP432E411Y-BGAEVM
2.4
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External 3.3-V and 5-V Source
To use external 3.3-V and 5-V supplies to power the EVM, connect the 3.3-V, 5-V, and GND pins of the
supply to the 3.3V, 5V, and GND pins of the external power header (J11) or the BoosterPack headers (J1
for 3.3V and J3 for 5V). Disconnect the onboard 3.3-V LDO (U5) from the 3.3-V power rail by removing
the jumper on JP8 to prevent back-powering the LDO. Figure 2 shows the location for JP8.
2.5
Measure Current Consumption
To measure current consumption, remove the JP1, JP2, or JP3 jumpers and place an ammeter across the
header pins. Connect this jumper when not performing current measurements. Figure 3 shows the location
of JP1, JP2, and JP3. Table 1 lists which power rail to measure on each jumper.
Figure 3. Current Measurement Headers
Table 1. Power Measurement Jumpers
4
Jumper
Power Rail Measured
JP1
Combined VDD and VDDA
JP2
VDD
JP3
VDDA
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Header Pinouts and Connections
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3
Header Pinouts and Connections
3.1
J11 – External Power Connector
Header J11 contains connections for 3.3 V, 5 V, and GND signals and is intended to be used to connect
external power supplies to the MSP432E411Y-BGAEVM. Figure 2 shows header J11, and Table 2 lists
the pinout.
Table 2. External Power Connector J11 Pinout
3.2
J11 Pin
Signal
1
3.3V
2
GND
3
GND
4
5V
J6 – Power Rail Header
Header J6 contains connections for all the power rails and reference voltages used by the MSP432E411Y
device. Figure 4 shows header J6 and Table 3 lists the pinout.
Figure 4. External Power Connector J6
Table 3. External Power Connector J6 Pinout
J6 Pin
Signal
1
VREFA+
Reference voltage for ADC positive input
Description
2
VREFA-
Reference voltage for ADC negative input
3
VBAT
Power source for hibernation module
4
VDD
Positive supply for I/O
5
VSS
Negative supply for I/O
6
VDDA
Positive supply for analog circuits
7
AVSS
Negative supply for analog circuits
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Header Pinouts and Connections
3.3
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J7 – External Peripheral Interface Header
Header J7 contains all the signals for the MSP432E411Y’s External Peripheral Interface (EPI). The EPI
can be connected to an onboard IS42S16320F-7TL – 512 megabit SDRAM, U2, buy shorting all the
header pins on J7 horizontally, as shown in Figure 5. Alternatively, the EPI pins can be used to connect to
an external device by removing the headers on J7, and connecting to the outside pins of J7, as shown in
Figure 6.
Figure 5. Header J7 With All Jumpers to Connect Onboard SDRAM
Figure 6. Header J7 With Jumpers Removed to Connect External Device to EPI
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Table 4 lists the pinout of J7.
Table 4. Header J7 Pinout
(1)
3.4
MSP432E411Y Signal
J7 Pin
J7 Pin
SDRAM Signal
EP0S35
1
2
NC (1)
EP0S34
3
4
NC
EP0S33
5
6
NC
EP0S32
7
8
NC
EP0S31
9
10
CLK
EP0S30
11
12
CKE
EP0S29
13
14
CS
EP0S28
15
16
WE
EP0S27
17
18
NC
EP0S26
19
20
NC
EP0S25
21
22
NC
EP0S24
23
24
NC
EP0S23
25
26
NC
EP0S22
27
28
NC
EP0S21
29
30
NC
EP0S20
31
32
NC
EP0S19
33
34
RAS
EP0S18
35
36
CAS
EP0S17
37
38
DQMH
EP0S16
39
40
DQML
EP0S15
41
42
DQ15
EP0S14
43
44
BA1, DQ14
EP0S13
45
46
BA0, DQ13
EP0S12
47
48
A12, DQ12
EP0S11
49
50
A11, DQ11
EP0S10
51
52
A10, DQ10
EP0S09
53
54
A9, DQ9
EP0S08
55
56
A8, DQ8
EP0S07
57
58
A7, DQ7
EP0S06
59
60
A6, DQ6
EP0S05
61
62
A5, DQ5
EP0S04
63
64
A4, DQ4
EP0S03
65
66
A3, DQ3
EP0S02
67
68
A2, DQ2
EP0S01
69
70
A1, DQ1
EP0S00
71
72
A0, DQ0
NC = no connection
LCD Interface Header
Header J9 contains all of the signals for the internal LCD controller in the MSP432E411Y to interface with
an external LCD panel, including four additional GPIO pins. The four additional GPIO pins can be used as
analog inputs to interface with a resistive touch screen. Alternatively, two of the pins (PE6 and PE7) can
be configured as I2C pins to interface with controllers that require an I2C interface. Figure 7 shows the
location of J9, and Table 5 lists the pinout of J9.
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Header Pinouts and Connections
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Figure 7. Header J9
Table 5. Header J9 Pinout
(1)
GPIO Pin
Function
J9 Pin
J9 Pin
Function
GPIO Pin
GND
GND
40
39
GND
GND
PE7
AIN21/I2C9SDA
38
37
AIN20/I2C9SCL
PE6
PP6
AIN23
36
35
AIN22
PP7
n/a (1)
5V
34
33
3.3 V
VDD
PS3
LCDDATA23
32
31
GPIO
PB4
PS1
LCDDATA21
30
29
LCDDATA20
PS0
PT3
LCDDATA19
28
27
LCDDATA18
PT2
PJ5
LCDDATA17
26
25
LCDDATA16
PJ4
PJ3
LCDDATA15
24
23
LCDDATA14
PJ2
PN6
LCDDATA13
22
21
LCDDATA12
PN7
PT1
LCDDATA11
20
19
LCDDATA10
PT0
PS7
LCDDATA09
18
17
LCDDATA08
PS6
PS5
LCDDATA07
16
15
LCDDATA06
PS4
PR7
LCDDATA05
14
13
LCDDATA04
PR6
PR3
LCDDATA03
12
11
LCDDATA02
PF7
PR5
LCDDATA01
10
9
LCDDATA00
PR4
PJ6
LCDAC
8
7
GND
GND
PR2
LCDLP
6
5
LCDCP
PR0
PF6
LCDMCLK
4
3
LCDFP
PR1
n/a
5V
2
1
3.3 V
VDD
n/a = not applicable
NOTE: On MSP432E411Y-BGAEVM Rev A boards, LCDDATA22 is not available on the J9 header.
If a connection for LCDDATA22 is required, make the connection to J5 pin 19
(MSP432E411Y pin PS2).
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3.5
J1, J2, J3, J4 – BoosterPack Interface Headers
Headers J1, J2, J3, and J4 are aligned correctly and follow the pinout requirements to comply with the
BoosterPack plug-in module pinout standard, as shown on www.ti.com/byob. Figure 8 shows the pinouts
for the J1, J2, J3, and J4 headers.
Figure 8. BoosterPack Plug-in Module Header Pinout
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Header Pinouts and Connections
3.6
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J5 – Additional GPIO Pin Header
Header J5 contains additional GPIO pins that are available for use. Figure 9 shows the location for J5,
and Table 6 lists the pinout.
Figure 9. Header J5 Location
Table 6. Header J5 Pinout
10
MSP432E411Y Pin
J5 Pin
J5 Pin
MSP432E411Y Pin
VDD (3.3 V)
40
39
GND
PD6
38
37
PG6
PQ5
36
35
PM5
PG2
34
33
PA1
PA0
32
31
PF3
PF4
30
29
PF2
PF0
28
27
PF1
PC0
26
25
PQ7
PG7
24
23
PQ6
PN2
22
21
PN1
PQ4
20
19
PS2
PB1
18
17
PB0
PL6
16
15
PC2
PL7
14
13
PC3
PC1
12
11
PN0
PF5
10
9
PJ0
PJ1
8
7
PH3
PG3
6
5
PG4
PG5
4
3
PD7
WAKE
2
1
HIB
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Communication Interfaces
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4
Communication Interfaces
4.1
Ethernet
The MSP432E411Y-BGAEVM development kit can connect directly to an Ethernet network using RJ45
connectors. The microcontroller contains a fully integrated Ethernet MAC and PHY. This integration
creates a simple, elegant, and cost-saving Ethernet circuit design. Example code is available for the lwIP
TCP/IP protocol stack. The embedded Ethernet on this device can be programmed to act as an HTTP
server, a client, or both. The design and integration of the circuit and microcontroller can also synchronize
events over the network using the IEEE 1588 precision time protocol. The existing SimpleLink SDK
network stack includes an example of using this feature.
The Ethernet jack on the EVM contains two LEDs, one green and one yellow, that are controlled by pins
PN0 and PN1 on the MSP432E411Y. When configured for Ethernet operation, the application should
control these pins directly, because the PHY-controlled LED pins have not been provided for LED
function.
4.2
USB-OTG
The EVM is USB 2.0 ready. A TPS2051B power switch is connected to and controlled by the
microcontroller USB peripheral, which manages power to the USB micro A/B connector when functioning
in a USB host. When functioning as a USB device, apply power to the EVM from an external source, (see
Section 2). USB 2.0 functionality is provided and supported directly out of the box with the target USB
micro A/B connector.
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Programming Interfaces
5
Programming Interfaces
5.1
JTAG
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The MSP432E411Y-BGAEVM supports JTAG programming through two different connectors. JA supports
the 20-pin Arm standard JTAG programming interface, and JB supports the 10-pin Arm standard miniJTAG programming interface. Figure 10 shows the two Arm JTAG connectors. When using an external
emulator, if the emulator does not provide power to the board, apply power as described in Section 2.
Figure 10. Arm JTAG Connectors
5.2
ETM Trace
The MSP432E411Y-BGAEVM supports ETM Trace capabilities through J12 (see Figure 11).
Figure 11. Arm ETM Trace Connector
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Programming Interfaces
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5.3
BSL
The MSP432E411Y-BGAEVM supports BSL communication with the MSP432E411Y device through
UART, I2C, or SPI BSL. Three switch banks (S3, S4, and S5) control which BSL interface is connected to
the BSL connector, BSL. Move the corresponding switch for the desired BSL interface to the ON position,
and move the other switches to the OFF position. Figure 12 shows the BSL switches and the BSL
connector, with the switches in position to enable the SPI BSL interface. Table 7 shows which switch bank
controls which BSL Interface. Switch bank S6 connects 4.7-kΩ resistors to the I2C BSL lines if I2C pullups
are needed.
Figure 12. BSL Area on MSP432E411Y-BGAEVM
Table 7. BSL Switch Bank Interfaces
Switch Bank
BSL Interface
SW3
SPI
SW4
UART
SW5
I2C
When connecting to the MSP432E411Y device through the BSL connector:
• If R15 is populated and R7 is not (the default), the BSL host supplies the 3.3-V rail.
• If R7 is populated and R15 is not, the BSL host can sense the 3.3-V rail, which must be externally
supplied to the MSP432E411Y-BGAEVM.
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Software Development
6
Software Development
6.1
Software Description
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The SimpleLink MSP432E4 Software Development Kit (SDK) provides drivers for all of the peripheral
devices supplied in the design. The Peripheral Driver Library is required to operate the on-chip peripherals
as part of the SDK. The SDK includes a set of example applications that use the Peripheral Driver Library.
These applications demonstrate the capabilities of the MSP432E411Y microcontroller and provide a
starting point for the development of the final application for use on the MSP432E411Y-BGAEVM.
6.2
Source Code
The source code is provided as part of the SimpleLink MSP432E4 SDK.
6.3
Tool Options
The source code installation includes directories containing projects, makefiles, and binaries for the
following tool-chains:
• Keil® Arm RealView Microcontroller Development System
• IAR Embedded Workbench® for Arm
• TI Code Composer Studio™ IDE for Arm and GCC compilers
For detailed information on using these tools, see the documentation included in the tool chain installation
or visit the website of the tools supplier.
14
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Schematics
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7
Schematics
1
2
R24
JA
GND
A
3V3
20
18
16
14
12
10
8
6
4
2
19
17
15
13
11
9
7
5
3
1
0
R25
4
5
6
27
SWDIOTMS
27
10
8
6
4
2
R20
SWCLKTCK
R18
R19
BSL
JB
RSTn
TDO
R17
27
3V3
BSLRX
0
3V3
3
BSLTX
R21
9
7
5
GND
3
1 3V3
5V0
BSLCLK
1
2
3
4
BSLSIMO
BSLSOMI
GND
BSLSCL
BSLSDA
BSLRX
BSLTX
9
7
5
3
1
10 BSLSTE
8
6
4 RSTn
2
SW4
PA1
PA0
78F01T
J11
SW3
2 BSLTX
4 BSLRX
1
3
DNP
TP3
DNP
TP4
PA4
PA5
PA2
PA3
27
R15
0
GND
R7
DNP
0
R36
10k
R34
R37
10k 3V3
R38 27
3V3
3V3
J12
R39
1
3
5
7
9
11
13
15
17
19
100
JP1
R42
0
GND
JP2
R43
VSS
2
4
6
8
10
12
14
16
18
20
27
R40
R41 27
27
GND
SWDIOTMS
SWCLKTCK
TDO
TDI
RSTn
0
VDDA
BSLSOMI
DNP
TP7
BSLSIMO
DNP
TP8
BSLCLK
DNP
BSLSTE
TP9
DNP
TP10
A
SW5
PB3
PB2
R35
10k
2
4
6
8
78H01T
R22 27
TDI
27
VDD
1
3
5
7
2 BSLSDA
DNP
TP5
4 BSLSCL
1
3
DNP
TP6
78F01T
SWDIOTMS
SWCLKTCK
R10
TDO
PB3
TDI
4.7k
R11
PB2
RSTn
TRCLK
TRD0
TRD1
TRD2
TRD3
4.7k
SW6
1
3
2
4
VDD
78F01T
AVSS
GND
JP3
JP8
B
U5 TPS73533DRVR
5V0
C35
1uF
C36
0.1uF
C37
0.01uF
6
IN
4
EN
OUT
1
NR
2
NC
5
C38
2.2uF
C39
0.01uF
3
7
GND
GND
B
3V3
GND
GND
GND
C
C
D
D
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
1
2
3
4
Orderable: MSP432E411Y-BGAEVM
TID #:
N/A
Number: MCU051
Rev: A
SVN Rev: Version control disabled
Drawn By:
Engineer: Mike Pridgen
5
Designed for: Public Release
Mod. Date: 6/1/2018
Project Title: MSP432E411Y-BGAEVM
Sheet Title:
Assembly Variant: 001
Sheet: 1 of 4
File: MCU051A_Power_JTAG.SchDoc
Size: B
Contact: http://www.ti.com/support
http://www.ti.com
© Texas Instruments 2018
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Figure 13. Schematics (1 of 3)
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Schematics
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1
2
3
4
SW2
R1
DNP
47k
PJ0
U1A
5
VDD
VBAT
PA0
PA1
PA2
PA3
PA4
PA5
EPI0S08
EPI0S09
A
TARGET_VBUS
EPI0S27
PB2
PB3
EPI0S28
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
LCDDATA22
PB5
PB6
PB7
SWCLKTCK
SWDIOTMS
TDI
TDO
EPI0S07
EPI0S06
EPI0S05
EPI0S04
PD0
PD1
PD2
PD3
PD4
PD5
B
PE0
PE1
PE2
PE3
PE4
PE5
AIN20
AIN21
V3
W3
T6
U5
V4
W4
V5
R7
A16
B16
A17
B17
C6
B6
F2
F1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
B15
C15
D14
C14
M2
M1
L2
K3
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
C2
C1
D2
D1
A4
B4
B3
B2
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
H3
H2
G1
G2
A5
B5
A7
B7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
U6
V6
W6
T7
V7
W7
T8
U8
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
N15
T14
V11
M16
K17
K15
V12
U14
PC0/TCK/SWCLK
PC1/TMS/SWDIO
PC2/TDI
PC3/TDO/SWO
PC4
PC5
PC6
PC7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
P4
R2
R1
T1
R3
T2
U2
V2
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
C8
E7
H17
F16
F18
E17
N1
K5
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
J1
J2
K1
K2
U19
V17
V16
W16
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
TRD2
TRD1
TRD0
TRCLK
TRD3
LCDMCLK
LCDDATA02
EPI0S11
EPI0S10
EPI0S00
EPI0S01
EPI0S02
VDD
40
PD6 38
PQ5 36
PG2 34
PA0 32
PF4 30
PF0 28
PC0 26
PG7 24
PN2 22
PQ4 20
PB1 18
PL6_EXT 16
PL7_EXT 14
PC1 12
PF5 10
PJ1 8
PG3 6
PG5 4
WAKE2
39
37 PG6
35 PM5
33 PA1
31 PF3
29 PF2
27 PF1
25 PQ7
23 PQ6
21 PN1
19 PS2
17 PB0
15 PC2
13 PC3
11 PN0
9 PJ0
7 PH3
5 PG4
3 PD7
1 HIBn
VSS
VDD
R4
10k
PK0
PK1
PK2
EPI0S03
EPI0S32
EPI0S31
EPI0S25
EPI0S24
2
4
R3
100
U18
RSTn
P18
1
3
G
G
C5
R5
1.0M
WAKE
RSTn
VSS
SW1
VSS
U1C
OSC0
E19
OSC1
D19
WAKE
C6
12pF
VSS
0.1uF
VSS
VSS
3
V15 EN0RXI_P
V14 EN0RXI_N
EN0RXIP
EN0RXIN
W13 EN0TXO_P
V13 EN0TXO_N
OSC0
RBIAS
NC
NC
NC
NC
NC
NC
XOSC0
XOSC1 T19
XOSC1
Y2
VSS
C8
0.1uF
R8
49.9
R9
49.9
R12
49.9
C9
0.1uF
R13
49.9
VSS
C10
12pF
VSS
D1
EN0TXO_P
C11
12pF
A
RBIAS
W15
R6
4.87k
C5
E13
V18
V19
W18
W19
VSS
MSP432E411YTZAD
VSS
5
M17 HIBn
EN0TXOP
EN0TXON
OSC1
C7
12pF
XOSC0 T18
2
1
GND
HIB
RST
Y1
VDD
PH4
PH5
PH6
PH7
LCDDATA14
LCDDATA15
LCDDATA16
LCDDATA17
LCDAC
PJ7
51
SW7
J5
RSTn
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
R2
C4
0.1uF
VSS
6
J10
1
TD+
4
CT
4
1 TX+
VDD
EN0TXO_N
6
3
2
TD-
2 TX-
EN0RXI_N
7
2
3
RD+
3 RX+
5
CT
J6
VREFA+
VREFA-
VBAT
VDD
VDDA
1
2
3
4
5
6
7
EN0RXI_P
VSS
8
1
6
AVSS
B
RD-
6 RX-
CDNBS08-SLVU2.8-4
C12
0.1uF
C13
0.1uF
7
MSP432E411YTZAD
8
4
5
NC
7
8
CHS GND
VSS
U1B
VSS
EPI0S15
EPI0S14
EPI0S13
EPI0S12
PM4
PM6
PM7
EPI0S30
EPI0S34
EPI0S35
LCDDATA13
LCDDATA12
PP0
PP1
EPI0S29
PP3
PP4
PP5
AIN23
AIN22
G16
H19
G18
J18
H18
G19
C18
B18
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
K18
K19
L18
L19
M18
G15
N19
N18
PN0
PN1
PN2
PN3
PN4
PN5
PN6
PN7
C10
B11
A11
B10
A10
B9
T12
U12
PP0 D6
PP1 D7
PP2 B13
PP3 C12
PP4 D8
PP5 B12
PP6 B8
PP7 A8
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PL7
PQ0
PQ1
PQ2
PQ3
PQ4
PQ5
PQ6
PQ7
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
PR0
PR1
PR2
PR3
PR4
PR5
PR6
PR7
PN0
PN1
PN2
PN3
PN4
PN5
PN6
PN7
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PT0
PT1
PT2
PT3
E3
E2
H4
M4
A13
W12
U15
M3
PQ0
PQ1
PQ2
PQ3
PQ4
PQ5
PQ6
PQ7
N5
N4
N2
V8
P3
P2
W9
R10
PR0
PR1
PR2
PR3
PR4
PR5
PR6
PR7
D12
D13
B14
A14
V9
T13
U10
R13
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
W10 PT0
V10 PT1
E18 PT2
F17 PT3
10
JP6
U1D
12
VDD
LCDCP
LCDFP
LCDLP
LCDDATA03
LCDDATA00
LCDDATA01
LCDDATA04
LCDDATA05
LCDDATA20
LCDDATA21
LCDDATA23
LCDDATA06
LCDDATA07
LCDDATA08
LCDDATA09
VDDA
F3
VDDC
LCDDATA10
LCDDATA11
LCDDATA18
LCDDATA19
E10
H16
VREFA+ F4
VREFA- G5
VBAT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDA
VDDC
VDDC
VREFA+
VREFA-
P19
VBAT
R18
D18
GNDX
GNDX2
VDDA
MSP432E411YTZAD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDA
A1
A2
A18
A19
B1
B19
F10
H10
H11
H12
J11
J12
K6
K9
K10
K13
K14
L8
L9
M8
M9
M10
N10
P16
R17
V1
W1
W2
C32
2.2uF
C33
1uF
C34
0.1uF
C29
1uF
VSS
C15
0.1uF
C16
0.1uF
C17
0.1uF
VSS
VDD
C19
0.1uF
C20
0.1uF
C21
0.1uF
C22
0.1uF
J8
TARGET_VBUS
VSS
VDD
C23
0.1uF
C24
0.1uF
C25
0.1uF
C26
0.1uF
PL7_EXT
R26
DNP
0
PL6_EXT
R28
DNP
0
TARGET_VBUS
D_N
PL7
D_P
PL6
VSS
5V0
C28
4.7uF
4
MSP432E411YTZAD
R33
10k
AVSS
C30
0.1uF
IN
EN
OUT
1
D-
OTGD_P
D+
R30
3
TARGET_ID 4
5
OC
3
GND
2
U4
VSS
ID
GND
TARGET_VBUS
PD7
6
TARGET_ID 2
OTGD_N 1
OTGD_P 3
R32
10k
4
TPS2051BDBVR
JP5
JP4
4
OTGD_N 2
R29
VSS
5
VSS
PD6
VBUS
0
100
C27
4.7uF
U3
1
R27
0
PB0
VSS
VSS
VBUS
DD+
ID
GND
R31
33k
NC
C31
0.22uF
5
VSS
D
TPD4S012DRYR
NOTE: TPD4S012 all protection circuits are identical
Connections chose for simple routing
AVSS
3
C
VSS
VSS
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
2
R14
1.0M
C18
4700pF
J0011D21BNL
R23
330
R16
330
VSS
VSS
13
14
Shield
Shield
11
JP7
C14
0.1uF
G4
VSS
D
PN1
VDD
G10
H9
J8
J9
J10
K7
K8
K11
K12
L10
L11
L12
M11
M12
N16
P10
P17
VDDC
1
9
PN0
EPI0S20
EPI0S21
EPI0S22
EPI0S23
6
8
10
C
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PL7
7
9
11
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S26
EPI0S33
Orderable: MSP432E411Y-BGAEVM
TID #:
N/A
Number: MCU051
Rev: A
SVN Rev: Version control disabled
Drawn By:
Engineer: Mike Pridgen
5
Designed for: Public Release
Mod. Date: 6/13/2018
Project Title: MSP432E411Y-BGAEVM
Sheet Title:
Assembly Variant: 001
Sheet: 2 of 4
File: MCU051A_MSP432E_Device.SchDoc
Size: B
Contact: http://www.ti.com/support
http://www.ti.com
© Texas Instruments 2018
6
Figure 14. Schematics (2 of 3)
16
MSP432E411Y-BGAEVM User's Guide
SLAU780 – August 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Schematics
www.ti.com
1
2
3
4
5
6
VDD_SD
U2
C1
0.1uF
C2
0.1uF
C3
0.1uF
VDD_SD
A
VSS
VDD_SD
VDD
LCDFP
LCDCP
VSS
VDD
LCDDATA00
LCDDATA02
LCDDATA04
LCDDATA06
LCDDATA08
LCDDATA10
LCDDATA12
LCDDATA14
LCDDATA16
LCDDATA18
LCDDATA20
LCDDATA22
AIN22
AIN20
J9
5V0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
LCDMCLK
LCDLP
LCDAC
LCDDATA01
LCDDATA03
LCDDATA05
LCDDATA07
LCDDATA09
LCDDATA11
LCDDATA13
LCDDATA15
LCDDATA17
LCDDATA19
LCDDATA21
5V0
LCDDATA23
AIN23
AIN21
B
1
14
27
3
9
43
49
J7
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
S00
S01
S02
S03
S04
S05
S06
S07
S08
S09
S10
S11
S12
S13
S14
S15
DQML
DQMH
15
39
S16
S17
NC
40
VSS
VSS
VSS
28
41
54
VSSQ
VSSQ
VSSQ
VSSQ
6
12
46
52
VDD
VDD
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VDDQ
VDDQ
VDDQ
VDDQ
S31
S30
S29
S19
S18
S28
38
37
19
18
17
16
S00
S01
S02
S03
S04
S05
S06
S07
S08
S09
S10
S11
S12
23
24
25
26
29
30
31
32
33
34
22
35
36
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
S13
S14
20
21
BA0
BA1
CLK
CKE
CS
RAS
CAS
WE
EPI0S35
EPI0S34
EPI0S33
EPI0S32
EPI0S31
EPI0S30
EPI0S29
EPI0S28
EPI0S27
EPI0S26
EPI0S25
EPI0S24
EPI0S23
EPI0S22
EPI0S21
EPI0S20
EPI0S19
EPI0S18
EPI0S17
EPI0S16
EPI0S15
EPI0S14
EPI0S13
EPI0S12
EPI0S11
EPI0S10
EPI0S09
EPI0S08
EPI0S07
EPI0S06
EPI0S05
EPI0S04
EPI0S03
EPI0S02
EPI0S01
EPI0S00
VSS
VSS
IS42S16320F-7TL
VSS
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S09
S08
S07
S06
S05
S04
S03
S02
S01
S00
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
A
B
VDD_SD
DNP
TP1
DNP
TP2
VSS
VDD_SD
VDD
J1/J3
VDD
5V0
PE1
PP0
PP1
PH4
PE4
PD3
PP4
PB6
PB7
C
1
2
3
4
5
6
7
8
9
10
+3.3V
Analog_In
LP_UART_RX
LP_UART_TX
GPIO !
Analog In
SPI_CLK
GPIO !
I2C_SCL
I2C_SDA
+5V
GND
Analog_In
Analog_In
Analog_In
Analog_In
Analog_In/I2S_WS
Analog_In/I2S_SCLK
Analog_Out/I2S_SDout
Analog_Out/I2S_SDin
21
22
23
24
25
26
27
28
29
30
GND
PWM/GPIO !
GPIO !
GPIO
RST
SPI_MOSI
SPI_MISO
SPI_CS/GPIO !
SPI_CS/GPIO !
GPIO !
20
19
18
17
16
15
14
13
12
11
JP9
PE5
PB5
PK0
PK1
PK2
PE0
PH5
PH6
VSS
C
J2/J4
PA2
PA3
PA4
PA5
PD4
PD5
PJ7
PM4
PE2
PE3
40
39
38
37
36
35
34
33
32
31
PWM/GPIO !
PWM/GPIO !
PWM/GPIO !
PWM/GPIO !
Timer_Cap/GPIO !
Timer_Cap/GPIO !
GPIO !
GPIO !
GPIO !
GPIO !
PM7
PP5
VSS
PH7
RSTn
PD1
PD0
PP3
PD2
PM6
D
D
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
1
2
3
4
Orderable: MSP432E411Y-BGAEVM
TID #:
N/A
Number: MCU051
Rev: A
SVN Rev: Version control disabled
Drawn By:
Engineer: Mike Pridgen
5
Designed for: Public Release
Mod. Date: 6/8/2018
Project Title: MSP432E411Y-BGAEVM
Sheet Title:
Assembly Variant: 001
Sheet: 3 of 4
File: MCU051A_LCD_Memory.SchDoc
Size: B
Contact: http://www.ti.com/support
http://www.ti.com
© Texas Instruments 2018
6
Figure 15. Schematics (3 of 3)
SLAU780 – August 2018
Submit Documentation Feedback
MSP432E411Y-BGAEVM User's Guide
Copyright © 2018, Texas Instruments Incorporated
17
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