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MUX36S08, MUX36D04
SBOS705D – JANUARY 2016 – REVISED FEBURARY 2019
MUX36xxx 36-V, low-capacitance, low-leakage-current, precision, analog multiplexers
1 Features
3 Description
•
The MUX36S08 and MUX36D04 (MUX36xxx) are
modern complementary metal-oxide semiconductor
(CMOS)
analog
multiplexers
(muxes).
The
MUX36S08 offers 8:1 single-ended channels,
whereas the MUX36D04 offers differential 4:1 or dual
4:1 single-ended channels. The MUX36S08 and
MUX36D04 work equally well with either dual
supplies (±5 V to ±18 V) or a single supply (10 V to
36 V). They also perform well with symmetric
supplies (such as VDD = 12 V, VSS = –12 V), and
unsymmetric supplies (such as VDD = 12 V,
VSS = –5 V). All digital inputs have TTL-logic
compatible thresholds, ensuring both TTL and CMOS
logic compatibility when operating in the valid supply
voltage range.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Low On-Capacitance
– MUX36S08: 9.4 pF
– MUX36D04: 6.7 pF
Low Input Leakage: 1 pA
Low Charge Injection: 0.3 pC
Rail-to-Rail Operation
Wide Supply Range: ±5 V to ±18 V, 10 V to 36 V
Low On-Resistance: 125 Ω
Transition Time: 92 ns
Break-Before-Make Switching Action
EN Pin Connectable to VDD
Logic Levels: 2 V to VDD
Low Supply Current: 45 µA
ESD Protection HBM: 2000 V
Industry-Standard TSSOP and smaller WQFN
Package
For Other Configurations, Refer to:
– TMUX6111/ 12/ 13 (4 ch. SPST)
– TMUX6121/ 22/ 23 (2 ch. SPST)
– TMUX6119 (1 ch. SPDT)
– TMUX6136 (2 ch. SPDT)
– TMUX6104 (1 ch. 4:1)
•
•
•
•
Device Information(1)
PART NUMBER
MUX36S08
MUX36D04
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
WQFN (16)
4.00 mm x 4.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
SPACER
2 Applications
•
The MUX36S08 and MUX36D04 have very low on
and off leakage currents, allowing these multiplexers
to switch signals from high input impedance sources
with minimal error. A low supply current of 45 µA
enables use in portable applications.
Factory Automation and Industrial Process
Controls
Programmable Logic Controllers (PLC)
Analog Input Modules
ATE Test Equipment
Battery Monitoring Systems
Simplified Schematic
Leakage Current vs Temperature
900
ID(ON)+
Bridge Sensor
±
Thermocouple
MUX36D04
ADC
PGA/INA
+
Current
Sensing
VINP
VINM
Leakage Current (pA)
600
ID(OFF)+
300
IS(OFF)+
0
IS(OFF)±
±300
ID(OFF)±
±600
ID(ON)±
Photo
LED Detector
Optical Sensor
±900
±75
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
C006
Analog Inputs
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MUX36S08, MUX36D04
SBOS705D – JANUARY 2016 – REVISED FEBURARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
4
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics: Dual Supply ..................... 7
Electrical Characteristics: Single Supply................... 9
Typical Characteristics ............................................ 11
Parameter Measurement Information ................ 15
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
Truth Tables ............................................................
On-Resistance ........................................................
Off-Leakage Current ...............................................
On-Leakage Current ...............................................
Differential On-Leakage Current .............................
Transition Time .......................................................
Break-Before-Make Delay.......................................
Turn-On and Turn-Off Time ....................................
Charge Injection ......................................................
Off Isolation ...........................................................
15
16
16
17
17
18
18
19
20
21
8.11 Channel-to-Channel Crosstalk .............................. 21
8.12 Bandwidth ............................................................. 22
8.13 THD + Noise ......................................................... 22
9
Detailed Description ............................................ 23
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
23
23
24
26
10 Application and Implementation........................ 27
10.1 Application Information.......................................... 27
10.2 Typical Application ............................................... 27
11 Power Supply Recommendations ..................... 29
12 Layout................................................................... 30
12.1 Layout Guidelines ................................................. 30
12.2 Layout Example .................................................... 30
13 Device and Documentation Support ................. 31
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
31
14 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2018) to Revision D
Page
•
Added Feature: For Other Configurations, Refer to ............................................................................................................... 1
•
Added RRJ (WQFN) package option to the MUX36D08 ...................................................................................................... 4
•
Changed the WQFN S6 pin number From: 19 To: 9.............................................................................................................. 4
•
Added the RRJ package option to the MUX36D04 ............................................................................................................... 5
•
Added WQFN (RRJ) data to Thermal Information ................................................................................................................. 7
•
Changed On-resistance drift unit value From: Ω To: %/°C .................................................................................................... 7
•
Changed IDL(ON) unit value From: nA To: pA........................................................................................................................... 7
Changes from Revision B (July 2016) to Revision C
Page
•
Added WQFN Package option in Features ............................................................................................................................ 1
•
Added WQFN package option in Device Information ............................................................................................................ 1
•
Changed Description column of MUX36D04 row in Device Comparison Table .................................................................... 4
•
Added WQFN (RUM) data to Thermal Information ................................................................................................................ 7
•
Changed On-resistance drift TYP value From: 0.52 To: 0.64 in Electrical Characteristics: Dual Supply .............................. 7
•
Changed Analog Switch, ID parameter in Electrical Characteristics: Dual Supply table: split parameter into ID(OFF) and
ID(ON) parameters, changed symbols, parameter names, and test conditions ....................................................................... 7
•
Changed Analog Switch, IDL(ON) parameter test conditions in Electrical Characteristics: Dual Supply table ......................... 7
•
Changed On-resistance drift TYP value From: 0.47 To: 1.13 in Electrical Characteristics: Single Supply ........................... 9
•
Changed Analog Switch, ID parameter in Electrical Characteristics: Single Supply table: split parameter into ID(OFF)
2
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SBOS705D – JANUARY 2016 – REVISED FEBURARY 2019
and ID(ON) parameters, changed symbols, parameter names, and ID(ON) test conditions ....................................................... 9
•
Changed and swapped data between 25°C and 85°C to fix the typo ................................................................................. 10
•
Changed Figure 30: changed low-voltage level to 0 V......................................................................................................... 18
•
Changed Figure 33: added 0 V line, flipped VS supply symbol............................................................................................ 20
•
Changed Figure 37: changed 5 VRMS marking in Audio Precision box ................................................................................ 22
•
Changed description of MUX36D04 in Overview section..................................................................................................... 23
•
Changed Figure 43: changed OPA140 amplifier and charge kickback filter box ................................................................. 27
Changes from Revision A (January 2016) to Revision B
Page
•
Added differential on-leakage current parameter to Electrical Characteristics table ............................................................. 7
•
Added Differential On-Leakage Current section................................................................................................................... 17
Changes from Original (January 2016) to Revision A
•
Page
Changed from product preview to production data ................................................................................................................ 1
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MUX36S08, MUX36D04
SBOS705D – JANUARY 2016 – REVISED FEBURARY 2019
www.ti.com
5 Device Comparison Table
PRODUCT
DESCRIPTION
MUX36S08
8-channel, single-ended analog multiplexer (8:1 mux)
MUX36D04
4-channel differential or dual 4:1 single-ended analog multiplexer (8:2 mux)
6 Pin Configuration and Functions
MUX36S08: PW Package
16-Pin TSSOP
Top View
EN
A0
A1
A2
16
15
14
13
MUX36S08: RUM and RRJ Package
16-Pin WQFN
Top View
A0
1
16
A1
EN
2
15
A2
VSS
3
14
GND
VSS
1
12
GND
S1
4
13
VDD
S1
2
11
VDD
10
S5
9
S6
11
S6
S3
4
S4
7
10
S7
D
8
9
S8
8
6
S7
S3
Pad
7
3
S8
S2
6
S5
5
12
D
5
S4
S2
Th ermal
No t to scale
Not to scale
RUM and RRJ have the same package
dimension, but different thermal pad
dimension and lead finger length.
Pin Functions: MUX36S08
PIN
NAME
FUNCTION
DESCRIPTION
TSSOP
WQFN
A0
1
15
Digital input
Address line 0
A1
16
14
Digital input
Address line 1
A2
15
13
Digital input
Address line 2
D
8
6
EN
2
16
Digital input
GND
14
12
Power supply
S1
4
2
Analog input or output Source pin 1. Can be an input or output.
S2
5
3
Analog input or output Source pin 2. Can be an input or output.
S3
6
4
Analog input or output Source pin 3. Can be an input or output.
S4
7
5
Analog input or output Source pin 4. Can be an input or output.
S5
12
10
Analog input or output Source pin 5. Can be an input or output.
S6
11
9
Analog input or output Source pin 6. Can be an input or output.
S7
10
8
Analog input or output Source pin 7. Can be an input or output.
S8
9
7
Analog input or output Source pin 8. Can be an input or output.
VDD
13
11
Power supply
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VSS
3
1
Power supply
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
Thermal
Pad (1)
-
-
Power supply
Exposed Pad. The exposed pad is electrically connected to VSS internally. Connect EP to VSS to
achieve rated thermal and ESD performance.
(1)
4
Analog input or output Drain pin. Can be an input or output.
Active high digital input. When this pin is low, all switches are turned off. When this pin is high,
the A[2:0] logic inputs determine which switch is turned on.
Ground (0 V) reference
RUM and RRJ have the same package dimension, but different thermal pad dimension and lead finger length.
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SBOS705D – JANUARY 2016 – REVISED FEBURARY 2019
MUX36D04: PW Package
16-Pin TSSOP
Top View
S1B
S2A
5
12
S2B
S3A
6
11
S3B
S4A
7
10
S4B
DA
8
9
DB
VSS
1
S1A
2
S2A
3
S3A
4
Not to scale
GND
13
13
4
Thermal
Pad
8
S1A
S4B
VDD
A1
14
14
3
7
VSS
DB
GND
A0
15
EN
2
15
EN
6
A1
5
16
DA
1
S4A
A0
16
MUX36D04: RUM and RRJ Package
16-Pin WQFN
Top View
12
VDD
11
S1B
10
S2B
9
S3B
Not to scale
RUM and RRJ have the same package
dimension, but different thermal pad
dimension and lead finger length.
Pin Functions: MUX36D04
PIN
NAME
FUNCTION
DESCRIPTION
TSSOP
WQFN
A0
1
15
Digital input
Address line 0
A1
16
14
Digital input
Address line 1
DA
8
6
Analog input or output Drain pin A. Can be an input or output.
DB
9
7
Analog input or output Drain pin B. Can be an input or output.
EN
2
16
GND
15
13
S1A
4
2
Analog input or output Source pin 1A. Can be an input or output.
S2A
5
3
Analog input or output Source pin 2A. Can be an input or output.
S3A
6
4
Analog input or output Source pin 3A. Can be an input or output.
S4A
7
5
Analog input or output Source pin 4A. Can be an input or output.
S1B
13
11
Analog input or output Source pin 1B. Can be an input or output.
S2B
12
10
Analog input or output Source pin 2B. Can be an input or output.
S3B
11
9
Analog input or output Source pin 3B. Can be an input or output.
S4B
10
8
Analog input or output Source pin 4B. Can be an input or output.
VDD
14
12
Power supply
Positive power supply. This pin is the most positive power supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VSS
3
1
Power supply
Negative power supply. This pin is the most negative power supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
Thermal
Pad (1)
-
-
Power supply
Exposed Pad. The exposed pad is electrically connected to VSS internally. Connect EP to VSS
to achieve rated thermal and ESD performance.
(1)
Digital input
Power supply
Active high digital input. When this pin is low, all switches are turned off. When this pin is high,
the A[1:0] logic inputs determine which pair of switches is turned on.
Ground (0 V) reference
RUM and RRJ have the same package dimension, but different thermal pad dimension and lead finger length.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply
Voltage
MIN
MAX
VDD
–0.3
40
VSS
–40
0.3
VDD – VSS
Digital input pins:
EN, A0, A1, A2
(2)
Sx, SxA, SxB, D, DA, DB
Current (3)
Operating, TA
Temperature
(2)
(3)
VSS – 0.3
VDD + 0.3
VSS – 2
VDD + 2
V
–30
30
mA
–55
150
Junction, TJ
150
Storage, Tstg
(1)
V
40
(2)
Analog input pins:
UNIT
–65
V
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Only one pin at a time
Voltage limits are valid if current is limited to ±30 mA.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
Dual supply
NOM
MAX
5
18
10
36
UNIT
VDD (1)
Positive power-supply voltage
VSS (2)
Negative power-supply voltage (dual supply)
–5
–18
V
VDD – VSS
Supply voltage
10
36
V
Single supply
(3)
V
VS
Source pins voltage
VSS
VDD
V
VD
Drain pins voltage
VSS
VDD
V
VEN
Enable pin voltage
VSS
VDD
V
VA
Address pins voltage
VSS
VDD
V
ICH
Channel current (TA = 25°C)
–25
25
mA
TA
Operating temperature
–40
125
°C
(1)
(2)
(3)
6
When VSS = 0 V, VDD can range from 10 V to 36 V.
VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 36 V.
VS is the voltage on all S pins.
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SBOS705D – JANUARY 2016 – REVISED FEBURARY 2019
7.4 Thermal Information
MUX36S08 and MUX36D04
THERMAL METRIC (1)
PW (TSSOP)
RUM (WQFN)
RRJ (WQFN)
16 PINS
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
103.8
37.3
46.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
36.8
31.6
37.7
°C/W
RθJB
Junction-to-board thermal resistance
49.8
16.2
21.7
°C/W
ψJT
Junction-to-top characterization parameter
2.7
0.5
0.7
°C/W
ψJB
Junction-to-board characterization parameter
49.1
16.2
21.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
6.1
6.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics: Dual Supply
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG SWITCH
Analog signal range
TA = –40°C to +125°C
VSS
VS = 0 V, ICH = 1 mA
RON
On-resistance
VS = ±10 V, ICH = 1 mA
VDD
V
125
170
Ω
145
200
TA = –40°C to +85°C
230
TA = –40°C to
+125°C
250
2.4
ΔRON
On-resistance mismatch
between channels
VS = ±10 V, ICH = 1 mA
TA = –40°C to +85°C
On-resistance flatness
On-resistance drift
VS = 10 V, 0 V, –10 V
Input leakage current
53
TA = –40°C to
+125°C
58
VS = 0 V
Switch state is off,
VS = ±10 V, VD = ±10 V (1)
0.64
TA = –40°C to +85°C
TA = –40°C to
+125°C
ID(OFF)
Output off leakage current
TA = -40°C to +85°C
TA = –40°C to
+125°C
Output on leakage current
Switch state is on,
VD = ±10 V, VS = floating
1.9
0.5
–2
2
IDL(ON)
Differential on-leakage
current
0.008
nA
0.1
TA = –40°C to +85°C
–0.5
0.5
TA = –40°C to
+125°C
–3.3
3.3
3
nA
0.1
–0.5
–15
Switch state is on,
VDA = VDB = ±10 V,
VS = floating
%/°C
–1.9
0.005
Ω
0.04
0.15
–0.1
ID(ON)
0.001
–0.15
–0.1
Switch state is off,
VS = ±10 V, VD = ±10 V (1)
6
TA = –40°C to +85°C
–0.04
IS(OFF)
Ω
11
2.4
RFLAT
6
9
TA = –40°C to
+125°C
Ω
nA
15
TA = –40°C to +85°C
–100
100
TA = –40°C to
+125°C
–500
500
pA
LOGIC INPUT
VIH
Logic voltage high
VIL
Logic voltage low
(1)
2
V
0.8
V
When VS is positive, VD is negative, and vice versa.
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Electrical Characteristics: Dual Supply (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER
ID
TEST CONDITIONS
MIN
TYP
Input current
MAX
UNIT
0.15
µA
SWITCH DYNAMICS (2)
88
tON
Enable turn-on time
VS = ±10 V, RL = 300 Ω,
CL= 35 pF
TA = –40°C to +85°C
144
TA = –40°C to
+125°C
151
63
tOFF
Enable turn-off time
VS = ±10 V, RL = 300 Ω,
CL= 35 pF
tt
Transition time
83
TA = –40°C to
+125°C
90
151
TA = –40°C to
+125°C
157
Break-before-make time
delay
VS = 10 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to
+125°C
QJ
Charge injection
CL = 1 nF, RS = 0 Ω
Off-isolation
RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz
Channel-to-channel crosstalk
CS(OFF)
Input off-capacitance
RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz
VS = 0 V
Output off-capacitance
f = 1 MHz, VS = 0 V
CS(ON),
CD(ON)
Output on-capacitance
f = 1 MHz, VS = 0 V
54
VS = –15 V to +15 V
±0.6
Nonadjacent channel
to D, DA, DB
–96
Adjacent channel to
D, DA, DB
–85
Nonadjacent
channels
–96
Adjacent channels
–88
ns
ns
0.3
f = 1 MHz, VS = 0 V
CD(OFF)
30
ns
143
TA = –40°C to +85°C
tBBM
ns
75
TA = –40°C to +85°C
92
VS = 10 V, RL = 300 Ω,
CL= 35 pF
136
pC
dB
dB
2.4
2.9
MUX36S08
7.5
8.4
MUX36D04
4.3
5
MUX36S08
9.4
10.6
MUX36D04
6.7
7.7
45
59
pF
pF
pF
POWER SUPPLY
VDD supply current
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V
TA = –40°C to +85°C
62
TA = –40°C to
+125°C
83
25
VSS supply current
(2)
8
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V
µA
34
TA = –40°C to +85°C
37
TA = –40°C to
+125·C
57
µA
Specified by design, not subject to production testing.
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7.6 Electrical Characteristics: Single Supply
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
V
ANALOG SWITCH
Analog signal range
TA = –40°C to +125°C
VSS
235
RON
On-resistance
VS = 10 V, ICH = 1 mA
TA = –40°C to +85°C
390
TA = –40°C to +125°C
430
3.1
ΔRON
On-resistance match
On-resistance drift
IS(OFF)
ID(OFF)
ID(ON)
Input leakage current
Output off leakage current
Output on leakage current
VS = 10 V, ICH = 1 mA
340
12
TA = –40°C to +85°C
19
TA = –40°C to +125°C
23
VS = 10 V
1.13
–-0.04
0.001
%/°C
TA = –40°C to +85°C
–0.15
0.15
TA = –40°C to +125°C
–1.9
1.9
Switch state is off,
VS = 1 V and VD = 10 V,
or VS = 10 V and VD = 1 V (1)
TA = –40°C to +85°C
Switch state is on,
VD = 1 V and 10 V,
VS = floating
TA = –40°C to +85°C
–0.5
0.5
TA = –40°C to +125°C
–3.3
3.3
TA = –40°C to +125°C
0.005
0.5
–2
2
0.008
nA
0.1
–0.5
–0.1
Ω
0.04
Switch state is off,
VS = 1 V and VD = 10 V,
or VS = 10 V and VD = 1 V (1)
–0.1
Ω
nA
0.1
nA
LOGIC INPUT
VIH
Logic voltage high
VIL
Logic voltage low
ID
Input current
2.0
V
0.8
V
0.15
µA
SWITCH DYNAMIC CHARACTERISTICS (2)
85
tON
Enable turn-on time
VS = 8 V, RL = 300 Ω,
CL= 35 pF
145
TA = –40°C to +125°C
149
48
tOFF
Enable turn-off time
VS = 8 V, RL = 300 Ω,
CL= 35 pF
94
TA = –40°C to +125°C
102
Transition time
87
TA = –40°C to +85°C
153
VS = 8 V, RL = 300 Ω,
CL= 35 pF
TA = –40°C to +125°C
155
Break-before-make time
delay
VS = 8 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C
QJ
Charge injection
CL = 1 nF, RS = 0 Ω
Off-isolation
RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz
Nonadjacent channel to D, DA, DB
-96
Adjacent channel to D, DA, DB
-85
Channel-to-channel
crosstalk
RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz
Nonadjacent channels
–96
Adjacent channels
-88
Input off-capacitance
f = 1 MHz, VS = 6 V
CS(OFF)
CD(OFF)
Output off-capacitance
f = 1 MHz, VS = 6 V
CS(ON),
CD(ON)
Output on-capacitance
f = 1 MHz, VS = 6 V
(1)
(2)
30
54
VS = 6 V
0.15
VS = 0 V to 12 V,
±0.4
ns
147
VS = 8 V, RL = 300 Ω,
CL= 35 pF
tBBM
ns
83
TA = –40°C to +85°C
VS = 8 V, CL= 35 pF
tt
140
TA = –40°C to +85°C
ns
ns
pC
dB
dB
2.7
3.2
MUX36S08
9.1
10
MUX36D04
5
5.7
MUX36S08
10.8
12
MUX36D04
6.9
8
pF
pF
pF
When VS is 1 V, VD is 10 V, and vice versa.
Specified by design; not subject to production testing.
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Electrical Characteristics: Single Supply (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
42
53
UNIT
POWER SUPPLY
VDD supply current
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V
TA = –40°C to +85°C
56
TA = –40°C to +125°C
77
23
VSS supply current
10
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V
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µA
31
TA = –40°C to +85°C
38
TA = –40°C to +125°C
51
µA
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7.7 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
250
250
TA = 125ƒC
VDD = 13.5 V VDD = 15 V
VSS = ±13.5 V VSS = ±15 V
150
100
50
VDD = 18 V
VSS = ±18 V
TA = 85ƒC
200
On Resistance (Ÿ)
On Resistance (Ÿ)
200
150
TA = 25ƒC
100
50
VDD = 16.5 V
VSS = ±16.5 V
TA = ±40ƒC
TA = 0ƒC
0
0
±20
±15
±10
±5
0
5
10
15
Source or Drain Voltage (V)
20
±18
±12
0
±6
6
12
Source or Drain Voltage (V)
C001
18
C002
VDD = 15 V, VSS = –15 V
Figure 1. On-Resistance vs Source or Drain Voltage
Figure 2. On-Resistance vs Source or Drain Voltage
700
700
VDD = 5 V
VSS = ±5 V
600
VDD = 6 V
VSS = ±6 V
500
On Resistance (Ÿ)
On Resistance (Ÿ)
600
400
300
200
VDD = 7 V
VSS = ±7 V
100
500
TA = 85ƒC
TA = 125ƒC
400
300
TA = 25ƒC
200
100
TA = 0ƒC
TA = ±40ƒC
0
0
±8
±6
±4
±2
0
2
4
6
Source or Drain Voltage (V)
0
8
2
4
6
8
10
Source or Drain Voltage (V)
C003
12
C004
VDD = 12 V, VSS = 0 V
Figure 3. On-Resistance vs Source or Drain Voltage
Figure 4. On-Resistance vs Source or Drain Voltage
700
250
VDD = 30 V
VSS = 0 V
On Resistance (Ÿ)
On Resistance (Ÿ)
200
150
100
50
VDD = 36 V
VSS = 0 V
VDD = 33 V
VSS = 0 V
VDD = 10 V
VSS = 0 V
600
VDD = 12 V
VSS = 0 V
500
400
VDD = 14 V
VSS = 0 V
300
200
100
0
0
0
6
12
18
24
Source or Drain Voltage (V)
30
36
0
2
Figure 5. On-Resistance vs Source or Drain Voltage
4
6
8
10
12
Source or Drain Voltage (V)
C023
14
C005
Figure 6. On-Resistance vs Source or Drain Voltage
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Typical Characteristics (continued)
250
250
200
200
On Resistance (Ÿ)
On Resistance (Ÿ)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
150
100
150
100
50
50
0
0
0
6
12
18
24
Source or Drain Voltage (V)
±12
0
±6
6
VDD = 24 V, VSS = 0 V
C024
VDD = 12 V, VSS = –12 V
Figure 7. On-Resistance vs Source or Drain Voltage
Figure 8. On-Resistance vs Source or Drain Voltage
900
900
ID(ON)+
ID(ON)+
600
Leakage Current (pA)
600
Leakage Current (pA)
12
Source or Drain Voltage (V)
C029
ID(OFF)+
300
IS(OFF)+
0
IS(OFF)±
±300
ID(OFF)±
±600
IS(OFF)+
300
ID(OFF)+
0
±300
IS(OFF)±
ID(OFF)±
±600
ID(ON)±
ID(ON)±
±900
±900
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±75
±50
±25
50
75
100
125
150
C007
VDD = 12 V, VSS = 0 V
Figure 9. Leakage Current vs Temperature
Figure 10. Leakage Current vs Temperature
2
2
VDD = 15 V
VSS = ±15 V
1
Charge Injection (pC)
Charge Injection (pC)
25
Temperature (ƒC)
VDD = 15 V, VSS = –15 V
0
VDD = 10 V
VSS = ±10 V
±1
VDD = 12 V
VSS = 0 V
1
VDD = 15 V
VSS = ±15 V
0
VDD = 10 V
VSS = ±10 V
±1
VDD = 12 V
VSS = 0 V
±2
±2
±15
±10
±5
0
5
10
Source Voltage (V)
MUX36S08, source-to-drain
Figure 11. Charge Injection vs Source Voltage
12
0
C006
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15
±15
±10
±5
0
5
10
Source Voltage (V)
C008
15
C025
MUX36D04, source-to-drain
Figure 12. Charge Injection vs Source Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
9
VDD = 15 V
VSS = ±15 V
6
Charge Injection (pC)
Turn On and Turn Off Times (ns)
150
VDD = 10 V
VSS = ±10 V
3
0
VDD = 12 V
VSS = 0 V
±3
±6
tON (VDD = 15 V, VSS = ±15 V)
120
tON (VDD = 12 V, VSS = 0 V)
90
60
30
tOFF (VDD = 15 V, VSS = ±15 V)
tOFF (VDD = 12 V, VSS = 0 V)
0
±9
±15
±10
0
±5
5
10
Drain voltage (V)
15
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C011
150
C010
Drain-to-source
Figure 14. Turn-On and Turn-Off Times vs Temperature
0
0
±20
±20
Adjacent Channel to D (Output)
±40
Adjacent Channels
±40
Crosstalk (dB)
Off Isolation (dB)
Figure 13. Charge Injection vs Source or Drain Voltage
±60
±80
±60
±80
±100
±100
±120
Non-Adjacent Channels
±120
Non-Adjacent Channel to D (Output)
±140
±140
10k
100k
1M
10M
100M
Frequency (Hz)
1G
10k
1M
10M
100M
Frequency (Hz)
Figure 15. Off Isolation vs Frequency
1G
C013
Figure 16. Crosstalk vs Frequency
100
3
VDD = 15 V
VSS = ±15 V
On Response (dB)
10
THD+N (%)
100k
C012
VDD = 5 V
VSS = ±5 V
1
0.1
0
±3
±6
0.01
10
100
1k
10k
Frequency (Hz)
100k
±9
100k
1M
Figure 17. THD+N vs Frequency
10M
100M
Frequency (Hz)
C014
1G
C018
Figure 18. On Response vs Frequency
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Typical Characteristics (continued)
18
18
15
15
Capacitance (pF)
Capacitance (pF)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
12
CD(ON)
9
6
CD(OFF)
9
CD(ON)
6
CD(OFF)
CS(OFF)
3
12
3
CS(OFF)
0
0
±15
±10
±5
0
5
10
Source Voltage (V)
15
±15
±5
0
5
10
Source or Drain Voltage (V)
MUX36S08, VDD = 15 V, VSS = –15 V
15
C026
MUX36D04, VDD = 15 V, VSS = –15 V
Figure 19. Capacitance vs Source Voltage
Figure 20. Capacitance vs Source Voltage
18
18
15
15
Capacitance (pF)
Capacitance (pF)
±10
C015
12
CD(ON)
9
6
12
CD(OFF)
9
CD(ON)
6
CD(OFF)
CS(OFF)
3
3
0
CS(OFF)
0
0
5
10
15
20
25
Source Voltage (V)
30
0
10
15
20
25
Source or Drain Voltage (V)
MUX36S08, VDD = 30 V, VSS = 0 V
30
C028
MUX36D04, VDD = 30 V, VSS = 0 V
Figure 21. Capacitance vs Source Voltage
Figure 22. Capacitance vs Source Voltage
18
18
15
15
CD(ON)
12
Capacitance (pF)
Capacitance (pF)
5
C016
9
6
CD(OFF)
CS(OFF)
3
12
CD(OFF)
9
CD(ON)
6
3
CS(OFF)
0
0
0
3
6
9
Source or Drain Voltage (V)
MUX36S08, VDD = 12 V, VSS = 0 V
Figure 23. Capacitance vs Source Voltage
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12
0
3
6
9
Source or Drain Voltage (V)
C022
12
C027
MUX36D04, VDD = 12 V, VSS = 0 V
Figure 24. Capacitance vs Source Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
25
20
Drain Current (mA)
15
10
5
0
±5
±10
±15
±20
±25
±25
±20
±15
±10
±5
0
5
10
15
20
Source Current (mA)
25
C021
Figure 25. Source Current vs Drain Current
8 Parameter Measurement Information
8.1 Truth Tables
Table 1 and Table 2 show the truth tables for the MUX36S08 and MUX36D04, respectively.
Table 1. MUX36S08 Truth Table
(1)
EN
A2
A1
A0
STATE
0
X (1)
X (1)
X (1)
All channels are off
1
0
0
0
Channel 1
1
0
0
1
Channel 2
1
0
1
0
Channel 3
1
0
1
1
Channel 4
1
1
0
0
Channel 5
1
1
0
1
Channel 6
1
1
1
0
Channel 7
1
1
1
1
Channel 8
X denotes don't care..
Table 2. MUX36D04 Truth Table
EN
0
(1)
A1
A0
(1)
(1)
X
X
STATE
All channels are off
1
0
0
Channels 1A and 1B
1
0
1
Channels 2A and 2B
1
1
0
Channels 3A and 3B
1
1
1
Channels 4A and 4B
X denotes don't care.
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8.2 On-Resistance
The on-resistance of the MUX36xxx is the ohmic resistance across the source (Sx, SxA, or SxB) and drain (D,
DA, or DB) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is
used to denote on-resistance. The measurement setup used to measure RON is shown in Figure 26. Voltage (V)
and current (ICH) are measured using this setup, and RON is computed as shown in Equation 1:
V
D
S
ICH
VS
Figure 26. On-Resistance Measurement Setup
RON = V / ICH
(1)
8.3 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 27
ID (OFF)
Is (OFF)
A
S
D
A
VS
VD
Figure 27. Off-Leakage Measurement Setup
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8.4 On-Leakage Current
On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in
the on state. The source pin is left floating during the measurement. Figure 28 shows the circuit used for
measuring the on-leakage current, denoted by ID(ON).
ID (ON)
D
S
A
NC
NC = No Connection
VD
Figure 28. On-Leakage Measurement Setup
8.5 Differential On-Leakage Current
In case of a differential signal, the on-leakage current is defined as the differential leakage current that flows into
or out of the drain pins when the switches is in the on state. The source pins are left floating during the
measurement. Figure 29 shows the circuit used for measuring the on-leakage current on each signal path,
denoted by IDA(ON) and IDB(ON). The absolute difference between these two current is defined as the differential
on-leakage current IDL(ON).
IDA(ON)
SxA
DA
A
NC
IDB(ON)
DB
SxB
A
NC
VD
NC = No Connection
Figure 29. Differential On-Leakage Measurement Setup
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8.6 Transition Time
Transition time is defined as the time taken by the output of the MUX36xxx to rise or fall to 90% of the transition
after the digital address signal has fallen or risen to 50% of the transition. Figure 30 shows the setup used to
measure transition time, denoted by the symbol tt.
VDD
VSS
VDD
VSS
3V
Address
Signal (VIN)
50%
50%
S1
VS1
A0
0V
A1
VIN
S2-S7
A2
tt
tt
VS8
S8
VS1
90%
Output
MUX36S08
Output
2V
EN
D
GND
300 Ÿ
35 pF
90%
VS8
Figure 30. Transition-Time Measurement Setup
8.7 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the MUX36xxx is
switching. The MUX36xxx output first breaks from the on-state switch before making the connection with the next
on-state switch. The time delay between the break and the make is known as break-before-make delay.
Figure 31 shows the setup used to measure break-before-make delay, denoted by the symbol tBBM.
VDD
VSS
VDD
VSS
3V
Address
Signal (VIN)
S1
VS
A0
0V
A1
VIN
S2-S7
A2
S8
Output
80%
Output
MUX36S08
80%
2V
D
EN
GND
300 Ÿ
35 pF
tBBM
Figure 31. Break-Before-Make Delay Measurement Setup
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8.8 Turn-On and Turn-Off Time
Turn-on time is defined as the time taken by the output of the MUX36xxx to rise to a 90% final value after the
enable signal has risen to a 50% final value. Figure 32 shows the setup used to measure turn-on time. Turn-on
time is denoted by the symbol tON.
Turn off time is defined as the time taken by the output of the MUX36xxx to fall to a 10% initial value after the
enable signal has fallen to a 50% initial value. Figure 32 shows the setup used to measure turn-off time. Turn-off
time is denoted by the symbol tOFF.
VDD
VSS
VDD
VSS
3V
Enable
Drive (VIN)
50%
50%
S1
A0
VS
A1
S2-S8
0V
A2
tOFF (EN)
tON (EN)
MUX36S08
0.9 VS
Output
Output
D
EN
GND
0.1 VS
VIN
300 Ÿ
35 pF
Figure 32. Turn-On and Turn-Off Time Measurement Setup
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8.9 Charge Injection
The MUX36xxx have a simple transmission-gate topology. Any mismatch in capacitance between the NMOS and
PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate
signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QINJ. Figure 33 shows the setup used to measure charge injection.
VSS
VDD
VDD
VSS
A0
3V
A1
VEN
A2
MUX36S08
0V
RS
S
D
VOUT
EN
VOUT
VOUT
CL
1 nF
VS
GND
QINJ = CL ×
VOUT
VEN
Figure 33. Charge-Injection Measurement Setup
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8.10 Off Isolation
Off isolation is defined as the voltage at the drain pin (D, DA, or DB) of the MUX36xxx when a 1-VRMS signal is
applied to the source pin (Sx, SxA, or SxB) of an off-channel. Figure 34 shows the setup used to measure off
isolation. Use Equation 2 to compute off isolation.
VDD
VSS
0.1 µF
0.1 µF
Network Analyzer
VSS
VDD
50
S
50 Ÿ
VS
D
VOUT
RL
50 Ÿ
GND
Figure 34. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
V
© S ¹
(2)
8.11 Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is defined as the voltage at the source pin (Sx, SxA, or SxB) of an off-channel,
when a 1-VRMS signal is applied at the source pin of an on-channel. Figure 35 shows the setup used to measure,
and Equation 3 is the equation used to compute, channel-to-channel crosstalk.
VSS
VDD
0.1 µF
0.1 µF
VSS
VDD
Network Analyzer
VOUT
S1
RL
50 Ÿ
R
50 Ÿ
S2
VS
GND
Figure 35. Channel-to-Channel Crosstalk Measurement Setup
Channel-to-Channel Crosstalk
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
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8.12 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to the
source pin of an on-channel, and the output is measured at the drain pin of the MUX36xxx. Figure 36 shows the
setup used to measure bandwidth of the mux. Use Equation 4 to compute the attenuation.
VSS
VDD
0.1 µF
0.1 µF
VSS
VDD
Network Analyzer
V1
50
S
VS
V2
D
VOUT
RL
50 Ÿ
GND
Figure 36. Bandwidth Measurement Setup
Attenuation
§V ·
20 ˜ Log ¨ 2 ¸
© V1 ¹
(4)
8.13 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the
ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux
output. The on-resistance of the MUX36xxx varies with the amplitude of the input signal and results in distortion
when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as
THD+N. Figure 37 shows the setup used to measure THD+N of the MUX36xxx.
VSS
VDD
0.1 µF
0.1 µF
Audio Precision
VSS
VDD
RS
S
IN
VS
VIN
D
5 VRMS
VOUT
RL
10 NŸ
GND
Figure 37. THD+N Measurement Setup
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9 Detailed Description
9.1 Overview
The MUX36xxx are a family of analog multiplexers. The Functional Block Diagram section provides a top-level
block diagram of both the MUX36S08 and MUX36D04. The MUX36S08 is an 8-channel, single-ended, analog
mux. The MUX36D04 is a 4-channel, differential or dual 4:1, single-ended, analog mux. Each channel is turned
on or turned off based on the state of the address lines and enable pin.
9.2 Functional Block Diagram
MUX36D04
MUX36S08
S1
S1A
S2
S2A
S3
S3A
S4
S4A
DA
S5
S1B
DB
S6
S2B
S7
S3B
S8
S4B
D
1-of-4
Decoder
1-of-8
Decoder
A0
A1
A2
EN
A0
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9.3 Feature Description
9.3.1 Ultralow Leakage Current
The MUX36xxx provide extremely low on- and off-leakage currents. The MUX36xxx are capable of switching
signals from high source-impedance inputs into a high input-impedance op amp with minimal offset error
because of the ultralow leakage currents. Figure 38 shows typical leakage currents of the MUX36xxx versus
temperature.
900
ID(ON)+
Leakage Current (pA)
600
ID(OFF)+
300
IS(OFF)+
0
IS(OFF)±
±300
ID(OFF)±
±600
ID(ON)±
±900
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C006
Figure 38. Leakage Current vs Temperature
9.3.2 Ultralow Charge Injection
The MUX36xxx have a simple transmission gate topology, as shown in Figure 39. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.
OFF ON
CGSN
CGDN
S
D
CGSP
CGDP
OFF ON
Figure 39. Transmission Gate Topology
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Feature Description (continued)
The MUX36xxx have special charge-injection cancellation circuitry that reduces the source-to-drain charge
injection to as low as 0.3 pC at VS = 0 V, and ±0.6 pC in the full signal range, as shown in Figure 40.
Charge Injection (pC)
2
1
VDD = 15 V
VSS = ±15 V
0
VDD = 10 V
VSS = ±10 V
±1
VDD = 12 V
VSS = 0 V
±2
±15
±10
±5
0
5
10
Source Voltage (V)
15
C025
Figure 40. Source-to-Drain Charge Injection vs Source or Drain Voltage
The drain-to-source charge injection becomes important when the device is used as a demultiplexer (demux),
where D becomes the input and Sx becomes the output. Figure 41 shows the drain-to-source charge injection
across the full signal range.
9
VDD = 15 V
VSS = ±15 V
Charge Injection (pC)
6
VDD = 10 V
VSS = ±10 V
3
0
VDD = 12 V
VSS = 0 V
±3
±6
±9
±15
±10
±5
0
5
10
Drain voltage (V)
15
C011
Figure 41. Drain-to-Source Charge Injection vs Source or Drain Voltage
9.3.3 Bidirectional Operation
The MUX36xxx are operable as both a mux and demux. The source (Sx, SxA, SxB) and drain (D, DA, DB) pins
of the MUX36xxx are used either as input or output. Each MUX36xxx channel has very similar characteristics in
both directions.
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Feature Description (continued)
9.3.4 Rail-to-Rail Operation
The valid analog signal for the MUX36xxx ranges from VSS to VDD. The input signal to the MUX36xxx swings
from VSS to VDD without any significant degradation in performance. The on-resistance of the MUX36xxx varies
with input signal, as shown in Figure 42
250
VDD = 13.5 V VDD = 15 V
VSS = ±13.5 V VSS = ±15 V
On Resistance (Ÿ)
200
150
100
50
VDD = 18 V
VSS = ±18 V
VDD = 16.5 V
VSS = ±16.5 V
0
±20
±15
±10
±5
0
5
10
15
Source or Drain Voltage (V)
20
C001
Figure 42. On-Resistance vs Source or Drain Voltage
9.4 Device Functional Modes
When the EN pin of the MUX36xxx is pulled high, one of the switches is closed based on the state of the
address lines. When the EN pin is pulled low, all the switches are in an open state irrespective of the state of the
address lines. The EN pin can be connected to VDD (as high as 36 V).
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The MUX36xxx family offers outstanding input/output leakage currents and ultralow charge injection. These
devices operate up to 36 V, and offer true rail-to-rail input and output. The on-capacitance of the MUX36xxx is
very low. These features makes the MUX36xxx a family of precision, robust, high-performance analog
multiplexer for high-voltage, industrial applications.
10.2 Typical Application
Figure 43 shows a 16-bit, differential, 4-channel, multiplexed, data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential mux. This TI Precision
Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the MUX36D04,
OPA192 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.
Analog Inputs
REF3140
Bridge Sensor
Thermocouple
MUX36D04
OPA192
+
OPA140
Photo
Detector
+
Gain Network
Gain Network
Current Sensing
LED
High-Voltage Multiplexed Input
OPA350
RC Filter
Reference Driver
+
OPA192
Optical Sensor
Gain Network
Gain Network
RC Filter
High-Voltage Level Translation
REF
Charge
Kickback
Filter
VINP
ADS8864
VINM
VCM
Figure 43. 16-Bit Precision Multiplexed Data-Acquisition System for High-Voltage Inputs With Lowest
Distortion
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Typical Application (continued)
10.2.1 Design Requirements
The primary objective is to design a ±20 V, differential, 4-channel, multiplexed, data-acquisition system with
lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure, sine-wave
input. The design requirements for this block design are:
• System supply voltage: ±15 V
• ADC supply voltage: 3.3 V
• ADC sampling rate: 400 kSPS
• ADC reference voltage (REFP): 4.096 V
• System input signal: A high-voltage differential input signal with a peak amplitude of 20 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.
10.2.2 Detailed Design Procedure
The purpose of this precision design is to design an optimal, high-voltage, multiplexed, data-acquisition system
for highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 43. The
circuit is a multichannel, data-acquisition signal chain consisting of an input low-pass filter, mux, mux output
buffer, attenuating SAR ADC driver, and the reference driver. The architecture allows fast sampling of multiple
channels using a single ADC, providing a low-cost solution. This design systematically approaches each analog
circuit block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal
input signal at each input channel.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIPD151, 16-Bit, 400-kSPS, 4-Channel Multiplexed Data-Acquisition
System for High-Voltage Inputs with Lowest Distortion.
10.2.3 Application Curve
1.0
Integral Non-Linearity (LSB)
0.8
0.6
0.4
0.2
0.0
±0.2
±0.4
±0.6
±0.8
±1.0
±20
±15
±10
±5
0
5
10
15
ADC Differential Peak-to-Peak Input (V)
20
C030
Figure 44. ADC 16-Bit Linearity Error for the Multiplexed Data-Acquisition Block
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11 Power Supply Recommendations
The MUX36xxx operates across a wide supply range of ±5 V to ±18 V (10 V to 36 V in single-supply mode).
They also perform well with unsymmetric supplies such as VDD = 12 V and VSS= –5 V. For reliable operation, use
a supply decoupling capacitor ranging between 0.1 µF to 10 µF at both the VDD and VSS pins to ground.
The on-resistance of the MUX36xxx varies with supply voltage, as illustrated in Figure 45
250
VDD = 13.5 V VDD = 15 V
VSS = ±13.5 V VSS = ±15 V
On Resistance (Ÿ)
200
150
100
50
VDD = 18 V
VSS = ±18 V
VDD = 16.5 V
VSS = ±16.5 V
0
±20
±15
±10
±5
0
5
10
15
Source or Drain Voltage (V)
20
C001
Figure 45. On-Resistance Variation With Supply and Input Voltage
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12 Layout
12.1 Layout Guidelines
Figure 46 illustrates an example of a PCB layout with the MUX36S08IPW, and Figure 47 illustrates an example
of a PCB layout with MUX36D04IPW.
Some key considerations are:
1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
2. Keep the input lines as short as possible. In case of the differential signal, make sure the A inputs and B
inputs are as symmetric as possible.
3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
C
AO
A1
A2
AO
Via to
ground plane
EN
12.2 Layout Example
A1
EN
A2
VSS
GND
S1
Via to
ground plane
MUX36S08 IPW
C
V DD
S2
S5
S3
S6
S4
S7
D
S8
Figure 46. MUX36S08IPW Layout Example
C
AO
A1
EN
GND
C
VDD
VSS
S 1A
Via to
ground plane
A1
AO
Via to
ground plane
EN
Via to
ground plane
MUX36D04 IPW
S 1B
S 2A
S 2B
S 3A
S 3B
S 4A
S 4B
DA
DB
Figure 47. MUX36D04IPW Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
• ADS8664 12-Bit, 500-kSPS, 4- and 8-Channel, Single-Supply, SAR ADCs with Bipolar Input Ranges
(SBAS492)
• OPA140 High-Precision, Low-Noise, Rail-to-Rail Output, 11-MHz JFET Op Amp (SBOS498)
• OPA192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp with
e-Trim™ (SBOS620)
13.2 Related Links
Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MUX36S08
Click here
Click here
Click here
Click here
Click here
MUX36D04
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MUX36D04IPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
MUXD04C
MUX36D04IPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
MUXD04C
MUX36D04IRRJR
ACTIVE
WQFN
RRJ
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
MUX
36D04
MUX36D04IRUMR
ACTIVE
WQFN
RUM
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
MUX
36D04
MUX36S08IPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
MUXS08B
MUX36S08IPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
MUXS08B
MUX36S08IRRJR
ACTIVE
WQFN
RRJ
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
MUX
36S08
MUX36S08IRUMR
ACTIVE
WQFN
RUM
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
MUX
36S08
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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