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NE5532, NE5532A, SA5532, SA5532A
SLOS075J – NOVEMBER 1979 – REVISED JANUARY 2015
NE5532x, SA5532x Dual Low-Noise Operational Amplifiers
1 Features
3 Description
•
The NE5532, NE5532A, SA5532, and SA5532A
devices are high-performance operational amplifiers
combining excellent DC and AC characteristics. They
feature very low noise, high output-drive capability,
high
unity-gain
and
maximum-output-swing
bandwidths, low distortion, high slew rate, inputprotection diodes, and output short-circuit protection.
These operational amplifiers are compensated
internally for unity-gain operation. These devices
have specified maximum limits for equivalent input
noise voltage.
1
•
•
•
•
•
Equivalent Input Noise Voltage:
5 nV/√Hz Typ at 1 kHz
Unity-Gain Bandwidth: 10 MHz Typ
Common-Mode Rejection Ratio: 100 dB Typ
High DC Voltage Gain: 100 V/mV Typ
Peak-to-Peak Output Voltage Swing 26 V Typ
With VCC± = ±15 V and RL = 600 Ω
High Slew Rate: 9 V/μs Typ
2 Applications
•
•
•
•
•
•
•
Device Information(1)
AV Receivers
Embedded PCs
Netbooks
Video Broadcasting and Infrastructure: Scalable
Platforms
DVD Recorders and Players
Multichannel Video Transcoders
Pro Audio Mixers
PART NUMBER
PACKAGE (PIN)
BODY SIZE (NOM)
NE5532x, SA5532x
SOIC (8)
4.90 mm × 3.91 mm
NE5532x, SA5532x
PDIP (8)
9.81 mm × 6.35 mm
NE5532x
SO (8)
6.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
VIN
RIN
RG
+
VOUT
RF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
NE5532, NE5532A, SA5532, SA5532A
SLOS075J – NOVEMBER 1979 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 7
9
Application and Implementation .......................... 8
9.1 Typical Application ................................................... 8
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
5 Revision History
Changes from Revision I (April 2009) to Revision J
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
2
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SLOS075J – NOVEMBER 1979 – REVISED JANUARY 2015
6 Pin Configuration and Functions
NE5532, NE5532A . . . D, P, OR PS PACKAGE
SA5532, SA5532A . . . D OR P PACKAGE
(TOP VIEW)
1OUT
1
8
VCC+
1IN–
2
7
2OUT
1IN+
3
6
2IN–
VCC–
4
5
2IN+
Pin Functions
PIN
NAME
NO.
1IN+
3
1INOUT1
TYPE
DESCRIPTION
I
Noninverting input
2
I
Inverting Input
1
O
Output
2IN+
5
I
Noninverting input
2IN-
6
I
Inverting Input
2OUT
7
O
Output
VCC+
8
—
Positive Supply
VCC-
4
—
Negative Supply
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SLOS075J – NOVEMBER 1979 – REVISED JANUARY 2015
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC+
Supply voltage (2)
VCC
VCC–
Input voltage, either input (2) (3)
Input current (4)
MIN
MAX
0
22
V
V
–22
0
VCC–
VCC+
–10
10
Duration of output short circuit (5)
Operating virtual-junction temperature
Tstg
Storage temperature range
(2)
(3)
(4)
(5)
V
mA
Unlimited
TJ
(1)
UNIT
150
–65
150
°C
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–.
The magnitude of the input voltage must never exceed the magnitude of the supply voltage.
Excessive input current will flow if a differential input voltage in excess of approximately 0.6 V is applied between the inputs, unless
some limiting resistance is used.
The output may be shorted to ground or either power supply. Temperature and/or supply voltages must be limited to ensure the
maximum dissipation rating is not exceeded.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
2000
Charged device model (CDM), per JEDEC specification JESD22C101, all pins (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VCC+
Supply voltage
VCC–
Supply voltage
TA
Operating free-air temperature
MIN
MAX
5
15
V
V
–5
–15
NE5532, NE5532A
0
70
SA5532, SA5532A
–40
85
UNIT
°C
7.4 Thermal Information
NE5532, NE5532A, SA5532, and SA5532A
THERMAL METRIC (1)
D
P
PS
UNIT
95
°C/W
8 PINS
RθJA
(1)
(2)
(3)
4
Junction-to-ambient thermal resistance
(2) (3)
97
85
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
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7.5 Electrical Characteristics
VCC± = ±15 V, TA = 25°C (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
VIO
Input offset voltage
VO = 0
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input-voltage range
VOPP
Maximum peak-to-peak output-voltage swing
TA = 25°C
TYP
MAX
0.5
4
TA = Full range (2)
5
TA = 25°C
10
200
TA = Full range (2)
nA
800
nA
1000
RL ≥ 600 Ω, VCC± = ±15 V
RL ≥ 2 kΩ, VO±10 V
mV
200
TA = 25°C
Large-signal differential-voltage amplification
UNIT
150
TA = Full range (2)
RL ≥ 600 Ω, VO = ±10 V
AVD
MIN
±12
±13
V
V
24
26
TA = 25°C
15
50
TA = Full range (2)
10
TA = 25°C
25
TA = Full range (2)
15
V/mV
100
Avd
Small-signal differential-voltage amplification
f = 10 kHz
2.2
V/mV
BOM
Maximum output-swing bandwidth
RL = 600 Ω, VO = ±10 V
140
kHz
B1
Unity-gain bandwidth
RL = 600 Ω, CL = 100 pF
ri
Input resistance
zo
Output impedance
30
AVD = 30 dB, RL = 600 Ω, f = 10 kHz
10
MHz
300
kΩ
0.3
Ω
dB
CMRR Common-mode rejection ratio
VIC = VICR min
70
100
kSVR
Supply-voltage rejection ratio (ΔVCC±/ΔVIO)
VCC± = ±9 V to ±15 V, VO = 0
80
100
IOS
Output short-circuit current
10
38
60
mA
ICC
Total supply current
VO = 0, No load
8
16
mA
Crosstalk attenuation (VO1/VO2)
V01 = 10 V peak, f = 1 kHz
(1)
(2)
dB
110
dB
All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified.
Full temperature ranges are: –40°C to 85°C for the SA5532 and SA5532A devices, and 0°C to 70°C for the NE5532 and NE5532A
devices.
7.6 Operating Characteristics
VCC± = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER
SR
TEST CONDITIONS
Slew rate at unity gain
Overshoot factor
Vn
Equivalent input noise voltage
In
Equivalent input noise current
NE5532, SA5532
MIN
TYP MAX
NE5532A, SA5532A
MIN
TYP
UNIT
MAX
9
9
V/μs
10
10
%
f = 30 Hz
8
8
10
f = 1 kHz
5
5
6
f = 30 Hz
2.7
2.7
f = 1 kHz
0.7
0.7
VI = 100 mV,
RL = 600 Ω,
AVD = 1,
CL = 100 pF
Copyright © 1979–2015, Texas Instruments Incorporated
nV/√Hz
pA/√Hz
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18
1.6
16
1.4
Equivalent input noise current (pA)
Equivalent input noise Voltage (nV)
7.7 Typical Characteristics
14
12
10
8
6
4
2
0
10
100
1000
Frequency (Hz)
10000
100000
1.2
1
0.8
0.6
0.4
0.2
0
10
100
Frequency (Hz)
D001
Figure 1. Equivalent Input Noise Voltage vs Frequency
1000
D002
Figure 2. Equivalent Input Noise Current vs Frequency
180
Output Swing Bandwidth (kHz)
160
140
120
100
80
60
40
20
0
-40
-20
0
20
40
Temperature (C)
60
80
100
D003
Figure 3. Output Swing Bandwidth
vs Temperature at VCC = ±10 V
6
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SLOS075J – NOVEMBER 1979 – REVISED JANUARY 2015
8 Detailed Description
8.1 Overview
The NE5532, NE5532A, SA5532, and SA5532A devices are high-performance operational amplifiers combining
excellent dc and ac characteristics. They feature very low noise, high output-drive capability, high unity-gain and
maximum-output-swing bandwidths, low distortion, high slew rate, input-protection diodes, and output shortcircuit protection. These operational amplifiers are compensated internally for unity-gain operation. These
devices have specified maximum limits for equivalent input noise voltage.
8.2 Functional Block Diagram
VCC+
36 pF
IN+
37 pF
14 pF
15 W
OUT
7 pF
IN–
15 W
460 W
VCC–
Component values shown are nominal.
8.3 Feature Description
8.3.1 Unity-Gain Bandwidth
The unity-gain bandwidth is the frequency up to which an amplifier with a unity gain may be operated without
greatly distorting the signal. The NE5532, NE5532A, SA5532, and SA5532A devices have a 10-MHz unity-gain
bandwidth.
8.3.2 Common-Mode Rejection Ratio
The common-mode rejection ratio (CMRR) of an amplifier is a measure of how well the device rejects unwanted
input signals common to both input leads. It is found by taking the ratio of the change in input offset voltage to
the change in the input voltage and converting to decibels. Ideally the CMRR would be infinite, but in practice,
amplifiers are designed to have it as high as possible. The CMRR of the NE5532, NE5532A, SA5532, and
SA5532A devices is 100 dB.
8.3.3 Slew Rate
The slew rate is the rate at which an operational amplifier can change its output when there is a change on the
input. The NE5532, NE5532A, SA5532, and SA5532A devices have a 9-V/ms slew rate.
8.4 Device Functional Modes
The NE5532, NE5532A, SA5532, and SA5532A devices are powered on when the supply is connected. Each of
these devices can be operated as a single supply operational amplifier or dual supply amplifier depending on the
application.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Typical Application
Some applications require differential signals. Figure 4 shows a simple circuit to convert a single-ended input of 2
V to 10 V into differential output of ±8 V on a single 15-V supply. The output range is intentionally limited to
maximize linearity. The circuit is composed of two amplifiers. One amplifier acts as a buffer and creates a
voltage, VOUT+. The second amplifier inverts the input and adds a reference voltage to generate VOUT–. Both
VOUT+ and VOUT– range from 2 V to 10 V. The difference, VDIFF, is the difference between VOUT+ and VOUT–.
R2
15 V
R1
VOUT+
+
R3
VREF
12 V
R4
VDIFF
±
VOUT+
+
VIN
Figure 4. Schematic for Single-Ended Input to Differential Output Conversion
9.1.1 Design Requirements
The design requirements are as follows:
• Supply voltage: 15 V
• Reference voltage: 12V
• Input: 2 V to 10 V
• Output differential: ±8 V
8
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SLOS075J – NOVEMBER 1979 – REVISED JANUARY 2015
Typical Application (continued)
9.1.2 Detailed Design Procedure
The circuit in Figure 4 takes a single-ended input signal, VIN, and generates two output signals, VOUT+ and VOUT–
using two amplifiers and a reference voltage, VREF. VOUT+ is the output of the first amplifier and is a buffered
version of the input signal, VIN Equation 1. VOUT– is the output of the second amplifier which uses VREF to add an
offset voltage to VIN and feedback to add inverting gain. The transfer function for VOUT– is Equation 2.
VOUT+ = VIN
(1)
æ R 4 ö æ R2 ö
R2
Vout - = Vref ´ ç
- Vin ´
÷ ´ ç1 +
÷
R1 ø
R1
è R3+ R 4 ø è
(2)
The differential output signal, VDIFF, is the difference between the two single-ended output signals, VOUT+ and
VOUT–. Equation 3 shows the transfer function for VDIFF. By applying the conditions that R1 = R2 and R3 = R4, the
transfer function is simplified into Equation 6. Using this configuration, the maximum input signal is equal to the
reference voltage and the maximum output of each amplifier is equal to the VREF. The differential output range is
2×VREF. Furthermore, the common mode voltage will be one half of VREF (see Equation 7).
æ
öæ
æ
R ö
R4
R2 ö
VD IF F = V O U T + - V O U T - = VIN ´ ç 1 + 2 ÷ - VR E F ´ ç
÷ ç1 +
÷
R1 ø
R1 ø
è
è R3 + R4 ø è
VOUT+ = VIN
VOUT– = VREF – VIN
VDIFF = 2×VIN – VREF
(3)
(4)
(5)
(6)
+ VOUT - ö 1
æV
Vcm = ç OUT +
÷ = VREF
2
è
ø 2
(7)
9.1.2.1 Amplifier Selection
Linearity over the input range is key for good dc accuracy. The common mode input range and the output swing
limitations determine the linearity. In general, an amplifier with rail-to-rail input and output swing is required.
Bandwidth is a key concern for this design. Since the NE5532 has a bandwidth of 10 MHz, this circuit will only be
able to process signals with frequencies of less than 10 MHz.
9.1.2.2 Passive Component Selection
Because the transfer function of VOUT– is heavily reliant on resistors (R1, R2, R3, and R4), use resistors with low
tolerances to maximize performance and minimize error. This design used resistors with resistance values of 36
kΩ with tolerances measured to be within 2%. But, if the noise of the system is a key parameter, the user can
select smaller resistance values (6 kΩ or lower) to keep the overall system noise low. This ensures that the noise
from the resistors is lower than the amplifier noise.
9.1.3 Application Curves
The measured transfer functions in Figure 5, Figure 6, and Figure 7 were generated by sweeping the input
voltage from 0 V to 12V. However, this design should only be used between 2 V and 10 V for optimum linearity.
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12
12
8
10
4
8
VOUT+ (V)
VDIFF (V)
Typical Application (continued)
0
6
±4
4
±8
2
0
±12
0
1
2
3
4
5
6
7
8
9
10
11
VIN (V)
12
0
1
2
3
4
5
6
VIN (V)
C003
Figure 5. Differential Output Voltage vs Input Voltage
7
8
9
10
11
12
C001
Figure 6. Positive Output Voltage Node vs Input Voltage
12
10
VOUTt (V)
8
6
4
2
0
0
1
2
3
4
5
6
VIN (V)
7
8
9
10
11
12
C002
Figure 7. Positive Output Voltage Node vs Input Voltage
10
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10 Power Supply Recommendations
The NE5532x and SA5532x devices are specified for operation over the range of ±5 to ±15 V; many
specifications apply from 0°C to 70°C (NE5532x) and -40°C to 85°C (SA5532x). The Typical Characteristics
section presents parameters that can exhibit significant variance with regard to operating voltage or temperature.
CAUTION
Supply voltages outside of the ±22 V range can permanently damage the device (see
the Absolute Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines.
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
For best operational performance of the device, use good PCB layout practices, including:
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational
amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, SLOA089.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
VIN
RIN
RG
+
VOUT
RF
Figure 8. Operational Amplifier Schematic for Noninverting Configuration
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Layout Example (continued)
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
VS+
RF
OUT1
VCC+
GND
IN1í
OUT2
VIN
IN1+
IN2í
VCCí
IN2+
RG
GND
RIN
Use low-ESR, ceramic
bypass capacitor
Only needed for
dual-supply
operation
GND
VS(or GND for single supply)
Ground (GND) plane on another layer
Figure 9. Operational Amplifier Board Layout for Noninverting Configuration
12
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
Parts
Product Folder
Sample & Buy
Technical
Documents
Tools & Software
Support &
Community
NE5532
Click here
Click here
Click here
Click here
Click here
NE5532A
Click here
Click here
Click here
Click here
Click here
SA5532
Click here
Click here
Click here
Click here
Click here
SA5532A
Click here
Click here
Click here
Click here
Click here
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
NE5532AD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
N5532A
Samples
NE5532ADR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
N5532A
Samples
NE5532ADRE4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
N5532A
Samples
NE5532ADRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
N5532A
Samples
NE5532AP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
NE5532AP
Samples
NE5532APE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
NE5532AP
Samples
NE5532APSR
ACTIVE
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
N5532A
Samples
NE5532APSRE4
ACTIVE
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
N5532A
Samples
NE5532D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
N5532
Samples
NE5532DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
0 to 70
N5532
Samples
NE5532DRE4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
N5532
Samples
NE5532DRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
N5532
Samples
NE5532P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU | SN
N / A for Pkg Type
0 to 70
NE5532P
Samples
NE5532PE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
NE5532P
Samples
NE5532PSR
ACTIVE
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
N5532
Samples
SA5532AD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
SA5532A
Samples
SA5532ADR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
SA5532A
Samples
SA5532AP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SA5532AP
Samples
SA5532APE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SA5532AP
Samples
SA5532D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
SA5532
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SA5532DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
SA5532
Samples
SA5532P
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SA5532P
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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