NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
NS16C2552/NS16C2752 Dual UART with 16-byte/64-byte FIFO's and up to 5 Mbit/s Data
Rate
Check for Samples: NS16C2552, NS16C2752
FEATURES
1
•
•
•
•
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Dual Independent UART
Up to 5 Mbits/s Data Transfer Rate
2.97 V to 5.50 V Operational Vcc
5 V Tolerant I/Os in the Entire Supply Voltage
Range
Industrial Temperature: -40°C to 85°C
Default Registers are Identical to the
PC16552D
NS16C2552/NS16C2752 is Pin-to-Pin
Compatible to TI PC16552D, EXAR ST16C2552,
XR16C2552, XR 16L2552, and Phillips
SC16C2552B
NS16C2752 is Compatible to EXAR
XR16L2752, and Register Compatible to
Phillips SC16C752
Auto Hardware Flow Control (Auto-CTS, AutoRTS)
Auto Software Flow Control (Xon, Xoff, and
Xon-any)
Fully Programmable Character Length (5, 6, 7,
or 8) with Even, Odd, or No Parity, Stop Bit
Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and Parity) to
or from the Serial Data
Independently Controlled and Prioritized
Transmit and Receive Interrupts
Complete Line Status Reporting Capabilities
Line Break Generation and Detection
Internal Diagnostic Capabilities
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Detection
Programmable Baud Generators Divide any
Input Clock by 1 to (216 - 1) and Generate the
16 X clock
IrDA v1.0 Wireless Infrared Encoder/Decoder
DMA Operation (TXRDY/RXRDY)
Concurrent Write to DUART Internal Register
Channels 1 and 2
•
•
Multi-Function Output Allows More Package
Functions with Fewer I/O Pins
44-PLCC or 48-TQFP Package
DESCRIPTION
The NS16C2552 and NS16C2752 are dual channel
Universal
Asynchronous
Receiver/Transmitter
(DUART). The footprint and the functions are
compatible to the PC16552D, while new features are
added to the UART device. These features include
low voltage support, 5V tolerant inputs, enhanced
features, enhanced register set, and higher data rate.
The two serial channels are completely independent
of each other, except for a common CPU interface
and crystal input. On power-up both channels are
functionally identical to the PC16552D. Each channel
can operate with on-chip transmitter and receiver
FIFO’s (in FIFO mode).
In the FIFO mode each channel is capable of
buffering 16 bytes (for NS16C2552) or 64 bytes (for
NS16C2752) of data in both the transmitter and
receiver. The receiver FIFO also has additional 3 bits
of error data per location. All FIFO control logic is onchip to minimize system software overhead and
maximize system efficiency.
To improve the CPU processing bandwidth, the data
transfers between the DUART and the CPU can be
done using DMA controller. Signaling for DMA
transfers is done through two pins per channel
(TXRDY and RXRDY). The RXRDYfunction is
multiplexed on one pin with the OUT2 and BAUDOUT
functions. The configuration is through Alternate
Function Register.
The fundamental function of the UART is converting
between parallel and serial data. Serial-to-parallel
conversion is done on the UART receiver and
parallel-to-serial conversion is done on the
transmitter. The CPU can read the complete status of
each channel at any time. Status information reported
includes the type and condition of the transfer
operations being performed by the DUART, as well
as any error conditions (parity, overrun, framing, or
break interrupt).
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
DESCRIPTION (CONTINUED)
The NS16C2552 and NS16C2752 include one programmable baud rate generator for each channel. Each baud
rate generator is capable of dividing the clock input by divisors of 1 to (216 - 1), and producing a 16X clock for
driving the internal transmitter logic and for receiver sampling circuitry. The NS16C2552 and NS16C2752 have
complete MODEM-control capability, and a processor-interrupt system. The interrupts can be programmed by the
user to minimize the processing required to handle the communications link.
System Block Diagram
Connection Diagrams
Figure 1. 44–PLCC
See Package Number FN0044A
2
Submit Documentation Feedback
Figure 2. 48–TQFP
See Package Number PFB0048A
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
Pin Descriptions
The NS16C2552/NS16C2752 pins are classified into the following interface categories.
• Bus Interface
• Serial I/O Interface
• Clock and Reset
• Power supply and Ground pins
Serial channel number (1 or 2) is designated by a numerical suffix after each pin name. If a numerical suffix (1 or
2) is not associated with the pin name, the information applies to both channels.
The I/O types are as follows:
Type: I
Input
Type: O
Output
Type: IO_Z
TRI-STATE I/O
PARALLEL BUS INTERFACE
Signal
Name
Type
PLCC
Pin #
TQFP
Pin #
Description
D7
D6
D5
D4
D3
D2
D1
D0
IO_Z
9
8
7
6
5
4
3
2
3
2
1
48
47
46
45
44
Data Bus:
Data bus comprises eight TRI-STATE input/output lines. The bus provides bidirectional
communications between the UART and the CPU. Data, control words, and status information
are transferred via the D7-D0 Data Bus.
A2
A1
A0
I
15
14
10
10
9
4
Register Addresses:
Address signals connected to these 3 inputs select a DUART register for the CPU to read
from or write to during data transfer. Table 1 shows the registers and their addresses. Note
that the state of the Divisor Latch Access Bit (DLAB), which is the most significant bit of the
Line Control Register, affects the selection of certain DUART registers. The DLAB must be
set high by the system software to access the Baud Generator Divisor Latches and the
Alternate Function Register.
CS
I
18
13
Chip Select:
When CS is low, the chip is selected. This enables communication between the DUART and
the CPU. Valid chip select should stabilize according to the tAW parameter.
CHSL
I
16
11
Channel Select:
CHSL directs the address and data information to the selected serial channel. (Table 1)
1 = channel 1 is selected.
0 = channel 2 is selected.
RD
I
24
20
IO Read:
The register data is placed on the D0 - D7 on the falling edge of RD. The CPU can read
status information or data from the selected DUART register on the rising edge.
WR
I
20
15
IO Write:
On the falling edge of WR, data is placed on the D0 - D7. On the rising edge, the data is
latched into the selected DUART register.
RXRDY1
RXRDY2
O
N/A
31
8
UART Receive-ready: The receiver DMA signaling is available through this pin which is a
separate pin on the TQFP package, while on the PLCC package it is available through the MF
pins (19, 35). When operating in the FIFO mode, the CPU selects one of two types of DMA
transfer via FCR[3]. When operating in the 16450 Mode, only DMA mode 0 is available. Mode
0 supports single transfer DMA (and a transfer is usually made between CPU bus cycles).
Mode 1 supports multi-transfer DMA where multiple transfers are made continuously until the
Rx FIFO is empty. Details regarding the active and inactive states of this signal are described
in FIFO CONTROL REGISTER (FCR) and DMA OPERATION.
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
Submit Documentation Feedback
3
NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
Signal
Name
Type
PLCC
Pin #
TQFP
Pin #
www.ti.com
Description
TXRDY1
TXRDY2
O
1
32
43
28
UART Transmit-ready:
Transmitter DMA signaling is available through this pin. When operating in the FIFO mode,
the CPU selects one of two types of DMA transfer via FCR[3]. When operating in the 16450
Mode, only DMA mode 0 is allowed. Mode 0 supports single transfer DMA (and a transfer is
usually made between CPU bus cycles). Mode 1 supports multi-transfer DMA where multiple
transfers are made continuously until the Tx FIFO is full. Details regarding the active and
inactive states of this signal are described in FIFO CONTROL REGISTER (FCR) and DMA
OPERATION.
INTR1
INTR2
O
34
17
30
12
Interrupt Output:
INTR goes high whenever any one of the following interrupt types has an active high
condition and is enabled via the IER: Receiver Error Flag; Received Data Available: time-out
(FIFO Mode only); Transmitter Holding Register Empty; MODEM Status; and hardware and
software flow control. The INTR signal is reset low upon the appropriate interrupt service or a
Master Reset operation.
SERIAL IO INTERFACE
Signal
Name
SOUT1
Type
PLCC
Pin #
TQFP
Pin #
O
38
35
UART Serial Data Out:
26
22
UART transmit data output or infrared data output. The SOUT signal is set to logic 1 upon reset or
idle in the UART mode when MCR[6]=0. The SOUT signal transitions to logic 0 (idle state of IrDA
mode) in the infrared mode when MCR[6]=1.
Note: SOUT1 and SOUT2 can not be reset to IrDA mode.
SOUT2
Description
SIN1
SIN2
I
39
25
36
21
UART Serial Data In:
UART receive data input or infrared data input. The SIN should be idling in logic 1 in the UART
mode. The SIN should be idling in logic 0 in the infrared mode. The SIN should be pulled high
through a 10K resistor if not used.
RTS1
RTS2
O
36
23
33
18
UART Request-to-send:
When low, RTS informs the remote link partner that it is ready to receive data. The RTS output
signal can be set to an active low by writing “1” to MCR[1]. The RTS output can also be configured
in auto hardware flow control based on FIFO trigger level. This pin stays logic 1 upon reset or idle
(i.e., between data transfers). Loop mode operation holds this signal in its inactive state.
DTR1
DTR2
O
37
27
34
23
UART Data-terminal-ready:
When low, DTR informs the remote link partner that the UART is ready to establish a
communications link. The DTR output signal can be set to an active low by writing “1” to MCR[0].
This pin stays at logic 1 upon reset or idle. Loop mode operation holds this signal to its inactive
state.
CTS1
CTS2
I
40
28
38
24
UART Clear-to-send:
When low, CTS indicates that the remote link partner is ready to receive data. The CTS signal is a
modem status input and can be read for the appropriate channel in MSR[4]. This bit reflects the
complement of the CTS signal. MSR[0] indicates whether the CTS input has changed state since
the previous read of the MSR. CTS can also be configured to perform auto hardware flow control.
Note: Whenever the CTS bit of the MSR changes state, an interrupt is generated if the MODEM
Status Interrupt is enabled.
DSR1
DSR2
I
41
29
39
25
UART Data-set-ready:
When low, DSR indicates that the remote link partner is ready to establish the communications
link. The DSR signal is a MODEM status input and can be read for the appropriate channel in
MSR[5]. This bit reflects the complement of the DSR signal. MSR[1] indicates whether the DSR
input has changed state since the previous read of the MODEM Status Register.
Note: Whenever the DSR bit of the MSR changes state, an interrupt is generated if the MODEM
Status Interrupt is enabled.
DCD1
DCD2
I
42
30
40
26
UART Data-carrier-detect:
When low, DCD indicates that the data carrier has been detected by the remote link partner. The
DCD signal is a MODEM status input and can be read for the appropriate channel in MSR[7]. This
bit reflects the complement of the DCD signal. MSR[3] indicates if the DCD input has changed
state since the previous reading of the MODEM Status Register. DCD has no effect on the
receiver.
Note: Whenever the DCD bit of the MSR changes state, an interrupt is generated if the MODEM
Status Interrupt is enabled.
4
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
NS16C2552, NS16C2752
www.ti.com
Signal
Name
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
Type
PLCC
Pin #
TQFP
Pin #
Description
RI1
RI2
I
43
31
41
27
UART Ring-detector:
When low, RI indicates that a telephone ringing is active. The RI signal is a MODEM status input
and can be read for the appropriate channel in MSR[6]. This bit reflects the complement of the RI
signal. MSR[2] indicates whether the RI input signal has changed state from low to high since the
previous reading of the MSR.
Note: Whenever the RI bit of the MSR changes from a high to a low state, an interrupt is
generated if the MODEM Status Interrupt is enabled.
MF1
MF2
O
35
19
32
14
UART Multi-function Pin:
MF can be programmed for any one of three signal functions OUT2, BAUDOUT or RXRDY. Bits 2
and 1 of the Alternate Function Register select which output signal will be present on this pin.
OUT2 is the default signal and it is selected immediately after master reset or power-up.
The OUT2 can be set active low by programming bit 3 (OUT2) of the MCR to a logic 1. A Master
Reset operation sets this signal to its inactive (high) state. Loop Mode holds this signal in its
inactive state.
The BAUDOUT signal is the 16X clock output that drives the transmitter and receiver logic of the
associated serial channel. This signal is the result of the XIN clock divided by the value in the
Divisor Latch Registers. The BAUDOUT signal for each channel is internally connected to provide
the receiver clock (formerly RCLK on the PC16550D).
The RXRDY signal can be used to request a DMA transfer of data from the RCVR FIFO. Details
regarding the active and inactive states of this signal are described in FIFO CONTROL
REGISTER (FCR) and DMA OPERATION.
CLOCK AND RESET
Signal
Name
Type
PLCC
Pin #
TQFP
Pin #
XIN
I
11
5
External Crystal Input:
XIN input is used in conjunction with XOUT to form a feedback circuit for the baud
rate generator's oscillator. If a clock signal is generated off-chip, then it should drive
the baud rate generator through this pin. Refer to CLOCK INPUT.
XOUT
O
13
7
External Crystal Output:
XOUT output is used in conjunction with XIN to form a feedback circuit for the baud
rate generator's oscillator. If the clock signal is generated off-chip, then this pin is
unused. Refer to CLOCK INPUT.
MR
I
21
16
Master Reset:
When MR input is high, it clears all the registers including Tx and Rx serial shift
registers (except the Receiver Buffer, Transmitter Holding, and Divisor Latches). The
output signals, such as OUT2, RTS, DTR, INTR, and SOUT are also affected by an
active MR input. (Refer to Table 26 and RESET).
Description
POWER AND GROUND
Signal
Name
Type
PLCC
Pin #
TQFP
Pin #
Description
VCC
I
33
44
29
42
VCC:
+2.97V to +5.5V supply.
GND
I
12
22
6
17
GND:
Device ground reference.
NC
I
N/A
19
37
No Connection:
These pins are only available on the TQFP package.
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
Submit Documentation Feedback
5
NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
Register Set
There are two identical register sets, one for each channel, in the DUART. All register descriptions in this section
apply to the register sets in both channels.
To clarify the descriptions of transmission and receiving operations, the nomenclatures through out this
documentation are as follows:
• Frame - Refers to all the bits between Start and Stop.
• Character or word - The payload of a frame, between 5 to 8 bits.
• “!=” - Not equal to.
• Res - Reserved bit.
The address and control pins to register selection is summarized in Table 1.
Table 1. Basic Register Addresses
C
H
A
N
N
E
L
1
C
H
A
N
N
E
L
2
6
DLAB1
CHSL
A2
A1
A0
Register
0
1
0
0
0
Receive Buffer (Read), Transmitter Holding Register (Write)
0
1
0
0
1
Interrupt Enable
0
1
0
1
0
Interrupt Identification (Read)
0
1
0
1
0
FIFO Control (Write)
x
1
0
1
1
Line Control
x
1
1
0
0
Modem Control
x
1
1
0
1
Line Status (Read)
x
1
1
1
0
Modem Status (Read)
x
1
1
1
1
Scratchpad
1
1
0
0
0
Divisor Latch (Least Significant Byte)
1
1
0
0
1
Divisor Latch (Most Significant Byte)
1
1
0
1
0
Alternate Function
DLAB1
CHSL
A2
A1
A0
Register
0
0
0
0
0
Receive Buffer (Read), Transmitter Holding Register (Write)
0
0
0
0
1
Interrupt Enable
0
0
0
1
0
Interrupt Identification (Read)
0
0
0
1
0
FIFO Control (Write)
x
0
0
1
1
Line Control
x
0
1
0
0
Modem Control
x
0
1
0
1
Line Status (Read)
x
0
1
1
0
Modem Status (Read)
x
0
1
1
1
Scratchpad
1
0
0
0
0
Divisor Latch (Least Significant Byte)
1
0
0
0
1
Divisor Latch (Most Significant Byte)
1
0
0
1
0
Alternate Function
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
Table 2. NS16C2552 Register Summary
Reg
Addr
A2-A0
RD/
WR
BIT 7
R/W
Data7
X
X
X
X
X
X
X
X
R/W
CTS Int
Ena
RTS Int
Ena
Xoff Int
Ena
Sleep Md
Ena
Modem
Stat Int
Ena
RX Line
Stat Int
Ena
Tx Empty
Int Ena
Rx Data
Int Ena
0
0
0
0
0
0
0
0
R
FIFOs
Ena
FIFOs
Ena
INT Src
Bit 5
INT Src
Bit 4
INT Src
Bit 3
INT Src
Bit 2
INT Src
Bit 1
INT Src
Bit 0
0
0
0
0
0
0
0
1
W
RX FIFO
Trigger
RX FIFO
Trigger
Tx FIFO
Trigger
(2752)
Tx FIFO
Trigger
(2752)
DMA Md
Ena
Tx FIFO
Reset
Rx FIFO
Reset
FIFOs Ena
0
0
0
0
0
0
0
0
R/W
Divisor
Ena
Set Tx
Break
Set
Parity
Even
Parity
Parity
Ena
Stop
Bits
Word
Length
Bit 1
Word
Length
Bit 0
0
0
0
0
0
0
0
0
R/W
Clk Div
Sel
IR Md
Ena
Xon
Any
Internal
Loopbk
Ena
OUT2
OUT1
RTS
Output
Control
DTR
Output
Control
0
0
0
0
0
0
0
0
R
Rx FIFO
Gbl Err
THR &
TSR
Empty
THR E
mpty
Rx
Break
Rx Frame
Error
Rx Parity
Error
Rx
Overrun
Error
Rx Data
Ready
0
1
1
0
0
0
0
0
DCD
Input
RI
Input
DSR
Input
CTS
Input
Delta
DCD
Delta
RI
Delta
DSR
Delta
CTS
DCD
RI
DSR
CTS
0
0
0
0
SCR
SCR
SCR
SCR
SCR
SCR
SCR
SCR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Data1
Data0
Comment
UART 16C550 Compatible Registers (Default Values Upon Reset)
RBR
THR
0x0
Default
IER
0x1
Default
IIR
0x2
Default
FCR
0x2
Default
LCR
0x3
Default
MCR
0x4
Default
LSR
0x5
Default
MSR
0x6
R
Default
SCR
R/W
0x7
Default
Data6
Data5
Data4
Data3
Data2
LCR[7] = 0
LCR !=
0xBF
Baud Rate Generator Divisor
DLL
R/W
0x0
Default
DLM
R/W
0x1
Default
DLL
DLL
DLL
DLL
DLL
DLL
DLL
DLL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
DLM
DLM
DLM
DLM
DLM
DLM
DLM
DLM
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Rsrvd
Rsrvd
Rsrvd
Rsrvd
Rsrvd
RXRDY
BAUDOUT
Concurrent
0x2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Sel
Sel
WR
Default
0
0
0
0
0
0
0
0
ID
Bit 7
ID
Bit 6
ID
Bit 5
ID
Bit 4
DREV
Bit 3
DREV
Bit 2
DREV
Bit 1
DREV
Bit 0
AFR
DREV
0x0
R/W
R
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
LCR[7] = 1
LCR !
0xBF
LCR[7] = 1
LCR !=
0xBF
DLL =
0x00
DLM =
0x00
Submit Documentation Feedback
7
NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
Table 2. NS16C2552 Register Summary (continued)
Reg
Addr
A2-A0
RD/
WR
BIT 7
BIT 6
BIT 5
BIT 4
Auto CTS
Ena
Auto RTS
Ena
Special
Char Sel
IER[7:4]
IIR[5:4]
FCR[5:4]
MCR[7:5]
0
0
0
XON1
XON1
Bit 7
Bit 6
0
BIT 3
BIT 2
BIT 1
BIT 0
SW Flow
Control Bit
3
SW Flow
Control Bit
2
SW Flow
Control Bit
1
SW Flow
Control Bit
0
0
0
0
0
0
XON1
XON1
XON1
XON1
XON1
XON1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
XON2
XON2
XON2
XON2
XON2
XON2
XON2
XON2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Comment
Enhanced Registers
EFR
0x2
R/W
Default
XON1
R/W
0x4
Default
XON2
R/W
0x5
Default
0
0
0
0
0
0
0
0
XOFF1
XOFF1
XOFF1
XOFF1
XOFF1
XOFF1
XOFF1
XOFF1
0x6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
0
0
0
0
0
0
0
0
XOFF2
XOFF2
XOFF2
XOFF2
XOFF2
XOFF2
XOFF2
XOFF2
0x7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
0
0
0
0
0
0
0
0
XOFF1
R/W
XOFF2
R/W
LCR =
0xBF
Legend:
• Bit Name
• Default Value
The Nomenclature of register descriptions:
• Register name, address, register bit, and value example:
– FCR 0x2.7:6 = 2’b11 - bits 6 and 7 of FCR are both 1.
– Alternative description: FCR[7:6] = 2’b11.
• ‘b - binary number.
• ‘h - hex number.
• 0xNN - hex number.
• n’bN - n is the number of bits; N is the bit value. Example 8’b01010111 = 8’h57 = 0x57.
RECEIVE BUFFER REGISTER (RBR)
The receiver section contains an 8-bit Receive Shift Register (RSR) and a 16 (or 64)-byte FIFO that can be
accessed through Receive Buffer Register (RBR).
Table 3. RBR (0x0)
8
Bit
Bit Name
R/W Def
7:0
RBR Data
R
0xXX
Submit Documentation Feedback
Description
Receive Buffer Register
Rx FIFO data.
Note: This register value does not change upon MR reset.
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
TRANSMIT HOLDING REGISTER (THR)
This register holds the byte-wide transmit data (THR). This is a write-only register.
Table 4. THR (0x0)
Bit
Bit Name
R/W Def
7:0
THR Data
W
0xXX
Description
Transmit Holding Register
Tx FIFO data.
Note: This register value does not change upon MR reset.
INTERRUPT ENABLE REGISTER (IER)
This register enables eight types of interrupts for the corresponding serial channel. Each interrupt source can
individually activate the interrupt (INTR) output signal. Setting the bits of the IER to a logic 1 unmasks the
selected interrupt(s). Similarly, the interrupt can be masked off by resetting bits 0 through 7 of the Interrupt
Enable Register (IER). If not desired to be used, masking an interrupt source prevents it from going active in the
IIR and activating the INTR output signal. While interrupt sources are masked off, all system functions including
the Line Status and MODEM Status still operate in their normal manner. Table 5 shows the contents of the IER.
Table 5. IER (0x1)
Bit
7
Bit Name
R/W
Def
CTS Int Ena
R/W
0
Description
CTS Input Interrupt Enable
1 = Enable the CTS to generate interrupt at low to high transition. Requires EFR 0x2.4 = 1.
0 = Disable the CTS interrupt (default).
6
RTS Int Ena
R/W
0
RTS Output Interrupt Enable
1 = Enable the RTS to generate interrupt at low to high transition. Requires EFR 0x2.4 = 1.
0 = Disable the RTS interrupt (default).
5
Xoff Int Ena
R/W
0
Xoff Input Interrupt Enable
1 = Enable the software flow control character Xoff to generate interrupt. Requires EFR 0x2.4 = 1.
0 = Disable the Xoff interrupt (default).
4
Sleep Mode
Ena
R/W
Mdm Stat Int
Ena
R/W
Rx Line Stat Int
Ena
R/W
0
Sleep Mode Enable
1 = Enable the Sleep Mode for the respective channel. Requires EFR 0x2.4 = 1.
0 = Disable Sleep Mode (default).
3
0
Modem Status Interrupt Enable
1 = Enable the Modem Status Register interrupt.
0 = Disable the Modem Status Register interrupt (default).
2
0
Receive Line Status Interrupt Enable
An interrupt can be generated when any of the LSR bits 0x5.4:1=1. LSR 0x5.1 generates an interrupt as
soon as an overflow frame is received. LSR 0x5.4:2 generate an interrupt when there is read error from
FIFO.
1 = Enable the receive line status interrupt.
0 = Disable the receive line status interrupt (default).
1
Tx_Empty Int
Ena
R/W
Rx_DV Int Ena
R/W
0
Tx Holding Reg Empty Interrupt Enable
1 = Enable the interrupt when Tx Holding Register is empty.
0 = Disable the Tx Holding Register from generating interrupt (default).
0
0
Rx Data Available Interrupt Enable
1 = Enable the Received Data Available and FIFO mode time-out interrupt.
0 = Disable the Received Data Available interrupt (default).
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
Submit Documentation Feedback
9
NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
INTERRUPT IDENTIFICATION REGISTER (IIR)
In order to provide minimum software overhead during data word transfers, each serial channel of the DUART
prioritizes interrupts into seven levels and records these levels in the Interrupt Identification Register. The seven
levels of interrupt conditions are listed in Table 7. When the CPU reads the IIR, the associated DUART serial
channel freezes all interrupts and indicates the highest priority pending interrupt to the CPU. While this CPU
access is occurring, the associated DUART serial channel records new interrupts, but does not change its
current indication until the access is complete. Table 6 shows the contents of the IIR.
Table 6. IIR (0x2)
Bit
Bit Name
7:6
FIFOs Ena
R/W
Def
Description
R
FIFO Enable Status (FCR 0x2.0)
00
2'b11 = Tx and Rx FIFOs enabled.
2'b00 = Tx and Rx FIFOs disabled (default).
5
INT Src 5
R
RTS/CTS Interrupt Status
0
1 = RTS or CTS changed state from low to high.
0 = No change on RTS or CTS from low to high (default).
4
INT Src 4
R
Xoff or Special Character Interrupt Status
0
1 = Receiver detected Xoff or special character.
0 = No Xoff character match (default).
3:1
INT Src 3:1
R
Interrupt Source Status
000
0
INT Src 0
These three bits indicates the source of a pending interrupt. Refer to Table 7 for interrupt
source and priority.
R
Interrupt Status
1
1 = No interrupt is pending (default).
0 = An interrupt is pending and the IIR content may be used as a pointer for the interrupt
service routine.
Table 7. Interrupt Source and Priority Level
IIR Register Status Bits
Priority
Level
5
4
3
2
1
0
1
0
0
0
1
1
0
LSR
2
0
0
1
1
0
0
RXRDY (Receive data time-out)
3
0
0
0
1
0
0
RXRDY (Receive data ready)
4
0
0
0
0
1
0
TXRDY (Transmit data ready)
5
0
0
0
0
0
0
MSR (Modem Status Register)
6
0
1
0
0
0
0
RXRDY (Received Xoff or special character)
7
1
0
0
0
0
0
CTS, RTS change state from low to high
-
0
0
0
0
0
1
None (default)
Interrupt Source
Table 8. Interrupt Sources and Clearing
Interrupt
Generation
Interrupt Sources
Interrupt Clearing
LSR
Any bit is set in LSR[4:1] (Break Interrupt, Framing, Rx
parity, or overrun error).
Read LSR register. (Interrupt flags and tags are not cleared until
the character(s) that generated the interrupt(s) has/have been
emptied or cleared.)
Rx Trigger
Rx FIFO reached trigger level.
Read FIFO data until FIFO pointer falls below the trigger level.
RXRDY Timer
Time-out in 4-word time plus 12-bit delay time.
Read RBR.
TXRDY
THR empty.
Read from IIR register or a write to THR.
MSR
Any state change in MSR[3:0].
Read from MSR register.
10
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
Table 8. Interrupt Sources and Clearing (continued)
Interrupt
Generation
Interrupt Sources
Interrupt Clearing
Xoff or Special
character
Detection of Xoff or Special character.
Read from IIR register or reception of Xon character (or
reception of next character if interrupt is caused by Special
character).
CTS
Input pin toggles from logic 0 to 1 during CTS auto flow
control mode.
Read from IIR or MSR.
RTS
Output pin toggles from logic 0 to 1 during RTS auto
flow control mode.
Read from IIR or MSR.
FIFO CONTROL REGISTER (FCR)
This is a write only register at the same location as the IIR (the IIR is a read only register). This register is used
to enable the FIFOs, clear the FIFOs, set the FIFO trigger level, and select the DMA mode.
Mode 0: Mode 0 allows for single transfer in each DMA cycle. When in the 16450 Mode (FCR[0] = 0) or in the
FIFO Mode (FCR[0] = 1, FCR[3] = 0) and there is at least one character in the RCVR FIFO or RCVR Buffer
Register, the RXRDY pin will go active low. After going active, the RXRDY pin will be inactive when there is no
character in the FIFO or Buffer Register.
On The Tx side, TXRDY is active low when XMIT FIFO or XMIT Holding Register is empty. TXRDY returns to
high when XMIT FIFO or XMIT holding register is not empty.
Mode 1: Mode 1 allows for multiple transfer or multi-character burst transfer. In the FIFO Mode (FCR[0] = 1,
FCR[3] = 1) when the number of characters in the RCVR FIFO equals the trigger threshold level or timeout
occurs, the RXRDY goes active low to initiate DMA transfer request. The RXRDY returns high when RCVR FIFO
becomes empty.
In the FIFO Mode (FCR[0] = 1, FCR[3] = 1) when there is (1) no character in the XMIT FIFO for NS16C2552, or
(2) empty spaces exceed the threshold level for NS16C2752; the TXRDY pin will go active low. This pin will
become inactive when the XMIT FIFO is completely full.
Table 9. FCR (0x2)
Bit
Bit Name
R/W
Def
7:6
Rx FIFO
W
Rx FIFO Trigger Select
Trig
Select
00
FCR[6] and FCR[7] are used to designate the interrupt trigger level. When the number of characters in the
RCVR FIFO equals the designated interrupt trigger level, a Received Data Available Interrupt is activated.
This interrupt must be enabled by IER[0]=1.
Description
For NS16C2552 with 16-byte FIFO:
FCR[7]
FCR[6]
Rx FIFO Trigger Level
1
1
= 14
1
0
=8
0
1
=4
0
0
= 1 (Default)
For NS16C2752 with 64-byte FIFO:
FCR[7]
FCR[6]
Rx FIFO Trigger Level
1
1
= 60
1
0
= 56
0
1
= 16
0
0
= 8 (Default)
Refer to SOFTWARE XON/XOFF FLOW CONTROL and DMA OPERATION for software flow control using
FIFO trigger level.
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
Submit Documentation Feedback
11
NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
Table 9. FCR (0x2) (continued)
Bit
Bit Name
5:4
Tx FIFO
Trig Level
Sel
R/W
Def
Description
W
Transmit FIFO Trigger Level Selection
00
The transmit FIFO trigger threshold selection is only available in NS16C2752. When enabled, a transmit
interrupt is generated and TXRDY is asserted when the number of empty spaces in the FIFO exceeds the
threshold level.
For NS16C2752 with 64-byte FIFO:
FCR[5]
FCR[4]
Tx FIFO Trigger Level
1
1
= 56
1
0
= 32
0
1
= 16
0
0
= 8 (Default)
Refer to TRANSMIT OPERATION and DMA OPERATION for transmit FIFO descriptions.
These two bits are reserved in NS16C2552 and have no impact when they are written to.
3
DMA
Mode
Select
W
DMA Mode Select
0
This bit controls the RXRDY and TXRDY initiated DMA transfer mode.
1 = DMA Mode 1. Allows block transfers. Requires FCR 0x2.0=1 (FIFO mode).
0 = DMA Mode 0 (default). Single transfers.
2
Tx FIFO
Reset
W
Transmit FIFO Reset
0
This bit is only active when FCR bit 0 = 1.
1 = Reset XMIT FIFO pointers and all bytes in the XMIT FIFO (the Tx shift register is not cleared and is
cleared by MR reset). This bit has the self-clearing capability.
0 = No impact (default).
Note: Reset pointer will cause the characters in Tx FIFO to be lost.
1
Rx FIFO
Reset
W
Receive FIFO Reset
0
This bit is only active when FCR bit 0 = 1.
1 = Reset RCVR FIFO pointers and all bytes in the RCVR FIFO (the Rx shift register is not cleared and is
cleared by MR reset). This bit has the self-clearing capability.
0 = No impact (default).
Note: Reset pointer will cause the characters in Rx FIFO to be lost.
0
Tx and Rx
FIFO
Enable
W
Transmit and Receive FIFO Enable
0
1 = Enable transmit and receive FIFO. This bit must be set before other FCR bits are written. Otherwise, the
FCR bits can not be programmed.
0 = Disable transmit and receive FIFO (default).
LINE CONTROL REGISTER (LCR)
The system programmer specifies the format of the asynchronous data communications exchange and sets the
Divisor Latch Access bit via the Line Control Register (LCR). This is a read and write register.
Table 10. LCR (0x3)
Bit
7
12
Bit Name
Default
R/W
Def
Divisor Latch
Ena
R/W
0
Description
Divisor Latch Access Bit (DLAB)
This bit must be set (logic 1) to access the Divisor Latches of the Baud Generator and the Alternate
Function Register during a read or write operation. It must be cleared (logic 0) to access any other
register.
1 = Enable access to the Divisor Latches of the Baud Generator and the AFR.
0 = Enable access to other registers (default).
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
Table 10. LCR (0x3) (continued)
Bit
Bit Name
Default
R/W
Def
6
Tx Break Ena
R/W
0
Description
Set Tx Break Enable
This bit is the Break Control bit. It causes a break condition to be transmitted to the receiving UART.
The Break Control bit acts only on SOUT and has no effect on the transmitter logic.
1 = Serial output (SOUT) is forced to the Spacing State (break state, logic 0).
0 = The break transmission is disabled (default).
Note: This feature enables the CPU to alert a terminal in a computer communication system. If the
following sequence is followed, no erroneous or extraneous character will be transmitted because of
the break.
1. Load an all 0s, pad character, in response to THRE.
2. Set break after the next THRE.
3. Wait for the transmitter to be idle, (Transmitter Empty TEMT = 1), and clear break when normal
transmission has to be restored.
During the break, the transmitter can be used as a character timer to establish the break duration.
During the break state, any word left in THR will be shifted out of the register but blocked by SOUT
as forced to break state. This word will be lost.
5
4
Forced
Parity Sel
Even/Odd
Parity Sel
R/W
0
R/W
0
Tx and Rx Forced Parity Select
When parity is enabled, this bit selects the forced parity format.
LCR[5]
LCR[4]
LCR[3]
1
1
1
Force parity to space = 0
Parity Select
1
0
1
Force parity to mark = 1
0
1
1
Even parity
0
0
1
Odd parity
X
X
0
No parity
Tx and Rx Even/Odd Parity Select
This bit is only effective when LCR[3]=1. This bit selects even or odd parity format.
1 = Odd parity is transmitted or checked.
0 = Even parity is transmitted or checked (default).
3
Tx/Rx Parity
Ena
R/W
0
Tx and Rx Parity Enable
This bit enables parity generation.
1 = A parity is generated during the data transmission. The receiver checks for parity error of the
data received.
0 = No parity (default).
2
Tx/Rx Stop-bit
Length Sel
R/W
0
Tx and Rx Stop-bit Length Select
This bit specifies the number of Stop bits transmitted with each serial character.
LCR[2]
Word Length Sel
Stop-bit Length
1
6,7,8
=2
1
5
= 1.5
0
5,6,7,8
= 1(Default)
Stop-bit length is measured in bit time.
1:0
Tx/Rx Word
Length Sel
R/W
0
Tx and Rx Word Length Select
These two bits specify the word length to be transmitted or received.
LCR[1]
LCR[0]
1
1
Word Length
=8
1
0
=7
0
1
=6
0
0
= 5 (Default)
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
Submit Documentation Feedback
13
NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
MODEM CONTROL REGISTER (MCR)
This register controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM).
There is a clock divider for each channel. Each is capable of taking a common clock input from DC to 80 MHz
and dividing the clock frequency by 1 (default) or 4 depending on the MCR[7] value. The clock divider and the
internal clock division flow is shown in Figure 3.
Figure 3. Internal Clock Dividers
Table 11. MCR (0x4)
Bit
Bit Name
7
Clk Divider
Sel
R/W
Def
R/W
0
Description
Clock Divider Select
This bit selects the clock divider from crystal or oscillator input. The divider output connects to the Baud
Rate Generator.
1 = Divide XIN frequency by 4.
0 = Divide XIN frequency by 1 (default).
6
IR Mode Sel
R/W
0
Infrared Encoder/Decoder Select
This bit selects standard modem or IrDA interface.
1 = Infrared IrDA Tx/Rx. The data input and output levels complies to the IrDA infrared interface. The Tx
output is at logic 0 during the idle state.
0 = Standard modem Tx/Rx (default).
5
Xon-Any
Ena
R/W
0
Xon-Any Enable
This bit enables Xon-Any feature.
1 = Enable Xon-Any function. When Xon/Xoff flow control is enabled, the transmission resumes when
any character is received. The received character is loaded into the Rx FIFO except for Xon or Xoff
characters.
0 = Disable Xon-Any function (default).
4
Internal
Loopback
Ena
R/W
0
Internal Loopback Enable
This bit provides a local loopback feature for diagnostic testing of the associated serial channel. (Refer
to INTERNAL LOOPBACK MODE and Figure 15.)
1 = the transmitter Serial Output (SOUT) is set to the Marking (logic 1) state; the receiver Serial Input
(SIN) is disconnected; the output of the Transmitter Shift Register is looped back into the Receiver Shift
Register input; the four MODEM Control inputs (DSR, CTS, RI, and DCD) are disconnected; the four
MODEM Control outputs (DTR, RTS, OUT1 and OUT2) are internally connected to the four MODEM
Control inputs; and the MODEM Control output pins are forced to their inactive state (high). In this
diagnostic mode, data that is transmitted is immediately received. This feature allows the processor to
verify transmit and receive data paths of the DUART. In this diagnostic mode, the receiver and
transmitter interrupts are fully operational. Their sources are external to the part. The MODEM Control
Interrupts are also operational, but the interrupt sources are now the lower four bits of the MODEM
Control Register instead of the four MODEM Control inputs. The interrupts are still controlled by the
Interrupt Ena
0 = Normal Tx/Rx operation; loopback disabled (default).
14
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
Table 11. MCR (0x4) (continued)
Bit
Bit Name
R/W
Def
3
OUT2
R/W
Description
Output2
0
This bit controls the Output 2 (OUT2) signal, which is an auxiliary user-designated output. Bit 3 affects
the OUT2 pin as described below. The function of this bit is multiplexed on a single output pin with two
other functions: BAUDOUT and RXDRY. The OUT2 function is the default function of the pin after a
master reset. See ALTERNATE FUNCTION REGISTER (AFR) for more information about selecting one
of these 3 pin functions.
1 = Force OUT2 to logic 0.
0 = Force OUT2 to logic 1 (default).
2
OUT1
R/W
Output1
0
In normal operation, OUT1 bit is not available as an output.
In internal Loopback Mode (MCR 0x4.4=1) this bit controls the state of the modem input RI in the MSR
bit 6.
1 = MSR 0x06.6 is at logic 1.
0 = MSR 0x06.6 is at logic 0.
1
RTS Output
R/W
RTS Output Control
0
This bit controls the RTS pin. If modem interface is not used, this output is used as a general purpose
output.
1 = Force RTS pin to logic 0.
0 = Force RTS pin to logic 1(default).
0
DTR Output
R/W
DTR Output Control
0
This bit controls the DTR pin. If modem interface is not used, this output is used as a general purpose
output.
1 = Force DTR pin to logic 0.
0 = Force DTR pin to logic 1(default).
LINE STATUS REGISTER (LSR)
This register provides status information to the CPU concerning the data transfer.
Bits 1 through 4 are the error conditions that produce a Receiver Line Status interrupt whenever any of the
corresponding conditions are detected and the interrupt is enabled.
Table 12. LSR (0x5)
Bit
Bit Name
R/W
Def
7
Rx FIFO Err
R
Rx FIFO Data Error
0
This bit is a global Rx FIFO error flag. In the 16450 Mode this bit is 0.
Description
1 = A sum of all error bits in the Rx FIFO. These errors include parity, framing, and break indication
in the FIFO data.
0 = No Rx FIFO error (default).
Note: The Line Status Register is intended for read operations only. Writing to this register is not
recommended as this operation is only used for factory testing.
6
THR & TSR
Empty
R
THR and TSR Empty
1
This bit is the Transmitter Empty (TEMT) flag.
1 = Whenever the Transmitter Holding Register (THR) (or the Tx FIFO in FIFO mode) and the
Transmitter Shift Register (TSR) are both empty (default).
0 = Whenever either the THR (or the Tx FIFO in FIFO mode) or the TSR contains a data word.
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
Submit Documentation Feedback
15
NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
Table 12. LSR (0x5) (continued)
Bit
Bit Name
R/W
Def
5
THR Empty
R
THR Empty
1
This bit is the Transmitter Holding Register Empty (THRE) flag. In the 16450 mode bit 5 indicates
that the associated serial channel is ready to accept a new character for transmission. In addition,
this bit causes the DUART to issue an interrupt to the CPU when the Transmit Holding Register
Empty interrupt enable is set.
Description
1 = In 16450 mode, whenever a character is transferred from the Transmitter Holding Register into
the Transmitter Shift Register, or in FIFO mode when the Tx FIFO is empty (default).
0 = In 16450 mode, this bit is reset to logic 0 concurrently with the loading of the Transmitter Holding
Register by the CPU. In FIFO mode, it is cleared when at least 1 byte is written to the Tx FIFO.
4
Rx Break
Interrupt
R
Receive Break Interrupt Indicator
0
This bit is the Break Interrupt (BI) indicator.
1 = Whenever the received data input is held in the Spacing (logic 0) state for longer than a full
frame transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).
0 = No break condition (default).
This bit is reset to 0 whenever the CPU reads the contents of the Line Status Register or when the
next valid character is loaded into the Receiver Buffer Register.
In the FIFO Mode this condition is associated with the particular character in the FIFO it applies to. It
is revealed to the CPU when its associated character is at the top of the FIFO. When break occurs
only one zero character is loaded into the FIFO. The next character transfer is enabled after SIN
goes to the Marking (logic 1) state and receives the next valid start bit.
3
Rx Frame Error
R
Framing Error Indicator
0
This bit is the Framing Error (FE) indicator.
1= Received character did not have a valid Stop bit when the serial channel detects a logic 0 during
the first Stop bit time.
0 = No frame error (default).
The bit is reset to 0 whenever the CPU reads the contents of the Line Status Register or when the
next valid character is loaded into the Receiver Buffer Register. In the FIFO Mode this error is
associated with the particular character in the FIFO it applies to. This error is revealed to the CPU
when its associated character is at the top of the FIFO. The serial channel will try to resynchronize
after a framing error. This assumes that the framing error was due to the next start bit, so it samples
this start bit twice and then takes in the data.
2
Rx Parity Error
R
Parity Error Indicator
0
This bit is the Parity Error (PE) indicator.
1 = Received data word does not have the correct even or odd parity, as selected by the evenparity-select bit during the character Stop bit time when the character has a parity error.
0 = No parity error (default).
This bit is reset to a logic 0 whenever the CPU reads the contents of the Line Status Register or
when the next valid character is loaded into the Receiver Buffer Register. In the FIFO mode this
error is associated with the particular character in the FIFO it applies to. This error is revealed to the
host when its associated character is at the top of the FIFO.
1
Rx Overrun
Error
R
Overrun Error Indicator
0
This bit is the Overrun Error (OE) indicator.
This bit indicates that the next character received was transferred into the Receiver Buffer Register
before the CPU could read the previously received character. This transfer overwrites the previous
character. It is reset whenever the CPU reads the contents of the Line Status Register. If the FIFO
mode data continues to fill the FIFO beyond the trigger level, an overrun error will occur only after
the FIFO is full and the next character has been completely received in the shift register. OE is
indicated to the CPU as soon as it happens. The character in the shift register can be overwritten,
but it is not transferred to the FIFO.
1 = Set to a logic 1 during the character stop bit time when the overrun condition exists.
0 = No overrun error (default).
0
Rx Data Ready
R
Receiver Data Indicator
0
This bit is the receiver Data Ready (DR) indicator.
1 = Whenever a complete incoming character has been received and transferred into the Receiver
Buffer Register (RBR) or the FIFO. Bit 0 is reset by reading all of the data in the RBR or the FIFO.
0 = No receive data available (default).
16
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
MODEM STATUS REGISTER (MSR)
This register provides the current state of the control lines from the MODEM (or peripheral device) to the CPU. In
addition to this current-state information, four bits of the MODEM Status Register provide change information.
The latter bits are set to a logic 1 whenever a control input from the MODEM changes state. They are reset to
logic 0 whenever the CPU reads the MODEM Status Register.
Table 13. MSR (0x6)
Bit
Bit Name
R/W
Def
7
DCD Input
R
Status
DCD
6
RI Input
Status
Description
DCD Input Status
This bit is the complement of the Data Carrier Detect (DCD) input. In the loopback mode, this bit is
equivalent to the OUT2 of the MCR.
1 = DCD input is logic 0.
0 = DCD input is logic 1.
R
RI Input Status
RI
This bit is the complement of the Ring Indicator (RI) input. In the loopback mode, this bit is equivalent to
OUT1 of the MCR.
1 = RI input is logic 0.
0 = RI input is logic 1.
5
DSR Input
Status
R
DSR
DSR Input Status
This bit is the complement of the Data Set Ready (DSR) input. In the loopback mode, this bit is
equivalent to DTR in the MCR.
1 = DSR input is logic 0.
0 = DSR input is logic 1.
4
CTS Input
Status
R
CTS
CTS Input Status
This bit is the complement of the Clear to Send (CTS) input. In the loopback mode, this bit is equivalent
to RTS in the MCR.
1 = CTS input is logic 0.
0 = CTS input is logic 1.
3
DDCD Input
Status
R
Delta DCD Input Indicator
0
This bit is the Delta Data Carrier Detect (DDCD) indicator. Bit 3 indicates that the DCD input has changed
state since the last read by the host.
1 = DCD input has changed state.
0 = DCD input has no state change (default).
Note: Whenever bit 0, 1, 2, or 3 is set to logic 1, a MODEM Status Interrupt is generated.
2
Falling Edge
RI Indicator
R
Falling Edge RI Indicator
0
This bit is theFalling Edge of Ring Indicator (TERI) detector. Bit 2 indicates that the RI input pin has
changed from a logic 0 to 1 since the last read by the host.
1 = RI input has changed state from logic 0 to 1.
0 = RI input has no state change from 0 to 1 (default).
1
DDSR Input
Indicator
R
Delta DSR Input Indicator
0
This bit is the Delta Data Set Ready (DDSR) indicator. Bit 1 indicates that the DSR input pin has changed
state since the last read by the host.
1 = DSR input has changed state from logic 0 to 1.
0 = DSR input has no state change from 0 to 1 (default).
0
DCTS Input
Indicator
R
Delta CTS Input Indicator
0
This bit is the Delta Clear to Send (DCTS) indicator. Bit 0 indicates that the CTS input pin has changed
state since the last time it was read by the host.
1 = CTS input has changed state.
0 = CTS input has no state change (default).
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
Submit Documentation Feedback
17
NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
SCRATCHPAD REGISTER (SCR)
This 8-bit Read/Write Register does not control the serial channel in any way. It is intended as a Scratchpad
Register to be used by the programmer to hold data temporarily.
Table 14. SCR (0x7)
Bit
Bit Name
7:0
SCR Data
R/W
Def
Description
R/W
0xFF
Scratchpad Register
This 8-bit register does not control the UART in any way. It is intended as a scratchpad register
to be used by the programmer to hold temporary data.
PROGRAMMABLE BAUD GENERATOR
The NS16C2552 contains two independently programmable Baud Generators. Each is capable of taking
prescaler input and dividing it by any divisor from 1 to 216 -1 (Figure 3). The highest input clock frequency
recommended with a divisor = 1 is 80MHz. The output frequency of the Baud Generator is 16 X the baud rate,
[divisor # = (frequency input) / (baud rate X 16)]. The output of each Baud Generator drives the transmitter and
receiver sections of the associated serial channel. Two 8-bit latches per channel store the divisor in a 16-bit
binary format. These Divisor Latches must be loaded during initialization to ensure proper operation of the Baud
Generator. Upon loading either of the Divisor Latches, a 16-bit Baud Counter is loaded.
Table 15. DLL (0x0, LCR[7] = 1, LCR != 0xBF)
Bit
Bit Name
7:0
DLL Data
R/W
Def
R/W
0xXX
Description
Divisor Latch LSB
This 8-bit register holds the least significant byte of the 16-bit baud rate generator divisor.
This register value does not change upon MR reset.
Table 16. DLM (0x1, LCR[7] = 1, LCR != 0xBF)
Bit
Bit Name
7:0
DLM Data
R/W
Def
R/W
0xXX
Description
Divisor Latch MSB
This 8-bit register holds the most significant byte of the 16-bit baud rate generator divisor.
This register value does not change upon MR reset.
Table 17 provides decimal divisors to use with crystal frequencies of 1.8432 MHz, 3.072 MHz and 18.432 MHz.
For baud rates of 38400 and below, the error obtained is minimal. The accuracy of the desired baud rate is
dependent on the crystal frequency chosen. Using a divisor of zero is not recommended.
Table 17. Baud Rate Generation Using 1.8432 MHz Clock with MCR[7]=0
18
Output Data
Baud Rate
Output 16x Clock
Divider (dec)
User 16x Clock
Divisor (hex)
DLM Program
Value (hex)
DLL Program
Value (hex)
Data Rate
Error (%)
50
2304
900
09
00
0
75
1536
600
06
00
0
150
768
300
03
00
0
300
384
180
01
80
0
600
192
C0
00
C0
0
1200
96
60
00
60
0
2400
48
30
00
30
0
4800
24
18
00
18
0
9600
12
0C
00
0C
0
19,200
6
06
00
06
0
38,400
3
03
00
03
0
115,200
1
01
00
01
0
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
NOTE
For baud rates of 250k, 300k, 375k, 500k, 750k and 1.5M using a 24MHz crystal causes
minimal error.
ALTERNATE FUNCTION REGISTER (AFR)
This is a read/write register used to select simultaneous write to both register sets and alter MF pin functions.
Table 18. AFR (0x2, LCR[7] = 1, LCR != 0xBF)
Bit
Bit Name
Default
7:3
Reserved
2:1
MF Output Sel
R/W
Def
Description
Reserved
These bits are set to a logic 0.
R/W
Multi-function Pin Output Select
0
0
Concurrent Write
Ena
These select the output signal that will be present on the multi-function pin, MF. These bits are
individually programmable for each channel, so that different signals can be selected on each
channel.
R/W
AFR[2]
AFR[1]
1
1
MF Function
= Reserved (MF output is forced logic 1)
1
0
= RXRDY
0
1
= BAUDOUT
0
0
= OUT2 (default)
Concurrent Write Enable
0
1 = CPU can write concurrently to the same register in both registers sets. This function is
intended to reduce the DUART initialization time. It can be used by a CPU when both channels
are initialized to the same state. The CPU can set or clear this bit by accessing either register set.
When this bit is set the channel select pin still selects the channel to be accessed during read
operations. Setting or clearing this bit has no effect on read operations.
The user should ensure that the DLAB bit LCR[7] of both channels are in the same state before
executing a concurrent write to register addresses 0, 1 and 2.
0 = No concurrent write (default). (No impact on read operations.)
DEVICE IDENTIFICATION REGISTER (ID)
The device ID for NS16C2552 is 0x03. DLL and DLM should be initialized to 0x00 before reading the ID register.
This is a read-only register.
Table 19. DREV (0x0, LCR[7]=1, LCR!=0xBF, DLL=DLM=0x00)
Bit
Bit Name
R/W
Def
7:4
Device ID
R
Device ID
Value = 0x3 for NS16C2552; 0x2 for NS16C2752
3:0
Device Rev
R
Device Revision
Value = 0x1.
Description
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
Submit Documentation Feedback
19
NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
ENHANCED FEATURE REGISTER (EFR)
This register enables the enhanced features of the device.
Table 20. EFR (0x2, LCR = 0xBF)
Bit
7
Bit Name
Default
R/W
Def
Auto CTS
Flow Ctl
Ena
R/W
Auto RTS
Flow Ctl
Ena
R/W
0
Description
Automatic CTS Flow Control Enable
1 = Enable automatic CTS flow control. Data transmission stops when CTS input deasserts to logic 1. Data
transmission resumes when CTS returns to logic 0.
0 = Automatic CTS flow control is disabled (Default)
6
0
Automatic RTS Flow Control Enable
By setting EFR[6] to logic 1, RTS output can be used for hardware flow control. When Auto RTS is selected,
an interrupt is generated when the receive FIFO is filled to the programmed trigger level and RTS de-asserts
to a logic 1. The RTS output must be logic 0 before the auto RTS can take effect. RTS pin functions as a
general purpose output when hardware flow control is disabled.
1 = Enable automatic RTS flow control.
0 = Automatic RTS flow control is disabled (Default)
5
Special
Char Det
Ena
R/W
Enhanced
Fun Bit Ena
R/W
0
Special Character Detect Enable
1 = Special character detect enabled. The UART compares each incoming received character with data in
Xoff-2 register (0x4, LCR = 0xBF). If a match is found, the received data will be transferred to FIFO and
IIR[4] is set to indicate the detection of a special character if IER[5] = 1. Bit 0 corresponds with the LSB of
the received character. If flow control is set for comparing Xon1, Xoff1 (EFR[1:0] = 10) then flow control and
special character work normally; If flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=01) then flow
control works normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special
character interrupt if IER[5] is enabled. Special character interrupts are cleared automatically after the next
received character.
0 = Special character detect disabled. (Default)
4
0
Enhanced Function Bits Enable
This bit enables IER[7:4], FCR[5:4], and MCR [7:5] to be changed. After changing the enhanced bits, EFR[4]
can be cleared to logic 0 to latch in the updated values. EFR[4] allows compatibility with the legacy mode
software by disabling alteration of the enhanced functions.
1 = Enables writing to IER[7:4], FCR[5:4], and MCR [7:5].
0 = Disable writing to IER[7:4], FCR[5:4], MCR [7:5] and, latching in updated value. Upon reset, IER[7:4],
IIR[5:4], FCR[5:4], and MCR [7:5] are cleared to logic 0. (Default)
3:0
Software
Flow
Control Sel
R/W
0
Software Flow Control Select
Single character and dual sequential character software flow control is supported. Combinations of software
flow control can be selected by programming the bits.
EFR[3]
EFR[1]
EFR[0]
Rx Flow Control
1
1
1
Rx compares Xon1 & Xon2, Xoff1 & Xoff2
1
0
1
1
Rx compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Rx compares Xon1 or Xon2, Xoff1 or Xoff2
0
0
1
1
Rx compares Xon1 & Xon2, Xoff1 & Xoff2
X
X
1
0
Rx compares Xon1, Xoff1
X
X
0
1
Rx compares Xon2, Xoff2
X
X
0
0
No Rx flow control
0
0
0
0
No Tx & Rx flow control (default)
EFR[3]
20
EFR[2]
1
EFR[2]
EFR[1]
EFR[0]
Tx Flow Control
1
1
X
X
Tx Xon1 and Xon2, Xoff1 and Xoff2
1
0
X
X
Tx Xon1, Xoff1
0
1
X
X
Tx Xon2, Xoff2
0
0
X
X
No Tx flow control
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
NS16C2552, NS16C2752
www.ti.com
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
SOFTWARE FLOW CONTROL REGISTERS (SFR)
The following four registers are used as programmable software flow control characters.
Table 21. Xon1 (0x4, LCR=0xBF)
Bit
Bit Name
7:0
Xon1 Data
R/W
Def
R/W
0
Description
Xon1 Data
Table 22. Xon2 (0x5, LCR=0xBF)
Bit
Bit Name
7:0
Xon2 Data
R/W
Def
R/W
0
Description
Xon2 Data
Table 23. Xoff1 (0x6, LCR=0xBF)
Bit
Bit Name
7:0
Xoff1 Data
R/W
Def
R/W
0
Description
Xoff1 Data
Table 24. Xoff2 (0x7, LCR=0xBF)
Bit
Bit Name
7:0
Xoff2 Data
R/W
Def
R/W
0
Description
Xoff2 Data
Operation and Configuration
CLOCK INPUT
The NS16C2552/2752 has an on-chip oscillator that accepts standard crystal with parallel resonant and
fundamental frequency. The generated clock is supplied to both UART channels with the capability range from
DC to 24 MHz. The frequency of the clock oscillator is divided by 16 internally, combined with an on-chip
programmable clock divider providing the baud rate for data transmission. The divisor is 16-bit with MSB byte in
DLM and LSB byte in DLL. The divisor calculation is shown in PROGRAMMABLE BAUD GENERATOR.
The external oscillator circuitry requires two load capacitors, a parallel resistor, and an optional damping resistor.
The oscillator circuitry is shown in Figure 4.
Figure 4. Crystal Oscillator Circuitry
The requirement of the crystal is listed in Table 25.
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: NS16C2552 NS16C2752
Submit Documentation Feedback
21
NS16C2552, NS16C2752
SNLS238D – AUGUST 2006 – REVISED APRIL 2013
www.ti.com
Table 25. Crystal Component Requirement
Parameter
Value
Crystal Frequency Range
B
NS16C2752TVS/NOPB
ACTIVE
TQFP
PFB
48
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
NS16C2
752TVS
NS16C2752TVSX/NOPB
ACTIVE
TQFP
PFB
48
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
NS16C2
752TVS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
