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ONET1131EC
SLLSEQ6A – SEPTEMBER 2016 – REVISED SEPTEMBER 2016
ONET1131EC Externally Modulated Laser Driver With Integrated
Clock and Data Recovery (CDR)
1 Features
3 Description
•
The ONET1131EC is a 2.5-V EML modulator driver
with transmit clock and data recovery (CDR)
designed to operate between 9.8 Gbps and 11.7
Gbps without the need for a reference clock. CDR
bypass mode can be used for operation at lower data
rates and a two-wire serial interface allows digital
control of features like output polarity select and input
equalization.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Modulator Driver with Minimum Output Amplitude
up to 2 Vpp Single-Ended and Bias Current up to
150 mA Source
Supports Externally Modulated Lasers Including
the Electro-Absorption Modulator Lasers (EML)
and the Mach-Zahnder Modulator (MZM) Based
lasers
Integrated CDR with 9.80 – 11.7 Gbps ReferenceFree Operation
Two-Wire Digital Interface with Integrated DACs
and ADC for Control and Diagnostic Management
Output Polarity Select
Programmable Jitter Transfer Bandwidth to Adjust
CDR Bandwidth
CDR Bypass Mode for Low Data Rate Operation
Automatic Power Control (APC) Loop with
Selectable Monitor PD Range
Programmable Transmit Input Equalizer
Transmitter Cross-Point Adjust and De-Emphasis
Includes Laser Safety Features
Power Supply Monitor and Temperature Sensor
Single 2.5 V Supply
–40°C to 100°C Operation
Surface Mount 4 mm x 4 mm 32-Pin QFN
Package with 0.4 mm Pitch
The transmit path consists of an adjustable input
equalizer for equalization of up to 300 mm
(12 inches) of microstrip or stripline transmission line
of FR4 printed circuit boards, a multi-rate CDR and
an output modulator driver. Output waveform control,
in the form of cross-point adjustment and deemphasis, is available to improve the optical eye
mask margin. The device provides bias current for
the laser and an integrated automatic power control
(APC) loop to compensate for variations in average
optical power over voltage, temperature and time.
The ONET1131EC contains internal analog to digital
and digital to analog converters to support transceiver
management and eliminate the need for special
purpose microcontrollers.
Device Information(1)
PART NUMBER
ONET1131EC
PACKAGE
VQFN (32)
BODY SIZE (NOM)
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
10-Gbps Passive Optical Network (PON), Optical
Line Terminal (OLT) Transceivers for FTTx
deployment
XFP and SFP+ 10-Gbps SONET OC-192 Optical
Transceivers
XFP and SFP+ 10GBASE-ER/ZR Optical
Transceivers
8x and 10x Fibre Channel Optical Transmitters
Simplified Block Diagram
Optical Module
n-bit
parallel
data
Backplane
Clock
DEMUX
Data
CDR
PA
TIA
Optical Transceiver
n-bit
parallel
data
Data
EQ
CDR
MUX
Clock
PD + Optical
DEMUX
Clock
Clock
ONET1131EC
LD
ROSA
Optical Fiber
Laser + Optical
MUX
TOSA
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ONET1131EC
SLLSEQ6A – SEPTEMBER 2016 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Function ...........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
3
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
DC Electrical Characteristics .................................... 6
AC Electrical Characteristics..................................... 8
Timing Requirements ................................................ 9
Timing Diagram Definitions ..................................... 10
Typical Characteristics ............................................ 11
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3
7.4
7.5
7.6
8
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Mapping ....................................................
16
21
21
22
Application Information and Implementations . 35
8.1 Application Information............................................ 35
8.2 Typical Application, Transmitter Differential Mode.. 35
9 Power Supply Recommendations...................... 39
10 Layout................................................................... 40
10.1 Layout Guidelines ................................................. 40
10.2 Layout Example .................................................... 40
11 Device and Documentation Support ................. 41
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
41
41
41
41
41
12 Mechanical, Packaging, and Orderable
Information ........................................................... 41
4 Revision History
Changes from Original (September 2016) to Revision A
Page
•
Deleted sentence "however, this function..." from the second paragraph of the CDR section ............................................ 16
•
Deleted the RX Registers section from Register Mapping .................................................................................................. 23
•
Deleted sentence "RX_CDRBP must be set to 1 for this function to operate." From Bit 3 of Table 6 ................................ 25
•
Deleted the RX Registers 42 (offset = 0000 0000 [reset = 0h] section from Register Mapping ......................................... 33
2
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SLLSEQ6A – SEPTEMBER 2016 – REVISED SEPTEMBER 2016
5 Pin Configuration and Function
The ONET1131EC is packaged in a small footprint 4 mm x 4 mm 32 pin RoHS compliant QFN package with a
lead pitch of 0.4 mm.
DIS
FLT
VCC
NC
NC
VCC
NC
NC
RSM Package
32 PIN VQFN
(Top View)
32
31
30
29
28
27
26
25
3
22 GND
DIN+
4
21 NC
DIN-
5
20 NC
GND
6
19 GND
PD
7
18 SCK
MONP
8
17 SDA
10
11
12
13
14
15
16
AMP
9
VDD
GND
VCC
23 COMP
OUT+
2
OUT-
MONB
VCC
24 NC
BIAS
1
LF
LOL
Pin Functions
NUMBER
LOL
MONB
NAME
Type
DESCRIPTION
1
Digital-out
Loss of lock indicator. High level indicates the transmitter CDR is out of lock. Open
drain output. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC for proper
operation. This pin is 3.3 V tolerant.
Bias current monitor.
2
Analog-out
GND
3, 6, 19, 22
Supply
DIN+
4
Analog-in
Non-inverted transmitter data input. On-chip differentially 100 Ω terminated to TXIN–.
Must be AC coupled.
DIN–
5
Analog-in
Inverted transmitter data input. On-chip differentially 100 Ω terminated to TXIN+. Must
be AC coupled.
PD
7
Analog
MONP
8
Analog-out
LF
9
Analog-in
BIAS
10
Analog
Sinks or sources the bias current for the laser in both APC and open loop modes.
VCC
11, 14, 27, 30
Supply
2.5 V ± 5% supply.
OUT–
12
CML-out
Inverted transmitter data output. Internally terminated in single-ended operation
mode.
OUT+
13
CML-out
Non-Inverted transmitter data output.
VDD
15
Supply
AMP
16
Analog-in
Circuit ground.
Photodiode input. Pin can source or sink current dependent on register setting.
Photodiode current monitor.
Transmitter loop filter capacitor.
2.5 V ± 5% supply for the digital circuitry.
Output amplitude control. Output amplitude can be adjusted by applying a voltage of
0 to 2 V to this pin. Leave open when not used.
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SLLSEQ6A – SEPTEMBER 2016 – REVISED SEPTEMBER 2016
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Pin Functions (continued)
NUMBER
NAME
Type
DESCRIPTION
2-wire interface serial data input. Requires an external 4.7-kΩ to10-kΩ pull-up resistor
to VCC. This pin is 3.3-V tolerant.
SDA
17
Digital-in/out
SCK
18
Digital-in
NC
20, 21, 24, 25,
26, 28, 29
2-wire interface serial clock input. Requires an external 4.7-kΩ to10-kΩ pull-up
resistor to VCC. This pin is 3.3-V tolerant.
Do not connect
COMP
23
Analog
Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01-µF
capacitor to ground.
FLT
31
Digital-out
Transmitter fault detection flag. High level indicates that a fault has occurred. Open
drain output. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC for proper
operation. This pin is 3.3-V tolerant.
Digital-in
Disables the bias current when set to high state. Includes a 250-kΩ pull-up resistor to
VCC. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC for proper
operation Toggle to reset a fault condition. This is an ORed function with the
TXBIASEN bit (bit 2 in register 1). This pin is 3.3-V tolerant.
DIS
4
32
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SLLSEQ6A – SEPTEMBER 2016 – REVISED SEPTEMBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
at VCC, VDD
–0.5
3
V
at 3.3-V tolerant pins LOL, SDA, SCK, FLT, DIS
–0.5
3.6
V
at all other pins MONB, DIN+, DIN–, PD, MONP, LF, BIAS,
OUT–, OUT+, AMP, COMP
–0.5
3
V
Maximum current at transmitter input pins DIN+, DIN–
10
mA
Maximum current at transmitter output
pins
125
mA
125
°C
150
°C
Supply voltage
Voltage
OUT+, OUT–
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply Voltage
VIH
Digital input high voltage
VIL
Digital input low voltage
Photodiode current range
Serial Data rate
DIS, SCK, SDA, 3.3-V tolerant IOs
MIN
TYP
MAX
UNIT
2.37
2.5
2.63
V
2
V
0.8
Control bit TXPDRNG = 1x, step size = 3 µA
3080
Control bit TXPDRNG = 01, step size = 1.5 µA
1540
Control bit TXPDRNG = 00, step size = 0.75 µA
770
µA
TXCDR_DIS = 0
9.8
11.7
TXCDR_DIS = 1
1
11.7
0
V
Gbps
VAMP
Amplitude control input voltage range
2
V
tR(IN)
Input rise time
20%–80%
30
45
ps
tF(IN)
Input fall time
20%–80%
30
45
ps
TC
Temperature at thermal pad
100
°C
–40
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6.4 Thermal Information
RSM (VQFN)
THERMAL METRIC (1)
32 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
37.2
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
30.1
°C/W
RθJB
Junction-to-board thermal resistance
7.8
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
7.6
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
2.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 DC Electrical Characteristics
Over recommended operating conditions, open loop operation, VOUT = 2 VPP single-ended, I(BIAS) = 80 mA, unless otherwise
noted. Typical operating condition is at VCC = 2.5 V and TA = 25°C
PARAMETER
VCC
TEST CONDITIONS
Supply voltage
Supply current in single-ended TX
mode with CDRs enabled
Power dissipation in single-ended TX
mode with CDRs enabled
Supply current in differential TX mode
with CDRs enabled
Power dissipation in differential TX
mode with CDRs enabled
IVCC
Supply current in single-ended TX
mode with CDRs disabled
Power dissipation in single-ended TX
mode with CDRs disabled
Supply current in differential TX mode
with CDRs disabled
Power dissipation in differential TX
mode with CDRs disabled
R(IN)
Data input resistance
MIN
TYP
MAX
UNIT
2.37
2.5
2.63
V
158
193
mA
380
508
mW
197
237
mA
493
623
mW
119
193
mA
298
376
mW
164
200
mA
410
526
mW
TXMODE = 1, TXCDR_DIS = 0, TX VOUT = 2
VPP single-ended, I(BIAS) = 0 mA
TXMODE = 0, TXCDR_DIS = 0, TX VOUT = 2
VPP single-ended, I(BIAS) = 0 mA
TXMODE = 1, TXCDR_DIS = 1, TX VOUT = 2
VPP single-ended, I(BIAS) = 0 mA
TXMODE = 0, TXCDR_DIS = 1, TX VOUT = 2
VPP single-ended, I(BIAS) = 0 mA;
Differential between DIN+ / DIN–
100
Data input termination mismatch
R(OUT)
Ooutput resistance
Single-ended at OUT+ or OUT–
Digital input current
DIS pull up to VCC
–20
VOH
Digital output high voltage
LOL, FLT pull-up to VCC,
ISOURCE = 37.5 μA
2.1
VOL
Digital output low voltage
LOL, FLT pull-up to VCC,
ISINK = 350 μA
I(BIAS-MIN)
Minimum bias current
See
I(BIAS-MAX)
I(BIAS-DIS)
Maximum bias current
Bias pin compliance voltage
Temperature sensor accuracy
(1)
6
60
Sink. BIASPOL = 1, DAC set to maximum,
open and closed loop
0.4
5
mA
150
mA
95
100
mA
100
±0.5
Source. TXBIASPOL = 0
With 1-point external mid-scale calibration
V
145
APC loop enabled
Sink. TXBIASPOL = 1
µA
V
(1)
Source. BIASPOL = 0, DAC set to maximum,
open and closed loop
Ω
20
Bias current during disable
Average power stability
Ω
5%
µA
dB
VCC - 0.45
0.45
V
V
±3
°C
The bias current can be set below the specified minimum according to the corresponding register setting; however, in closed loop
operation settings below the specified value may trigger a fault.
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SLLSEQ6A – SEPTEMBER 2016 – REVISED SEPTEMBER 2016
DC Electrical Characteristics (continued)
Over recommended operating conditions, open loop operation, VOUT = 2 VPP single-ended, I(BIAS) = 80 mA, unless otherwise
noted. Typical operating condition is at VCC = 2.5 V and TA = 25°C
PARAMETER
TEST CONDITIONS
Photodiode reverse bias voltage
APC active, I(PD) = 1500 μA
Photodiode fault current level
Percent of target I(PD)
V(PD)
Photodiode current monitor ratio
MIN
TYP
1.3
2.3
(2)
MAX
V
150%
I(MONP) / I(PD) with control bit PDRNG = 1X
10%
12.5%
15%
I(MONP) / I(PD) with control bit PDRNG = 01
20%
25%
30%
I(MONP) / I(PD) with control bit TXPDRNG = 00
40%
50%
60%
Monitor diode DMI accuracy
With external mid-scale calibration
–15%
Bias current monitor ratio
I(MONB) / I(BIAS) (nominal 1/100 = 1%), V(MONB)
< 1.5V
0.9%
Bias current DMI accuracy
I(BIAS) ≥ 20 mA
–15%
15%
Power supply monitor accuracy
With external mid-scale calibration
–2%
2%
VCC(RST)
VCC reset threshold voltage
VCC voltage level which triggers power-on
reset
VCC(RSTHYS)
VCC reset threshold voltage hysteresis
V(MONB-FLT)
Fault voltage at MONB
V(MONP-FLT)
Fault voltage at MONP
TXFLTEN = 1, TXMONPFLT = 1, TXDMONP
= 0, Fault occurs if voltage at MONP
exceeds this value
(2)
15%
1%
1.8
1..1%
2.1
100
TXFLTEN = 1, TXDMONB = 0, Fault occurs
if voltage at MONB exceeds this value
UNIT
V
mV
1.15
1.2
1.25
V
1.15
1.2
1.25
V
Specified by design over process, supply and temperature variation
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6.6 AC Electrical Characteristics
Over recommended operating conditions, open loop operation, VOUT = 2 VPP single-ended, I(BIAS) = 80 mA unless otherwise
noted. Typical operating condition is at VCC = 2.5 V and TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
11.7
Gbps
TX INPUT SPECIFICATIONS
CDR lock range
SDD11
Differential input return loss
CPRI, Ethernet, SONET, Fibre Channel
9.80
0.05 GHz < f ≤ 0.1 GHz
20
0.1 GHz < f ≤ 5.5 GHz
12
5.5 GHz < f < 12 GHz
8
15
dB
15
dB
SDD11
Differential to common mode conversion
0.1 GHz < f < 12 GHz
10
SDD11
Common mode input return loss
0.1 GHz < f < 12 GHz
3
dB
15
mV
Input AC common mode voltage tolerance
Total Non-DDJ
T(JTX)
Total Jitter
S(JTX)
Sinusoidal Jitter Tolerance
VIN
Differential input voltage swing
EQ(boost)
EQ high freq boost
Total jitter less ISI
0.45
UIPP
0.65
UIPP
1000
mVPP
With addition of input jitter, See Figure 1
UIPP
100
Maximum setting; 7 GHz
6
9
dB
12
dB
TX OUTPUT SPECIFICATIONS
VO(MIN)
Differential output return loss
0.01 GHz < f < 12 GHz
Minimum output amplitude
AC Coupled Outputs, 50-Ω single-ended load
0.5
VPP
TX OUTPUT SPECIFICATIONS in SINGLE-ENDED MODE of OPERATION (TXMODE = 1)
VO(MAX)
Maximum output amplitude
AC Coupled Outputs, 50-Ω load, single-ended
Output amplitude stability
AC Coupled Outputs, 50-Ω load, single-ended
High Cross Point Control Range
50-Ω load, single-ended
Low Cross Point Control Range
50-Ω load, single-ended
Cross Point Stability
50-Ω load, single-ended
Output de-emphasis
2
VPP
230
70%
mVPP
75%
35%
-5
40%
5
TXDEADJ[0..3] = 1111, TXPKSEL = 0
5
TXDEADJ[0..3] = 1111, TXPKSEL = 1
6
pp
dB
TX OUTPUT SPECIFICATIONS in DIFFERENTIAL MODE of OPERATION (TXMODE = 0)
VO(MAX)
Maximum output amplitude
AC Coupled Outputs, 100-Ω differential load
Output amplitude stability
AC Coupled Outputs, 100-Ω differential load
High Cross Point Control Range
100-Ω differential load
Low Cross Point Control Range
100-Ω differential load
Cross Point Stability
100-Ω differential load
Output de-emphasis
3.6
VPP
230
65%
mVPP
75%
35%
–5
40%
5
TXDEADJ[0..3] = 1111, TXPKSEL = 0
5
TXDEADJ[0..3] = 1111, TXPKSEL = 1
6
pp
dB
CDR SPECIFICATIONS
BW(TX)
Jitter Transfer Bandwidth
9.95 Gbps, PRBS31
8
MHz
J(PTX)
Jitter Peaking
> 120 kHz
1
dB
JGEN(rms)
Random RMS jitter generation
Clock pattern, 50 kHz to 80 MHz
6
mUIrms
JGEN(PP)
Total jitter generation
Clock pattern, 50 kHz to 80 MHz, BER = 10-12
60
mUIPP
8
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SLLSEQ6A – SEPTEMBER 2016 – REVISED SEPTEMBER 2016
6.7 Timing Requirements
Over recommended operating conditions, typical operating condition is at VCC = 2.5 V and TA = 25°C
MIN
t(APC)
APC time constant
CAPC 0.01 µF, IPD = 500 µA, PD coupling ratio CR = 150,
PDRNG = 01
t(INIT1)
Power-on to initialize
Power-on to registers ready to be loaded
t(INIT2)
Initialize to transmit
Register load STOP command to part ready to transmit valid data
t(OFF)
Transmitter disable time
Rising edge of DIS to I(BIAS) ≤ 0.1 × I(BIAS-NOMINAL)
t(ON)
Disable negate time
Falling edge of DIS to I(BIAS) ≥ 0.9 × I(BIAS-NOMINAL)
t(RESET)
DIS pulse width
Time DIS must held high to reset part
t(FAULT)
Fault assert time
Time from fault condition to FLT high
TYP
50
0.2
1
MAX
UNIT
µs
1
ms
2
ms
5
µs
1
ms
50
µs
100
ns
OUTPUT SPECIFICATIONS in SINGLE-ENDED MODE of OPERATION (TXMODE = 1)
tR(OUTTX)
Output rise time
20% - 80%, AC Coupled Outputs, 50-Ω load, single-ended
30
42
ps
tF(OUTTX)
Output fall time
20% - 80%, AC Coupled Outputs, 50-Ω load, single-ended
30
42
ps
TXEQ_DIS = 1, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage
4
12
TXEQ_DIS = 0, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage, maximum
equalization with 18-inch transmission line at the input.
7
ISI(TX)
R(JTX)
Intersymbol interference
Serial data output random
jitter
Output de-emphasis width
ps
0.4
TXPKSEL = 0
28
TXPKSEL = 1
35
0.75
psRMS
ps
OUTPUT SPECIFICATIONS in DIFFERENTIAL MODE of OPERATION (TXMODE = 0)
tR(OUTTX)
Output rise time
20%–80%, AC Coupled Outputs, 100-Ω differential load
30
42
ps
tF(OUTTX)
Output fall time
20%–80%, AC Coupled Outputs, 100-Ω differential load
30
42
ps
TXEQ_DIS = 1, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage
4
10
TXEQ_DIS = 0, 11.3 Gbps, PRBS9 pattern, 150-mVpp,
600-mVpp, 1200-mVpp differential input voltage, maximum
equalization with 18-inch transmission line at the input.
7
ISI(TX)
R(JTX)
Intersymbol interference
Serial data output random
jitter
Output Peaking Width
ps
0.4
TXPKSEL = 0
28
TXPKSEL = 1
35
0.75
psRMS
ps
CDR SPECIFICATIONS
t(Lock,TX)
CDR Acquisition time
LOL assert time
2
ms
500
μs
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Figure 1. Input Sinusoidal Jitter Tolerance (INF-8077i Rev. 4.5 XFP MSA)
SDA
tBUF±
tLOW
tf
tr
SCK
P
tHDSTA
tHIGH
S
S
tHDDAT
P
tSUDAT
tHDSTA
tSUSTA
tSUSTO
Figure 2. 2-Wire Interface Diagram
6.8 Timing Diagram Definitions
MIN
TYP
MAX
UNIT
400
kHz
fSCK
SCK clock frequency
tBUF
Bus free time between START and STOP conditions
1.3
µs
tHDSTA
Hold time after repeated START condition. After this period, the first
clock pulse is generated
0.6
µs
tLOW
Low period of the SCK clock
1.3
µs
tHIGH
High period of the SCK clock
0.6
µs
tSUSTA
Setup time for a repeated START condition
0.6
µs
tHDDAT
Data HOLD time
0
µs
tSUDAT
Data setup time
100
ns
tR
Rise time of both SDA and SCK signals
300
tF
Fall time of both SDA and SCK signals
300
tSUSTO
Setup time for STOP condition
10
0.6
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ns
µs
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6.9 Typical Characteristics
8
8
7
7
6
6
5
5
ISI (psPP)
ISI (psPP)
Typical operating condition is at VCC = 2.5 V, TA = 25°C, VOUT = 2 VPP Single-ended, DIN = 600 mVPP differential, CDR
enabled (unless otherwise noted).
4
3
4
3
2
2
1
1
0
0
0
20
40
60
80 100 120 140 160
TXMOD Register 12 Setting (Decimal)
180
0
200
TXMODE = 0
180
200
D011
Figure 4. Deterministic Jitter vs Modulation Current
8
8
6
6
ISI (psPP)
ISI (psPP)
40
60
80 100 120 140 160
TXMOD Register 12 Setting (Decimal)
TXMODE = 1
Figure 3. Deterministic Jitter vs Modulation Current
4
4
2
2
0
-40
-20
0
20
40
60
Free-Air Temperature (°C)
80
0
-40
100
Figure 5. Deterministic Jitter vs Temperature
80
100
D013
Figure 6. Deterministic Jitter vs Temperature
0.9
0.9
0.8
0.8
Random Jitter (ps rms)
1
0.7
0.6
0.5
0.4
0.3
0.7
0.6
0.5
0.4
0.3
0.2
0.2
0.1
0.1
0
20
0
20
40
60
Free-Air Temperature (°C)
TXMODE = 1
1
0
-20
D012
TXMODE = 0
Random Jitter (ps rms)
20
D010
40 60 80 100 120 140 160 180 200 220
Modulation Current Register Setting (Decimal)
D014
TXMODE = 1
0
-40
-20
0
20
40
60
Free-Air Temperature (°C)
80
100
D015
TXMODE = 1
Figure 7. Random Jitter vs Modulation Current
Figure 8. Random Jitter vs Temperature
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Typical Characteristics (continued)
40
35
35
30
30
Transition Time (ps)
Transition Time (ps)
Typical operating condition is at VCC = 2.5 V, TA = 25°C, VOUT = 2 VPP Single-ended, DIN = 600 mVPP differential, CDR
enabled (unless otherwise noted).
25
20
15
10
5
15
10
40 60 80 100 120 140 160 180 200 220
TXMOD Register 12 Setting - Decimal
D016
TXMODE = 1
0
20
40
60
Free-Air Temperature (°C)
80
100
D017
Figure 10. Rise-Time and Fall-Time vs Temperature
180
180
160
160
Sink OL Bias Current (mA)
Source OL Bias Current (mA)
-20
TXMODE = 1
Figure 9. Rise-Time and Fall-Time vs Modulation Current
140
120
100
80
60
40
20
140
120
100
80
60
40
20
0
0
0
200
400
600
800
1000
TXBIAS Register 15 and 16 Setting (Decimal)
1200
0
200
400
600
800
1000
TXBIAS Register 15 and 16 Setting (Decimal)
D018
Figure 11. Source Bias Current in Open Loop Mode vs Bias
Register Setting
1200
D019
Figure 12. Sink Bias Current in Open Loop Mode vs Bias
Register Setting
0.5
1.8
Photodiode Monitor Current (mA)
1.6
Bias Monitor Current (mA)
Rise Time
Fall Time
0
-40
0
20
20
5
Rise Time
Fall Time
0
25
1.4
1.2
1
0.8
0.6
0.4
0.2
0.4
0.3
0.2
0.1
0
0
0
20
40
60
80
100 120
Bias Current (mA)
140
160
180
0
0.1
D020
0.2
0.3 0.4 0.5 0.6 0.7
Photodiode Current (mA)
0.8
0.9
1
D021
TXPDRNG[0..1] = 00
Figure 13. Bias-Monitor Current I(MONB) vs Bias Current
12
Figure 14. Photodiode-Monitor Current I(MONP) vs PD Current
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Typical Characteristics (continued)
Typical operating condition is at VCC = 2.5 V, TA = 25°C, VOUT = 2 VPP Single-ended, DIN = 600 mVPP differential, CDR
enabled (unless otherwise noted).
4.5
2.5
Differential Output Voltage (V)
Differential Output Voltage (V)
4
3.5
3
2.5
2
1.5
1
2
1.5
1
0.5
0.5
0
0
0
20
40 60 80 100 120 140 160 180 200 220
TXMOD Register 12 Setting (Decimal)
D022
0
TXMODE = 0
40 60 80 100 120 140 160 180 200 220
TXMOD Register 12 Setting (Decimal)
D023
TXMODE = 1
Figure 15. Output Voltage vs Modulation Current
Figure 16. Output Voltage vs Modulation Current
300
260
290
250
280
240
Supply Current (mA)
Supply Current (mA)
20
270
260
250
240
230
220
210
200
190
230
220
-40
-20
0
20
40
60
Free Air Temperature (°C
TXMODE = 0
80
180
-40
100
-20
0
20
40
60
Free Air Temperature (°C)
D024
Bias Current = 0
TXMODE = 1
Figure 17. Supply Current vs Temperature
80
100
D025
Bias Current = 0
Figure 18. Supply Current vs Temperature
180
1.2
160
PD Fault Current (mA)
Bias Fault Current (mA)
1
140
120
100
80
60
40
0.8
0.6
0.4
0.2
20
0
0
0
50
100
150
200
250
TXBMF Register 17 Setting (Decimal)
300
0
D026
Figure 19. Bias Current Monitor Fault vs TXBMF Register
Setting
50
100
150
200
250
TXPMF Register 18 Setting (Decimal)
300
D027
Figure 20. Photodiode Current Monitor Fault vs TXPMF
Register Setting
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Typical Characteristics (continued)
Typical operating condition is at VCC = 2.5 V, TA = 25°C, VOUT = 2 VPP Single-ended, DIN = 600 mVPP differential, CDR
enabled (unless otherwise noted).
TXMODE = 0
15 ps/Div
TXMODE = 1
Figure 21. Eye-Diagram at 11.3 Gbps
14
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15 ps/Div
Figure 22. Eye-Diagram at 11.3 Gbps
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7 Detailed Description
7.1 Overview
A simplified block diagram of the ONET1131EC is shown in Functional Block Diagram.
The ONET1131EC consists of a transmitter path, an analog reference block, an analog to digital converter, and a
2-wire serial interface and control logic block with power-on reset.
The transmit path consists of an adjustable input equalizer, a multi-rate CDR and an output modulator driver. The
output driver provides a differential output voltage but can be operated in a single-ended mode to reduce the
power consumption. Output waveform control, in the form of cross-point adjustment and de-emphasis are
available to improve the optical eye mask margin. Bias current for the laser is provided and an integrated
automatic power control (APC) loop to compensate for variations in average optical power over voltage,
temperature and time is included.
The ONET1131EC contains an analog to digital converter to support transceiver digital diagnostics and can
report the supply voltage, laser bias current, laser photodiode current and internal temperature.
The 2-wire serial interface is used to control the operation of the device and read the status of the control
registers.
7.2 Functional Block Diagram
VCC
Modulator
Driver
60
60
OUT+
LF
OUT-
DIN+
100
Referenceless
CDR and
Retimer
Equalizer
DIN-
2-Wire Interface &
Control Logic
VDD
Modulation
and Bias
Current
Generator &
APC
CDR_CTRL
AMP
AMP
BIAS
BIAS
FLT
FLT
PD
PD
COMP
COMP
MONB
MONB
MONP
MONP
MONB
EEPROM
MONP
LOL
Power-On
Reset
Analog to
Digital
Conversion
Band-Gap, Analog
References, Power Supply
Monitor & Temperature
Sensor
PSM
SCK
TS
SDA
LOL
DIS
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7.3 Feature Description
7.3.1 Equalizer
The data signal is applied to an input equalizer by means of the input signal pins DIN+ / DIN–, which provide onchip differential 100-Ω line termination. The equalizer is enabled by default and can be disabled by setting the
transmitter equalizer disable bit TXEQ_DIS = 1 (bit 1 of register 10). Equalization of up to 300 mm (12 inches) of
microstrip or stripline transmission line on FR4 printed circuit boards can be achieved. The amount of
equalization is set through register settings TXCTLE [0..3] (register 11). The device can accept input amplitude
levels from 100 mVpp up to 1000 mVpp.
7.3.2 CDR
The clock and data recovery function consists of a Phase-Locked Loop (PLL) and retimer. The CDR can be
operated without a reference clock and the Voltage Controlled Oscillator (VCO) can cover 9.8 Gbps to 11.7 Gbps
data rates. The PLL is phase locked to the incoming data stream and attenuates the high frequency jitter on the
data, producing a recovered clean clock with substantially reduced jitter. An external capacitor for the PLL loop
filter is connected to the LF pin. A value of 2.2 nF is recommended. The clean clock is used to retime the
incoming data, producing an output signal with reduced jitter, and in effect, resetting the jitter budget for the
transmitter.
The CDR is enabled by default. The CDR can be disabled and bypassed by setting the transmitter CDR disable
bit TXCDR_DIS = 1 (bit 4 of register 10). Alternatively, the CDR can be left powered on but bypassed by setting
the transmitter CDR bypass bit TX_CDRBP = 1 (bit 3 of register 10).
The CDR is designed to meet the XFP Datacom requirements and Telecom requirements for a maximum of 1-dB
jitter peaking at a frequency greater than 120 kHz. The CDR is not designed to meet the Telecom regenerator
requirements of jitter peaking less than 0.03 dB at a frequency less than 120 kHz. The default CDR bandwidth is
typically 4.5 MHz and can be adjusted using the SEL_RES[0..2] bits (bits 5 to 7 of register 51). Adjusting these
bits changes the bandwidth of both the transmitter and receiver CDRs.
For the majority of applications, the default settings in register 19 for the transmitter CDR can be used. However,
for some applications or for test purposes, some modes of operation may be useful. The frequency detector for
the PLL is set to an automatic mode of operation by default. When a signal is applied to the transmitter input the
frequency detector search algorithm will be initiated to determine the frequency of the data. The default algorithm
ensures a fast CDR lock time of less than 2 ms. The fast lock can be disabled by setting the transmitter CDR fast
lock disable bit TXFL_DIS = 1 (bit 3 of register 19). Once the frequency has been detected then the frequency
detector will be disabled and the supply current will decrease by approximately 10mA. In some applications, such
as when there are long periods of idle data, it may be advantageous to keep the frequency detector permanently
enabled by setting the transmitter frequency detector enable bit TXFD_EN = 1 (bit 5 of register 19). For test
purposes, the frequency detector can be permanently disabled by setting the transmitter frequency detector
disable bit TXFD_DIS = 1 (bit 4 of register 19). For fast lock times the frequency detector can be set to one of
two preselected data rates using the transmitter frequency detection mode selection bits TXFD_MOD[0..1] (bits 6
and 7 of register 19). If it is desired to use the retimer at lower data rates than the standard 9.8 to 11.7Gbps then
the transmitter divider ratio should be adjusted accordingly through TXDIV[0..2] (bits 0 to 2 of register 19). For
example, for re-timed operation at 2.5 Gbps the divider should be set to divide by 4.
7.3.3 Modulator Driver
The modulation current is sunk from the common emitter node of the limiting output driver differential pair by
means of a modulation current generator, which is digitally controlled by the 2-wire serial interface.
The collector nodes of the output stages are connected to the transmitter output pins TXOUT+ and TXOUT–.
The collectors have internal 50Ω back termination resistors to VCC_TX. The outputs are optimized to drive a 50
Ω single-ended load and to obtain the maximum single-ended output voltage of 2.0Vpp, AC coupling and
inductive pull-ups to VCC are required. For reduced power consumption the DC resistance of the inductive pullups should be minimized to provide sufficient headroom on the TXOUT+ and TXOUT– pins.
The polarity of the output pins can be inverted by setting the transmitter output polarity switch bit, TXOUTPOL
(bit 5 of register 10) to 1. In addition, the output driver can be disabled by setting the transmitter output driver
disable bit TXOUT_DIS = 1 (bit 6 of register 10).
16
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Feature Description (continued)
The output driver is set to differential output by default. In order to reduce the power consumption for singleended applications driving an electroabsorptive modulated laser (EML) the output drive register 13 should be set
to single-ended mode. The single-ended output signal is enabled by setting the transmitter mode select bit
TXMODE = 1 (bit 6 of register 13). The positive output is active by default. To enable the negative output and
disable the positive output set TXOUTSEL = 1 (bit 7 of register 13).
Output de-emphasis can be applied to the signal by adjusting the transmitter de-emphasis bits TXDEADJ[0..3]
(bits 0 to 3 of register 13). In addition, the width of the applied de-emphasis can be increased by setting the
transmitter output peaking width TXPKSEL = 1 (bit 6 of register 11). The wide peaking width would typically be
useful for a more capacitive transmitter load. How de-emphasis is applied is controlled through the TXSTEP bit
(bit 5 of register 13). Setting TXSTEP = 1 delays the time of the applied de-emphasis and has more of an impact
on the falling edge. A graphical representation of the two de-emphasis modes is shown in Figure 23. Using deemphasis can help to optimize the transmitted output signal; however, it will add to the power consumption.
The output edge speed can be set to slow mode of operation through the TXSLOW bit (bit 4 of register 13). For
transmitter modulation output settings (TXMOD - register 12) below 0xC0 it is recommended to set TXSLOW = 1
to reduce the output jitter.
Register 13
Bits 0±3
Register 13
Bits 0±3
Register 11
Bit 6
Register 11
Bit 6
Transmitter De-Emphasis
Register 13 Bit 5 = 0
Transmitter De-Emphasis
Register 13 Bit 5 = 1
Figure 23. Transmitter De-Emphasis Modes
7.3.4 Modulation Current Generator
The modulation current generator provides the current for the high speed output driver described above. The
circuit can be digitally controlled through the 2-wire interface block or controlled by applying an analog voltage in
the range of 0 to 2 V to the AMP pin. The default method of control is through the 2-wire interface. To use the
AMP pin set the transmitter amplitude control bit TXAMPCTRL = 1 (bit 0 of register 10).
An 8-bit wide control bus, TXMOD[0..7] (register 12), is used to set the desired modulation current and the output
voltage.
The entire transmitter signal path, including CDR, can be disabled and powered down by setting TX_DIS = 1 (bit
7 of register 10).
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Feature Description (continued)
7.3.5 DC Offset Cancellation and Cross Point Control
The ONET1131EC transmitter has DC offset cancellation to compensate for internal offset voltages. The offset
cancellation can be disabled by setting TXOC_DIS = 1 (bit 2 of register 10).
The crossing point can be moved toward the one level by setting TXCPSGN = 1 (bit 7 of register 14) and it can
be moved toward the zero level by setting TXCPSGN = 0. The percentage of shift depends upon the register
settings of the transmitter cross-point adjustment bits TXCPADJ[0..6] (register 14).
7.3.6 Bias Current Generation and APC Loop
The bias current for the laser is turned off by default and has to be enabled by setting the laser bias current
enable bit TXBIASEN = 1 (bit 2 of register 1). In open loop operation, selected by setting TXOLENA = 1 (bit 4 of
register 1), the bias current is set directly by the 10-bit wide control word TXBIAS[0..9] (register 15 and register
16). In Automatic Power Control (APC) mode, selected by setting TXOLENA = 0, the bias current depends on
the register settings TXBIAS[0..9] and the coupling ratio (CR) between the laser bias current and the photodiode
current. CR = IBIAS/IPD. If the photodiode cathode is connected to VCC and the anode is connected to the PD pin
(PD pin is sinking current) set TXPDPOL = 1 (bit 0 of register 1). If the photodiode anode is connected to ground
and the cathode is connected to the PD pin (PD pin is sourcing current), set TXPDPOL = 0.
Three photodiode current ranges can be selected by means of the photodiode current range bits TXPDRNG[0..1]
(bits 5 and 6 of register 1). The photodiode range should be chosen to keep the laser bias control DAC,
TXBIAS[0..9], close to the center of its range. This keeps the laser bias current set point resolution high. For
details regarding the bias current setting in open-loop mode as well as in closed-loop mode, see the Register
Mapping table.
The ONET1131EC has the ability to source or sink the bias current. The default condition is for the BIAS pin to
source the current (TXBIASPOL = 0). To act as a sink, set TXBIASPOL = 1 (bit 1 of register 1).
The bias current is monitored using a current mirror with a gain equal to 1/100. By connecting a resistor between
MONB and GND, the bias current can be monitored as a voltage across the resistor. A low temperature
coefficient precision resistor should be used. The bias current can also be monitored as a 10 bit unsigned digital
word by setting the transmitter bias current digital monitor selection bit TXDMONB = 1 (bit 5 of register 16) and
removing the resistor from MONB to ground.
The photodiode current is monitored using a current mirror with various gains that are dependent upon the
photodiode current range being used. By connecting a resistor between MONP and GND, the photodiode current
can be monitored as a voltage across the resistor. A low temperature coefficient precision resistor should be
used. The photodiode current can also be monitored as a 10 bit unsigned digital word by setting the transmitter
photodiode current digital monitor selection bit TXDMONP = 1 (bit 6 of register 16) and removing the resistor
from MONP to ground.
7.3.7 Laser Safety Features and Fault Recovery Procedure
The ONET1131EC provides built in laser safety features. The following fault conditions are detected if the
transmitter fault detection enable bit TXFLTEN = 1 (bit 3 of register 1):
1. Voltage at MONB exceeds the bandgap voltage (1.2 V) or, alternately, if TXDMONB = 1 and the bias current
exceeds the bias current monitor fault threshold set by TXBMF[0..7] (register 17). When using the digital
monitor, the resistor from the MONB pin to ground must be removed.
2. Voltage at MONP exceeds the bandgap voltage (1.2 V) and the analog photodiode current monitor fault
trigger bit, TXMONPFLT (bit 7 of register 1), is set to 1. Alternately, a fault can be triggered if TXDMONP = 1
and the photodiode current exceeds the photodiode current monitor fault threshold set by TXPMF[0..7]
(register 18). When using the digital monitor, the resistor from the MONP pin to ground must be removed.
3. Photodiode current exceeds 150% of its set value,
4. Bias control DAC drops in value by more than 50% in one step.
If the fault detection is being used then to avoid a fault from occurring at start-up it is recommended to set up the
required bias current and APC loop conditions first and enable the laser bias current (TXBIASEN = 1) as the last
step in the sequence of commands.
18
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Feature Description (continued)
If one or more fault conditions occur and the transmitter fault enable bit TXFLTEN is set to 1, the ONET1131EC
responds by:
1. Setting the bias current to zero.
2. Asserting and latching the TX_FLT pin.
3. Setting the TX_FLT bit (bit 5 of register 43) to 1.
Fault recovery is performed by the following procedure:
1. The transmitter disable pin TX_DIS and/or the transmitter bias current enable bit TXBIASEN are toggled for
at least the fault latch reset time.
2. The TX_FLT pin de-asserts while the transmitter disable pin TX_DIS is asserted or the transmitter bias
current enable bit TXBIASEN is de-asserted.
3. If the fault condition is no longer present, the part returns to normal operation with its prior output settings
after the disable negate time.
4. If the fault condition is still present, TX_FLT re-asserts once TX_DIS is set to a low level and/or TXBIASEN is
set to 0 and the part will not return to normal operation.
7.3.8 Analog Block
7.3.8.1 Analog Reference and Temperature Sensor
The ONET1131EC is supplied by a single 2.5 V ±5% supply voltage connected to the VCC and VDD pins. This
voltage is referred to ground (GND) and can be monitored as a 10 bit unsigned digital word through the 2-wire
interface.
On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from which
all other internally required voltages and bias currents are derived.
In order to minimize the module component count, the ONET1131ECprovides an on-chip temperature sensor.
The temperature can be monitored as a 10 bit unsigned digital word through the 2-wire interface.
7.3.8.2 Power-On Reset
The ONET1131EC has power on reset circuitry which ensures that all registers are reset to default values during
startup. After the power-on to initialize time (tINIT1), the internal registers are ready to be loaded. The part is ready
to transmit data after the initialize to transmit time (tINIT2), assuming that the enable chip bit EN_CHIP = 1 (bit 0 of
register 0). In addition, the disable pin DIS must be set to zero.
The ONET1131EC bias current can be disabled by setting the DIS pin high. The internal registers are not reset.
After the transmitter disable pin DIS is set low the part returns to its prior output settings.
7.3.8.3 Analog to Digital Converter
The ONET1131EC has an internal 10 bit analog to digital converter (ADC) that converts the analog monitors for
temperature, power supply voltage, bias current and photodiode current into a 10 bit unsigned digital word. The
first 8 most significant bits (MSBs) are available in register 40 and the 2 least significant bits (LSBs) are available
in register 41. Depending on the accuracy required, 8 bits or 10 bits can be read. However, due to the
architecture of the 2-wire interface, in order to read the 2 registers, 2 separate read commands have to be sent.
The ADC is enabled by default so to monitor a particular parameter, select the parameter with ADCSEL[0..2]
(bits 0 to 2 of register 3). Table 1 shows the ADCSEL bits and the parameter that is monitored.
Table 1. ADC Selection Bits and the Monitored Parameter
ADCSEL2
ADCSEL1
ADCSEL0
MONITORED PARAMETER
0
0
0
Temperature
0
0
1
Supply voltage
0
1
0
Bias current
0
1
1
Photodiode current
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To digitally monitor the photodiode current, ensure that TXDMONP = 1 (bit 6 of register 16) and that a resistor is
not connected to the MONP pin. To digitally monitor the bias current, ensure that TXDMONB = 1 (bit 5 of register
16) and that a resistor is not connected to the MONB pin. The ADC is disabled by default. To enable the ADC,
set the ADC oscillator enable bit OSCEN = 1 (bit 6 of register 3) and set the ADC enable bit ADCEN = 1 (bit 7 of
register 3).
The digital word read from the ADC can be converted to its analog equivalent through the following formulas.
7.3.8.3.1 Temperature
Temperature (°C) = (0.5475 × ADCx) – 273
(1)
7.3.8.3.2 Power Supply Voltage
Power supply voltage (V) = (1.36m × ADCx) + 1.76
(2)
7.3.8.3.3 Photodiode Current Monitor
IPD(μA) = 2 x [ (0.62 × ADCx) – 16] for TXPDRNG00
IPD(μA) = 4 x [ (0.62 × ADCx) – 16] for TXPDRNG01
IPD(μA) = 8 x [ (0.62 × ADCx) – 16] for TXPDRNG1x
(3)
(4)
(5)
7.3.8.3.4 Bias Current Monitor
IBIAS (mA) = (0.2 × ADCx) – 4.5
(6)
Where: ADCx = the decimal value read from the ADC
7.3.8.4 2-Wire Interface and Control Logic
The ONET1131EC uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCK, are
driven, respectively, by the serial data and serial clock from a microprocessor, for example. The SDA and SCK
pins require external 4.7-kΩ to 10-kΩ pull-up resistor to VCC for proper operation.
The 2-wire interface allows write access to the internal memory map to modify control registers and read access
to read out the control signals. The ONET1131EC is a slave device only which means that it cannot initiate a
transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The
master device provides the clock signal as well as the START and STOP commands. The protocol for a data
transmission is as follows:
1. START command
2. Seven (7) bit slave address (0001000) followed by an eighth bit which is the data direction bit (R/W). A zero
indicates a WRITE and a 1 indicates a READ.
3. 8 bit register address
4. 8 bit register data word
5. STOP command
Regarding timing, the ONET1131EC is I2C compatible. The typical timing is shown in Figure 2 and a complete
data transfer is shown in Figure 24. Parameters for Figure 2 are defined in the Timing Diagram Definitions.
7.3.8.5 Bus Idle
Both SDA and SCK lines remain HIGH
7.3.8.6 Start Data Transfer
A change in the state of the SDA line, from HIGH to LOW, while the SCK line is HIGH, defines a START
condition (S). Each data transfer is initiated with a START condition.
7.3.8.7 Stop Data Transfer
A change in the state of the SDA line from LOW to HIGH while the SCK line is HIGH defines a STOP condition
(P). Each data transfer is terminated with a STOP condition; however, if the master still wishes to communicate
on the bus, it can generate a repeated START condition and address another slave without first generating a
STOP condition.
20
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7.3.8.8 Data Transfer
Only one data byte can be transferred between a START and a STOP condition. The receiver acknowledges the
transfer of data.
7.3.9 Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the
SDA line and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Setup and
hold times must be taken into account. When a slave-receiver doesn’t acknowledge the slave address, the data
line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If the
slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any more
data bytes, the master must abort the transfer. This is indicated by the slave generating the not acknowledge on
the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition, see
Figure 2.
7.4 Device Functional Modes
The ONET1131EC has two main functional modes of operation: differential transmitter output and single-ended
transmitter output.
7.4.1 Differential Transmitter Output
Operation with differential output is the default mode of operation. This mode is intended for externally modulated
lasers requiring differential drive such as Mach Zehnder modulators.
7.4.2 Single-Ended Transmitter Output
In order to reduce the power consumption for single-ended EML applications the output driver should be set to
single-ended mode. The single-ended output signal can be enabled by setting the transmitter mode select bit
TXMODE = 1 (bit 6 of register 13). The positive output is active by default. To enable the negative output and
disable the positive output set TXOUTSEL = 1 (bit 7 of register 13).
7.5 Programming
Write Sequence
1
7
1
1
8
1
8
1
1
S
Slave Address
Wr
A
Register Address
A
Data Byte
A
P
Read Sequence
1
7
1
1
8
1
1
7
1
1
8
1
1
S
Slave Address
Wr
A
Register Address
A
S
Slave Address
Rd
A
Data Byte
N
P
Legend
S
Start Condition
Wr
Write Bit (Bit Value = 0)
Rd
Read Bit (Bit Value = 1)
A
Acknowledge
N
Not Acknowledge
P
Stop Condition
Figure 24. Programming Sequence
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7.6 Register Mapping
7.6.1 R/W Control Registers
7.6.1.1 Core Level Register 0 (offset = 0100 0001 [reset = 41h]
Figure 25. Core Level Register 0
7
GLOBAL SW_PIN RESET
RWSC
6
5
4
Reserved
3
RW
2
RWSC
1
I2C RESET
RWSC
0
EN_CHIP
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset. RWSC = Read/Write self clearing (always reads back to zero)
Table 2. Core Level Register 0 Field Descriptions
Bit
7
6:3
Field
Type
Reset
Description
GLOBAL SW_PIN RESET
RWSC
0
Global Reset SW
1 = reset, resets all I2C and EEPROM modules to default
0 = normal operation (self-clearing, always reads back ‘0’)
Reserved
R/W
1
Reserved
RWSC
0
Reserved
2
22
1
I2C RESET
RWSC
0
Chip reset bit
1 = resets all I2C registers to default
0 = normal operation (self-clearing, always reads back ‘0’)
0
EN_CHIP
R/W
1
Enable chip bit
1 = Chip enabled
0 = Chip disabled
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7.6.1.2
SLLSEQ6A – SEPTEMBER 2016 – REVISED SEPTEMBER 2016
Core Level Register 1 (offset = 0000 0000) [reset = 0h]
Figure 26. Core Level Register 1
7
TXMONPFLT
R/W
6
TXPDRNG1
R/W
5
TXPDRNG0
R/W
4
TXOLENA
R/W
3
TXFLTEN
R/W
2
TXBIASEN
R/W
1
TTXBIASPOL
R/W
0
TXPDPOL
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3. Core Level Register 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
TXMONPFLT
R/W
0
Analog photodiode current monitor fault trigger bit
1 = Fault trigger on MONP pin is enabled
0 = Fault trigger on MONP pin is disabled
6
5
TXPDRNG1
TXPDRNG0
R/W
0
Photodiode current range bits
1X: up to 3080 μA / 3 μA resolution
01: up to 1540 μA / 1.5 μA resolution
00: up to 770 μA / 0.75 μA resolution
4
TXOLENA
R/W
0
Open loop enable bit
1 = Open loop bias current control
0 = Closed loop bias current control
3
TXFLTEN
R/W
0
Fault detection enable bit
1 = Fault detection on
0 = Fault detection off
2
TXBIASEN
R/W
0
Laser Bias current enable bit
1 = Bias current enabled. Toggle to 0 to reset a fault condition.
0 = Bias current disabled
1
TXBIASPOL
R/W
0
Laser Bias current polarity bit
1 = Bias pin sinks current
0 = Bias pin sources current
0
TXPDPOL
R/W
0
Photodiode polarity bit
1 = Photodiode cathode connected to VCC
0 = Photodiode anode connected to GND
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7.6.1.3
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Core Level Register 2 (offset = 0000 0000 ) [reset = 0h]
Figure 27. Core Level Register 2
7
6
5
4
3
2
1
0
1
ADCSEL1
R/W
0
ADCSEL0
R/W
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4. Core Level Register 2 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R/W
0
Reserved
7.6.1.4 Core Level Register 3 (offset = 0000 0000) [reset = 0h]
Figure 28. Core Level Register 3
7
ADCEN
R/W
6
OSCEN
R/W
5
Reserved
R/W
4
ADCRST
R/W
3
Reserved
R/W
2
ADCSEL2
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5. Core Level Register 3 Field Descriptions
Bit
24
Field
Type
Reset
Description
7
ADCEN
R/W
0h
ADC enabled bit
1 = ADC enabled
0 = ADC disabled
6
OSCEN
R/W
0h
ADC oscillator bit
1 = Oscillator enabled
0 = Oscillator disabled
5
Reserved
R/W
0h
Reserved
4
ADCRST
R/W
0h
ADC reset
1 = ADC reset
0 = ADC no reset
3
Reserved
R/W
0h
Reserved
2
ADCSEL2
R/W
0h
1
ADCSEL1
R/W
0h
0
ADCSEL0
R/W
0h
ADC input selection bits
000 selects the temperature sensor
001 selects the power supply monitor
010 selects IMONB
011 selects IMONP
1XX are reserved
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7.6.2 TX Registers
7.6.2.1 TX Register 10 (offset = 0000 0000) [reset = 0h]
Figure 29. TX Register 10
7
TX_DIS
R/W
6
TXOUT_DIS
R/W
5
TXOUTPOL
R/W
4
TXCDR_DIS
R/W
3
TX_CDRBP
R/W
2
TXOC_DIS
R/W
1
TXEQ_DIS
R/W
0
TXAMPCTRL
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. TX Register 10 Field Descriptions
Bit
Field
Type
Reset
Description
7
TX_DIS
R/W
0
TX disable bit
1 = TX disabled (power-down)
0 = TX enabled
6
TXOUT_DIS
R/W
0
TX Output Driver disable bit
1 = output disabled
0 = output enabled
5
TXOUTPOL
R/W
0
TX Output polarity switch bit
1 = inverted polarity
0 = normal polarity
4
TXCDR_DIS
R/W
0
TX CDR disable bit
1 = TX CDR is disabled and bypassed
0 = TX CDR is enabled
3
TX_CDRBP
R/W
0
TX CDR bypass bit
1 = TX-CDR bypassed.
0 = TX-CDR not bypassed
2
TXOC_DIS
R/W
0
TX OC disable bit
1 = TX Offset Cancellation disabled
0 = TX Offset Cancellation enabled
1
TXEQ_DIS
R/W
0
TX Equalizer disable bit
1 = TX Equalizer is disabled and bypassed
0 = TX Equalizer is enabled
0
TXAMPCTRL
R/W
0
TX AMP Ctrl
1 = TX AMP Control is enabled (analog amplitude control)
0 = TX AMP Control is disabled (digital amplitude control)
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7.6.2.2 TX Register 11 (offset = 0000 0000) [reset = 0h]
Figure 30. TX Register 11
7
TXAMPRNG
R/W
6
TXPKSEL
R/W
5
TXTCSEL1
R/W
4
TXTCSEL0
R/W
3
TXCTLE3
R/W
2
TXCTLE2
R/W
1
TXCTLE1
R/W
0
TXCTLE0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. TX Register 11 Field Descriptions
Bit
Field
Type
Reset
Description
7
TXAMPRNG
R/W
0
TX output AMP range
1 = Half TX output amplitude range
0 = Full TX output amplitude range
6
TXPKSEL
R/W
0
TX output peaking width
1 = wide peaking width
0 = narrow peaking width
5
TXTCSEL1
R/W
0
TXOUT temperature compensation select bit 1
4
TXTCSEL0
R/W
0
TXOUT temperature compensation select bit 0
3
TXCTLE3
R/W
0
2
TXCTLE2
R/W
0
1
TXCTLE1
R/W
0
TX input CTLE setting
0000 = minimum
1111 = maximum
0
TXCTLE0
R/W
0
7.6.2.3 TX Register 12 (offset = 0000 0000) [reset = 0h]
Figure 31. TX Register 12
7
TXMOD7
R/W
6
TXMOD76
R/W
5
TXMOD5
R/W
4
TXMOD4
R/W
3
TXMOD3
R/W
2
TXMOD2
R/W
1
TXMOD1
R/W
0
TXMOD0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. TX Register 12 Field Descriptions
Bit
26
Field
Type
Reset
7
TXMOD7
R/W
0
6
TXMOD6
R/W
0
5
TXMOD5
R/W
0
4
TXMOD4
R/W
0
3
TXMOD3
R/W
0
2
TXMOD2
R/W
0
1
TXMOD1
R/W
0
0
TXMOD0
R/W
0
Description
TX Modulation current setting: sets the output voltage
Output Voltage: 2.4 Vpp / 9.5 mVpp steps
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7.6.2.4 TX Register 13 (offset = 0h) [reset = 0]
Figure 32. TX Register 13
7
TXOUTSEL
R/W
6
TXMODE
R/W
5
TXSTEP
R/W
4
TXSLOW
R/W
3
TXDEADJ3
R/W
2
TXDEADJ2
R/W
1
TXDEADJ1
R/W
0
TXDEADJ0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. TX Register 13 Field Descriptions
Bit
Field
Type
Reset
Description
7
TXOUTSEL
R/W
0
TX output selection bit
1 = The negative output TXOUT– is active
0 = The positive output TXOUT+ is active
6
TXMODE
R/W
0
TX output mode selection bit
1 = Single-ended mode
0 = Differential mode
5
TXSTEP
R/W
0
TX output de-emphasis mode selection bit
1 = Delayed de-emphasis
0 = Normal de-emphasis
4
TXSLOW
R/W
0
TX edge speed selection bit
1 = Slow edge speed
0 = Normal operation
3
TXDEADJ3
R/W
0
2
TXDEADJ2
R/W
0
1
TXDEADJ1
R/W
0
0
TXDEADJ0
R/W
0
TX de-emphasis setting
0000 = minimum
1111 = maximum
7.6.2.5 TX Register 14 (offset = 0000 0000) [reset = 0h]
Figure 33. TX Register 14
7
TXCPSGN
R/W
6
TXCPADJ6
R/W
5
TXCPADJ5
R/W
4
TXCPADJ4
R/W
3
TXCPADJ3
R/W
2
TXCPADJ2
R/W
1
TXCPADJ61
R/W
0
TXCPADJ60
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. TX Register 14 Field Descriptions
Bit
Field
Type
Reset
Description
7
TXCPSGN
R/W
0
TX Eye cross-point adjustment setting
6
TXCPADJ6
R/W
0
TXCPSGN = 1 (positive shift)
5
TXCPADJ5
R/W
0
Maximum shift for 1111111
4
TXCPADJ4
R/W
0
3
TXCPADJ3
R/W
0
Minimum shift for 0000000
TXCPSGN = 0 (negative shift)
2
TXCPADJ2
R/W
0
1
TXCPADJ1
R/W
0
0
TXCPADJ0
R/W
0
Maximum shift for 1111111
Minimum shift for 0000000
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7.6.2.6 TX Register 15 (offset = 0000 0000) [reset = 0h]
Figure 34. TX Register 15
7
TXBIAS9
R/W
6
TXBIAS8
R/W
5
TXBIAS7
R/W
4
TXBIAS6
R/W
3
TXBIAS5
R/W
2
TXBIAS4
R/W
1
TXBIAS3
R/W
0
TXBIAS2
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. TX Register 15 Field Descriptions
Bit
Field
Type
Reset
Description
7
TXBIAS9
R/W
0
6
TXBIAS8
R/W
0
5
TXBIAS7
R/W
0
4
TXBIAS6
R/W
0
3
TXBIAS5
R/W
0
Bias current settings (8MSB; 2LSBs are in register 16)
Closed loop (APC):
Coupling ratio CR = IBIAS / IPD, TXBIAS = 0..1023, IBIAS ≤ 150 mA:
TXPDRNG = 00; IBIAS = 0.75 μA x CR x TXBIAS
TXPDRNG = 01; IBIAS = 1.5 μA x CR x TXBIAS
TXPDRNG = 1X; IBIAS = 3 μA x CR x TXBIAS
2
TXBIAS4
R/W
0
1
TXBIAS3
R/W
0
0
TXBIAS2
R/W
0
Open Loop:
IBIAS ~ 147 μA x TXBIAS in source mode
IBIAS ~ 147 μA x TXBIAS in sink mode
7.6.2.7 TX Register 16 (offset = 0000 0000) [reset = 0h]
Figure 35. TX Register 16
7
Reserved
R/W
6
TXDMONP
R/W
5
TXDMONB
R/W
4
3
Reserved
R/W
R/W
2
R/W
1
TXBIAS1
R/W
0
TXBIAS1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. TX Register 16 Field Descriptions
Bit
28
Field
Type
Reset
Description
7
Reserved
R/W
0
Reserved
6
TXDMONP
R/W
0
Digital photodiode current monitor selection bit (MONP)
1 = Digital photodiode monitor is active (no external resistor is needed)
0 = Analog photodiode monitor is active (external resistor is required)
5
TXDMONB
R/W
0
Digital bias current monitor selection bit (MONB)
1 = Digital bias current monitor is active (no external resistor is needed)
0 = Analog bias current monitor is active (external resistor is required)
4:2
Reserved
R/W
0
Reserved
1
TXBIAS1
R/W
0
0
TXBIAS0
R/W
0
Laser Bias current setting (2 LSBs)
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7.6.2.8 TX Register 17 (offset = 0000 0000) [reset = 0h]
Figure 36. TX Register 17
7
TXBMF7
R/W
6
TXBMF6
R/W
5
TXBMF5
R/W
4
TXBMF4
R/W
3
TXBMF3
R/W
2
TXBMF2
R/W
1
TXBMF1
R/W
0
TXBMF0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. TX Register 17 Field Descriptions
Bit
Field
Type
Reset
Description
7
TXBMF7
R/W
0
6
TXBMF6
R/W
0
5
TXBMF5
R/W
0
4
TXBMF4
R/W
0
Bias current monitor fault threshold
With TXDMONB = 1
Register sets the value of the bias current that will trigger a fault.
The external resistor on the MONB pin must be removed to use this
feature.
3
TXBMF3
R/W
0
2
TXBMF2
R/W
0
1
TXBMF1
R/W
0
0
TXBMF0
R/W
0
7.6.2.9 TX Register 18 (offset = 0000 0000) [reset = 0h]
Figure 37. TX Register 18
7
TXPMF7
R/W
6
TXPMF6
R/W
5
TXPMF5
R/W
4
TXPMF4
R/W
3
TXPMF3
R/W
2
TXPMF2
R/W
1
TXPMF1
R/W
0
TXPMF0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. TX Register 18 Field Descriptions
Bit
Field
Type
Reset
Description
7
TXPMF7
R/W
0
6
TXPMF6
R/W
0
5
TXPMF5
R/W
0
4
TXPMF4
R/W
0
Power monitor fault threshold
With TXDMONP = 1
Register sets the value of the photodiode current that will trigger a fault.
The external resistor on the MONP pin must be removed to use this
feature.
3
TXPMF3
R/W
0
2
TXPMF2
R/W
0
1
TXPMF1
R/W
0
0
TXPMF0
R/W
0
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7.6.2.10 TX Register 19 (offset = 0000 0000) [reset = 0h]
Figure 38. TX Register 19
7
TXFD_MOD1
R/W
6
TXFD_MOD0
R/W
5
TXFD_EN
R/W
4
TXFD_DIS
R/W
3
0TXFL_DIS
R/W
2
TXDIV2
R/W
1
TXDIV1
R/W
0
TXDIV0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. TX Register 19 Field Descriptions
Bit
30
Field
Type
Reset
Description
7
TXFD_MOD1
R/W
0
6
TXFD_MOD0
R/W
0
TX frequency detection mode selection
00 = auto selection enabled
01 = Pre-selected to 10.3 Gbps
10 = Pre-select to 11.1 Gbps
11 = test mode (do not use)
5
TXFD_EN
R/W
0
TX frequency detector enable bit
1 =TX frequency detector is always enabled
0 = TX frequency detector in automatic mode
4
TXFD_DIS
R/W
0
TX frequency detector disable bit
1 = TX frequency detector is always disabled
0 = TX frequency detector is in automatic mode
3
TXFL_DIS
R/W
0
TX CDR fast lock disable bit
1 = TX CDR fast lock disabled
0 = TX CDR in fast lock mode
2
TXDIV2
R/W
0
1
TXDIV1
R/W
0
0
TXDIV0
R/W
0
TX Divider Ratio
000: Full-Rate,
001: Divide by 2
010: Divide by 4
011: Divide by 8
100: Divide by 16
101: Divide by 32
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7.6.3 Reserved Registers
7.6.3.1 Reserved Registers 20-39
Figure 39. Reserved Registers 20-39
7
6
5
4
3
2
1
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. Reserved Registers 20-39 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R
0
Reserved
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7.6.4 Read Only Registers
7.6.4.1 Core Level Register 40 (offset = 0000 0000) [reset = 0h]
Figure 40. Core Level Register 40
7
ADC9
R
6
ADC8
R
5
ADC5
R
4
ADC4
R
3
ADC3
R
2
ADC2
R
1
ADC1
R
0
ADC0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. Core Level Register 40 Field Descriptions
Bit
Field
Type
Reset
Description
7
ADC9 (MSB)
R
0
Digital representation of the ADC input source (read only)
6
ADC8
R
0
5
ADC7
R
0
4
ADC6
R
0
3
ADC5
R
0
2
ADC4
R
0
1
ADC3
R
0
0
ADC2
R
0
7.6.4.2 Core Level Register 41 (offset = 0000 0000) [reset = 0h]
Figure 41. Core Level Register 41
7
6
5
4
3
2
Reserved
R
1
ADC1
R
0
ADC0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. Core Level Register 41 Field Descriptions
32
Bit
Field
Type
Reset
Description
7:2
Resereved
R
0h
Reserved
1
ADC1
R
0h
Digital representation of the ADC input source (read only)
0
ADC0 (LSB)
R
0h
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7.6.4.3 TX Register 43 (offset = 0000 0000) [reset = 0h]
Figure 42. Core Level Register 43
7
TXCDRLock
R
6
TXCDRLock
R
5
TX_FLT
R
4
TX_DRVDIS
R
3
2
1
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; RCLR = Read clear
Table 19. TX Registers 43 Field Descriptions
Bit
Field
Type
Reset
Description
7
TXCDRLock
R
0
TX CDR lock status bit
1 = TX CDR is not locked
0 = TX CDR is locked
6
TXCDRLock (latched Low)
RCLR
0
Latched low status of bit 7. Cleared when read.
Latched low bit set to 0 when raw status goes low and keep it low even if
raw status goes high.
5
TX_FLT
R
0
TX fault status bit
1 = TX fault detected
0 = TX fault not detected
4
TX_DRVDIS
R
0
TX driver disable status bit
1 = TX fault logic disables the driver
0 = TX fault logic does not disable the driver
Reserved
R
0
Reserved
3:0
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7.6.5 Adjustment Registers
7.6.5.1 Adjustment Registers 44-50
Figure 43. Adjustment Registers 44-50
7
6
5
4
3
2
1
0
1
0
1
0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. Adjustment Registers 44-50 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R
0
Reserved
7.6.5.2 Adjustment Register 51 (offset = 0100 0000) [reset = 40h]
Figure 44. Adjustment Register 51
7
SEL_RES_2
R
6
SEL_RES_1
R
5
SEL_RES_0
R
4
3
2
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. Adjustment Register 51 Field Descriptions
Bit
Field
Type
Reset
Description
7
SEL_RES_2
R/W
0
6
SEL_RES_1
R/W
1
5
SEL_RES_0
R/W
0
CDR Loop Filter Resistor
000: 75,
001: 150
010: 225
011: 300
100: 375
101: 450
110: 525
111: 600
Default = 225
Reserved
R/W
0
4:0
Reserved
7.6.5.3 Adjustment Registers 52-55
Figure 45. Adjustment Registers 52-55
7
6
5
4
3
2
Reserved
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. Adjustment Registers 52-55 Field Descriptions
34
Bit
Field
Type
Reset
Description
7:0
Reserved
R
0
Reserved
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8 Application Information and Implementations
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ONET1131EC is designed to be used in conjunction with a Transmitter Optical Sub-Assembly (TOSA). The
ONET1131EC, TOSA, microcontroller and power management circuitry will typically be used in an XFP or SFP+
10 Gbps optical transceiver. Figure 46 shows the ONET1131EC in differential mode of operation modulating a
differentially driven Mach Zehnder (MZ) modulator TOSA and Figure 48 and Figure 49 show the device in singleended output mode with an Electroabsorptive Modulated Laser (EML) TOSA. Figure 48 has the photodiode
cathode available and Figure 49 has the photodiode anode available.
8.2 Typical Application, Transmitter Differential Mode
VCC_T
VCC
4.7k
to10k
4.7k
to10k
4.7k
to10k
TX_FLT
0.1 F
TX_DIS
0.1 F
NC
NC
NC
VCC
NC
VCC
FLT
DIS
VCC
LOL
LOL
NC
0.01 F
MONB
COMP
GND
GND
0.1 F
DIN+
DIN+
NC
ONET1131EC
MONP
SDA
VDD
AMP
SCK
VCC
GND
PD
OUT+
GND
OUT-
NC
VCC
DIN-
LF
0.1 F
BIAS
DIN-
SCK
SDA
4.7k
to10k
4.7k
to10k
VCC
2.2nF
VDD
0.1 F
VCC
0.1 F
0.1 F
0.1 F
MZ MOD+
MZ MODCopyright © 2016, Texas Instruments Incorporated
Figure 46. Typical Application Circuit in Differential Mode
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Typical Application, Transmitter Differential Mode (continued)
8.2.1 Design Requirements
Table 23. Design Parameters
PARAMETER
VALUE
Supply voltage
2.5 V
Transmitter input voltage
100 mVpp to 1000 mVpp differential
Transmitter output voltage
1 Vpp to 3.6 Vpp differential
8.2.2 Detailed Design Procedure
In the transmitter differential mode of operation, the output driver is intended to be used with a differentially
driven Mach Zehnder (MZ) modulator TOSA. On the input side, the DIN+ and DIN- pins are required to be AC
coupled to the signal from the host system and the input voltage should be between 100 mVpp and 1000 mVpp
differential. On the output side, the OUT+ pin is AC coupled to the modulator positive input and the OUT– pin is
AC coupled to the modulator negative input. A bias-T from VCC to both the OUT+ and OUT– pins is required to
supply sufficient headroom voltage for the output driver transistors. It is recommended that the inductance in the
bias-T have low DC resistance to limit the DC voltage drop and maximize the voltage supplied to the OUT+ and
OUT– pins. If the voltage on these pins drops below approximately 2.1 V then the output rise and fall times can
be adversely affected.
8.2.3 Application Curve
Figure 47. Differential Mode Transmitter Output Eye Diagram
36
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8.2.4 Typical Application, Transmitter Single-Ended Mode
VCC_T
VCC
4.7k to
10k
4.7k to
10k
4.7k
to10k
TX_FLT
0.1 F
TX_DIS
0.1 F
NC
NC
VCC
NC
NC
VCC
FLT
DIS
VCC
LOL
LOL
NC
0.01 F
MONB
COMP
GND
GND
0.1 F
DIN+
DIN+
NC
ONET1131EC
DIN-
MONP
SDA
SDA
LF
AMP
SCK
VDD
SCK
VCC
PD
PD
OUT+
GND
OUT-
GND
VCC
NC
BIAS
DIN0.1 F
4.7k
to10k
4.7k
to10k
VCC
VDD
VCC
0.1 F
Modulator Anode
2.2nF
0.1 F
0.1 F
0.1 F
PD
50
Laser
PD
EA BIAS
EML TOSA
0.1 F
-3V
Copyright © 2016, Texas Instruments Incorporated
Figure 48. Typical Application Circuit in Single-Ended Mode with an EML and the PD Monitor Cathode
Available
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VCC_T
VCC
4.7k
to10k
4.7k
to10k
4.7k
to10k
TX_FLT
0.1 F
TX_DIS
0.1 F
NC
NC
VCC
NC
NC
VCC
FLT
DIS
VCC
LOL
LOL
NC
0.01 F
MONB
COMP
GND
GND
0.1 F
DIN+
DIN+
DIN-
DIN-
NC
GND
GND
PD
SCK
SCK
MONP
SDA
SDA
NC
AMP
VDD
VCC
OUT+
OUT-
LF
PD
VCC
0.1 F
BIAS
ONET1131EC
4.7k
to10k
4.7k
to10k
VCC
VDD
VCC
0.1 F
Modulator Anode
2.2nF
0.1 F
0.1 F
0.1 F
50
Laser
PD
PD
EA BIAS
EML TOSA
0.1 F
Copyright © 2016, Texas Instruments Incorporated
Figure 49. Typical Application Circuit in Single-Ended Mode with an EML and the PD Monitor Anode
Available
38
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8.2.4.1 Design Requirements
Table 24. Design Parameters
PARAMETER
VALUE
Supply voltage
2.5 V
Transmitter input voltage
100 mVpp to 1000 mVpp differential
Transmitter output voltage
0.5 Vpp to 2 Vpp single-ended
8.2.4.2 Detailed Design Procedure
In the transmitter single-ended mode of operation, the output driver is intended to be used with a single-ended
driven Electroabsorptive Modulated Laser (EML) TOSA. On the input side, the DIN+ and DIN– pins are required
to be AC coupled to the signal from the host system and the input voltage should be between 100 mVpp and
1000 mVpp differential. On the output side, it is recommended that the OUT+ pin is AC coupled to the modulator
input and the OUT– pin can be left unterminated or terminated to VCC through a 50-Ω resistor. A bias-T from
VCC to the OUT+ pin is required to supply sufficient headroom voltage for the output driver transistors. It is
recommended that the inductance in the bias-T have low DC resistance to limit the DC voltage drop and
maximize the voltage supplied to the TXOUT+ pin. If the voltage on this pins drops below approximately 2.1V
then the output rise and fall times can be adversely affected.
8.2.4.3 Application Curves
Figure 50. Single-Ended Mode Transmitter Output Eye Diagram
9 Power Supply Recommendations
The ONET1131EC is designed to operate from an input supply voltage range between 2.37 V and 2.63 V. To
reduce digital coupling into the analog circuitry, there are separate supplies for the transmitter, and digital
circuitry. VCC is used to supply power to the transmitter, and VDD is used to supply power to the digital block.
Power supply decoupling capacitors should be placed as close as possible to the respective power supply pins.
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10 Layout
10.1 Layout Guidelines
For optimum performance, use 50-Ω transmission lines (100-Ω differential) for connecting the high speed inputs
and outputs. The length of transmission lines should be kept as short as possible to reduce loss and patterndependent jitter.
If the single-ended mode of operation is being used (TXMODE = 1) then it is recommended to terminate the
unused output with a 50-Ω resistor to VCC. Figure 51 shows a typical layout for the high speed inputs and
outputs.
10.2 Layout Example
AC-coupling
capacitors
TXIN+
From
Host
TXINTXOUT-
TXOUT+
Bias-T
Ferrites
To
TOSA
50O to VCC
Termination
Figure 51. Board Layout
40
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ONET1131ECRSMR
ACTIVE
VQFN
RSM
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 100
ONET
1131EC
ONET1131ECRSMT
ACTIVE
VQFN
RSM
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 100
ONET
1131EC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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