ONET1141LRGER

ONET1141L www.ti.com SLLSEB7 – MAY 2012 11.3 Gbps Modulator Driver Check for Samples: ONET1141L FEATURES 1 • • • • • • • • Digitally Selectable Output Amplitude up to 2.0VPP Single-Ended Digitally Selectable Bias Current up to 145mA Source 2-wire Digital Interface with Integrated DACs and ADC for Control and Diagnostic Management Automatic Power Control (APC) Loop Adjustable Rise and Fall Times Programmable Input Equalizer Cross-Point Control Selectable Monitor PD Current Range and Polarity • • • • Includes Laser Safety Features Single 3.3V Supply –40°C to 100°C Operation Surface Mount Small Footprint 4mm × 4mm 24 Pin RoHS Compliant QFN Package APPLICATIONS • • • • • 10 Gigabit Ethernet Optical Transmitters SONET OC-192/SDH STM-64 Optical Transmitters 10G-EPON and XG-PON SFP+ and XFP Transceiver Modules XENPAK, XPAK, X2 and 300-pin MSA Transponder Modules DESCRIPTION The ONET1141L is a high-speed, 3.3V electroabsorption modulator driver designed to bias and modulate an electroabsorptive modulated laser (EML) at data rates from 1 Gbps up to 11.3 Gbps. The device provides a two-wire serial interface which allows digital control of the modulation and bias currents, eliminating the need for external components. Output waveform control, in the form of cross-point adjustment and rise and fall time adjustment are available to improve the optical eye mask margin. An optional input equalizer can be used for equalization of up to 150mm (6”) of microstrip or stripline transmission line on FR4 printed circuit boards. The device contains internal analog to digital and digital to analog converters to eliminate the need for special purpose microcontrollers. The ONET1141L includes an integrated automatic power control (APC) loop which compensates for variations in laser average optical power over voltage and temperature and circuitry to support laser safety and transceiver management systems. The modulator driver is characterized for operation from –40°C to 100°C case temperatures and is available in a small footprint 4mm × 4mm 24 pin RoHS compliant QFN package. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated ONET1141L SLLSEB7 – MAY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. BLOCK DIAGRAM A simplified block diagram of the ONET1141L is shown in Figure 1. The modulator driver consists of an input equalizer with selectable bypass, a limiter, an output driver, DC offset cancellation with cross point control, power-on reset circuitry, a 2-wire serial interface including a control logic block, a modulation current generator, a bias current generator with automatic power control loop, an analog to digital converter and an analog reference block. VCCO Crosspoint Adjust To all Blocks Except Output Driver VCC DC Offset Cancellation 60Ω 60Ω OUT+ Equalizer 100Ω OUT- Amplifier Limiter + DIN+ DIN- + Bypass Mod. Current Generator VCC Adjustable Boost 10kΩ 10kΩ 10kΩ 8 Bit Register 8 Bit Register SDA SDA SCK SCK DIS DIS Settings Settings 10 Bit Register IMOD 10 Bit Register IBIAS 8 Bit Register 8 Bit Register 5 Bit Register 8 Bit Register 3 Bit Register Equalizer Crosspoint Crosspoint Settings Limiter Current Monitor Settings 8 Bit Register 8 Bit Register Bias Current Fault 8 Bit Register ADC Settings ADR1 ADR1 ADR2 2-Wire Interface & Control Logic MONB MONP Analog to Digital Conversion PD Current Fault ADR0 10 Bit Register BIAS Bias Current MONB Generator/ MONP Monitor & FLT APC Crosspoint Adjust PD COMP BIAS MONB MONP FLT PD COMP Band-Gap, Analog References, Power supply Monitor & Temperature Sensor ADC Power-On Reset PSM RZTC TS RZTC Figure 1. Simplified Block Diagram of the ONET1141L PACKAGE The ONET1141L is packaged in a small footprint 4mm X 4mm 24 pin RoHS compliant QFN package with a lead pitch of 0.5mm. The pin out is shown below. 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L ONET1141L www.ti.com SLLSEB7 – MAY 2012 VCCO GND OUT- GND OUT+ VCCO 24 PIN QFN PACKAGE, 4mm x 4mm (TOP VIEW) 24 23 22 21 20 19 PD 1 18 BIAS 17 GND ADR0 2 ONET1141L 1101L ONET ADR1 3 16 VCC 24 Lead QFN 24 Lead QFN “ RGE” DIS 4 15 COMP 13 MONB 9 10 11 12 RZTC 8 GND 7 DIN+ DIN - SDA 6 GND 14 MONP FLT SCK 5 PIN FUNCTIONS NO. PIN NAME TYPE DESCRIPTION 1 PD Analog Photodiode input. Pin can source or sink current dependent on register setting. 2 ADR0 Digital-in 2-wire interface address programming pin. Leave this pad open for a default address of 0001000. Pulling the pin to VCC changes the 1st address bit to a 1 (address = 0001001) 3 ADR1 Digital-in 2-wire interface address programming pin. Leave this pad open for a default address of 0001000. Pulling the pin to VCC changes the 2nd address bit to a 1 (address = 0001010) 4 DIS Digital-in Disables both bias and modulation currents when set to high state. Includes a 10kΩ or 40kΩ pull-up resistor to VCC. Toggle to reset a fault condition. 5 SCK Digital-in 2-wire interface serial clock input. Includes a 10kΩ or 40kΩ pull-up resistor to VCC. 6 SDA Digital-in/out 2-wire interface serial data input/output. Includes a 10kΩ or 40kΩ pull-up resistor to VCC. 7 FLT Digital-out Fault detection flag. High level indicates that a fault has occurred. Open drain output. Requires an external 4.7kΩ to 10kΩ pull-up resistor to VCC for proper operation. Supply Circuit ground. Exposed die pad (EP) must be grounded. 8, 11, 17, GND 20, 23, EP 9 DIN+ Analog-in Non-inverted data input. On-chip differentially 100Ω terminated to DIN–. Must be AC coupled. 10 DIN– Analog-in Inverted data input. On-chip differentially 100Ω terminated to DIN+. Must be AC coupled. 12 RZTC Analog Connect external zero TC 28.7kΩ resistor to ground (GND). Used to generate a defined zero TC reference current for internal DACs. 13 MONB Analog-out Bias current monitor. Sources a 1% replica of the bias current. Connect an external resistor to ground (GND) to use the analog monitor (DMONB = 0). If the voltage at this pin exceeds 1.16V a fault is triggered. Typically choose a resistor to give MONB voltage of 0.8V at the maximum desired bias current. If the digital monitor function is used (DMONB = 1) the resistor must be removed. 14 MONP Analog-out Photodiode current monitor. Sources a 12.5% replica of the photodiode current when PDRNG = 1X, a 25% replica when PDRNG = 01 and a 50% replica when PDRNG = 00. Connect an external resistor (5kΩ typical) to ground (GND) to use the analog monitor (DMONP = 0). If the voltage at this pin exceeds 1.16V a fault is triggered when MONPFLT = 1. If the digital monitor function is used (DMONP = 1) the resistor must be removed. 15 COMP Analog Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01µF capacitor to ground. 16 VCC Supply 3.3V ± 10% supply voltage. 18 BIAS Analog Sinks or sources the bias current for the laser in both APC and open loop modes. 19, 24 VCCO Supply 3.3V ± 10% supply voltage for the output stage. 21 OUT– CML-out Inverted data output. 22 OUT+ CML-out Non-inverted data output. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L 3 ONET1141L SLLSEB7 – MAY 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT MIN MAX VCC Supply voltage (2) –0.3 4.0 V VADR0, VADR1, VDIS, VRZTC, VSCK, VSDA, VDIN+, VDIN-, VFLT, VMONB, VMONP, VCOMP, VPD, VBIAS, VOUT+, VOUT- Voltage at ADR0, ADR1, DIS, RZTC, SCK, SDA, DIN+, DIN–, FLT, MONB, MONP, COMP, PD, BIAS, OUT+, OUT– (2) –0.3 4.0 V IDIN-, IDIN+ Maximum current at input pins 25 mA IOUT+, IOUT– Maximum current at output pins 120 mA IBIAS-MAX Maximum bias current 180 ESD ESD rating at all pins TJ,max Maximum junction temperature TSTG Storage temperature range TC Case temperature (1) (2) 2 mA kV (HBM) 125 °C –65 150 °C –40 110 °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VCC Supply voltage VIH Digital input high voltage DIS, SCK, SDA VIL Digital input low voltage DIS, SCK, SDA Photodiode current range RRZTC Zero TC resistor value (1) MIN TYP MAX UNIT 2.97 3.3 3.63 V 2.0 V 0.8 Control bit PDRNG = 1X,step size = 3 µA 3080 Control bit PDRNG = 01,step size = 1.5 µA 1540 Control bit PDRNG = 00,step size = 0.75 µA 770 28.7 V µA 1.16V bandgap bias acrossresistor, E96, 1% accuracy 28.4 EQENA = 1 160 1000 29 EQENA = 0 400 1000 kΩ vIN Differential input voltage swing tR-IN Input rise time 20%–80% 30 55 tF-IN Input fall time 20%–80% 30 55 ps TC Temperature at thermal pad 100 °C (1) 4 -40 mVp-p ps Changing the value will alter the DAC ranges. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L ONET1141L www.ti.com SLLSEB7 – MAY 2012 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions, with 50Ω output load, open loop operation, VOUT = 2.0Vpp, IBIAS = 80 mA, and RRZTC = 28.7kΩ unless otherwise noted. Typical operating condition is at VCC =3.3V and TA = 25°C PARAMETER VCC CONDITION MIN TYP MAX UNIT 2.97 3.3 3.63 V VOUT = 2.0Vpp, IBIAS = 0mA, EQENA = 0 143 170 VOUT = 2.0Vpp, IBIAS = 0mA, EQENA = 1 151 182 Output off (DIS = HIGH), VOUT = 2.0Vpp, IBIAS = 80 mA, EQENA = 0 40 Supply voltage IVCC Supply current mA RIN Data input resistance Differential between DIN+ / DIN– 82 100 118 Ω ROUT Output resistance Single-ended at OUT+ or OUT– 50 60 70 Ω Digital input current SCK, SDA, pull up to VCC 2 360 470 µA Digital input current DIS, pull up to VCC 2 360 470 µA VOH Digital output high voltage FLT, pull-up to VCC, ISOURCE = 50 µA VOL Digital output low voltage FLT, pull-up to VCC, ISINK = 350 µA IBIAS-MIN Minimum bias current See IBIAS-MAX IBIAS-DIS Maximum bias current 2.4 V 0.4 (1) 5 Source. BIASPOL = 0, DAC set to maximum, open and closed loop Sink. BIASPOL = 1, DAC set to maximum, open and closed loop 145 160 93 105 mA Bias current during disable 100 Average power stability APC loop enabled Bias pin compliance voltage Source. BIASPOL = 0 ±0.5 V VCC–0.9 Temperature sensor accuracy With 1-point external mid scale calibration Photodiode reverse bias voltage APC active, IPD = max Photodiode fault current level Photodiode current monitor ratio Percent of target IPD 1.3 (2) °C 2.3 V IMONP / IPD with control bit PDRNG = 1X 10% 12.5% 15% IMONP / IPD with control bit PDRNG = 01 20% 25% 30% IMONP / IPD with control bit PDRNG = 00 40% 50% 60% With external calibration at 200 µA -10% Bias current monitor ratio IMONB / IBIAS (nominal 1/100 = 1%) 0.9% Bias current DMI accuracy Bias current ≥ 30 mA Power supply monitor accuracy With external mid scale calibration VCC-RST VCC reset threshold voltage VCC voltage level which triggers power-on reset VCC-RSTHYS VCC reset threshold voltage hysteresis VMONB-FLT Fault voltage at MONB (2) ±3 150% Monitor diode DMI accuracy (1) µA dB 0.9 Sink. BIASPOL = 1 VPD V mA 10% 1.0% 1.1% ±10% –2% 2% 2.5 2.8 100 Fault occurs if voltage at MONB exceeds value 1.1 1.16 V mV 1.24 V The bias current can be set below the specified minimum according to the corresponding register setting, however in closed loop operation settings below the specified value may trigger a fault. Assured by simulation over process, supply and temperature variation. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L 5 ONET1141L SLLSEB7 – MAY 2012 www.ti.com AC ELECTRICAL CHARACTERISTICS Over recommended operating conditions, with 50Ω output load, open loop operation, VOUT = 2.0Vpp, IBIAS = 80 mA, and RRZTC = 28.7kΩ unless otherwise noted. Typical operating condition is at VCC =3.3V and TA = 25°C PARAMETER CONDITION MIN 0.01 GHz f < 5 GHz TYP MAX –15 UNIT SDD11 Differential input return gain SCD11 Differential to common mode conversion gain 0.01 GHz < f < 11.1 GHz tR-OUT Output rise time 20%–80%, tR-IN < 40 ps, 50Ω load, single-ended, crosspoint = 50% 28 40 ps tF-OUT Output fall time 20%–80%, tF-IN < 40 ps, 50Ω load, single-ended, crosspoint = 50% 28 40 ps VO-MIN Minimum output amplitude 50Ω load, single-ended VO-MAX Maximum output amplitude 50Ω load, single-ended Output Amplitude Stability 50Ω load, single-ended Modulation voltage step size 50Ω load, 10 Bit Register VMOD-STEP DJ Deterministic output jitter RJ 5 GHz < f < 11.1 GHz –20 200 mVpp Vpp 250 2.5 EQENA = 1 with maximum equalization, K28.5 pattern at 11.3 Gbps, 160mVpp, 600mVpp, 1000mVpp differential input voltage, single-ended output 5 EQENA = 1, K28.5 pattern at 11.3 Gbps, maximum equalization with 6” transmission line at the input, 160mVpp, 600mVpp, 1000mVpp input to transmission line, single-ended output 7 0.2 APC time constant CAPC 0.01 µF, IPD = 100 µA, PD coupling ratio CR = 40 (1) High cross point control range 50Ω load, single-ended 75% Low cross point contro lrange 50Ω load, single-ended 30% Cross point stability 50Ω load, single-ended, VIN ≥ 400mVpp ±5% Transmitter disable time Rising edge of DIS to IBIAS ≤ 0.1 × IBIAS-NOMINAL (1) 0.05 TON Disable negate time Falling edge of DIS to IBIAS ≥ 0.9 × IBIAS-NOMINAL (1) TINIT1 Power-on to initialize Power-on to registers ready to be loaded TINIT2 Initialize to transmit Register load STOP command to part ready to transmit valid data (1) TRESET DIS pulse width Time DIS must held high to reset part (1) (1) 6 Fault assert time Time from fault condition to FLT high mV 15 0.6 psRMS 120 (1) mV psp-p TOFF TFAULT dB 2.0 Random output jitter τAPC dB –8 1 µs 5 µs 1 ms 10 ms 2 ms 100 ns 50 µs Assured by simulation over process, supply and temperature variation. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L ONET1141L www.ti.com SLLSEB7 – MAY 2012 DETAILED DESCRIPTION EQUIALIZER The data signal is applied to an input equalizer by means of the input signal pins DIN+/DIN–, which provide onchip differential 100Ω line-termination. The equalizer is enabled by setting EQENA = 1 (bit 1 of register 0). Equalization of up to 150mm (6”) of microstrip or stripline transmission line on FR4 printed circuit boards can be achieved. The amount of equalization is digitally controlled by the two-wire interface and control logic block and is dependant on the register settings EQADJ[0..7] (register 6). The equalizer can be turned off and bypassed by setting EQENA = 0 and the supply current is reduced. For details about the equalizer settings, see Table 19. LIMITER By limiting the output signal of the equalizer to a fixed value, the limiter removes any overshoot after the input equalization and provides the input signal for the output driver. Adjustments to the limiter bias current and emitter follower current can be made to trade off the rise and fall times and supply current. The limiter bias current is adjusted through LIMCSGN (bit 7 of register 9) and LIMC[0..2] (bits 4, 5 and 6 of register 9). The emitter follower current is adjusted through EFCSGN (bit 3 of register 9) and EFC[0..2] (bits 0, 1 and 2 of register 9). HIGH-SPEED OUTPUT DRIVER The modulation current is sunk from the common emitter node of the limiting output driver differential pair by means of a modulation current generator, which is digitally controlled by the 2-wire serial interface. The collector nodes of the output stages are connected to the output pins OUT+ and OUT–. The collectors have internal 60Ω back termination resistors to VCCO. The outputs are optimized to drive a 50Ω single-ended load and to obtain the maximum single-ended output voltage of 2.0Vpp, AC coupling and inductive pull-ups to VCC are required The polarity of the output pins can be inverted by setting the output polarity switch bit, POL (bit 2 of register 0) to 1. MODULATION CURRENT GENERATOR The modulation current generator provides the current for the current modulator described above. The circuit is digitally controlled by the 2-wire interface block. A 10-bit wide control bus, MODC[0..9] (registers 2 and 3), is used to set the desired modulation current, and therefore, the output voltage. The modulation current can be increased by setting HCENA = 1 (bit 4 of register 1) and enabling the high modulation current mode, however, the single-ended output voltage should be kept below 2Vpp for the best performance. The modulation current can be disabled by setting the DIS input pin to a high level or setting ENA = 0 (bit 7 of register 0). The modulation current is also disabled in a fault condition if the internal fault detection enable register flag FLTEN is set to 1 (bit 3 of register 0). DC OFFSET CANCELATION AND CROSS POINT CONTROL The ONET1141L has DC offset cancellation to compensate for internal offset voltages. The offset cancellation can be disabled by setting OCDIS = 1 (bit 3 of register 1). To adjust the eye crossing point, set CPENA = 1 (bit 2 of register 8). The crossing point can be moved toward the one level be setting CPSGN = 1 (bit 7 of register 7) and it can be moved toward the zero level by setting CPSGN = 0. The percentage of shift depends upon the register settings CPADJ[0..6] (register 7), and the cross point adjustment range bits CPRNG[0..1] (register 8). Setting CPRNG1 = 0 and CPRNG0 = 0 results in minimum adjustment capability and setting CPRNG1 = 1 and CPRNG0 = 1 results in maximum adjustment capability. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L 7 ONET1141L SLLSEB7 – MAY 2012 www.ti.com BIAS CURRENT GENERATION AND APC LOOP The bias current generation and APC loop are controlled by means of the 2-wire interface. In open loop operation, selected by setting OLENA = 1 (bit 4 of register 0) the bias current is set directly by the 10-bit wide control word BIASC[0..9] (registers 4 and 5). In automatic power control mode, selected by setting OLENA = 0, the bias current depends on the register settings BIASC[0..9] and the coupling ratio (CR) between the laser bias current and the photodiode current. CR = IBIAS/IPD. If the photodiode anode is connected to the PD pin (PD pin is sinking current), set PDPOL = 1 (bit 0 of register 0) and if the photodiode cathode is connected to the PD pin (PD pin is sourcing current), set PDPOL = 0. Three photodiode current ranges can be selected by means of the PDRNG[0..1] bits (register 0). The photodiode range should be chosen to keep the laser bias control DAC, BIASC[0..9], close to the center of its range. This keeps the laser bias current set point resolution high. For details regarding the bias current setting in open-loop as well as in closed-loop mode, see Table 19. The ONET1141L has the ability to source or sink the bias current. The default condition is for the BIAS pin to source the current (BIASPOL = 0). To act as a sink, set BIASPOL = 1 (bit 2 of register 1). The bias current is monitored using a current mirror with a gain equal to 1/100. By connecting a resistor between MONB and GND, the bias current can be monitored as a voltage across the resistor. A low temperature coefficient precision resistor should be used. The bias current can also be monitored as a 10 bit unsigned digital word through the 2-wire interface by setting DMONB = 1 (bit 0 of register 10) and removing the resistor to ground. ANALOG REFERENCE AND TEMPERATURE SENSOR The ONET1141L modulator driver is supplied by a single 3.3V±10% supply voltage connected to the VCC and VCCO pins. This voltage is referred to ground (GND) and can be monitored as a 10 bit unsigned digital word through the 2-wire interface. On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from which all other internally required voltages and bias currents are derived. An external zero temperature coefficient resistor must be connected from the RZTC pin of the device to ground. This resistor is used to generate a precise, zero-TC current which is required as a reference current for the onchip DACs. The ONET1141L provides an on-chip temperature sensor which can be monitored as a 10 bit unsigned digital word through the 2-wire interface. POWER-ON RESET The ONE1141L has power on reset circuitry which ensures that all registers are reset to zero during startup. After the power-on to initialize time (tINIT1), the internal registers are ready to be loaded. The part is ready to transmit data after the initialize to transmit time (tINIT2), assuming that the chip enable bit ENA is set to 1 and the disable pin DIS is low. The DIS pin has an internal 10kΩ pull up resistor so the pin must be pulled low to enable the outputs. The ONET1141L can be disabled using either the ENA control register bit or the disable pin DIS. In both cases the internal registers are not reset. After the disable pin DIS is set low and/or the enable bit ENA is set back to 1, the part returns to its prior output settings. To reduce the disable time, only the output stage can be disabled by setting DISMODE = 1 (bit 1 of register 1). ANALOG TO DIGITAL CONVERTER The ONET1141L has an internal 10 bit analog to digital converter (ADC) that converts the analog monitors for temperature, power supply voltage, bias current and photodiode current into a 10 bit unsigned digital word. The first 8 most significant bits (MSBs) are available in register 14 and the 2 least significant bits (LSBs) are available in register 15. Depending on the accuracy required, 8 bits or 10 bits can be read. However, due to the architecture of the 2-wire interface, in order to read the 2 registers, 2 separate read commands have to be sent. The ADC is enabled by default so to monitor a particular parameter, select the parameter with ADCSEL[0..1] (bits 0 and 1 of register 13). Table 1 shows the ADCSEL bits and the parameter that is monitored. 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L ONET1141L www.ti.com SLLSEB7 – MAY 2012 Table 1. ADC Selection Bits and the Monitored Parameter ADCSEL1 ADCSEL0 Monitored Parameter 0 0 Temperature 0 1 Supply voltage 1 0 Photodiode current 1 1 Bias current To digitally monitor the photodiode current, ensure that DMONP = 1 (bit 1 of register 10) and that a resistor is not connected to the MONP pin. To digitally monitor the bias current, ensure that DMONB = 1 (bit 0 of register 10) and that a resistor is not connected to the MONB pin. If it is not desired to use the ADC to monitor the various parameters then the ADC can be disabled by setting ADCDIS = 1 (bit 7 of register 13) and OSCDIS = 1 (bit 6 of register 13). The digital word read from the ADC can be converted to its analog equivalent through the following formulas: Temperature Without a Mid-Point Calibration Temperature (°C ) = (ADCx - 264 ) / 6 (1) Temperature With a Mid-Point Calibration Temperature (°C ) = (T _ cal(°C) + 273) ´ (ADCx + 1362 ) / (ADC _ cal + 1362 ) – 273 (2) Power Supply Voltage Power supply voltage (V ) = 2.25 ´ (ADCx +1380 ) / 1409 (3) Photodiode Current Monitor IPD (mA ) = 1.3 ´ ADCx (4) Bias Current Monitor Source mode : IBIAS (mA ) = 0.177 ´ ADCx Sink mode : IBIAS (mA ) = 0.19 ´ ADCx (5) Where: ADCx = the decimal value read from the ADC T_cal = the calibration temperature ADC_cal = the decimal value read from the ADC at the calibration temperature 2-WIRE INTERFACE AND CONTROL LOGIC The ONET1141L uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCK, are driven, respectively, by the serial data and serial clock from a microprocessor, for example. The SDA and SCK pins have internal 10kΩ pull ups to VCC. If a common interface is used to control multiple parts, the internal pull ups can be set to 40kΩ by setting TWITERM to 1 (bit 7 of register 1). This will also set the internal pullup on the DIS pin to 40 kΩ. The 2-wire interface allows write access to the internal memory map to modify control registers and read access to read out the control signals. The ONET1141L is a slave device only which means that it cannot initiate a transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The master device provides the clock signal as well as the START and STOP commands. The protocol for a data write transmission is as follows: 1. START command 2. 7 bit slave address (0001000) followed by an eighth bit (value = 0) which is the data write bit (W). 3. 8 bit register address 4. 8 bit register data word 5. STOP command The first 2 bits of the slave address can be changed to 1 by grounding the ADR0 and ADR1 pins. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L 9 ONET1141L SLLSEB7 – MAY 2012 www.ti.com Regarding timing, the ONET1141L is I2C compatible. The typical timing is shown in Figure 2 and complete data write and read transfers are shown in Figure 3. Parameters for Figure 2 are defined in Table 2. Bus Idle: Both SDA and SCK lines remain HIGH Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCK line is HIGH, defines a START condition (S). Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCK line is HIGH defines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, if the master still wishes to communicate on the bus, it can generate a repeated START condition and address another slave without first generating a STOP condition. Data Transfer: Only one data byte can be transferred between a START and a STOP condition. The receiver acknowledges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver doesn’t acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition. SDA t BUF tLOW tR tHIGH tF tHDSTA SCK P S S tHDSTA tHDDAT tSUDAT P tSUSTA tSUSTO Figure 2. I2C Timing Diagram Table 2. Timing Diagram Definitions SYMBOL PARAMETER MIN MAX UNIT 400 kHz fSCK SCK clock frequency tBUF Bus free time between STOP and START conditions 1.3 μs tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.6 μs tLOW Low period of the SCK clock 1.3 μs tHIGH High period of the SCK clock 0.6 μs tSUSTA Setup time for a repeated START condition 0.6 μs tHDDAT Data HOLD time 0 μs tSUDAT Data setup time tR Rise time of both SDA and SCK signals 300 ns tF Fall time of both SDA and SCK signals 300 ns tSUSTO Setup time for STOP condition 10 100 0.6 Submit Documentation Feedback ns μs Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L ONET1141L www.ti.com SLLSEB7 – MAY 2012 Write Sequence 1 7 1 1 8 1 8 1 1 S Slave Address Wr A Register Address A Data Byte A P Read Sequence 1 7 1 1 8 1 1 7 1 1 8 1 1 S Slave Address Wr A Register Address A S Slave Address Rd A Data Byte N P Legend S Start Condition Wr Write Bit (bit value = 0) Rd Read Bit (bit value = 1) A Acknowledge N Not Acknowledge P Stop Condition Figure 3. Programming Sequence REGISTER MAPPING The register mapping for register addresses 0 (0x00) through 15 (0x0F) are shown in Table 3 through Table 18. Table 19 describes the circuit functionality based on the register settings. Table 3. Register 0 (0x00) Mapping – Control Settings bit 7 ENA bit 6 PDRNG1 bit 5 PDRNG0 register address 0 (0x00) bit 4 bit 3 OLENA FLTEN bit 2 POL bit 1 EQENA bit 0 PDPOL bit 1 DISMODE bit 0 LOGENA bit 1 MODC1 bit 0 MODC0 bit 1 MODC3 bit 0 MODC2 Table 4. Register 1 (0x01) Mapping – Control Settings bit 7 TWITERM bit 6 HIEFCENA bit 5 HIEQGENA register address 1 (0x01) bit 4 bit 3 HCENA OCDIS bit 2 BIASPOL Table 5. Register 2 (0x02) Mapping – Modulation Current bit 7 – bit 6 – bit 5 – register address 2 (0x02) bit 4 bit 3 – – bit 2 – Table 6. Register 3 (0x03) Mapping – Modulation Current bit 7 MODC9 bit 6 MODC8 bit 5 MODC7 register address 3 (0x03) bit 4 bit 3 MODC6 MODC5 bit 2 MODC4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L 11 ONET1141L SLLSEB7 – MAY 2012 www.ti.com Table 7. Register 4 (0x04) Mapping – Bias Current bit 7 – bit 6 – bit 5 – register address 4 (0x04) bit 4 bit 3 – – bit 2 – bit 1 BIASC1 bit 0 BIASC0 bit 1 BIASC3 bit 0 BIASC2 bit 1 EQADJ1 bit 0 EQADJ0 bit 1 CPADJ1 bit 0 CPADJ0 Table 8. Register 5 (0x05) Mapping – Bias Current bit 7 BIASC9 bit 6 BIASC8 bit 5 BIASC7 register address 5 (0x05) bit 4 bit 3 BIASC6 BIASC5 bit 2 BIASC4 Table 9. Register 6 (0x06) Mapping – Equalizer Adjust bit 7 EQADJ7 bit 6 EQADJ6 bit 5 EQADJ5 register address 6 (0x06) bit 4 bit 3 EQADJ4 EQADJ3 bit 2 EQADJ2 Table 10. Register 7 (0x07) Mapping – Cross Point Adjust bit 7 CPSGN bit 6 CPADJ6 bit 5 CPADJ5 register address 7 (0x07) bit 4 bit 3 CPADJ4 CPADJ3 bit 2 CPADJ2 Table 11. Register 8 (0x08) Mapping – Cross Point Control Settings bit 7 IDRV bit 6 – bit 5 – register address 8 (0x08) bit 4 bit 3 CPREF – bit 2 CPENA bit 1 CPRNG1 bit 0 CPRNG0 Table 12. Register 9 (0x09) Mapping – Limiter Bias Current Adjust bit 7 LIMCSGN bit 6 LMC2 bit 5 LIMC1 register address 9 (0x09) bit 4 bit 3 LIMC0 EFCSGN bit 2 EFC2 bit 1 EFC1 bit 0 EFC0 bit 1 DMONP bit 0 DMONB Table 13. Register 10 (0x0A) Mapping – Monitor Settings bit 7 – bit 6 – bit 5 – register address 10 (0x0A) bit 4 bit 3 – – bit 2 MONPFLT Table 14. Register 11 (0x0B) Mapping – Bias Monitor Fault Settings bit 7 BMF7 bit 6 BMF6 bit 5 BMF5 register address 11 (0x0B) bit 4 bit 3 BMF4 BMF3 bit 2 BMF2 bit 1 BMF1 bit 0 BMF0 Table 15. Register 12 (0x0C) Mapping – Power Monitor Fault Settings bit 7 PMF7 bit 6 PMF6 bit 5 PMF5 register address 12 (0x0C) bit 4 bit 3 PMF4 PMF3 bit 2 PMF2 bit 1 PMF1 bit 0 PMF0 bit 1 ADCSEL1 bit 0 ADCSEL0 Table 16. Register 13 (0x0D) Mapping – ADC Settings bit 7 ADCDIS 12 bit 6 OSCDIS bit 5 – register address 13 (0x0D) bit 4 bit 3 – – Submit Documentation Feedback bit 2 – Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L ONET1141L www.ti.com SLLSEB7 – MAY 2012 Table 17. Register 14 (0x0E) Mapping – ADC Output (Read Only) bit 7 ADC9 bit 6 ADC8 bit 5 ADC7 register address 14 (0x0E) bit 4 bit 3 ADC6 ADC5 bit 2 ADC4 bit 1 ADC3 bit 0 ADC2 Table 18. Register 15 (0x0F) Mapping – ADC Output (Read Only) bit 7 – bit 6 – bit 5 – register address 15 (0x0F) bit 4 bit 3 – – bit 2 – bit 1 ADC1 bit 0 ADC0 Table 19. Register Functionality REGISTER 0 BIT SYMBOL FUNCTION 7 ENA Enable chip bit 1 = Chip enabled. Can be toggled low to reset a fault condition. 0 = Chip disabled 6 5 PDRNG1 PDRNG0 Photodiode current range bits 1X: up to 3080µA / 3µA resolution 01: up to 1540µA / 1.5µA resolution 00: up to 770μA / 0.75μA resolution 4 OLENA Open loop enable bit 1 = Open loop bias current control, 0 = Closed loop bias current control 3 FLTEN Fault detection enable bit 1 = Fault detection on 0 = Fault detection off 2 POL Output polarity switch bit 1: pin 22 = OUT- and pin 21= OUT+ 0: pin 22 = OUT+ and pin 21 = OUT- 1 EQENA Equalizer enable bit 1 = Equalizer is enabled 0 = Equalizer is disabled and bypassed 0 PDPOL Photodiode polarity bit 1 = Photodiode cathode connected to VCC 0 = Photodiode anode connected to GND Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L 13 ONET1141L SLLSEB7 – MAY 2012 www.ti.com Table 19. Register Functionality (continued) REGISTER 1 3 2 5 4 14 BIT SYMBOL 7 TWITERM Two wire interface input termination select bit 1 = 40kΩ selected 0 = 10kΩ selected FUNCTION 6 HIEFCENA High emitter follower drive current enable bit 1 = High current enabled 0 = High current disabled 5 HIEQGENA High gain enable for EQ stage (with EQENA = 1) 1 = High gain enabled 0 = High gain disabled 4 HCENA High modulation current enable bit 1 = High modulation current enabled 0 = High modulation current disabled 3 OCDIS Offset cancellation disable bit 1 = DC offset cancellation is disabled 0 = DC offset cancellation is enabled 2 BIASPOL Bias current polarity bit 1 = Bias pin sinks current 0 = Bias pin sources current 1 DISMODE Disable mode setting bit 1 = Only the output stage is disabled (fast disable mode) 0 = Major parts of the signal path are disabled 0 LOGENA Low gain enable for input amplifier (with EQENA = 0) 1 = Low gain enabled 0 = Default gain 7 MODC9 Modulation current setting: sets the output voltage 6 MODC8 5 MODC7 4 MODC6 3 MODC5 2 MODC4 1 MODC3 0 MODC2 1 MODC1 0 MODC0 7 BIASC9 Bias curent settings Closed loop (APC): 6 BIASC8 Coupling ratio CR = IBIAS / IPD, BIASC = 0..1023, IBIAS ≤ 150mA: 5 BIASC7 4 BIASC6 PDRNG = 00 (see above); IBIAS = 0.75µA x CR x BIASC 3 BIASC5 PDRNG = 01 (see above); IBIAS = 1.5µA x CR x BIASC 2 BIASC4 PDRNG = 1X (see above); IBIAS = 3µA x CR x BIASC 1 BIASC3 0 BIASC2 Open loop: 1 BIASC1 IBIAS ~ 150µA x BIASC in source mode 0 BIASC0 IBIAS ~ 100µA x BIASC in sink mode Output Voltage: 2.3Vpp / 2.5mV steps Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L ONET1141L www.ti.com SLLSEB7 – MAY 2012 Table 19. Register Functionality (continued) REGISTER 6 7 8 9 BIT SYMBOL 7 EQADJ7 FUNCTION 6 EQADJ6 5 EQADJ5 EQENA = 0 (see above) 4 EQADJ4 Equalizer is turned off and bypassed 3 EQADJ3 2 EQADJ2 EQENA = 1 (see above) 1 EQADJ1 Maximum equalization for 00000000 0 EQADJ0 Minimum equalization for 11111111 7 CPSGN Eye cross-point adjustment setting 6 CPADJ6 CPSGN = 1 (positive shift) 5 CPADJ5 Maximum shift for 1111111 4 CPADJ4 Minimum shift for 0000000 3 CPADJ3 CPSGN = 0 (negative shift) 2 CPADJ2 Maximum shift for 1111111 1 CPADJ1 Minimum shift for 0000000 0 CPADJ0 7 IDRV 6 - 5 - 4 CPREF 3 - 2 CPENA Cross point adjustment enable bit 1 = Cross point adjustment is enabled 0 = Cross point adjustment is disabled 1 0 CPRNG1 CPRNG0 Cross point adjustment range bits Minimum adjustment range for 00 Maximum adjustment range for 11 7 LIMCSGN Limiter bias current sign bit 1 = Decrease limiter bias current 0 = Increase limiter bias current 6 5 4 LIMC2 LIMC1 LIMC0 Limiter bias current selection bits 000 = No change 111 = Maximum current change 3 EFCSGN Emitter follower sign bit 1 = Decrease emitter follower current 0 = Increase emitter follower current 2 1 0 EFC2 EFC1 EFC0 Emitter follower current selection bits 000 = No change 111 = Maximum current change Equalizer adjustment setting Output Driver Tail Current Bit 1 = Output driver tail current is increased 0 = Output driver tail current is set to default Cross point temperature coefficient selection bit 1 = Reverses the behavior MM and EQENA = 1: temperature coefficient disabled MM and EQENA = 0: temperature coefficient enabled 0 = Default condition MM and EQENA = 1: temperature coefficient enabled MM and EQENA = 0: temperature coefficient disabled Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L 15 ONET1141L SLLSEB7 – MAY 2012 www.ti.com Table 19. Register Functionality (continued) REGISTER BIT 10 7 - 6 - 5 - 4 - 3 - 2 MONPFLT Analog photodiode current monitor fault trigger bit 1 = Fault trigger on MONP pin is enabled 0 = Fault trigger on MONP pin is disabled 1 DMONP Digital photodiode current monitor selection bit (MONP) 1 = Digital photodiode monitor is active (external resistor must not be installed) 0 = Analog photodiode monitor is active (external resistor is required) 0 DMONB Digital bias current monitor selection bit (MONB) 1 = Digital bias current monitor is active (external resistor must not be installed) 0 = Analog bias current monitor is active (external resistor is required) 7 BMF7 Bias current monitor fault threshold 6 BMF6 With DMONB = 1 5 BMF5 Register sets the value of the bias current that will trigger a fault. 4 BMF4 The external resistor on the MONB pin must be removed to use this feature. 3 BMF3 2 BMF2 1 BMF1 0 BMF0 7 PMF7 Power monitor fault threshold 6 PMF6 With DMONP = 1 5 PMF5 Register sets the value of the photodiode current that will trigger a fault 4 PMF4 The external resistor on the MONP pin must be removed to use this feature. 3 PMF3 2 PMF2 1 PMF1 0 PMF0 7 ADCDIS ADC disable bit 1 = ADC disabled 0 = ADC enabled 6 OSCDIS ADC oscillator bit 1 = Oscillator disabled 0 = Oscillator enabled ADCSEL1 ADCSEL0 ADC input selection bits 00 selects the temperature sensor 01 selects the power supply monitor 10 selects MONP 11 selects MONB 11 12 13 SYMBOL FUNCTION 5 4 3 2 1 0 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L ONET1141L www.ti.com SLLSEB7 – MAY 2012 Table 19. Register Functionality (continued) REGISTER BIT 14 7 ADC9 (MSB) 6 ADC8 5 ADC7 4 ADC6 3 ADC5 2 ADC4 1 ADC3 0 ADC2 7 - 6 - 5 - 4 - 3 - 2 - 1 ADC1 0 ADC0 (LSB) 15 SYMBOL FUNCTION Digital representation of the ADC input source (read only) Digital representation of the ADC input source (read only) LASER SAFETY FEATURES AND FAULT RECOVERY PROCEDURE The ONET1141L provides built in laser safety features. The following fault conditions are detected: 1. Voltage at MONB exceeds the voltage at RZTC (1.16V) or, alternately, if DMONB = 1 and the bias current exceeds the bias current monitor fault threshold set by BMF[0..7] (register 11). When using the digital monitor, the resistor to ground must be removed. 2. Voltage at MONP exceeds the voltage at RZTC (1.16V) and the analog photodiode current monitor fault trigger bit, MONPFLT (bit 2 of register 10), is set to 1. Alternately, a fault can be triggered if DMONP = 1 and the photodiode current exceeds the photodiode current monitor fault threshold set by PMF[0..7] (register 12). When using the digital monitor, the resistor to ground must be removed. 3. Photodiode current exceeds 150% of its set value, 4. Bias control DAC drops in value by more than 50% in one step. If one or more fault conditions occur and the fault enable bit FLTEN is set to 1, the ONET1141L responds by: 1. Setting the bias current to zero. 2. Setting the modulation current to zero. 3. Asserting and latching the FLT pin. Fault recovery is performed by the following procedure: 1. The disable pin DIS and/or the internal enable control bit ENA are toggled for at least the fault latch reset time. 2. The FLT pin de-asserts while the disable pin DIS is asserted or the enable bit ENA is de-asserted. 3. If the fault condition is no longer present, the part will return to normal operation with its prior output settings after the disable negate time. 4. If the fault condition is still present, FLT re-asserts once DIS is set to a low level and the part will not return to normal operation. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L 17 ONET1141L SLLSEB7 – MAY 2012 www.ti.com TYPICAL CHARACTERISTICS Typical operating condition is at VCC = 3.3V, TA = 25°C, IBIASC = 80mA, VOUT = 2VPP, VIN = 400mVpp (unless otherwise noted). DETERMINISTIC JITTER vs MODULATION CURRENT DETERMINISTIC JITTER vs TEMPERATURE 12 8 Deterministic Jitter - pspp Deterministic Jitter - pspp 10 8 6 4 6 4 2 2 0 300 400 500 600 700 800 900 Modulation Current Register Setting - Decimal 0 -40 1000 -20 0 20 40 60 TA - Free-Air Temperature - °C Figure 4. Figure 5. RANDOM JITTER vs MODULATION CURRENT RANDOM JITTER vs TEMPERATURE 1 80 100 0.4 0.9 0.8 Random Jitter - psrms Random Jitter - psrms 0.3 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.2 0.1 0 300 400 500 600 700 800 900 Modulation Current Register Setting - Decimal 1000 0 -40 -20 Figure 6. 18 0 20 40 60 TA - Free-Air Temperature - °C 80 100 Figure 7. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L ONET1141L www.ti.com SLLSEB7 – MAY 2012 TYPICAL CHARACTERISTICS (continued) Typical operating condition is at VCC = 3.3V, TA = 25°C, IBIASC = 80mA, VOUT = 2VPP, VIN = 400mVpp (unless otherwise noted). RISE-TIME AND FALL-TIME vs MODULATION CURRENT RISE-TIME AND FALL-TIME vs TEMPERATURE 35 35 25 Fall Time 20 15 20 15 10 5 5 400 500 600 700 800 900 Modulation Current Register Setting - Decimal Fall Time 25 10 0 300 Rise Time 30 Rise Time Transition Time - ps Transition Time - ps 30 0 -40 1000 -20 0 20 40 60 TA - Free-Air Temperature - °C 80 Figure 8. Figure 9. BIAS CURRENT IN OPEN LOOP MODE vs BIAS CURRENT REGISTER SETTING BIAS CURRENT IN OPEN LOOP MODE vs BIAS CURRENT REGISTER SETTING 100 120 180 160 Sink OL Bias Current - mA Source OL Bias Current - mA 100 140 120 100 80 60 80 60 40 40 20 20 0 0 0 200 400 600 800 1000 Bias Current Register Setting - Decimal 1200 0 200 Figure 10. 400 600 800 1000 Bias Current Register Setting - Decimal 1200 Figure 11. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L 19 ONET1141L SLLSEB7 – MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Typical operating condition is at VCC = 3.3V, TA = 25°C, IBIASC = 80mA, VOUT = 2VPP, VIN = 400mVpp (unless otherwise noted). PHOTODIODE MONITOR CURRENT vs PHOTODIODE CURRENT BIAS MONITOR CURRENT vs BIAS CURRENT 1.8 0.8 Photodiode Monitor Current - mA 1.6 Bias Monitor Current - mA 1.4 1.2 1 0.8 0.6 0.4 0.6 0.4 0.2 0.2 0 0 20 40 60 80 100 120 Bias Current - mA 140 160 0 180 0 0.2 0.4 0.6 0.8 1 Photodiode Current - mA Figure 12. Figure 13. OUTPUT VOLTAGE vs MODC REGISTER SETTING SUPPLY CURRENT vs TEMPERATURE 3 1.2 1.4 1.6 200 190 2.5 Supply Current - mA SE Output Voltage - V 180 2 1.5 1 170 160 150 140 130 120 0.5 110 0 0 200 400 600 800 1000 Modulation Current Register Setting - Decimal 1200 100 -40 -20 Figure 14. 20 0 20 40 60 TA - Free-Air Temperature - °C 80 100 Figure 15. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L ONET1141L www.ti.com SLLSEB7 – MAY 2012 TYPICAL CHARACTERISTICS (continued) Typical operating condition is at VCC = 3.3V, TA = 25°C, IBIASC = 80mA, VOUT = 2VPP, VIN = 400mVpp (unless otherwise noted). EYE-DIAGRAM AT 10.31GBPS VOUT=2VPP, EQ Set to 00 500 mV/div EYE-DIAGRAM AT 11.3GBPS VOUT=2VPP, EQ Set to 00, 50% Cross Point 15 ps/div 15 ps/div 500 mV/div Figure 16. Figure 17. EYE-DIAGRAM AT 11.3GBPS VOUT=2VPP, EQ Set to 00, 30% Cross Point EYE-DIAGRAM AT 11.3GBPS VOUT=2VPP, EQ Set to 00, 70% Cross Point 15 ps/div 500 mV/div 500 mV/div 15 ps/div Figure 18. Figure 19. EYE-DIAGRAM AT 11.3GBPS VOUT=2VPP, EQ Set to 00, 6’’ OF FR4 AT INPUTS 15 ps/div 500 mV/div Figure 20. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L 21 ONET1141L SLLSEB7 – MAY 2012 www.ti.com APPLICATION INFORMATION Figure 21 and Figure 22 show typical application circuits using the ONET1141L. The modulator must be AC coupled to the driver for proper operation. The laser driver is controlled via the 2-wire interface SDA/SCK by a microcontroller. In a typical application, the FLT, MONB and MONP outputs are also connected to the microcontroller for transceiver management purposes. The component values in Figure 21 and Figure 22 are typical examples and may be varied according to the intended application. DIS VCC SDK 0.1μF PD ADR0 ADR1 DIS SCK SDA SDA 0.1μF FLT VCCO GND GND DIN+ DIN+ MOD- DIN- DIN– MOD+ GND GND RZTC VCCO FLT C1 0.1μF ONET1141L C2 0.1μF EA BIAS 0.1μF EML TOSA 50Ω Modulator Anode 0.1μF 0.1μF BIAS GND VCC COMP MONP MONB 50Ω Laser PD RZTC 28.7kΩ 0.1μF 0.01μF MONB RMONB 1kΩ MONP RMONP 5kΩ CCOMP 0.01μF Figure 21. AC Coupled Drive with PD Monitor Cathode Available 22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L ONET1141L www.ti.com SLLSEB7 – MAY 2012 DIS VCC SDK 0.1μF PD ADR0 ADR1 DIS SCK SDA SDA 0.1μF FLT VCCO GND GND DIN+ DIN+ MOD- DIN- DIN– MOD+ GND GND RZTC VCCO FLT C1 0.1μF ONET1141L C2 0.1μF EA BIAS 0.1μF EML TOSA 50Ω Modulator Anode 0.1μF 0.1μF BIAS GND VCC COMP MONP MONB 50Ω Laser PD RZTC 28.7kΩ 0.1μF 0.01μF -3V MONB RMONB 1kΩ MONP RMONP 5kΩ CCOMP 0.01μF Figure 22. AC Coupled Drive with PD Monitor Anode Available Layout Guidelines For optimum performance, use 50Ω transmission lines (100Ω differential) for connecting the signal source to the DIN+ and DIN– pins and 50Ω transmission lines (100Ω differential) for connecting the modulation current outputs, MOD+ and MOD–, to the laser. The length of the transmission lines should be kept as short as possible to reduce loss and pattern-dependent jitter. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s) :ONET1141L 23 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ONET1141LRGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 100 ONET 1141L ONET1141LRGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 100 ONET 1141L (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of