ONET2501PARGT

   
     SLLS602B − MARCH 2004 − REVISED OCTOBER 2005 features D Multi-Rate Operation From 155 Mbps Up To D D D D D D D D 2.5 Gbps Low Power Consumption Input Offset Cancellation High Input Dynamic Range Output Disable Output Polarity Select CML Data Outputs Receive Signal Strength Indicator (RSSI) Loss Of Signal Detection (LOS) D Single 3.3-V Supply D Surface Mount Small Footprint 3 mm × 3 mm 16-Pin QFN Package applications D SONET/SDH Transmission Systems at OC3, D D OC12, OC24, OC48 1.0625-Gbps and 2.125-Gbps Fibre Channel Receivers Gigabit Ethernet Receivers description The ONET2501PA is a versatile high-speed limiting amplifier for multiple fiber optic applications with data rates up to 2.5 Gbps. This device provides a gain of about 50 dB, which ensures a fully differential output swing for input signals as low as 3 mVp−p. The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal swings as high as 1200 mVp−p. The ONET2501PA is available in a small footprint 3 mm × 3 mm, 16-pin QFN package. The circuit requires a single 3.3-V supply. This power efficient limiting amplifier is characterized for operation from –40°C to 85°C Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2005, Texas Instruments Incorporated 

   !  "#$!   # %"! &!$ &#"! " ! $""! $ !'$ !$  $( !#$! !&& )!* &#"! "$+ &$ ! $"$%* "%#&$ !$!+  %% $!$ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
   
     SLLS602B − MARCH 2004 − REVISED OCTOBER 2005 block diagram A simplified block diagram of the ONET2501PA is shown in Figure 1. This compact, low power 2.5-Gbps limiting amplifier consists of a high-speed data path with offset cancellation block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation block. The limiting amplifier requires a single 3.3-V supply voltage. All circuit parts are described in detail below. COC2 COC1 VCC Offset Cancellation GND OUTPOL VCCO DIN+ + DIN− − Input Buffer + + − Gain Stage + + − − − Gain Stage Gain Stage DOUT+ DOUT− CML Output Buffer DISABLE Bandgap Voltage Reference and Bias Current Generation Loss of Signal and RSSI Detection LOS RSSI TH Figure 1. Block Diagram high-speed data path The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data path consists of the input stage with 2 × 50-Ω on-chip line termination to VCC, three gain stages, which provide the required typical gain of about 50 dB, and a CML output stage. The amplified data output signal is available at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω back-termination to VCCO. The output stage also includes a data polarity switching function, which is controlled by the OUTPOL input, and a disable function, controlled by the signal applied to the DISABLE input pin. An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even for small input data signals. The low frequency cutoff is as low as 45 kHz with the built-in filter capacitor. For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be connected to the COC1/COC2 pins. los of signal and RSSI detection The output signal of the input buffer is monitored by the loss of signal and RSSI detection circuitry. In this block a signal is generated, which is linearly proportional to the input amplitude over a wide input voltage range. This signal is available at the RSSI output pin. Furthermore, this circuit block compares the input signal to a threshold, which can be programmed by means of an external resistor connected to the TH pin. If the input signal falls below the specified threshold, a loss of signal is indicated at the LOS pin. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
     SLLS602B − MARCH 2004 − REVISED OCTOBER 2005 The relationship between the LOS assert voltage VAST (in mVP-P) and the external resistor RTH (in kΩ) connected to the TH pin can be approximated as given below: R V TH + AST V + 43 kW * 600 W ńmV p*p AST 43 mV p*p R ńkW ) 0.6 TH bandgap voltage and bias generation The ONET2501PA limiting amplifier is supplied by a single 3.3-V ±10% supply voltage connected to the VCC and VCCO pins. This voltage is referred to ground (GND). An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other internally required voltages and bias currents are derived. package For the ONET2501PA a small footprint 3 mm × 3 mm 16-pin QFN package is used, with a lead pitch of 0,5 mm. The pin out is shown in Figure 2. VCC 1 DIN+ 2 GND COC2 COC1 RSSI RGT PACKAGE (TOP VIEW) 16 15 14 13 12 VCCO 11 DOUT+ DOUT− EP 4 9 5 6 7 8 GND VCC LOS 10 DISABLE 3 TH DIN− OUTPOL Figure 2. Pin Out of ONET2501PA in a 3 mm y 3 mm 16-Pin QFN Package, Top View POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
   
     SLLS602B − MARCH 2004 − REVISED OCTOBER 2005 terminal functions The following table shows a pin description for the ONET2501PA in a 3 mm x 3 mm 16-pin QFN package. TERMINAL TYPE NAME NO. VCC 1, 4 Supply DESCRIPTION 3.3-V ±10% supply voltage DIN+ 2 Analog in Noninverted data input. On-chip 50-Ω terminated to VCC. DIN– 3 Analog in Inverted data input. On-chip 50-Ω terminated to VCC. TH 5 Analog in LOS threshold adjustment with resistor to GND. DISABLE 6 CMOS in Disables CML output stage when set to high level. LOS 7 CMOS out GND 8, 16, EP Supply High level indicates that the input signal amplitude is below the programmed threshold level. OUTPOL 9 CMOS in Output data signal polarity select (internally pulled up): Setting to high level or leaving pin open selects normal polarity. Low level selects inverted polarity. Circuit ground. Exposed die pad (EP) must be grounded. DOUT– 10 CML out Inverted data output. On-chip 50-Ω back-terminated to VCCO DOUT+ 11 CML out Noninverted data output. On-chip 50-Ω back-terminated to VCCO VCCO 12 Supply RSSI 13 Analog out COC1 14 Analog Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15). COC2 15 Analog Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15). 3.3-V ±10% supply voltage for output stage Analog output voltage proportional to the input data amplitude. Indicates the strength of the received signal (RSSI). absolute maximum ratings over operating free-air temperature range unless otherwise noted† VCC, VCCO VDIN+, VDIN− Supply voltage, See Note 1 VTH,VDISABLE,VLOS,VOUTPOL,VDOUT+, VDOUT−, VRSSI, VCOC1, VCOC2 Voltage at TH, DISABLE, LOS, OUTPOL, DOUT+, DOUT–, RSSI, COC1, and COC2, See Note 1 VCOC,DIFF VDIN,DIFF Differential voltage between COC1 and COC2 ILOS IDIN+, IDIN−, IDOUT+, IDOUT– Current into LOS ESD ESD rating at all pins TJ(max) Tstg Maximum junction temperature TA TL Voltage at DIN+, DIN–, See Note 1 Differential voltage between DIN+ and DIN– Continuous current at inputs and outputs VALUE UNIT –0.3 to 4 V 0.5 to 4 V –0.3 to 4 V ±1 V ±2.5 V –1 to 9 mA –25 to 25 mA 3 kV (HBM) 125 °C Storage temperature range −65 to 85 °C Characterized free-air operating temperature range −40 to 85 °C 260 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network ground terminal. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
     SLLS602B − MARCH 2004 − REVISED OCTOBER 2005 recommended operating conditions MIN TYP MAX 3 3.3 3.6 V 85 °C Supply voltage, VCC, VCCO Operating free-air temperature, TA −40 UNIT dc electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VCC,VCCO ICC TEST CONDITIONS MIN Supply voltage 3 Supply current DISABLE = low (excludes CML output current) DISABLE = high VOD Differential data output voltage swing rIN, rOUT Data input/output resistance V(IN_MIN) V(IN_MAX) DISABLE = low 600 Single ended TYP 3.6 40 mA 10 780 1200 mVp−p mVp−p Ω 100 RSSI output voltage Input = 80 mVp−p, RRSSI ≥ 10 kΩ 2800 RSSI linearity 20-dB input signal, VIN ≤ 80 mVpp BER < 10–10 ±3% ±8% 3 5 Data input overload 2.1 LOS hysteresis LOS assert threshold range 223−1 PRBS (at 2.5 Gbps and 155 Mbps) Power supply noise rejection f < 2 MHz 2.4 V V 0.8 2.5 mVp−p mVp−p V 0.6 ISINK = –30 µA ISOURCE = 1 mA 223−1 PRBS (at 2.5 Gbps and 155 Mbps) LOS low voltage mV 1200 CMOS input low voltage LOS high voltage V 32 Input = 2 mVp−p, RRSSI ≥ 10 kΩ Data input sensitivity UNIT 0.25 50 CMOS input high voltage VAST PSNR MAX 3.3 4.5 V dB 5−40 mVp−p dB 26 ac electrical characteristics over recommended operating conditions (unless otherwise noted) typical operating condition is at VCC = 3.3 V and TA = 25°C PARAMETER Low frequency −3-dB bandwidth TEST CONDITIONS Input referred noise DJ Deterministic jitter, See Note 2 TYP MAX 45 COC = 100 nF 0.8 Data rate vNI MIN COC = open UNIT 70 kHz 2.5 Gb/s 300 K28.5 pattern at 2.5 Gbps 223−1 PRBS equivalent pattern at 2.5 Gbps 223−1 PRBS equivalent pattern at 155 Mbps 8.5 25 9.3 30 25 50 Input = 5 mVpp 6.5 µVRMS psp−p RJ Random jitter tr tf Output rise time 20% to 80% 60 85 ps Output fall time 20% to 80% 60 85 ps tDIS tLOS Disable response time Input = 10 mVpp psRMS 3 20 LOS assert/deassert time 2 ns 100 µs NOTE 2: Deterministic jitter does not include pulse-width distortion due to residual small output offset voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
   
     SLLS602B − MARCH 2004 − REVISED OCTOBER 2005 APPLICATION INFORMATION Figure 3 shows the ONET2501PA connected with an ac-coupled interface to the data signal source as well as to the output load. Besides the ac-coupling capacitors C1 through C4 in the input and output data signal lines, the only required external component is the LOS threshold setting resistor RTH. In addition, an optional external filter capacitor (COC) may be used if a lower cutoff frequency is desired. RSSI RSSI COC1 COC2 GND COC Optional VCC DIN− DOUT+ ONET2501PA 16-Pin QFN TH VCC DOUT− VCC C3 DOUT+ C4 DOUT− OUTPOL OUTPOL GND DIN+ LOS DIN− C2 VCCO DISABLE DIN+ C1 DISABLE LOS RTH Figure 3. Basic Application Circuit With AC-Coupled I/Os 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
   
     SLLS602B − MARCH 2004 − REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS Typical operating condition is at VCC = VCCO = 3.3 V and TA = 25°C, unless otherwise noted RANDOM JITTER vs DIFFERENTIAL INPUT VOLTAGE 900 10 800 9 8 700 Random Jitter − psRMS VOD − Differential Output Voltage − mVP-P DIFFERENTIAL OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 600 500 400 300 200 7 6 5 4 3 2 100 1 0 0 1 2 3 4 5 6 0 5 10 15 20 25 30 35 VID − Differential Input Voltage − mVP-P VID − Differential Input Voltage − mVP-P Figure 4 Figure 5 BIT ERROR RATIO vs DIFFERENTIAL INPUT VOLTAGE SMALL SIGNAL GAIN vs FREQUENCY 100 60 10-2 55 40 50 10-4 Small Signal Gain − dB 45 Bit Error Ratio 10-6 10-8 10-10 10-12 10-14 40 35 30 25 20 15 10 10-16 10-18 1.0 5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.01 0.1 1 10 100 VID − Differential Input Voltage − mVP-P f − Frequency − MHz Figure 6 Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1k 10k 7 
   
     SLLS602B − MARCH 2004 − REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS Typical operating condition is at VCC = VCCO = 3.3 V and TA = 25°C, unless otherwise noted OUTPUT EYE-DIAGRAM at 2.5 GBPS and MAXIMUM INPUT VOLTAGE (1200 mVPP) VOD − Differential Output Voltage − 100 mV/Div VOD − Differential Output Voltage − 100 mV/Div OUTPUT EYE-DIAGRAM at 2.5 GBPS and MINIMUM INPUT VOLTAGE (5 mVPP) t − Time − 100 ps/Div t − Time − 100 ps/Div Figure 8 Figure 9 LOS ASSERT/DEASSERT VOLTAGE vs THRESHOLD VOLTAGE SETTING RESISTANCE DIFFERENTIAL INPUT RETURN GAIN vs FREQUENCY 0 SDD11 − Differential Input Return Gain − dB LOS Assert/Deassert Voltage − mVP-P 70 60 50 40 30 LOS Deassert Voltage 20 10 LOS Assert Voltage 0 0 8 1 2 3 4 5 6 7 8 9 10 −5 −10 −15 −20 −25 −30 −35 −40 −45 −50 0.1 1 Rth − Threshold Voltage Setting Resistance − kΩ f − Frequency − GHz Figure 10 Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
   
     SLLS602B − MARCH 2004 − REVISED OCTOBER 2005 TYPICAL CHARACTERISTICS Typical operating condition is at VCC = VCCO = 3.3 V and TA = 25°C, unless otherwise noted RECEIVE SIGNAL STRENGTH INDICATOR VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE SDD22 − Differential Output Return Gain − dB 0 −5 −10 −15 −20 −25 −30 −35 −40 −45 −50 0.1 1 5 RSSI − Receive Signal Strength Indicator Voltage − mV DIFFERENTIAL OUTPUT RETURN GAIN vs FREQUENCY 2800 2600 2400 2200 2000 1800 1600 1400 1200 1000 800 600 400 200 0 0 10 20 30 40 50 60 70 80 f − Frequency − GHz VID − Differential Input Voltage − mVP-P Figure 12 Figure 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 90 9 IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you (individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of this Notice. 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