ONET2511PARGTTG4

    
     SLLS604 − MARCH 2004 features D Multi-Rate Operation from 155 Mbps Up to D D D D D D 2.5 Gbps Ultralow Power Consumption Input Offset Cancellation High Input Dynamic Range Output Disable Output Polarity Select CML Data Outputs D Single 3.3-V Supply D Surface Mount Small Footprint 3 mm × 3 mm 16-Pin QFN Package applications D SONET/SDH Transmission Systems at OC3, D D OC12, OC24, OC48 1.0625-Gbps and 2.125-Gbps Fibre Channel Receivers Gigabit Ethernet Receivers description The ONET2511PA is a versatile high-speed limiting amplifier for multiple fiber optic applications with data rates up to 2.5 Gbps. This device provides a gain of about 50 dB, which ensures a fully differential output swing for input signals as low as 3 mVp−p. The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal swings as high as 1200 mVp−p. The ONET2511PA is available in a small footprint 3 mm × 3 mm 16-pin QFN package. The circuit requires a single 3.3-V supply. This power efficient limiting amplifier is characterized for operation from –40°C to 85°C available options TA −40°C to 85°C PACKAGED DEVICE FEATURES ONET2511PARGT 2.5-Gbps ultralow power limiting amplifier Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated 

     !"#   "$! %# %"! !   #!! # &# #  #' "# %% () %"! !#* %#  #!#$) !$"%# #*  $$ ## POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
    
     SLLS604 − MARCH 2004 block diagram A simplified block diagram of the ONET2511PA is shown in Figure 1. These compact, low power 2.5-Gbps limiting amplifier consists of a high-speed data path with offset cancellation block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation block. The limiting amplifier requires a single 3.3-V supply voltage. All circuit parts are described in detail below. COC2 COC1 Bandgap Voltage Reference and Bias Current Generation Offset Cancellation VCC OUTPOL GND DIN+ DIN− VCCO + − Input Buffer + + + Gain Stage Gain Stage + DOUT+ − DOUT− Gain Stage CML Output Buffer DISABLE Figure 1. Block Diagram high-speed data path The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data path consists of the input stage with 2 × 50-Ω on-chip line termination to VCC, three gain stages which provide the required typical gain of about 50 dB, and a CML output stage. The amplified data output signal is available at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω back-termination to VCCO. The output stage also includes a data polarity switching function, which is controlled by the OUTPOL input and a disable function, controlled by the signal applied to the DISABLE input pin. An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even for small input data signals. The low frequency cutoff is as low as 45 kHz with the built-in filter capacitor. For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be connected to the COC1/COC2 pins. bandgap voltage and bias generation The ONET2511PA limiting amplifier is supplied by a single 3.3-V ±10% supply voltage connected to the VCC and VCCO pins. This voltage is referred to ground (GND). An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other internally required voltages and bias currents are derived. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
     SLLS604 − MARCH 2004 package N.C. COC1 GND COC2 For the ONET2511PA a small footprint 3 mm × 3 mm 16-pin QFN package is used, with a lead pitch of 0,5 mm. The pinout is shown in Figure 2. VCC VCCO OUTPOL N.C. DOUT− VCC GND DIN− DISABLE DOUT+ N.C. DIN+ Figure 2. Pinout of ONET2511PA in a 3 mm y 3 mm 16-Pin QFN Package terminal functions The following table shows a pin description for the ONET2511PA in a 3 mm x 3 mm 16-pin QFN package. TERMINAL TYPE NAME NO. VCC 1, 4 Supply DESCRIPTION 3.3-V ±10% supply voltage DIN+ 2 Analog in Noninverted data input. On-chip 50-Ω terminated to VCC DIN– 3 Analog in Inverted data input. On-chip 50-Ω terminated to VCC N.C. 5, 7, 13 DISABLE 6 Not connected CMOS in Disables CML output stage when set to high level GND 8, 16, EP Supply OUTPOL 9 CMOS in Circuit ground. Exposed die pad (EP) must be grounded. Output data signal polarity select (internally pulled up): Setting to high level or leaving pin open selects normal polarity. Low level selects inverted polarity. DOUT– 10 CML out Inverted data output. On-chip 50-Ω back-terminated to VCCO DOUT+ 11 CML out Noninverted data output. On-chip 50-Ω back-terminated to VCCO VCCO 12 Supply 3.3-V ±10% supply voltage for output stage COC1 14 Analog Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15). COC2 15 Analog Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
    
     SLLS604 − MARCH 2004 absolute maximum ratings over operating free-air temperature range unless otherwise noted† VALUE UNIT –0.3 to 4 V 0.5 to 4 V –0.3 to 4 V ±1 V VCC, VCCO VDIN+, VDIN− Supply voltage, See Note 1 VDISABLE, VOUTPOL, VDOUT+,VDOUT−, VCOC1, VCOC2+ Voltage at TH, DISABLE, OUTPOL, DOUT+, DOUT–, COC1, and COC2, See Note 1 VCOC_DIFF VDIN_DIFF Differential voltage between COC1 and COC2 IDIN+, IDIN−, IDOUT+, IDOUT– TJ(max) Continuous current at inputs and outputs Tstg TA Storage temperature range Characterized free-air operating temperature range −40 to 85 °C Voltage at DIN+, DIN–, See Note 1 Differential voltage between DIN+ and DIN– Maximum junction temperature ±2.5 V –25 to 25 mA 125 °C −65 to 85 °C TL Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network ground terminal. recommended operating conditions Supply voltage, VCC, VCCO Operating free-air temperature, TA MIN TYP MAX 3 3.3 3.6 V 85 °C −40 UNIT dc electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VCC,VCCO IVCC Supply voltage VOD Differential data output voltage swing RIN, ROUT Data input/output resistance VIN,MIN VIN,MAX Data input sensitivity Supply current MIN TYP MAX 3 3.3 3.6 V 22 28 mA 0.25 10 780 1200 mVp−p mVp−p DISABLE = low (excludes CML output current) DISABLE = high DISABLE = low 600 Single ended BER < 10–10 3 2.1 CMOS input low voltage 4 Power supply noise rejection 5 1200 CMOS input high voltage PSNR Ω 50 Data input overload POST OFFICE BOX 655303 26 • DALLAS, TEXAS 75265 mVp−p mVp−p V 0.6 f < 2 MHz UNIT V dB 
    
     SLLS604 − MARCH 2004 ac electrical characteristics over recommended operating conditions (unless otherwise noted) typical operating condition is at VCC = 3.3 V and TA = 25°C PARAMETER TEST CONDITIONS MIN COC = open COC = 2.2 nF Low frequency −3-dB bandwidth DJ MAX 45 70 2.5 Gb/s Input referred noise 300 Deterministic jitter, See Note 2 UNIT kHz 0.8 Data rate vNI TYP K28.5 pattern at 2.5 Gbps 223−1 PRBS equivalent pattern at 2.5 Gbps 8.5 25 9.3 30 223−1 PRBS equivalent pattern at 155 Mbps 25 50 Input = 5 mVpp 6.5 µVRMS psp−p RJ Random jitter tr tf Output rise time 20% to 80% 60 85 ps Output fall time 20% to 80% 60 85 ps Input = 10 mVpp psRMS 3 tDIS Disable response time NOTE 2: Deterministic jitter does not include pulse-width distortion due to residual small output offset voltage. 20 ns APPLICATION INFORMATION Figure 3 shows the ONET2511PA connected with an ac-coupled interface to the data signal source as well as to the output load. The ac-coupling capacitors C1 through C4 in the input and output data signal lines are the only required external components. In addition, an optional external filter capacitor (COC) may be used if a low cutoff frequency is desired. NC COC1 GND COC2 COC Optional VCC DIN+ DIN− ONET2501PA DOUT+ 16 Pin QFN DOUT− NC VCC OUTPOL NC C2 VCC C3 C4 DOUT+ DOUT− OUTPOL GND DIN− VCCO DISABLE DIN+ C1 DISABLE Figure 3. Basic Application Circuit With AC-Coupled I/Os POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2004, Texas Instruments Incorporated