ONET8551T
www.ti.com
SLLSEI5 – OCTOBER 2013
11.3-Gbps Limiting Transimpedance Amplifier With RSSI
Check for Samples: ONET8551T
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
9-GHz Bandwidth
10-kΩ Differential Small Signal
Transimpedance
–20-dBm Sensitivity
0.9-μARMS Input Referred Noise
2.5-mAp-p Input Overload Current
Received Signal Strength Indication (RSSI)
92-mW Typical Power Dissipation
CML Data Outputs With On-Chip 50-Ω BackTermination
On Chip Supply Filter Capacitor
Single +3.3-V Supply
Die Size: 870 μm x 1036 μm
10-G Ethernet
8-G and 10-G Fibre Channel
10-G EPON
SONET OC-192
6-G and 10-G CPRI and OBSAI
PIN and APD Preamplifier-Receivers
DESCRIPTION
The ONET8551T device is a high-speed, high-gain,
limiting transimpedance amplifier used in optical
receivers with data rates up to 11.3 Gbps. It features
low-input referred noise, 9-GHz bandwidth, 10-kΩ
small signal transimpedance, and a received signal
strength indicator (RSSI).
The ONET8551T device is available in die form,
includes an on-chip VCC bypass capacitor, and is
optimized for packaging in a TO can.
The ONET8551T device requires a single +3.3-V
supply. The power-efficient design typically dissipates
less than 95 mW. The device is characterized for
operation from –40°C to 100°C case (IC back-side)
temperature.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
ONET8551T
SLLSEI5 – OCTOBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
BW1
GND
BW0
GND
Bond Pad Assignment of ONET8551T
(TOP VIEW)
8551T
20 19 18 17
2
15
OUT±
GND
3
14
GND
VCC_OUT
4
13
RSSI_EB
VCC_IN
5
12
RSSI_IB
7
8
9
10 11
NC
6
GND
OUT+
FILTER2
GND
IN
16
FILTER1
1
GND
GND
Figure 1. The ONET8551T is available in die form. Bond pad locations are shown in this top view.
Table 1. BOND PAD DESCRIPTION
Pad
Symbol
1, 3, 6, 10, 14,
16, 18, 19
GND
Supply
Circuit ground. All GND pads are connected on die. Bonding all pads is optional. However,
for optimum performance, a good ground connection is mandatory.
2
OUT+
Analog output
Non-inverted CML data output; on-chip 50-Ω back-terminated to VCC
4
Type
VCC_OUT Supply
Description
2.8-V to 3.63-V supply voltage for AGC amplifier
5
VCC_IN
Supply
2.8-V to 3.63-V supply voltage for input TIA stage
7, 9
FILTER
Analog
Bias voltage for photodiode cathode
IN
Analog input
Data input to TIA (photodiode anode)
11
NC
No connect
Do not connect
12
RSSI_IB
Analog output
Analog output current is proportional to the input data amplitude. It indicates the strength of
the received signal (RSSI), if the photodiode is biased from the TIA. Connected to an external
resistor to ground (GND). For proper operation, ensure that the voltage at the RSSI pad does
not exceed VCC – 0.65 V. Leave this pad open if the RSSI feature is not used.
13
RSSI_EB
Analog output
Optional use when operated with external PD bias (e.g. APD). Analog output current
proportional to the input data amplitude. Indicates the strength of the received signal (RSSI).
Connected to an external resistor to ground (GND). For proper operation, ensure that the
voltage at the RSSI pad does not exceed VCC – 0.65 V. Leave this pad open if the RSSI
feature is not used.
15
OUT–
Analog output
Inverted CML data output; on-chip 50-Ω back-terminated to VCC.
17
BW1
Digital input
Bandwidth adjustment. Ground the pad to increase the bandwidth. Internally pulled-up to VCC
20
BW0
Digital input
Bandwidth adjustment. Ground the pad to increase the bandwidth. Internally pulled-up to VCC
Back-side of
die
GND
Supply
Conductive epoxy must be used to attach the die to ground.
8
2
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ONET8551T
ONET8551T
www.ti.com
SLLSEI5 – OCTOBER 2013
VCC_OUT
To voltage amplifier and output buffer
To TIA
VCC_IN
GND
FILTER 1
FILTER 2
RSSI_IB
AGC, RSSI,
and DC Offset
Cancellation
RF
Voltage
Amplifier
CML Output
Buffer
TIA
OUT+
IN
OUT±
RSSI_EB
BW0
BW1
Figure 2. Simplified Block Diagram of the ONET8551T Device
Figure 2 shows a simplified block diagram of the ONET8551T device.
The ONET8551T device consists of the signal path, supply filters, a control block for DC input bias, automatic
gain control (AGC), and received signal strength indication (RSSI). The RSSI provides the bias for the TIA stage
and the control for the AGC.
The signal path consists of a transimpedance amplifier stage, a voltage amplifier, and a CML output buffer. The
on-chip filter circuit provides a filtered VCC for the PIN photodiode and for the transimpedance amplifier.
The DC input bias circuit and automatic gain control use internal low pass filters to cancel the DC current on the
input and to adjust the transimpedance amplifier gain. Furthermore, circuitry is provided to monitor the received
signal strength.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ONET8551T
3
ONET8551T
SLLSEI5 – OCTOBER 2013
www.ti.com
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted) (1)
VALUE
UNIT
MIN
MAX
VCC_IN, VCC_OUT
Supply voltage (2)
–0.3
4.0
VBW0, VBW1,
VFILTER1, VFILTER2,
VOUT+, VOUT–,
VRSSI_IB, VRSSI_EB
Voltage at BW0, BW1, FILTER1, FILTER2, OUT+, OUT–, RSSI_IB, and
RSSI_EB (2)
–0.3
4.0
IIN
Current into IN
–0.7
4.0
IFILTER
Current into FILTER1 and FILTER2
–8
8
IOUT+, IOUT–
Continuous current at outputs
–8
8
ESD rating at all pins except input IN
ESD
ESD rating at input IN
TJ
(1)
(2)
2
V
mA
kV (HBM)
0.5
Maximum junction temperature
125
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
3.3
VCC
Supply voltage
2.80
TA
Operating back-side die temperature
–40
LFILTER, LIN
Wire-bond inductance at pins FILTERi and IN
0.3
CPD
Photodiode capacitance
0.2
(1)
4
MAX
UNIT
3.63
V
100 (1)
°C
0.5
nH
pF
105°C max junction temperature.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ONET8551T
ONET8551T
www.ti.com
SLLSEI5 – OCTOBER 2013
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions with BW0 = GND and BW1 = Open (unless otherwise noted). Typical values are at
VCC = +3.3 V and TA = 25°C.
PARAMETER
VCC
TEST CONDITIONS
Supply voltage
IVCC
Supply current
Input current IIN < 1000
μAP-P
IVCC
Supply current
Input current IIN < 2500
μAP-P
VIN
Input bias voltage
ROUT
Output resistance
VFILTER
Photodiode bias voltage (2)
ARSSI_IB
ARSSI_EB
(1)
(2)
(3)
Single-ended to VCC
RSSI gain internal bias
RSSI internal bias output offset current (no light)
RSSI gain external bias
RSSI external bias output offset current (no light)
Resistive load to GND (3)
Resistive load to GND (3)
MIN
TYP
MAX
UNIT
2.80
3.3
3.63
V
28
(1)
mA
45 (1)
mA
40
0.75
0.85
0.98
V
40
50
60
Ω
2.55
3.2
0.49
0.51
0.54
0
0.9
2.5
μA
0.63
A/A
V
0.46
A/A
μA
25
Including RSSI current
Regulated voltage typically 100 mV lower than VCC.
The RSSI output is a current output, which requires a resistive load to ground (GND). The voltage gain can be adjusted for the intended
application by choosing the external resistor. However, for proper operation, ensure that the voltage at RSSI does not exceed VCC –
0.65 V.
AC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions with BW0 = GND and BW1 = Open (unless otherwise noted). Typical values are at
VCC = +3.3 V and TA = 25°C.
PARAMETER
Z21
Small signal transimpedance
fHSS,
TEST CONDITIONS
Differential output; Input current iIN = 20 µAP-P
(1)
Small signal bandwidth
iIN = 20 µAP-P
fL,3dB
Low frequency –3-dB
bandwidth
16 µAP-P < iIN < 2000 µAP-P
iN,IN
Input referred RMS noise
SUS
Unstressed sensitivity
electrical
3dB
7
MAX
9
GHz
10-GHz bandwidth (2)
0.9
1.4
10.3125 Gbps, PRBS31 pattern, 1310 nm,
extinction ratio > 9 dB, BER 10-12
–20
25 µAP-P< iIN < 500 µAP-P (10.3125 Gbps, K28.5
pattern)
VOUT, D, MAX
Maximum differential output
voltage
Input current iIN = 500 µAP-P
PSNR
Power supply noise rejection
F < 10 MHz (3), supply filtering according to
SFF8431
500 µAP-P < iIN < 2500 µAP-P (10.3125 Gbps,
K28.5 pattern)
180
UNIT
Ω
150
Deterministic jitter
(2)
(3)
TYP
10000
30
DJ
(1)
MIN
7500
kHz
μA
dBm
6
15
10
24
300
420
–15
psP-P
mVP-P
dB
The small signal bandwidth is specified over process corners, temperature, and supply voltage variation. The assumed photodiode
capacitance is 0.2 pF and the bond-wire inductance is 0.3 nH. The small signal bandwidth strongly depends on environmental parasitics.
Careful attention to layout parasitics and external components is necessary to achieve optimal performance.
Input referred RMS noise is (RMS output noise) divided by (gain at 100 MHz).
PSNR is the differential output amplitude divided by the voltage ripple on supply. No input current at IN.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ONET8551T
5
ONET8551T
SLLSEI5 – OCTOBER 2013
www.ti.com
DETAILED DESCRIPTION
SIGNAL PATH
The first stage of the signal path is a transimpedance amplifier, which converts the photodiode current into a
voltage. If the input signal current exceeds a certain value, the transimpedance gain is reduced by a nonlinear
AGC circuit to limit the signal amplitude.
The second stage is a limiting voltage amplifier that provides additional limiting gain and converts the singleended input voltage into a differential data signal. The output stage provides CML outputs with an on-chip 50-Ω
back-termination to VCC.
FILTER CIRCUITRY
The FILTER pins provide a regulated and filtered VCC for a PIN photodiode bias. The supply voltages for the
transimpedance amplifier are filtered by on-chip capacitors, thus an external supply filter capacitor is not
necessary. The input stage has a separate VCC supply (VCC_IN), which is not connected on chip to the supply
of the limiting and CML stages (VCC_OUT).
AGC AND RSSI
The voltage drop across the regulated FILTER FET is monitored by the bias and RSSI control circuit block in the
case where a PIN diode is biased using the FILTER pins.
If the DC input current exceeds a certain level, then it is partially cancelled by a controlled current source. This
process keeps the transimpedance amplifier stage within sufficient operating limits for optimum performance.
The automatic gain control circuitry adjusts the voltage gain of the AGC amplifier to ensure limiting behavior of
the complete amplifier.
Finally this circuit block senses the current through the FILTER FET and generates a mirrored current that is
proportional to the input signal strength. The mirrored current is available at the RSSI_IB output and can be sunk
to GND using an external resistor. For proper operation, ensure that the voltage at the RSSI_IB pad does not
exceed VCC – 0.65 V.
If an APD or PIN photodiode is used with an external bias, then the RSSI_EB pin can be used. However, for
greater accuracy under external photodiode biasing conditions, TI recommends deriving the RSSI from the
external bias circuitry.
6
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ONET8551T
ONET8551T
www.ti.com
SLLSEI5 – OCTOBER 2013
APPLICATION INFORMATION
Figure 3 shows the ONET8551T device used in a typical fiber optic receiver with the internal photodiode bias.
The ONET8551T device converts the electrical current generated by the PIN photodiode into a differential output
voltage. The FILTER output provides a low-pass filtered DC bias voltage for the PIN. The photodiode must be
connected to the FILTER pad for the bias to function correctly, because the bias circuit senses and uses the
voltage drop across the FET.
The RSSI output is used to mirror the photodiode output current and can be connected via a resistor to GND.
The voltage gain can be adjusted for the intended application by choosing the external resistor. However, for
proper operation of the ONET8551T, ensure that the voltage at RSSI never exceeds VCC – 0.65 V. Leave the
RSSI output open, if the RSSI output is not used while operating with internal PD bias.
The OUT+ and OUT– pins are internally terminated by 50-Ω pullup resistors to VCC. The outputs must be AC
coupled, for example by using 0.1-μF capacitors, to the succeeding device.
For PIN diode applications, TI recommends grounding the BW0 pin. However, for higher bandwidth, the BW1
pin, or both the BW0 and BW1 pins, can be grounded. To reduce the bandwidth, the BW0 and BW1 pins can be
left open.
VCC_OUT
0.1 F
OUT+
0.1 F
OUT±
VCC_IN
RSSI
RRSSI
GND
Figure 3. Basic Application Circuit for PIN Receivers
Figure 4 shows the ONET8551T device used in a typical fiber-optic receiver using an external photodiode bias
for an avalanche photodiode. To increase the bandwidth using APDs, ground the BW0 and BW1 pins. This
configuration can also be used for a PIN diode. However, it may be beneficial to reduce the bandwidth, and
therefore the noise, by grounding only the BW0 pin. The external bias RSSI signal is based on the DC offset
value and is not as accurate as the internal bias RSSI, which is based on the photodiode current.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ONET8551T
7
ONET8551T
SLLSEI5 – OCTOBER 2013
www.ti.com
VCC_OUT
0.1 F
OUT+
0.1 F
OUT-
VCC_IN
V_BIAS
RSSI
RRSSI
GND
Figure 4. Basic Application Circuit for APD Receivers
DEVICE INFORMATION
ASSEMBLY RECOMMENDATIONS
Careful attention to assembly parasitics and external components is necessary to achieve optimal performance.
Recommendations that optimize performance include:
• Minimize the total capacitance on the IN pad by using a low capacitance photodiode and paying attention to
stray capacitances. Place the photodiode close to the ONET8551T die in order to minimize the bond wire
length, and thus the parasitic inductance.
• Use identical termination and symmetrical transmission lines at the AC coupled differential output pins, OUT+
and OUT–.
• Use short bond wire connections for the supply terminals VCC_IN, VCC_OUT, and GND. Supply voltage
filtering is provided on chip, but filtering may be improved by using an additional external capacitor.
• The die has back-side metal. Conductive epoxy must be used to attach the die to ground.
8
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ONET8551T
ONET8551T
www.ti.com
SLLSEI5 – OCTOBER 2013
CHIP DIMENSIONS AND PAD LOCATIONS
8551T
1036 m
20 19 18 17
1
16
2
15
3
14
4
13
5
12
y
6
7
8
9
10 11
870 m
x
Figure 5. Die Thickness: 203 ±13 μm, Pad Dimensions: 105 μm x 65 μm, and Die Size: 870 ±40 μm x 1036
±40 μm
PAD
COORDINATES (Referenced to Pad 1)
SYMBOL
TYPE
DESCRIPTION
x (μm)
y (μm)
1
0
0
GND
Supply
Circuit ground
2
0
–115
OUT+
Analog output
Non-inverted data output
3
0
–230
GND
Supply
Circuit ground
4
0
–460
VCC_OUT
Supply
3.3-V supply voltage
5
0
–575
VCC_IN
Supply
3.3-V supply voltage
6
116
–728
GND
Supply
Circuit ground
7
226
–728
FILTER1
Analog output
Bias voltage for photodiode
8
336
–728
IN
Analog input
Data input to TIA
9
446
–728
FILTER2
Analog output
Bias voltage for photodiode
10
556
–728
GND
Supply
Circuit ground
11
666
–728
NC
No connect
Do not connect
12
671
–575
RSSI_IB
Analog output
RSSI output signal for internally biased receivers
13
671
–460
RSSI_EB
Analog output
RSSI output signal for externally biased receivers
14
671
–230
GND
Supply
Circuit ground
15
671
–115
OUT–
Analog output
Inverted data output
16
671
0
GND
Supply
Circuit ground
17
508
109
BW1
Digital input
Bandwidth adjustment
18
393
109
GND
Supply
Circuit ground
19
278
109
GND
Supply
Circuit ground
20
163
109
BW0
Digital input
Bandwidth adjustment
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ONET8551T
9
ONET8551T
SLLSEI5 – OCTOBER 2013
www.ti.com
TO46 LAYOUT EXAMPLE
Figure 6 shows an example of a layout using a ground-signal-ground (GSG) type PIN photodiode in a 5-pin
TO46 can. Figure 7 shows an example of a PIN photodiode with two contacts on the top-side.
OUT+
OUT±
VCC
RSSI
Figure 6. TO46 5-Pin Layout Using the ONET8551T With a GSG PIN Diode
OUT+
OUT±
VCC
RSSI
Figure 7. TO46 5-Pin Layout Using the ONET8551T With a Two-Contact PIN Diode
10
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ONET8551T
ONET8551T
www.ti.com
SLLSEI5 – OCTOBER 2013
Figure 8 shows an example of a layout using an external bias voltage for the photodiode in a 5-pin TO46 can.
Figure 9 shows an example with a back-side cathode contact photodiode using the internal bias voltage.
OUT±
OUT+
Capacitor
Capacitor or
ceramic
substrate
VCC
VAPD
Capacitor
Figure 8. TO46 5-Pin Layout Using the ONET8551T With an Avalanche Photodiode
OUT±
OUT+
Capacitor
Backside
Cathode
Capacitor or
ceramic
substrate
VCC
RSSI
Figure 9. TO46 5-Pin Layout Using the Internal Bias Voltage for a Back-Side Cathode Contact
Photodiode
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ONET8551T
11
ONET8551T
SLLSEI5 – OCTOBER 2013
www.ti.com
TYPICAL OPERATION CHARACTERISTICS
Typical operating condition is at VCC = +3.3 V and TA = +25°C (unless otherwise noted).
SMALL SIGNAL TRANSIMPEDANCE
vs
AMBIENT TEMPERATURE
12.00
12000
10.00
10000
Transimpedance (:)
Transimpedance (k:)
TRANSIMPEDANCE
vs
INPUT CURRENT
8.00
6.00
4.00
2.00
8000
6000
4000
2000
0.00
0.00
0
200.00
400.00
600.00
800.00
1000.00
-40
-20
0
IIN (PAP-P)
20
40
60
80
100
80
100
Ambient Temperature (°C)
Figure 10.
Figure 11.
GAIN (dB)
vs
FREQUENCY (GHz)
SMALL SIGNAL BANDWIDTH
vs
AMBIENT TEMPERATURE
3
14
0
12
Bandwidth (GHz)
-3
Gain (dB)
-6
-9
-12
-15
10
8
6
4
-18
2
-21
-24
0.01
0
0.1
1
10
100
-40
-20
0
40
60
Ambient Temperature (°C)
Figure 13.
DIFFERENTIAL OUTPUT VOLTAGE
vs
INPUT CURRENT
DETERMINISTIC JITTER
vs
INPUT CURRENT
350
14
300
250
200
150
100
12
10
8
6
4
2
50
0
0.00
0
100.00
200.00
300.00
400.00
500.00
0
200
400
600
800
1000 1200 1400 1600 1800 2000
Input Current (PAP-P)
IIN (PAP-P)
Figure 14.
12
20
Figure 12. Small Signal Transfer Characteristics
Deterministic Jitter (ps)
Differential Output Voltage (mVP-P)
Frequency (GHz)
Figure 15.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ONET8551T
ONET8551T
www.ti.com
SLLSEI5 – OCTOBER 2013
TYPICAL OPERATION CHARACTERISTICS (continued)
Typical operating condition is at VCC = +3.3 V and TA = +25°C (unless otherwise noted).
INPUT REFERRED NOISE
vs
TEMPERATURE
RSSI_IB OUTPUT CURRENT
vs
AVERAGE INPUT CURRENT
1000
RSSI_IB Output Current (PA)
Input Referred Noise (PArms)
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
900
800
700
600
500
400
300
200
100
0
0.00
-40
-20
0
20
40
60
80
100
0
200
400
600
800
1000
1200
Ambient Temperature (°C)
Average Input Current (PAP-P)
Figure 16.
Figure 17.
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
AND 20 µAP-P INPUT CURRENT
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
AND 100 µAP-P INPUT CURRENT
16.8 ps/Div
100 mV/Div
100 mV/Div
16.8 ps/Div
Figure 18.
Figure 19.
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
AND 500 µAP-P INPUT CURRENT
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
AND 2 mAP-P INPUT CURRENT
100 mV/Div
16.8 ps/Div
16.8 ps/Div
100 mV/Div
Figure 20.
1400
Figure 21.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ONET8551T
13
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ONET8551TY
ACTIVE
DIESALE
Y
0
1800
TBD
Call TI
Call TI
-40 to 100
ONET8551TYS4
ACTIVE
WAFERSALE
YS
0
1
TBD
Call TI
Call TI
-40 to 100
ONET8551TYS9
ACTIVE
WAFERSALE
YS
0
1
TBD
Call TI
Call TI
-40 to 100
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
