OP07, OP07C, OP07D
SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023
OP07x Precision Operational Amplifiers
1 Features
3 Description
•
•
•
•
The OP07C and OP07D (OP07x) devices offer low
offset and long-term stability by means of a lownoise, chopperless, bipolar‑input‑transistor amplifier
circuit. For most applications, external components
are not required for offset nulling and frequency
compensation. The true differential input, with a
wide input-voltage range and outstanding commonmode rejection, provides maximum flexibility and
performance in high-noise environments and in
noninverting applications. Low bias currents and
extremely high input impedances are maintained over
the entire temperature range.
•
Low noise
No external components required
Replace chopper amplifiers at a lower cost
Wide input-voltage range:
0 V to ±14 V (typ, ±15-V supply)
Wide supply-voltage range: ±3 V to ±18 V
2 Applications
•
•
•
•
•
Analog input module
Battery test
Lab and field instrumentation
Temperature transmitter
Merchant network & server PSU
For improved performance and wider temperature
range, see the next generation OPA207 with low
power, and OPA202 with heavy capacitive load drive
capability.
Package Information
PART NUMBER
OP07C, OP07D
(1)
OFFSET N1
IN+
PACKAGE(1)
BODY SIZE (NOM)
D (SOIC, 8)
4.90 mm × 3.91 mm
P (PDIP, 8)
9.81 mm × 6.35 mm
PS (SO, 8)
6.20 mm × 5.30 mm
For all available packages and the OP07, see the orderable
addendum at the end of the data sheet.
1
3
+
6
OUT
IN−
OFFSET N2
2
−
8
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OP07, OP07C, OP07D
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SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 6
7 Detailed Description........................................................7
7.1 Overview..................................................................... 7
7.2 Functional Block Diagram........................................... 7
7.3 Feature Description.....................................................7
7.4 Device Functional Modes............................................7
8 Application and Implementation.................................... 8
8.1 Application Information............................................... 8
8.2 Typical Application...................................................... 8
8.3 Power Supply Recommendations...............................9
8.4 Layout....................................................................... 10
9 Device and Documentation Support............................11
9.1 Receiving Notification of Documentation Updates.... 11
9.2 Support Resources................................................... 11
9.3 Trademarks............................................................... 11
9.4 Electrostatic Discharge Caution................................ 11
9.5 Glossary.................................................................... 11
10 Mechanical, Packaging, and Orderable
Information.................................................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (November 2014) to Revision H (July 2022)
Page
• Added supply condition to wide input voltage range feature bullet.....................................................................1
• Changed VCC+ to V+ and VCC− to V−...............................................................................................................3
• Changed supply voltage abbreviation from VCC+ and VCC– to VS in Absolute Maximum Ratings and
throughout the data sheet...................................................................................................................................4
• Changed note 5 in Absolute Maximum Ratings to include a note that fast-ramping shorts to the positive
supply can damage the device........................................................................................................................... 4
• Changed Electrostatic discharge Human-body model and Charged-device model from 1000 V to ±1000 V.... 4
• Added new values to Thermal Information ........................................................................................................ 4
• Changed Electrical Characteristics format .........................................................................................................5
• Changed parameter name from supply-voltage sensitivity to power supply rejection ratio in Electrical
Characteristics ................................................................................................................................................... 5
• Changed parameter name from input offset voltage to Input voltage noise density in Electrical Characteristics
............................................................................................................................................................................5
• Changed input current noise density unit from nV/√Hz to pA/√Hz in Electrical Characteristics ........................ 5
• Changed parameter name from large-signal differential voltage gain to open-loop voltage gain in Electrical
Characteristics ................................................................................................................................................... 5
• Changed parameter name from peak output voltage to voltage output swing in Electrical Characteristics....... 5
• Changed functional block diagram..................................................................................................................... 7
• Changed text to clarify how to adjust input mismatches using null pins in Application Information ...................8
Changes from Revision F (January 2014) to Revision G (November 2014)
Page
• Added Applications, Device Information table, Pin Functions table, Handling Ratings table, Thermal
Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
Changes from Revision E (May 2004) to Revision F (January 2014)
Page
• Deleted Ordering Information table.....................................................................................................................1
2
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SLOS099H – SEPTEMBER 1983 – REVISED MARCH 2023
5 Pin Configuration and Functions
OFFSET N1
1
IN–
2
IN+
3
V–
4
8
OFFSET N2
–
7
V+
+
6
OUT
5
NC
Not to scale
Figure 5-1. D Package, 8-Pin SOIC,
P Package, 8-Pin PDIP,
and PS Package, 8-Pin SO
(Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
IN+
3
Input
Noninverting input
IN–
2
Input
Inverting input
NC
5
—
Do not connect
OFFSET N1
1
Input
External input offset voltage adjustment
OFFSET N2
8
Input
External input offset voltage adjustment
OUT
6
Output
V+
7
—
Positive supply
V–
4
—
Negative supply
Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage(2)
VS
MAX
Single supply
Input voltage
UNIT
44
Dual supply
±22
Differential(3)
±30
Single-ended(4)
±22
Output short-circuit(5)
V
V
Continous
TJ
Operating junction temperature
–55
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values, unless otherwise noted, are with respect to the midpoint between V+ and V−.
Differential voltages are at IN+ with respect to IN−.
The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
The output can be shorted to ground or to the negative power supply. Fast ramping shorts to the positive supply can cause permanent
damage and eventual destruction.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Single supply
VS
Supply voltage
VCM
Common-mode input voltage
TA
Operating ambient temperature
NOM
MAX
UNIT
6
36
Dual supply
±3
±18
VS = ±15 V
–13
13
V
0
70
°C
V
6.4 Thermal Information
OP07x
THERMAL METRIC(1)
P (PDIP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
127.6
85
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
67.1
68.6
°C/W
RθJB
Junction-to-board thermal resistance
71.4
55..6
°C/W
ψJT
Junction-to-top characterization parameter
18.7
38.3
°C/W
ψJB
Junction-to-board characterization parameter
70.6
55.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
4
D (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = 25°C, VS = ±15 V, RL = 2 kΩ connected to mid-supply, and VCM = VOUT = mid-supply (unless otherwise noted)(1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±60
OP07C
VOS
TA = 0°C to 70°C
Input offset voltage
±150
OP07D
dVOS/dT
Input offset voltage drift
±85
TA = 0°C to 70°C
TA = 0°C to 70°C
±250
OP07C
±0.5
OP07D
±2.5
Long-term drift of input
offset voltage(2)
PSRR
±0.4
Offset adjustment range
Rs = 20 kΩ, see Section 8.1
Power supply rejection
ratio
VS = ±3 V to ±18 V
μV
µV/mo
±4
TA = 0°C to 70°C
μV/°C
mV
7
32
10
51
μV/V
INPUT BIAS CURRENT
±1.8
OP07C
IB
TA = 0°C to 70°C
Input bias current
±12
OP07D
Input bias current drift
TA = 0°C to 70°C
±18
OP07D
±50
pA/°C
±0.8
TA = 0°C to 70°C
Input offset current
±1.6
±6
OP07D
Input offset current drift
nA
±14
OP07C
OP07C
IOS
±2.2
TA = 0°C to 70°C
nA
±8
OP07C
12
OP07D
±50
pA/°C
NOISE
Input voltage noise
eN
f = 0.1 Hz to 10 Hz
0.38
f = 10 Hz
10.5
Input voltage noise density f = 100 Hz
Input current noise
10.2
f = 1 kHz
9.8
f = 0.1 Hz to 10 Hz
15
f = 10 Hz
iN
μVPP
nV/√Hz
pApp
0.35
Input current noise density f = 100 Hz
0.15
f = 1 kHz
pA/√Hz
0.13
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
CMRR
Common-mode rejection
ratio
TA = 0°C to 70°C
OP07C
VCM = ±13 V
OP07D
VCM = ±13 V
TA = 0°C to 70°C
TA = 0°C to 70°C
±13
±14
±13
±13.5
100
120
97
120
94
110
94
106
7
33
100
400
V
dB
INPUT CAPACITANCE
rI
Input resistance
MΩ
OPEN-LOOP GAIN
1.4 V < VO < 11.4 V,
RL = 500 kΩ
AOL
OP07C
OP07D
Open-loop voltage gain
VO = ±10 V
TA = –40°C to
+125°C
400
120
400
100
400
V/mV
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6.5 Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 2 kΩ connected to mid-supply, and VCM = VOUT = mid-supply (unless otherwise noted)(1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.4
0.6
MHz
0.3
V/μs
FREQUENCY RESPONSE
Unity gain bandwidth
SR
Slew rate
VS = 5 V, RL = 2 kΩ
OUTPUT
Voltage output swing
±11.5
±12.8
TA = 0°C to 70°C
±11
±12.6
RL = 10 kΩ
±12
±13
RL = 1 kΩ
V
±12
POWER SUPPLY
PD
(1)
(2)
Power dissipation
No load
VS = ±3 V, no load
80
150
4
8
mW
The specifications listed in the Electrical Characteristics apply to OP07C and OP07D.
Because long-term drift cannot be measured on the individual devices before shipment, this specification is not intended to be a
warranty. This specification is an engineering estimate of the averaged trend line of drift versus time over extended periods after the
first 30 days of operation.
6.6 Typical Characteristics
Input Offset Voltage (µV)
200
150
Low
Mean
High
100
50
0
–50
–50
0
50
Temperature (ºC)
100
150
Figure 6-1. Input-Offset Voltage vs Temperature
6
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7 Detailed Description
7.1 Overview
These devices offer low offset and long-term stability by means of a low-noise, chopperless, bipolar-inputtransistor amplifier circuit. For most applications, external components are not required for offset nulling and
frequency compensation. The true differential input, with a wide input-voltage range and outstanding commonmode rejection, provides maximum flexibility and performance in high-noise environments and in noninverting
applications. Low bias currents and extremely high input impedances are maintained over the entire temperature
range.
These devices are characterized for operation from 0°C to 70°C.
7.2 Functional Block Diagram
V+
OFFSET N1
OFFSET N2
Input Bias
Cancellation
Second Stage
Amplifier and
Biasing
OUT
IN+
IN
V
7.3 Feature Description
7.3.1 Offset-Voltage Null Capability
The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, currentgain betas (β), collector or emitter resistors, and so on. The input offset pins allow the designer to adjust for
these mismatches by external circuitry. See Section 8 for more details on design techniques.
7.3.2 Slew Rate
The slew rate is the rate at which an operational amplifier can change the output when there is a change on the
input. The OP07x have a 0.3-V/μs slew rate.
7.4 Device Functional Modes
The OP07x are powered on when the supply is connected. The devices can be operated as single-supply
operational amplifiers or dual-supply amplifiers, depending on the application.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, currentgain betas (β), collector or emitter resistors, and so on. The input offset pins allow the designer to adjust for
these mismatches with external circuitry. Figure 8-1 shows how these input mismatches can be adjusted by
putting resistors or a potentiometer between the null pins. Use a potentiometer to fine tune the circuit during
testing or for applications that require precision offset control. For more information about designing using the
input-offset pins, see the Nulling Input Offset Voltage of Operational Amplifiers application report.
20 kΩ
V+
OFFSET
N2
OFFSET N1
1
IN+
IN
3
+
2
–
8
7
6
OUT
4
V
Figure 8-1. Input Offset-Voltage Null Circuit
8.2 Typical Application
The voltage follower configuration of the operational amplifier is used for applications where a weak signal is
used to drive a relatively high current load. This circuit is also called a buffer amplifier or unity gain amplifier. The
inputs of an operational amplifier have a very high resistance that puts a negligible current load on the voltage
source. The output resistance of the operational amplifier is almost negligible, so the amplifier can provide as
much current as necessary to the output load.
10 k
12 V
VOUT
+
VIN
Figure 8-2. Voltage Follower Schematic
8.2.1 Design Requirements
•
•
Output range of 2 V to 11 V
Input range of 2 V to 11 V
8
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Swing
The output voltage of an operational amplifier is limited by the internal circuitry to some level less than the supply
rails. For this amplifier, the output voltage swing is within ±12 V, which accommodates the input and output
voltage requirements.
8.2.2.2 Supply and Input Voltage
For correct operation of the amplifier, neither input must be higher than the recommended positive supply rail
voltage or lower than the recommended negative supply rail voltage. The chosen amplifier must be able to
operate at the supply voltage that accommodates the inputs. Because the input for this application goes up to
11 V, the supply voltage must be 12 V. Using a negative voltage on the lower rail, rather than ground, allows the
amplifier to maintain linearity for inputs below 2 V.
8.2.3 Application Curves
12
0.4
10
0.3
0.2
IIO (mA)
VOUT (V)
8
6
0.1
0.0
4
±0.1
2
±0.2
0
±0.3
0
2
4
6
8
10
0
12
VIN (V)
2
4
6
8
VIN (V)
C001
Figure 8-3. Output Voltage vs Input Voltage
10
12
C002
Figure 8-4. Current Drawn by the Input of the
Voltage Follower (IIO) vs Input Voltage
3.0
2.5
ICC (mA)
2.0
1.5
1.0
0.5
0.0
0
2
4
6
8
10
VIN (V)
12
C003
Figure 8-5. Current Drawn from Supply (ICC) vs Input Voltage
8.3 Power Supply Recommendations
The OP07x operate from ±3 V to ±18 V supplies; many specifications apply from 0°C to 70°C.
CAUTION
Supply voltages larger than ±22 V can permanently damage the device. See also Section 6.1.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more details on bypass capacitor placement, see Section 8.4.1.
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8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
•
•
•
•
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. On multilayer PCBs, one or more layers are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.
If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicularly, as
opposed to in parallel, with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Section 8.4.2.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
8.4.2 Layout Example
RIN
VIN
+
VOUT
RG
RF
Figure 8-6. Operational Amplifier Schematic for Noninverting Configuration
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
RF
OFFSET N2
OFFSET N1
VS+
Use low-ESR, ceramic
bypass capacitor
RG
GND
VIN
IN−
V+
IN+
OUT
V−
NC
RIN
GND
Only needed for
dual-supply
operation
GND
VS-
VOUT
(or GND for single supply)
Ground (GND) plane on another layer
Figure 8-7. Operational Amplifier Board Layout for Noninverting Configuration
10
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9 Device and Documentation Support
9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
OP-07DP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
OP-07DP
Samples
OP-07DPS
ACTIVE
SO
PS
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
OP-07D
Samples
OP-07DPSR
ACTIVE
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
OP-07D
Samples
OP-07DPSRG4
ACTIVE
SO
PS
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
OP-07D
Samples
OP07-W
ACTIVE
WAFERSALE
YS
0
3603
TBD
Call TI
Call TI
OP07CD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
OP07C
Samples
OP07CDE4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
OP07C
Samples
OP07CDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
OP07C
Samples
OP07CDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
0 to 70
OP07C
Samples
OP07CDRE4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
OP07C
Samples
OP07CDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
OP07C
Samples
OP07CP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
OP07CP
Samples
OP07CPE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
OP07CP
Samples
OP07DD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
OP07D
Samples
OP07DDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
OP07D
Samples
OP07DDRE4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
OP07D
Samples
OP07DP
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
OP07DP
Samples
OP07DPE4
ACTIVE
PDIP
P
8
50
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
OP07DP
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2022
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
