OP07EP

OP-07 Low Offset, Low Drift Operational Amplifier General Description Features The OP-07 has very low input offset voltage which is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP-07 also features low input bias current and high openloop gain. The low offsets and high open-loop gain make the OP-07 particularly useful for high-gain applications. The wide input voltage range of g 13V minimum combined with high CMRR of 110 dB and high input impedance provide high accuracy in the non-inverting circuit configuration. Excellent linearity and gain accuracy can be maintained even at high closed-loop gains. Stability of offsets and gain with time or variation in temperature is excellent. The OP-07 is available in TO-99 metal can, ceramic or molded DIP. For improved specifications, see the LM607. Y Y Y Y Y Y Y Y Low VOS 75 mV Max Low VOS Drift 0.6 mV/§ C Max Ultra-Stable vs Time 1.0 mV/Month Max Low Noise 0.6 mVp-p Max g 14V Wide Input Voltage Range g 3V to g 18V Wide Supply Voltage Range Fits 725/108A/308A, 741, AD510 Sockets Replaces the mA714 Applications Y Y et Y Strain Gauge Amplifiers Thermocouple Amplifiers Precision Reference Buffer Analog Computing Functions e Y Connection Diagram bs ol Dual-In-Line Package TL/H/10550 – 1 See NS Package Number N08E Ordering Information O TA e 25§ C VOSMax (mV) N08E Plastic Operating Temperature Range 75 OP07EP COM 150 OP07CP COM 150 OP07DP COM *Also available per SMD Ý8203602 C1995 National Semiconductor Corporation TL/H/10550 RRD-B30M115/Printed in U. S. A. OP-07 Low Offset, Low Drift Operational Amplifier December 1994 Absolute Maximum Ratings Storage Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Junction Temperature g 22V Internal Power Dissipation (Note 5) Differential Input Voltage Input Voltage (Note 6) Output Short-Circuit Duration b 65§ C to a 150§ C Lead Temperature (Soldering, 60 sec.) 260§ C b 65§ C to a 150§ C Operating Temperature Range 500 mW g 30V g 22V Continuous OP-07E, OP-07C, OP-07D 0§ C to a 70§ C bs ol et e Simplified Schematic O *R2A and R2B are electronically trimmed on chip at the factory for minimum offset voltage. 2 TL/H/10550 – 3 Electrical Characteristics Unless otherwise specified, VS e g 15V, TA e 25§ C. Boldface type refers to limits over 0§ C s TA s 70§ C Symbol Parameter OP-07E Conditions Min VOS Input Offset Voltage (Note 1) VOS/t Long-Term VOS Stability (Note 2) IOS Input Offset Current IB Input Bias Current OP-07C Typ Max 30 45 Min Units Typ Max 75 130 60 85 150 250 mV 0.3 1.5 0.4 2.0 mV/Mo 0.5 0.9 3.8 5.3 0.8 1.6 6.0 8.0 nA g 1.2 g 4.0 g 1.8 g 7.0 g 1.5 g 5.5 g 2.2 g 9.0 nA Input Noise Voltage 0.1 Hz to 10 Hz (Note 3) 0.35 0.6 0.38 0.65 mVp-p en Input Noise Voltage Density fO e 10 Hz fO e 100 Hz (Note 3) fO e 1000 Hz 10.3 10.0 9.6 18.0 13.0 11.0 10.5 10.2 9.8 20.0 13.5 11.5 nV/0Hz inp-p Input Noise Current 0.1 Hz to 10 Hz (Note 3) in Input Noise Current Density fO e 10 Hz fO e 100 Hz (Note 3) fO e 1000 Hz RIN Input Resistance Differential-Mode (Note 4) RINCM Input Resistance Common-Mode IVR Input Voltage Range PSRR AVO VO SR 30 15 35 pAp-p 0.80 0.23 0.17 0.35 0.15 0.13 0.90 0.27 0.18 pA/0Hz et 14 0.32 0.14 0.12 15 50 8 160 Common-Mode Rejection Ratio VCM e g 13V Power Supply Rejection Ratio VS e g 3V to g 18V VS e g 3V to g 18V Large Signal Voltage Gain RL t 2 kX, VO e g 10V RL t 2 kX RL t 500X, VO e g 0.5V, VS e g 3V (Note 4) Output Voltage Swing RL t 10 kX RL t 2 kX RL t 2 kX RL t 1 kX 33 MX 120 GX g 13.0 g 14.0 g 13 g 14 V 106 103 123 123 100 97 120 120 dB bs ol CMRR e enp-p 5 7 20 32 7 10 200 180 500 450 120 100 400 400 150 400 100 400 g 12.5 g 13.0 g 12.0 g 13.0 g 12.0 g 12.8 g 11.5 g 12.8 g 12.0 g 12.6 g 11.0 g 12.6 g 10.5 g 12.0 32 51 mV/V V/mV V g 12.0 Slew Rate RL t 2 kX (Note 3) 0.1 0.3 0.1 0.3 V/ms Closed-Loop Bandwidth AVCL e a 1 (Note 3) 0.4 0.6 0.4 0.6 MHz RO Output Resistance VO e 0, IO e 0 60 Pd Power Consumption VS e g 15V, No Load VS e g 3V, No Load 75 4 O BW 60 120 6 80 4 X 150 8 Offset Adj. Range RP e 20 kX g4 Average Input Offset Voltage Drift Without External Trim With External Trim (Note 4) 0.3 1.3 0.5 1.8 RP e 20 kX (Note 4) 0.3 1.3 0.4 1.6 TCIOS Average Input Offset Current Drift (Note 3) 8 35 12 50 pA/§ C TCIB Average Input Bias Current Drift (Note 3) 13 35 18 50 pA/§ C TCVOS TCVOSn g4 mW mV mV/§ C 3 Electrical Characteristics Unless otherwise specified, VS e g 15V, TA e 25§ C. Boldface type refers to limits over 0§ C s TA s a 70§ C Symbol Parameter OP-07D Conditions Min Units Typ Max VOS Input Offset Voltage (Note 1) 60 85 150 250 mV VOS/t Long-Term VOS Stability (Note 2) 0.5 3.0 mV/Mo IOS Input Offset Current 0.8 1.6 6.0 8.0 nA IB Input Bias Current en 0.1 Hz to 10 Hz (Note 3) 0.38 0.65 mVp-p Input Noise Voltage Density fO e 10 Hz fO e 100 Hz (Note 3) fO e 1000 Hz 10.5 10.3 9.8 20.0 13.5 11.5 nV/0Hz 15 35 pAp-p Input Noise Current 0.1 Hz to 10 Hz (Note 3) in Input Noise Current Density fO e 10 Hz fO e 100 Hz (Note 3) fO e 1000 Hz RIN Input Resistance Differential-Mode (Note 4) RINCM Input Resistance Common-Mode IVR Input Voltage Range PSRR Power Supply Rejection Ratio VS e g 3V to g 18V Large Signal Voltage Gain RL s 2 kX, VO e g 10V RL e 2 kX, VO e g 10V RL t 500X, VO e g 0.5V, VS g 3V (Note 4) BW RO 31 MX GX g 13 g 14 V 94 94 110 106 dB 7 10 RL t 10 kX RL t 2 kX RL t 2 kX RL t 1 kX 120 100 32 51 400 400 mV/V V/mV 400 g 12.0 g 13.0 g 11.5 g 12.8 g 11.0 g 12.6 V g 12.0 Slew Rate RL t 2 kX (Note 3) 0.1 0.3 V/ms Closed-Loop Bandwidth AVCL e a 1 (Note 3) 0.4 0.6 MHz Output Resistance VO e 0, IO e 0 60 Power Consumption VS e g 15V, No Load VS e g 3V, No Load 80 4 O Pd pA/0Hz et Common-Mode Rejection Ratio Output Voltage Swing 0.90 0.27 0.18 120 bs ol CMRR SR 0.35 0.15 0.13 7 VCM e g 13V VO nA Input Noise Voltage inp-p AVO g 12.0 g 14.0 e enp-p g 2.0 g 3.0 X 150 8 mW Offset Adj. Range RP e 20 kX g4 (Note 4) 0.7 2.5 mV/§ C TCVOSn Average Input Offset Voltage Drift Without External Trim With External Trim RP e 20 kX (Note 4) 0.7 2.5 mV/§ C TCIOS Average Input Offset Current Drift (Note 3) 12 50 pA/§ C TCIB Average Input Bias Current Drift (Note 3) 18 50 pA/§ C TCVOS mV Note 1: VOS is measured approximately 0.5 second after application of power. Note 2: Long-Term Offset Voltage Stability refers to the averaged trend line of VOS vs Time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 mV. Parameter is sample tested. Note 3: Sample Tested. Note 4: Guaranteed by design. 4 Test Circuits Offset Voltage Test Circuit Low Frequency Noise Test Circuit TL/H/10550 – 4 TL/H/10550 – 5 e Optional Offset Nulling Circuit O bs ol et TL/H/10550 – 6 5 e et Order Number OP-07EP, OP-07CP or OP-07DP NS Package Number N08E bs ol OP-07 Low Offset, Low Drift Operational Amplifier Physical Dimensions inches (millimeters) (Continued) LIFE SUPPORT POLICY O NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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