OPA121KM

® OPA121 Low Cost Precision Difet ® OPERATIONAL AMPLIFIER FEATURES q LOW NOISE: 6nV/√Hz typ at 10kHz q LOW BIAS CURRENT: 5pA max q LOW OFFSET: 2mV max q LOW DRIFT: 3µV/°C typ q HIGH OPEN-LOOP GAIN: 110dB min q HIGH COMMON-MODE REJECTION: 86dB min APPLICATIONS q OPTOELECTRONICS q DATA ACQUISITION q TEST EQUIPMENT q MEDICAL EQUIPMENT q RADIATION HARD EQUIPMENT DESCRIPTION The OPA121 is a precision monolithic dielectricallyisolated FET (Difet ®) operational amplifier. Outstanding performance characteristics are now available for low-cost applications. Noise, bias current, voltage offset, drift, open-loop gain, common-mode rejection, and power supply rejection are superior to BIFET® amplifiers. Very low bias current is obtained by dielectric isolation with on-chip guarding. Laser-trimming of thin-film resistors gives very low offset and drift. Extremely low noise is achieved with new circuit design techniques (patented). A new cascode design allows high precision input specifications and reduced susceptibility to flicker noise. Standard 741 pin configuration allows upgrading of existing designs to higher performance levels. Case (TO-99) and Substrate 8 7 +VCC –In 2 3 +In Noise-Free Cascode* 6 Output Trim 10kΩ 1 5 Trim 10kΩ 2k Ω 2k Ω 2k Ω 2k Ω 4 *Patented OPA121 Simplified Circuit –VCC Difet ®, Burr-Brown Corp. BIFET®, National Semiconductor Corp. International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1984 Burr-Brown Corporation • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-539F Printed in U.S.A. September, 1993 SPECIFICATIONS ELECTRICAL At VCC = ±15VDC and TA = +25°C unless otherwise noted. Pin 8 connected to ground. OPA121KM PARAMETER INPUT NOISE Voltage, fO = 10Hz fO = 100Hz fO = 1kHz fO = 10kHz fB = 10Hz to 10kHz fB = 0.1Hz to 10 Hz Current, fB = 0.1Hz to 10Hz fO = 0.1Hz thru 20kHz OFFSET Input Offset Voltage Average Drift Supply Rejection BIAS CURRENT(2) Input Bias Current OFFSET CURRENT(2) Input Offset Current IMPEDANCE Differential Common-Mode VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection OPEN-LOOP GAIN, DC Open-Loop Voltage Gain FREQUENCY RESPONSE Unity Gain, Small Signal Full Power Response Slew Rate Settling Time, 0.1% 0.01% Overload Recovery, 50% Overdrive(3) RATED OUTPUT Voltage Output Current Output Output Resistance Load Capacitance Stability Short Circuit Current POWER SUPPLY Rated Voltage Voltage Range, Derated Performance Current, Quiescent TEMPERATURE RANGE Specification Operating Storage θ Junction-Ambient ±10 86 110 VOLTAGE(2) VCM = 0VDC TA = TMIN to TMAX 86 ±0.5 ±3 104 ±6 ±1 ±2 ±10 86 ±50 ±5 ±0.5 ±3 104 ±6 ±1 ±3 ±10 ±50 ±10 mV µV/°C dB µV/V pA CONDITIONS MIN TYP MAX MIN OPA121KP, KU TYP MAX UNITS (1) (1) (1) (1) (1) (1) (1) (1) 40 15 8 6 0.7 1.6 15 0.8 50 18 10 7 0.8 2 21 1.1 nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms µVp-p fA, p-p fA/√Hz VCM = 0VDC Device Operating VCM = 0VDC Device Operating ±0.7 ±4 ±0.7 ±8 pA 1013 || 1 1014 || 3 ±11 104 120 2 32 2 6 10 5 ±11 ±5.5 ±12 ±10 100 1000 40 ±15 ±5 IO = 0mADC Ambient Temperature Ambient Temperature Ambient Temperature 0 –40 –65 200 2.5 ±18 4 +70 +85 +150 ±5 ±11 ±5.5 ±10 82 106 1013 || 1 1014 || 3 ±11 100 114 2 32 2 6 10 5 ±12 ±10 100 1000 40 ±15 ±18 4.5 +70 +85 +125 150(4) Ω || pF Ω || pF V dB dB MHz kHz V/µs µs µs µs V mA Ω pF mA VDC VDC mA °C °C °C °C/W VIN = ±10VDC RL ≥ 2kΩ 20Vp-p, RL = 2kΩ VO = ±10V, RL = 2kΩ Gain = –1, RL = 2kΩ 10V Step Gain = –1 RL = 2kΩ VO = ±10VDC DC, Open Loop Gain = +1 10 10 2.5 0 –25 –55 NOTES: (1) Sample tested. (2) Offset voltage, offset current, and bias current are specified with the units fully warmed up. (3) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. (4) 100°C/W for KU grade. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA121 2 ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) At VCC = ±15VDC and TA = TMIN to TMAX unless otherwise noted. OPA121KM PARAMETER TEMPERATURE RANGE Specification Range INPUT OFFSET VOLTAGE(1) Input Offset Voltage Average Drift Supply Rejection BIAS CURRENT(1) Input Bias Current OFFSET CURRENT(1) Input Offset Current VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection OPEN-LOOP GAIN, DC Open-Loop Voltage Gain RATED OUTPUT Voltage Output Current Output Short Circuit Current POWER SUPPLY Current, Quiescent CONDITIONS Ambient Temperature MIN 0 TYP MAX +70 MIN 0 OPA121KP, KU TYP MAX +70 UNITS °C VCM = 0VDC 82 ±1 ±3 94 ±20 ±23 ±3 ±10 82 ±80 ±115 ±1 ±3 94 ±20 ±23 ±5 ±10 ±80 ±250 mV µV/°C dB µV/V pA VCM = 0VDC Device Operating VCM = 0VDC Device Operating ±10 82 106 ±10.5 ±5.25 10 ±16 ±100 ±16 ±200 pA VIN = ±10VDC RL ≥ 2kΩ RL = 2kΩ VO = ±10VDC VO = 0VDC IO = 0mADC ±11 98 116 ±11 ±10 40 2.5 4.5 ±10 80 100 ±10.5 ±5.25 10 ±11 96 110 ±11 ±10 40 2.5 5 V dB dB V mA mA mA NOTE: (1) Offset voltage, offset current, and bias current are measured with the units fully warmed up. ABSOLUTE MAXIMUM RATINGS Supply ........................................................................................... ±18VDC Internal Power Dissipation(1) ......................................................... 500mW Differential Input Voltage ............................................................... ±36VDC Input Voltage Range ..................................................................... ±18VDC Storage Temperature Range M package .................................................................... –65°C to +150°C P, U packages ............................................................... –55°C to +125°C Operating Temperature Range M package ...................................................................... –40°C to +85°C P, U packages ................................................................. –25°C to +85°C Lead Temperature M, P packages (soldering, 10s) ................................................... +300°C U package (soldering, 3s) ........................................................... +260°C Output Short-Circuit Duration(2) ............................................... Continuous Junction Temperature .................................................................... +175°C NOTES: (1) Packages must be derated based on θJA = 150° C/W (P package); θJA = 200°C/W (M package); θJA = 100°C/W (U package). (2) Short circuit may be to power supply common only. Rating applies to +25°C ambient. Observe dissipation limit and TJ. CONNECTION DIAGRAMS Top View M-Package TO-99 (Hermetic) Substrate and Case Offset Trim 1 –In 2 8 7 +VCC OPA121 6 Output +In 3 4 –V CC 5 Offset Trim Top View P-Package Plastic Mini-DIP U-Package Plastic SOIC PACKAGE INFORMATION MODEL OPA121KM OPA121KP OPA121KU PACKAGE TO-99 8-Pin Plastic DIP 8-Pin SOIC PACKAGE DRAWING NUMBER(1) 001 006 182 Offset Trim –In +In –V CC 1 2 OPA121 3 4 8 7 6 5 Substrate +VCC Output Offset Trim NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL OPA121KM OPA121KP OPA121KU PACKAGE TO-99 8-Pin Plastic DIP 8-Pin SOIC TEMPERATURE RANGE 0°C to +70°C 0°C to +70°C 0°C to +70°C ® 3 OPA121 TYPICAL PERFORMANCE CURVES TA = +25°C, VCC = ±15VDC unless otherwise noted. BIAS AND OFFSET CURRENT vs TEMPERATURE 1k 1k INPUT VOLTAGE NOISE SPECTRAL DENSITY 1k Voltage Noise (nV/√Hz) 100 100 100 Bias Current (pA) KP, KU 10 10 10 KM 1 1 0.1 0.1 0.01 –50 –25 0 +25 +50 +75 +100 +125 Ambient Temperature (°C) 1 1 10 100 1k 10k Frequency (Hz) 100k 1M 0.01 BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE 10 10 Power Supply Rejection (dB) 140 120 100 80 60 40 20 0 1 10 POWER SUPPLY REJECTION vs FREQUENCY Bias Current (pA) 1 Bias Current Offset Current 1 0.1 KM 0.1 0.01 –15 –10 –5 0 +5 +10 +15 Common-Mode Voltage (V) 0.01 Offset Current (pA) 100 1k 10k 100k 1M 10M Frequency (Hz) COMMON-MODE REJECTION vs FREQUENCY 140 KM Common-Mode Rejection (dB) OPEN-LOOP FREQUENCY RESPONSE 140 KM 120 –45 120 Voltage Gain (dB) 100 80 60 40 20 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 100 80 60 40 20 0 1 10 Ø –90 Phase Margin ∼ ≈ 65° –135 –180 100 1k 10k 100k 1M 10M Frequency (Hz) ® OPA121 4 Phase Shift (Degrees) Gain Offset Current (pA) KM TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC unless otherwise noted. LARGE SIGNAL TRANSIENT RESPONSE +80 +15 Output Voltage (mV) Output Voltage (V) +40 SMALL SIGNAL TRANSIENT RESPONSE 0 0 +40 -15 +80 0 25 50 0 1 2 3 4 5 Time(µs) Time(µs) INPUT CURRENTS vs INPUT VOLTAGE WITH ±VCC PINS GROUNDED +2 Input Current (mA) +1 IIN Maximum Safe Current V 0 –1 Maximum Safe Current –2 –15 –10 –5 0 Input Voltage (V) +5 +10 +15 APPLICATIONS INFORMATION OFFSET VOLTAGE ADJUSTMENT The OPA121 offset voltage is laser-trimmed and will require no further trim for most applications. As with most amplifiers, externally trimming the remaining offset can change drift performance by about 0.3µV/°C for each 100µV of adjusted offset. Note that the trim (Figure 1) is similar to operational amplifiers such as 741 and AD547. The OPA121 can replace most BIFET amplifiers by leaving the external null circuit unconnected. INPUT PROTECTION Conventional monolithic FET operational amplifiers require external current-limiting resistors to protect their inputs against destructive currents that can flow when input FET gate-to-substrate isolation diodes are forward-biased. Most BIFET amplifiers can be destroyed by the loss of –VCC. Unlike BIFET amplifiers, the Difet OPA121 requires input current limiting resistors only if its input voltage is greater 2 +VCC 7 6 1 5 4 ±10mV Typical Trim Range *10k Ω to 1M Ω Trim Potentiometer (100k Ω Recommended) OPA121 3 * –VCC FIGURE 1. Offset Voltage Trim. than 6V more negative than –VCC. A 10kΩ series resistor will limit input current to a safe level with up to ±15V input levels even if both supply voltages are lost. Static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers (both bipolar and FET types), ® 5 OPA121 this may cause a noticeable degradation of offset voltage and drift. Static protection is recommended when handling any precision IC operational amplifier. Non-Inverting Buffer 2 8 OPA121 6 Out 2 3 In 8 OPA121 6 Out GUARDING AND SHIELDING As in any situation where high impedances are involved, careful shielding is required to reduce “hum” pickup in input leads. If large feedback resistors are used, they should also be shielded along with the external input circuitry. Leakage currents across printed circuit boards can easily exceed the bias current of the OPA121. To avoid leakage problems, it is recommended that the signal input lead of the OPA121 be wired to a Teflon™ standoff. If the OPA121 is to be soldered directly into a printed circuit board, utmost care must be used in planning the board layout. A “guard” pattern should completely surround the high-impedance input leads and should be connected to a low-impedance point which is at the signal input potential. The amplifier case should be connected to any input shield or guard via pin 8. This insures that the amplifier itself is fully surrounded by guard potential, minimizing both leakage and noise pickup (see Figure #2). If guarding is not required, pin 8 (case) should be connected to ground. BIAS CURRENT CHANGE VERSUS COMMON-MODE VOLTAGE Input Bias Current (pA) In In 3 Inverting TO-99 Bottom View 4 56 7 1 8 2 3 OPA121 8 6 Out 3 2 Mini-DIP Bottom View 8 7 6 5 4 1 2 3 BOARD LAYOUT FOR INPUT GUARDING Guard top and bottom of board. Alternate: use Teflon standoff for sensitive input pins. FIGURE 2. Connection of Input Guard. 80 70 60 50 40 30 20 10 0 –10 LF155 AD547 OPA121 OP-15/16/17 "Perfect Bias Current Cancellation" –10 –5 0 +5 +10 OPA121 LF156/157 AD547 LF155 TA = +25°C; curves taken from mfg. published typical data LF156/157 The input bias currents of most popular BIFET operational amplifiers are affected by common-mode voltage (Figure 3). Higher input FET gate-to-drain voltage causes leakage and ionization (bias) currents to increase. Due to its cascode input stage, the extremely-low bias current of the OPA121 is not compromised by common-mode voltage. Teflon™ E.I. du Pont de Nemours & Co. –20 Common-Mode Voltage (VDC) FIGURE 3. Input Bias Current vs Common-Mode Voltage. ® OPA121 6