OPA124

® OPA 124 OPA124 Low Noise Precision Difet ® OPERATIONAL AMPLIFIER FEATURES q LOW NOISE: 6nV/√Hz (10kHz) q LOW BIAS CURRENT: 1pA max q LOW OFFSET: 250µV max q LOW DRIFT: 2µV/°C max q HIGH OPEN-LOOP GAIN: 120dB min q HIGH COMMON-MODE REJECTION: 100dB min q AVAILABLE IN 8-PIN PLASTIC DIP AND 8-PIN SOIC PACKAGES Substrate APPLICA TIONS q PRECISION PHOTODIODE PREAMP q MEDICAL EQUIPMENT q OPTOELECTRONICS q DATA ACQUISITION q TEST EQUIPMENT DESCRIPTION The OPA124 is a precision monolithic FET operational amplifier using a Difet (dielectrical isolation) manufacturing process. Outstanding DC and AC performance characteristics allow its use in the most critical instrumentation applications. Bias current, noise, voltage offset, drift, open-loop gain, common-mode rejection and power supply rejection are superior to BIFET and CMOS amplifiers. Difet fabrication achieves extremely low input bias currents without compromising input voltage noise performance. Low input bias current is maintained over a wide input common-mode voltage range with unique cascode circuitry. This cascode design also allows high precision input specifications and reduced susceptibility to flicker noise. Laser trimming of thinfilm resistors gives very low offset and drift. Compared to the popular OPA111, the OPA124 gives comparable performance and is available in an 8-pin PDIP and 8-pin SOIC package. BIFET® National Semiconductor Corp., Difet ® Burr-Brown Corp. +VCC 7 8 –In 2 +In 3 Noise-Free Cascode(2) Output 6 Trim(1) 1 Trim(1) 5 10k Ω 10k Ω 2k Ω 2k Ω 2k Ω 2k Ω –V CC 4 OPA124 Simplified Circuit NOTES: (1) Omitted on SOIC. (2) Patented. International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1993 Burr-Brown Corporation PDS-1203C 1 Printed in U.S.A. March, 1998 OPA124 SPECIFICATIONS ELECTRICAL At VCC = ±15VDC and TA = +25° C, unless otherwise noted. OPA124U, P PARAMETER INPUT NOISE Voltage, fO = 10Hz(4) fO = 100Hz(4) fO = 1kHz(4) fO = 10kHz(5) fB = 10Hz to 10kHz(5) fB = 0.1Hz to 10Hz Current, fB = 0.1Hz to 10Hz fO = 0.1Hz thru 20kHz OFFSET VOLTAGE(1) Input Offset Voltage vs Temperature Supply Rejection vs Temperature BIAS CURRENT(1) Input Bias Current OFFSET Input Offset Current IMPEDANCE Differential Common-Mode VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection vs Temperature OPEN-LOOP GAIN, DC Open-Loop Voltage Gain FREQUENCY RESPONSE Unity Gain, Small Signal Full Power Response Slew Rate THD Settling Time, 0.1% 0.01% Overload Recovery, 50% Overdrive(2) RATED OUTPUT Voltage Output Current Output Output Resistance Load Capacitance Stability Short Circuit Current POWER SUPPLY Rated Voltage Voltage Range, Derated Current, Quiescent TEMPERATURE RANGE Specification Storage θ Junction-Ambient: PDIP SOIC T Specification same as OPA124U, P NOTES: (1) Offset voltage, offset current, and bias current are measured with the units fully warmed up. For performance at other temperatures see Typical Performance Curves. (2) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. (3) For performance at other temperatures see Typical Performance Curves. (4) Sample tested, 98% confidence. (5) Guaranteed by design. ±10 92 86 106 CURRENT(1) VCM = 0VDC ±1 1013 || 1 1014 || 3 ±11 110 100 125 1.5 32 1.6 0.0003 6 10 5 ±11 ±5.5 ±12 ±10 100 1000 40 ±15 2.5 –25 –65 90 100 T T T 94 T T ±5 ±0.5 T T T T T T T T T T T T T T T T T T T ±18 3.5 +85 +125 T T T T T T T T T T T T T T T T T T T 100 90 120 ±1 ±0.25 T T T T T T T T T T T T T T T T T T T T T T T ±0.5 pA Ω || pF Ω || pF V dB dB dB MHz kHz V/µs % µs µs µs V mA Ω pF mA VDC VDC mA °C °C °C/W °C/W VCM = 0VDC TA = TMIN to TMAX VCC = ±10V to ±18V TA = TMIN to TMAX VCM = 0VDC CONDITION MIN TYP 40 15 8 6 0.7 1.6 9.5 0.5 ±200 ±4 110 100 ±1 MAX 80 40 15 8 1.2 3.3 15 0.8 ±800 ±7.5 90 86 ±5 MIN OPA124UA, PA TYP T T T T T T T T ±150 ±2 T T ±0.5 MAX T T T T T T T T ±500 ±4 100 90 ±2 MIN OPA124PB TYP T T T T T T T T ±100 ±1 T T ±0.35 MAX T T T T T T T T ±250 ±2 UNITS nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms µVp-p fAp-p fA/√Hz µV µV/°C dB dB pA 88 84 ±1 VIN = ±10VDC TA = TMIN to TMAX RL ≥ 2kΩ 20Vp-p, RL = 2kΩ VO = ±10V, RL = 2kΩ Gain = –1, RL = 2kΩ 10V Step Gain = –1 RL = 2kΩ VO = ±10VDC DC, Open Loop Gain = +1 16 1 T T T T 10 T T ±5 IO = 0mADC TMIN and TMAX ® OPA124 2 CONNECTION DIAGRAMS Top View DIP Top View SOIC Offset Trim –In +In –VS 1 2 3 4 8 7 6 5 Substrate +VS Output Offset Trim NC –In +In –VS 1 2 3 4 NC = No Connect 8 7 6 5 Substrate +VS Output NC PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 182 006 182 006 006 TEMPERATURE RANGE –25°C to +85°C –25°C to +85°C –25°C to +85°C –25°C to +85°C –25°C to +85°C BIAS CURRENT pA, max 5 5 2 2 1 OFFSET DRIFT µV/°C, max 7.5 7.5 4 4 2 PRODUCT OPA124U OPA124P OPA124UA OPA124PA OPA124PB PACKAGE 8-Lead SOIC 8-Pin Plastic DIP 8-Lead SOIC 8-Pin Plastic DIP 8-Pin Plastic DIP NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS(1) Supply ........................................................................................... ±18VDC Internal Power Dissipation(2) ......................................................... 750mW Differential Input Voltage(3) .......................................................... ±36VDC Input Voltage Range(3) ................................................................. ±18VDC Storage Temperature Range .......................................... –65°C to +150°C Operating Temperature Range ....................................... –40°C to +125°C Lead Temperature (soldering, 10s) ................................................ +300°C Output Short Circuit Duration(4) ............................................... Continuous Junction Temperature .................................................................... +175°C NOTES: (1) Stresses above these ratings may cause permanent damage. (2) Packages must be derated based on θJA = 90°C/W for PDIP and 100°C/W for SOIC. (3) For supply voltages less than ±18VDC, the absolute maximum input voltage is equal to +18V > VIN > –VCC – 6V. See Figure 2. (4) Short circuit may be to power supply common only. Rating applies to +25°C ambient. Observe dissipation limit and TJ. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA124 TYPICAL PERFORMANCE CURVES At TA = +25° C, and VCC = ±15VDC, unless otherwise noted. INPUT CURRENT NOISE SPECTRAL DENSITY 100 1k INPUT VOLTAGE NOISE SPECTRAL DENSITY Voltage Noise (nV/√Hz) Current Noise (fA/√Hz) 10 100 U, P 10 PB 1 PB 0.1 1 10 100 1k Frequency (Hz) 10k 100k 1M 1 1 10 100 1k Frequency (Hz) 10k 100k 1M TOTAL(1) INPUT VOLTAGE NOISE SPECTRAL DENSITY vs SOURCE RESISTANCE 1k R S = 10M Ω TOTAL(1) INPUT VOLTAGE NOISE (PEAK-TO-PEAK) vs SOURCE RESISTANCE 1k Voltage Noise (nV/√Hz) 100 R S = 100kΩ Voltage Noise (µVp-p) R S = 1MΩ 100 NOTE: (1) Includes contribution from source resistance. 10 PB NOTE: (1) Includes contribution from source resistance. R S = 100 Ω 10 PB fB = 0.1Hz to 10Hz 1 0.1 1 10 100 Frequency (Hz) 1k 10k 100k 1 10 4 10 5 10 6 10 7 10 8 10 9 10 10 Source Resistance (Ω) VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs TEMPERATURE 12 f O = 1kHz Voltage Noise (nV/√Hz) 10 10 Current Noise (fA/√Hz) 100 1k TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY AT 1kHz vs SOURCE RESISTANCE EO Voltage Noise, EO (nV/√Hz) 100 RS 8 1 10 OPA124PB + Resistor 6 0.1 Resistor Noise Only 1 100 1k 10k 100k 1M 10M 100M Source Resistance (Ω) 4 –50 –25 0 25 50 75 100 Temperature (°C) 0.01 125 ® OPA124 4 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VCC = ±15VDC, unless otherwise noted. BIAS AND OFFSET CURRENT vs TEMPERATURE 1k 1k 10 BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE 10 100 Bias Current (pA) 100 Offset Current (pA) 10 PB 10 1 Bias Current 1 1 1 0.1 Offset Current 0.1 0.1 0.1 0.01 –50 –25 0 25 50 75 100 Ambient Temperature (°C) 0.01 125 0.01 –15 –10 –5 0 5 10 15 Common-Mode Voltage (V) 0.01 POWER SUPPLY REJECTION vs FREQUENCY 140 140 COMMON-MODE REJECTION vs FREQUENCY 100 80 60 40 20 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) Common-Mode Rejection (dB) Power Supply Rejection (dB) 120 120 100 80 60 40 20 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE 120 OPEN-LOOP FREQUENCY RESPONSE 140 120 –45 Phase Shift (Degrees) ® Common-Mode Rejection (dB) 110 100 Voltage Gain (dB) 100 80 60 40 20 Gain Phase Margin ≈ 65° –90 90 –135 80 70 –15 0 –10 –5 0 5 10 15 –180 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) Common-Mode Voltage (V) 5 OPA124 Offset Current (pA) Bias Current (pA) TYPICAL PERFORMANCE CURVES (CONT) At TA = +25° C, and VCC = ±15VDC, unless otherwise noted. GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE 4 4 GAIN-BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE 3 3 Gain Bandwidth (MHz) 3 3 Gain Bandwidth (MHz) Slew Rate (V/µs) 2 2 2 2 1 1 1 1 0 –50 –25 0 25 50 75 100 0 125 0 0 5 10 Supply Voltage (±VCC ) 15 20 0 Ambient Temperature (°C) OPEN-LOOP GAIN vs TEMPERATURE 140 MAXIMUM UNDISTORTED OUTPUT VOLTAGE vs FREQUENCY 30 130 Voltage Gain (dB) Output Voltage (Vp-p) 20 120 10 110 100 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) 0 1k 10k Frequency (Hz) 100k 1M LARGE SIGNAL TRANSIENT RESPONSE 15 10 Output Voltage (mV) SMALL SIGNAL TRANSIENT RESPONSE 60 40 20 0 –20 –40 –60 Output Voltage (V) 5 0 –5 –10 –15 0 10 20 Time (µs) 30 40 50 0 1 2 Time (µs) 3 4 5 ® OPA124 6 Slew Rate (V/µs) TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VCC = ±15VDC, unless otherwise noted. SETTLING TIME vs CLOSED-LOOP GAIN 100 4 SUPPLY CURRENT vs TEMPERATURE 80 60 0.01% 0.1% Supply Current (mA) 3 Settling Time (µs) 2 40 1 20 0 1 10 100 1k –50 –25 0 25 50 75 100 125 Closed-Loop Gain (V/V) Ambient Temperature (°C) 0 INPUT OFFSET VOLTAGE WARM-UP DRIFT 20 INPUT OFFSET VOLTAGE CHANGE DUE TO THERMAL SHOCK 150 Offset Voltage Change (µV) Offset Voltage Change (µV) U, P 75 PB 0 +25°C +85°C TA = +25°C to TA = +85°C Air Environment –75 10 0 –10 –20 0 1 2 3 4 5 6 Time From Power Turn-On (Minutes) –150 –1 0 1 2 3 4 5 Time From Thermal Shock (Minutes) ® 7 OPA124 APPLICATIONS INFORMATION OFFSET VOLTAGE ADJUSTMENT The OPA124 offset voltage is laser-trimmed and will require no further trim for most applications. In order to reduce layout leakage errors, the offset adjust capability has been removed from the SOIC versions (OPA124UA and OPA124U). The PDIP versions (OPA124PB, OPA124PA, and OPA124P) do have pins available for offset adjustment. As with most amplifiers, externally trimming the remaining offset can change drift performance by about 0.3µV/°C for each 100µV of adjusted offset. The correct circuit configuration for offset adjust for the PDIP packages is shown in Figure 1. INPUT PROTECTION Conventional monolithic FET operational amplifiers require external current-limiting resistors to protect their inputs against destructive currents that can flow when input FET gate-to-substrate isolation diodes are forward-biased. Most BIFET amplifiers can be destroyed by the loss of –VCC. Unlike BIFET amplifiers, the Difet OPA124 requires input current limiting resistors only if its input voltage is greater than 6V more negative than –VCC. A 10kΩ series resistor will limit input current to a safe level with up to ±15V input levels, even if both supply voltages are lost (Figure 2). Static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers (both bipolar and FET types), this may cause a noticeable degradation of offset voltage and drift. Static protection is recommended when handling any precision IC operational amplifier. GUARDING AND SHIELDING As in any situation where high impedances are involved, careful shielding is required to reduce “hum” pickup in input leads. If large feedback resistors are used, they should also be shielded along with the external input circuitry. Leakage currents across printed circuit boards can easily exceed the bias current of the OPA124. To avoid leakage problems, the OPA124 should be soldered directly into a printed circuit board. Utmost care must be used in planning the board layout. A “guard” pattern should completely surround the high impedance input leads and should be connected to a low impedance point which is at the signal input potential. The amplifier substrate should be connected to any input shield or guard via pin 8 minimizing both leakage and noise pickup (see Figure 3). If guarding is not required, pin 8 should be connected to ground. 2 3 +VCC 7 6 1 5 4 –VCC NOTE: No trim on SOIC. OPA124P 10kΩ to 1MΩ trim potentiometer. (100kΩ recommended). ±10mV typical trim range. FIGURE 1. Offset Voltage Trim for PDIP packages. 2 I IN Input Current (mA) 1 Maximum Safe Current V 0 –1 Maximum Safe Current –2 –15 –10 –5 0 Input Voltage (V) 5 10 15 FIGURE 2. Input Current vs Input Voltage with ±VCC Pins Grounded. Non-Inverting Buffer 2 8 OPA124 6 2 Out 8 OPA124 6 Out In 3 In 3 Inverting In Bottom View 2 OPA124 3 8 6 Out 8 7 6 5 1 4 Board layout for PDIP input guarding: guard top and bottom of board. FIGURE 3. Connection of Input Guard. ® OPA124 8