OPA129PB

® OPA129 Ultra-Low Bias Current Difet® OPERATIONAL AMPLIFIER FEATURES q ULTRA-LOW BIAS CURRENT: 100fA max q q q q q LOW OFFSET: 2mV max LOW DRIFT: 10µV/°C max HIGH OPEN-LOOP GAIN: 94dB min LOW NOISE: 15nV/√Hz at 10kHz PLASTIC DIP and SOIC PACKAGE APPLICATIONS q PHOTODETECTOR PREAMP q q q q q CHROMATOGRAPHY ELECTROMETER AMPLIFIERS MASS SPECTROMETER pH PROBE AMPLIFIER ION GAGE MEASUREMENT DESCRIPTION The OPA129 is an ultra-low bias current monolithic operational amplifier offered in an 8-pin PDIP and SO-8 package. Using advanced geometry dielectrically-isolated FET (Difet®) inputs, this monolithic amplifier achieves a high performance level. Substrate 8 7 V+ Difet fabrication eliminates isolation-junction leakage current—the main contributor to input bias current with conventional monolithic FETs. This reduces input bias current by a factor of 10 to 100. Very low input bias current can be achieved without resorting to small-geometry FETs or CMOS designs which can suffer from much larger offset voltage, voltage noise, drift, and poor power supply rejection. The OPA129's special pinout eliminates leakage current that occurs with other op amps. Pins 1 and 4 have no internal connection, allowing circuit board guard traces—even with the surface-mount package version. OPA129 is available in 8-pin DIP and SO-8 packages, specified for operation from –40°C to +85°C. –In 2 3 +In Noise-Free Cascode 6 Output 30kΩ 30kΩ 5 V– Simplified Circuit Difet® Burr-Brown Corp. International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1994 Burr-Brown Corporation PDS-1195A Printed in U.S.A. July, 1994 SPECIFICATIONS ELECTRICAL At VS = ±15V and TA = +25°C unless otherwise noted. Pin 8 connected to ground. OPA129PB, UB PARAMETER INPUT BIAS CURRENT(1) vs Temperature INPUT OFFSET CURRENT OFFSET VOLTAGE Input Offset Voltage vs Temperature Supply Rejection NOISE Voltage CONDITION VCM = 0V VCM = 0V VCM = 0V VS = ±5V to ±18V f = 10Hz f = 100Hz f = 1kHz f = 10kHz fB = 0.1Hz to 10Hz f = 10kHz MIN TYP MAX MIN OPA129P, U TYP * * * ±2 ±10 ±100 ±1 ±5 * * * * * * * * * * * * * * * * * * * * * * * ±55 * * * * * ±18 1.8 +85 +125 +125 90 100 * * * * * * * * * * * * ±5 * MAX ±250 UNITS fA fA mV µV/°C µV/V nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVp-p fA/√Hz Ω || pF Ω || pF V dB dB MHz kHz V/µs µs µs µs V mA pF mA V V mA °C °C °C °C/W °C/W ±30 ±100 Doubles every 10°C ±30 ±0.5 ±3 ±3 85 28 17 15 4 0.1 1013 || 1 1015 || 2 ±10 80 94 ±12 118 120 1 47 2.5 5 10 5 ±12 ±6 ±13 ±10 1000 ±35 ±15 1.2 –40 –40 –40 Current INPUT IMPEDANCE Differential Common-Mode VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection OPEN-LOOP GAIN, DC Open-Loop Voltage Gain FREQUENCY RESPONSE Unity Gain, Small Signal Full Power Response Slew Rate Settling Time: 0.1% 0.01% Overload Recovery, 50% Overdrive(2) RATED OUTPUT Voltage Output Current Output Load Capacitance Stability Short-Circuit Current POWER SUPPLY Rated Voltage Voltage Range, Derated Performance Current, Quiescent TEMPERATURE Specification Operating Storage Thermal Resistance PDIP—"P" SOIC—"U" VIN = ±10V RL ≥ 2kΩ 20Vp-p, RL = 2kΩ VO = ±10V, RL = 2kΩ G = –1, RL = 2kΩ, 10V Step 1 * G = –1 RL = 2kΩ VO = ±12V Gain = +1 * ±5 IO = 0mA Ambient Temperature Ambient Temperature θJA, Junction-to-Ambient NOTES: (1) High-speed automated test. (2) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA129 2 ABSOLUTE MAXIMUM RATINGS Power Supply Voltage ...................................................................... ±18V Differential Input Voltage ............................................................ V– to V+ Input Voltage Range .................................................................... V– to V+ Storage Temperature Range ......................................... –40°C to +125°C Operating Temperature Range ..................................... –40°C to +125°C Lead Temperature (soldering, 10s; SOIC 3s) ............................... +300°C Output Short Circuit Duration(1) .................................................................. Continuous Junction Temperature (TJ) ............................................................. +150°C NOTE: (1) Short circuit may be to power supply common at +25°C ambient. PACKAGE INFORMATION MODEL OPA129P OPA129PB OPA129U OPA129UB PACKAGE 8-pin Plastic DIP 8-pin Plastic DIP 8-pin SOIC 8-pin SOIC PACKAGE DRAWING NUMBER(1) 006 006 182 182 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. CONNECTION DIAGRAM ELECTROSTATIC DISCHARGE SENSITIVITY Any integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. Top View NC –In +In NC 1 2 OPA 3 4 6 5 Output V– 8 7 Substrate V+ DIP/SOIC NC: No internal connection. TYPICAL PERFORMANCE CURVES TA = +25°C, +15VDC, unless otherwise noted. OPEN-LOOP FREQUENCY RESPONSE 140 POWER SUPPLY REJECTION vs FREQUENCY 140 Power Supply Rejection (dB) 45 120 120 100 80 +PSRR 60 –PSRR 40 20 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) Voltage Gain (dB) 100 80 60 40 20 0 1 10 θ 90 Phase Margin ≈90° 135 180 100 1k 10k 100k 1M 10M Frequency (Hz) Pulse Shift (degrees) Gain ® 3 OPA129 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, +15VDC, unless otherwise noted. COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE 120 Common-Mode Rejection (dB) 140 COMMON-MODE REJECTION vs FREQUENCY Common-Mode Rejection (dB) 15 10 5 0 5 10 15 120 100 80 60 40 20 0 1 10 100 1k 10k 100k 1M 10M 110 100 90 80 70 Common-Mode Voltage (V) Frequency (Hz) BIAS AND OFFSET CURRENT vs TEMPERATURE 100pA BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE 10 Normalized Bias and Offset Current Bias and Offset Current (fA) 10pA 1 1pA IB and IOS 100 0.1 10 1 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) 0.01 15 –10 –5 0 5 10 15 Common-Mode Voltage (V) INPUT VOLTAGE NOISE SPECTRAL DENSITY 1k 30 FULL-POWER OUTPUT vs FREQUENCY Voltage Density (nV/√Hz) Output Voltage (Vp-p) 20 100 10 10 1 10 100 1k 10k 100k Frequency (Hz) 0 1k 10k 100k Frequency (Hz) 1M ® OPA129 4 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, +15VDC, unless otherwise noted. GAIN BANDWIDTH AND SLEW RATE vs TEMPERATURE 4 4 3 GAIN BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE 6 Gain Bandwidth (MHz) 3 3 Gain Bandwidth (MHz) Slew Rate (V/µs) 2 +Slew –Slew 1 GBW 4 2 2 2 1 1 0 –75 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) 0 0 0 5 10 Supply Voltage (±VCC) 15 20 0 SUPPLY CURRENT vs TEMPERATURE 2 130 OPEN-LOOP GAIN, PSR AND CMR vs TEMPERATURE Supply Current (mA) 1.5 PSR, CMR, Voltage Gain (dB) 120 A OL CMR 1 110 0.5 100 PSR 90 0 –75 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) –75 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) LARGE SIGNAL TRANSIENT RESPONSE 80 SMALL SIGNAL TRANSIENT RESPONSE 0 Output Voltage (mV) Output Voltage (V) 10 40 0 –10 –40 –80 0 25 Time (µs) 50 0 2 4 6 8 10 Time (µs) Slew Rate (v/µs) ® 5 OPA129 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, +15VDC, unless otherwise noted. COMMON-MODE INPUT RANGE vs SUPPLY VOLTAGE 15 BIAS CURRENT vs ADDITIONAL POWER DISSIPATION 100pA Common-Mode Voltage (+V) 10pA 10 Bias Current (fA) 1pA 100 5 10 0 0 5 10 Supply Voltage (±VCC) 15 20 1 0 50 100 150 200 250 300 350 Additional Power Dissipation (mW) APPLICATIONS INFORMATION NON-STANDARD PINOUT The OPA129 uses a non-standard pinout to achieve lowest possible input bias current. The negative power supply is connected to pin 5—see Figure 1. This is done to reduce the leakage current from the V- supply (pin 4 on conventional op amps) to the op amp input terminals. With this new pinout, sensitive inputs are separated from both power supply pins. Due to its laser-trimmed input stage, most applications do not require external offset voltage trimming. If trimming is required, the circuit shown in Figure 1 can be used. Power supply voltages are divided down, filtered and applied to the non-inverting input. The circuit shown is sensitive to variation in the supply voltages. Regulation can be added, if needed. GUARDING AND SHIELDING Ultra-low input bias current op amps require precautions to achieve best performance. Leakage current on the surface of circuit board can exceed the input bias current of the amplifier. For example, a circuit board resistance of 1012Ω from a power supply pin to an input pin produces a current of 15pA—more than one-hundred times the input bias current of the op amp. To minimize surface leakage, a guard trace should completely surround the input terminals and other circuitry connecting to the inputs of the op amp. The DIP package should have a guard trace on both sides of the circuit board. The guard ring should be driven by a circuit node equal in potential to the op amp inputs—see Figure 2. The substrate, pin 8, should also be connected to the circuit board guard to assure that the amplifier is fully surrounded by the guard potential. This minimizes leakage current and noise pick-up. Careful shielding is required to reduce noise pickup. Shielding near feedback components may also help reduce noise pick-up. Triboelectric effects (friction-generated charge) can be a troublesome source of errors. Vibration of the circuit board, input connectors and input cables can cause noise and drift. Make the assembly as rigid as possible. Attach cables to avoid motion and vibration. Special low noise or low leakage cables may help reduce noise and leakage current. Keep all input connections as short possible. Surface-mount components may reduce circuit board size and allow a more rigid assembly. 6 RF V+ RIN VIN 2 3 7 OPA129 5 V– 470kΩ 6 VOUT V+ 470kΩ 220Ω 0.1µF V– FIGURE 1. Offset Adjust Circuit. OFFSET VOLTAGE TRIM The OPA129 has no conventional offset trim connections. Pin 1, next to the critical inverting input, has no internal connection. This eliminates a source of leakage current and allows guarding of the input terminals. Pin 1 and pin 4, next to the two input pins, have no internal connection. This allows an optimized circuit board layout with guarding—see “circuit board layout.” ® OPA129 CIRCUIT BOARD LAYOUT The OPA129 uses a new pinout for ultra low input bias current. Pin 1 and pin 4 have no internal connection. This allows ample circuit board space for a guard ring surrounding the op amp input pins—even with the tiny SO-8 surfacemount package. Figure 3 shows suggested circuit board layouts. The guard ring should be connected to pin 8 (substrate) as shown. It should be driven by a circuit node equal in potential to the input terminals of the op amp—see Figure 2 for common circuit configurations. TESTING Accurately testing the OPA129 is extremely difficult due to its high performance. Ordinary test equipment may not be able to resolve the amplifier’s extremely low bias current. Inaccurate bias current measurements can be due to: 1. Test socket leakage, 2. Unclean package, 3. Humidity or dew point condensations, 4. Circuit contamination from fingerprints or anti-static treatment chemicals, 5. Test ambient temperature, 6. Load power dissipation, 7. Mechanical stress, 8. Electrostatic and electromagnetic interference. (A) Non-Inverting (B) Buffer 1000MΩ RF V+ IIN 2 Current Input 3 7 OPA129 8 5 V– VO = –IIN • RF VO = –1V/nA 6 Output 18kΩ 2kΩ FIGURE 4. Current-to-Voltage Converter. 500Ω Guard 2 3 8 7 OPA129 5 V– pH Probe RS ≈ 500MΩ 50mV Out 6 1VDC Output 9.5kΩ V+ FIGURE 5. High Impedance (1015Ω) Amplifier. CF 10pF 1011Ω 2 3 In 8 6 Out 2 3 In (C) Inverting 8 6 Out RF V+ 2 ∆Q 3 8 7 6 Output VOUT OPA129 5 In 2 6 Out 3 8 Low frequency cutoff = V– 1/(2πR C ) = 0.16Hz FF VOUT = –∆Q/CF FIGURE 6. Piezoelectric Transducer Charge Amplifier. Guard top and bottom of board. FIGURE 2. Connection of Input Guard. 1 8 V+ V0 V– 4 5 (A) DIP package 1 8 V+ V0 4 5 V– Connect to proper circuit node, depending on circuit configuration (see Figure 2). Connect to proper circuit node, depending on circuit configuration (see Figure 2). ~1pF to prevent gain peaking 1010 Ω Guard Pin photodiode HP 5082-4204 2 3 +15V 8 OPA129 0.1µF 7 6 Output 5 x 109V/W 5 0.1µF –15V Circuit must be well shielded. (B) SOIC package FIGURE 3. Suggested Board Layout for Input Guard. 7 FIGURE 7. Sensitive Photodiode Amplifier. ® OPA129