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Design
OPA1641, OPA1642, OPA1644
SBOS484D – DECEMBER 2009 – REVISED APRIL 2016
OPA164x SoundPlus™ High-Performance, JFET-Input Audio Operational Amplifiers
1 Features
3 Description
•
•
The OPA1641 (single), OPA1642 (dual), and
OPA1644 (quad) series are JFET-input, ultralow
distortion, low-noise operational amplifiers fully
specified for audio applications.
1
•
•
•
•
•
•
•
•
•
Superior Sound Quality
True JFET Input Operational Amplifier
With Low Input Bias Current
Low Noise: 5.1 nV/√Hz at 1 kHz
Ultralow Distortion: 0.00005% at 1 kHz
High Slew Rate: 20 V/μs
Unity Gain Stable
No Phase Reversal
Low Quiescent Current:
1.8 mA per Channel
Rail-to-rail Output
Wide Supply Range: ±2.25 V to ±18 V
Single, Dual, and Quad Versions Available
The OPA1641, OPA1642, and OPA1644 rail-to-rail
output swing allows increased headroom, making
these devices ideal for use in any audio circuit.
Features include 5.1-nV/√Hz noise, low THD+N
(0.00005%), a low input bias current of 2 pA, and low
quiescent current of 1.8 mA per channel.
These devices operate over a very wide supply
voltage range of ±2.25 V to ±18 V. The OPA1641,
OPA1642, and OPA1644 series of operational
amplifiers are unity-gain stable and provide excellent
dynamic behavior over a wide range of load
conditions.
2 Applications
•
•
•
•
•
The dual and quad versions feature completely
independent circuitry for lowest crosstalk and
freedom from interactions between channels, even
when overdriven or overloaded.
Professional Audio Equipment
Analog and Digital Mixing Consoles
Broadcast Studio Equipment
High-End A/V Receivers
High-End Blu-ray™ Players
The OPA1641, OPA1642, and OPA1644
specified from –40°C to +85°C. SoundPlus™
are
Device Information(1)
PART NUMBER
OPA1641
OPA1642
OPA1644
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.90 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
Simplified Internal Schematic
Extremely Stable Input Capacitance
7.5
Pre-Output Driver
IN-
OUT
IN+
V-
Common-Mode Capacitance (pF)
V+
7
Traditional JFET-Input Amplifier
6.5
6
OPA164x Family
5.5
5
4.5
4
±10
±8
±6
±4
±2
0
2
4
Common-Mode Voltage (V)
6
8
10
C004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA1641, OPA1642, OPA1644
SBOS484D – DECEMBER 2009 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
6
6.1
6.2
6.3
6.4
6.5
6.6
6
6
6
6
7
9
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
17
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 25
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
31
31
31
31
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2015) to Revision D
Page
•
Added TI Design .................................................................................................................................................................... 1
•
Changed MSOP to VSSOP throughout document ................................................................................................................ 1
•
Changed Supply voltage parameter in Recommended Operating Conditions table to split single and dual supply
specifications into separate rows for clarity ............................................................................................................................ 6
•
Changed last column header in Thermal Information table from DGK (VSSOP) to PW (TSSOP) ........................................ 6
•
Changed Noise subsection of Electrical Characteristics table: changed Input voltage noise parameter typical
specification and changed first two en parameter typical specifications................................................................................. 7
•
Changed Input Bias Current subsection of Electrical Characteristics table ........................................................................... 7
•
Changed VO parameter test conditions in Electrical Characteristics table ............................................................................ 8
•
Added ISC parameter specifications to Electrical Characteristics table ................................................................................. 8
•
Changed Temperature Range subsection of Electrical Characteristics table ....................................................................... 8
•
Changed third paragraph of Power Dissipation and Thermal Protection section for clarity ................................................ 23
•
Changed second paragraph of Electrical Overstress section for clarity............................................................................... 23
•
Added text reference for Equation 5 .................................................................................................................................... 27
Changes from Revision B (August 2010) to Revision C
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Added text to last bullet of Layout Guidelines section.......................................................................................................... 28
Changes from Revision A (April 2010) to Revision B
•
2
Page
Removed product-preview information for MSOP-8 package version of OPA1641............................................................... 1
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Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: OPA1641 OPA1642 OPA1644
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SBOS484D – DECEMBER 2009 – REVISED APRIL 2016
Changes from Original (December 2009) to Revision A
•
Page
Removed product-preview information for OPA1644 device packages throughout document.............................................. 1
Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: OPA1641 OPA1642 OPA1644
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3
OPA1641, OPA1642, OPA1644
SBOS484D – DECEMBER 2009 – REVISED APRIL 2016
www.ti.com
5 Pin Configuration and Functions
OPA1641: D and DGK Packages
8-Pin SOIC and VSSOP
Top View
NC
(1)
(1)
1
8
NC
-In
2
7
V+
+In
3
6
Out
V-
4
5
NC
(1)
(1) NC denotes no internal connection.
Pin Functions: OPA1641
PIN
NO.
NAME
I/O
DESCRIPTION
1
NC
—
No connection
2
–IN
I
Inverting input
3
+IN
I
Noninverting input
4
V–
—
Negative (lowest) power supply
5
NC
—
No connection
6
OUT
O
Output
7
V+
—
Positive (highest) power supply
8
NC
—
No connection
OPA1642: D and DGK Packages
8-Pin SOIC and VSSOP
Top View
OUT A
1
-In A
2
+In A
3
V-
4
A
B
8
V+
7
Out B
6
-In B
5
+In B
Pin Functions: OPA1642
PIN
I/O
DESCRIPTION
NO.
NAME
1
OUT A
O
Output, channel A
2
–IN A
I
Inverting input, channel A
3
+IN A
I
Noninverting input, channel A
4
V–
—
5
+IN B
I
Noninverting input, channel B
6
–IN B
I
Inverting input, channel B
7
OUT B
O
Output, channel B
8
V+
—
Positive (highest) power supply
4
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Negative (lowest) power supply
Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: OPA1641 OPA1642 OPA1644
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SBOS484D – DECEMBER 2009 – REVISED APRIL 2016
OPA1644: D and PW Packages
14-Pin SOIC and TSSOP
Top View
Out A
1
-In A
2
A
14
Out D
13
-In D
D
+In A
3
12
+In D
V+
4
11
V-
+ In B
5
10
+ In C
B
C
-In B
6
9
-In C
Out B
7
8
Out C
Pin Functions: OPA1644
PIN
I/O
DESCRIPTION
NO.
NAME
1
OUT A
O
Output, channel A
2
–IN A
I
Inverting input, channel A
3
+IN A
I
Noninverting input, channel A
4
V+
—
5
+IN B
I
Noninverting input, channel B
6
–IN B
I
Inverting input, channel B
7
OUT B
O
Output, channel B
8
OUT C
O
Output, channel C
9
–IN C
I
Inverting input, channel C
10
+IN C
I
Noninverting input, channel C
11
V–
—
12
+IN D
I
Noninverting input, channel D
13
–IN D
I
Inverting input, channel D
14
OUT D
O
Output, channel D
Positive (highest) power supply
Negative (lowest) power supply
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OPA1641, OPA1642, OPA1644
SBOS484D – DECEMBER 2009 – REVISED APRIL 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS
MAX
UNIT
40
V
Supply voltage
(2)
VIN
Input voltage
IIN
Input current (2)
(V–) – 0.5
(V+) + 0.5
V
±10
mA
±VS
V
VIN(DIFF) Differential input voltage
(3)
IO
Output short-circuit
TA
Operating temperature
–55
125
°C
TJ
Junction temperature
–65
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Continuous
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current-limited to 10 mA or less. The input voltage and output negative-voltage ratings can be exceeded if the input and output current
ratings are followed.
Short-circuit to VS / 2 (ground in symmetrical dual-supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage (V+, V–)
Single supply
Dual supply
NOM
MAX
4.5
36
±2.25
±18
–40
85
Specified temperature
UNIT
V
°C
6.4 Thermal Information
OPA1641, OPA1642
THERMAL METRIC (1)
RθJA
DGK (VSSOP)
D (SOIC)
PW (TSSOP)
8 PINS
8 PINS
14 PINS
14 PINS
UNIT
160
180
97
135
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
75
55
56
45
°C/W
RθJB
Junction-to-board thermal resistance
60
130
53
66
°C/W
ψJT
Junction-to-top characterization parameter
9
n/a
19
n/a
°C/W
ψJB
Junction-to-board characterization parameter
50
120
46
60
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
n/a
°C/W
(1)
6
Junction-to-ambient thermal resistance
OPA1644
D (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOS484D – DECEMBER 2009 – REVISED APRIL 2016
6.5 Electrical Characteristics
at TA = 25°C, VS = 4.5 V to 36 (±2.25 V to ±18 V), RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
THD+N
IMD
Total harmonic distortion + noise
Intermodulation distortion
0.00005%
G = +1, f = 1 kHz, VO = 3 VRMS
–126
SMPTE/DIN two-tone, 4:1
(60 Hz and 7 kHz), G = +1,
VO = 3 VRMS
0.00004%
DIM 30 (3-kHz square wave and
15-kHz sine wave), G = +1,
VO = 3 VRMS
0.00008%
CCIF twin-tone
(19 kHz and 20 kHz), G = +1,
VO = 3 VRMS
0.00007%
dB
–128
dB
–122
dB
–123
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
G=1
11
SR
Slew rate
G=1
20
V/μs
Full-power bandwidth (1)
VO = 1 VP
3.2
MHz
Overload recovery time (2)
G = –10
Channel separation (dual and quad) f = 1 kHz
MHz
600
ns
–126
dB
NOISE
Input voltage noise
f = 20 Hz to 20 kHz
en
Input voltage noise density
In
Input current noise density
μVPP
4.3
f = 10 Hz
8
f = 100 Hz
5.8
f = 1 kHz
5.1
f = 1 kHz
0.8
nV/√Hz
fA/√Hz
OFFSET VOLTAGE
VOS
Input offset voltage
VS = ±18 V
PSRR
VOS vs power supply
VS = ±2.25 V to ±18 V
1
3.5
0.14
2
mV
μV/V
INPUT BIAS CURRENT
IB
Input bias current
VCM = 0 V
±2
±20
pA
IOS
Input offset current
VCM = 0 V
±2
±20
pA
(V+)–3.5
V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(V–)–0.1
VCM = (V–) – 0.1 V to (V+) – 3.5 V,
VS = ±18 V
120
126
dB
INPUT IMPEDANCE
1013 || 8
Differential
Common-mode
13
VCM = (V–) – 0.1 V to (V+) – 3.5 V
10
|| 6
Ω || pF
Ω || pF
OPEN-LOOP GAIN
AOL
(1)
(2)
Open-loop voltage gain
(V–) + 0.2 V ≤ VO ≤ (V+) – 0.2 V,
RL = 10 kΩ
120
134
(V–) + 0.35 V ≤ VO ≤ (V+) – 0.35 V,
RL = 2 kΩ
114
126
dB
Full power bandwidth = SR / (2π × VP), where SR = slew rate.
See Figure 19 and Figure 20.
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SBOS484D – DECEMBER 2009 – REVISED APRIL 2016
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Electrical Characteristics (continued)
at TA = 25°C, VS = 4.5 V to 36 (±2.25 V to ±18 V), RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VO
Voltage output swing from rail
IOUT
Output current
ZO
Open-loop output impedance
ISC
Short-circuit current
CLOAD
Capacitive load drive
RL = 10 kΩ, AOL ≥ 120 dB
(V–)+0.2
(V+)–0.2
RL = 2 kΩ, AOL ≥ 114 dB
(V–)+0.35
(V+)–0.35
V
See Typical Characteristics
See Typical Characteristics
Source
36
Sink
mA
–30
See Typical Characteristics
POWER SUPPLY
VS
Specified voltage
IQ
Quiescent current (per amplifier)
±2.25
IOUT = 0 A
1.8
±18
V
2.3
mA
TEMPERATURE RANGE
Specified range
–40
85
°C
Operating range
–55
125
°C
Thermal resistance
8-pin SOIC package
138
8-pin VSSOP package
180
14-pin SOIC package
97
14-pin TSSOP package
8
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°C/W
135
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SBOS484D – DECEMBER 2009 – REVISED APRIL 2016
6.6 Typical Characteristics
at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
100nV/div
Voltage Noise Density (nV/ÖHz)
100
10
1
0.1
1
10
100
1k
10k
100k
Time (1s/div)
Frequency (Hz)
Figure 2. 0.1-Hz to 10-Hz Noise
Figure 1. Input Voltage Noise Density vs Frequency
160
35
25
Common-Mode Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
Output Voltage (VPP)
Maximum output
voltage range
without slew-rate
induced distortion
VS = ±15V
30
20
15
VS = ±5V
10
VS = ±2.25V
5
140
CMRR
120
100
-PSRR
80
+PSRR
60
40
20
0
0
10k
100k
1M
1
10M
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 4. CMRR and PSRR vs Frequency
(Referred to Input)
Figure 3. Maximum Output Voltage vs Frequency
140
180
30
120
Gain
90
60
40
Phase
45
20
Gain (dB)
80
G = +10
Phase (degrees)
Gain (dB)
20
135
100
10
G = +1
0
-10
G = -1
0
-20
50 100
1k
10k
100k
1M
10M
0
100M
-20
100k
1M
Frequency (Hz)
10M
100M
Frequency (Hz)
Figure 5. Gain and Phase vs Frequency
Figure 6. Closed-Loop Gain vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
G = +1
RL = 600W
G = -1
RL = 600W
0.0001
-120
G = +1
RL = 2kW
0.00001
100
1k
VOUT = 3VRMS
BW > 500kHz
G = -1
RL = 600W
0.001
G = +1
RL = 600W
-120
0.0001
G = +1
RL = 2kW
10
10k 20k
100
1k
Figure 8. THD+N Ratio vs Frequency
Figure 7. THD+N Ratio vs Frequency
0.0001
-120
G = -1, RL = 2kW
G = +1, RL = 2kW
0.1
-140
1
10
Intermodulation Distortion (%)
Total Harmonic Distortion + Noise (%)
-100
0.01
0.0001
CCIF Twin-Tone
(19kHz and 20kHz)
0.00001
20
-140
0.1
1
10
20
Output Amplitude (VRMS)
Figure 10. Intermodulation Distortion
vs Output Amplitude
VS = ±15V
VOUT = 3VRMS
G = +1
Output
-100
RL = 600W
5V/div
Channel Separation (dB)
-120
-110
-120
+18V
RL = 2kW
OPA1641
Output
-130
-18V
37VPP
Sine Wave
(±18.5V)
RL = 5kW
-140
10
100
1k
10k
100k
Frequency (Hz)
Figure 11. Channel Separation vs Frequency
10
-100
DIM30
(3kHz square wave
and 15kHz sine wave)
Figure 9. THD+N Ratio vs Output Amplitude
-90
SMPTE/DIN
Two-Tone
4:1 (60Hz and 7kHz)
0.001
Output Amplitude (VRMS)
-80
-80
G = +1
Intermodulation Distortion (dB)
0.001
Total Harmonic Distortion + Noise (dB)
-80
BW = 80kHz
1kHz Signal
RSOURCE = 0W
0.00001
-140
100k
10k
Frequency (Hz)
Frequency (Hz)
0.01
-100
G = -1
RL = 2kW
0.00001
-140
10
-80
0.01
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
G = -1
RL = 2kW
Total Harmonic Distortion + Noise (dB)
-100
VOUT = 3VRMS
BW = 80kHz
Total Harmonic Distortion + Noise (dB)
0.001
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Time (0.4ms/div)
Figure 12. No Phase Reversal
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Typical Characteristics (continued)
at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
G = -1
CL = 100pF
20mV/div
20mV/div
G = +1
CL = 100pF
+15V
OPA1641
-15V
RL
RI
= 2kW
RF
= 2kW
+15V
OPA1641
CL
CL
-15V
Time (100ns/div)
Time (100ns/div)
Figure 14. Small-Signal Step Response (100 mV)
G = +1
CL = 100pF
G = -1
CL = 100pF
2V/div
2V/div
Figure 13. Small-Signal Step Response (100 mV)
Time (400ns/div)
Time (400ns/div)
Figure 15. Large-Signal Step Response
VOUT
Figure 16. Large-Signal Step Response
G = -10
G = -10
5V/div
5V/div
VIN
20kW
20kW
2kW
VIN
2kW
OPA1641
VOUT
OPA1641
VIN
VOUT
VIN
VOUT
Time (0.4ms/div)
Figure 17. Positive Overload Recovery
Time (0.4ms/div)
Figure 18. Negative Overload Recovery
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Typical Characteristics (continued)
at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
40
45
G = +1
ROUT = 0W
35
40
ROUT
ROUT = 0W
RF = 2kW
RI = 2kW
+15V
+15V
OPA1641
RL
-15V
OPA1641
CL
25
ROUT = 24W
20
ROUT
35
CL
Overshoot (%)
Overshoot (%)
30
15
ROUT = 51W
30
25
20
ROUT = 51W
15
10
10
5
5
G = -1
0
0
0
ROUT = 24W
-15V
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Capacitive Load (pF)
Figure 19. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 20. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
80
0
70
-0.2
60
10kW
IB and IOS (pA)
AOL (mV/V)
-0.4
-0.6
2kW
-0.8
+IB
50
40
30
20
-IB
10
0
-1.0
-10
-1.2
-40
-IOS
-20
10
-15
35
60
-40
85
10
-15
8
85
2.5
VS = ±18V
6
2.0
+IB
4
-IB
2
0
IQ (mA)
IB and IOS (pA)
60
Figure 22. IB and IOS vs Temperature
Figure 21. Open-Loop Gain vs Temperature
10
35
Temperature (°C)
Temperature (°C)
IOS
-2
1.5
1.0
-4
-6
0.5
-8
Common-Mode Range
-10
-18
-12
-6
0
6
12
18
0
-40 -25 -10
5
Common-Mode Voltage (V)
Figure 23. IB and IOS vs Common-Mode Voltage
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20
35
50
65
80
95
110 125
Temperature (°C)
Figure 24. Quiescent Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
2.00
60
1.75
50
1.50
ISC-SOURCE
40
ISC (mA)
IQ (mA)
1.25
1.00
0.75
30
ISC-SINK
20
0.50
0.25
10
Specified Supply-Voltage Range
0
VOUT = Midsupply
(includes self-heating)
0
0
4
8
12
16
20
24
28
32
36
-50
-25
0
25
50
75
100
125
Temperature (°C)
Supply Voltage (V)
Figure 26. Short-Circuit Current vs Temperature
Figure 25. Quiescent Current vs Supply Voltage
1k
18.0
17.5
16.5
100
16.0
-40°C +25°C
+85°C
ZO (W)
Output Voltage (V)
17.0
+125°C
-16.0
10
-16.5
-17.0
-17.5
1
-18.0
0
10
20
30
40
50
10
100
1k
Output Current (mA)
Figure 27. Output Voltage vs Output Current
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 28. Open-Loop Output Impedance vs Frequency
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7 Detailed Description
7.1 Overview
The OPA164x family of operational amplifiers combine an ultra low noise JFET input stage with a rail-to-rail
output stage to provide high overall performance in audio applications. The internal topology is selected
specifically to deliver extremely low distortion, consume limited power, and accommodate small packages. These
amplifiers are well-suited for analog signal processing applications such as active filter circuits, pre-amplifiers,
and tone controls. The unique input stage design and semiconductor processes used in this device deliver
extremely high performance even in applications with high source impedance and wide common-mode voltage
swings.
7.2 Functional Block Diagram
V+
Pre-Output Driver
IN-
OUT
IN+
V-
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7.3 Feature Description
7.3.1 Phase Reversal Protection
The OPA164x family has internal phase-reversal protection. Many op amps exhibit phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The input of the OPA164x prevents phase reversal with excessive common-mode
voltage. Instead, the appropriate rail limits the output voltage. This performance is shown in Figure 29.
5V/div
Output
+18V
OPA1641
Output
-18V
37VPP
Sine Wave
(±18.5V)
Time (0.4ms/div)
Figure 29. Output Waveform Devoid of Phase Reversal During an Input Overdrive Condition
7.3.2 Output Current Limit
The output current of the OPA164x series is limited by internal circuitry to 36 mA and –30 mA (sourcing and
sinking), to protect the device if the output is accidentally shorted. This short-circuit current depends on
temperature; see Figure 26.
Although uncommon for most modern audio applications to require 600-Ω load drive capability, many audio
operational amplifier applications continue to specify the total harmonic distortion (THD+N) at 600-Ω load for
comparative purposes. Figure 7 and Figure 8 provide typical THD+N measurement curves for the OPA164x
series, where the output drives a 3-VRMS signal into a 600-Ω load. However, correct device operation cannot be
ensured when driving 600-Ω loads at full supply. Depending on supply voltage and temperature, this operating
condition can possibly trigger the output current limit circuitry of the device.
7.3.3 EMI Rejection Ratio (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many operational amplifiers is a change in the offset voltage as a
result of RF signal rectification. An operational amplifier that is more efficient at rejecting this change in offset as
a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in
many ways, but this document provides the EMIRR IN+, which specifically describes the EMIRR performance
when the RF signal is applied to the noninverting input pin of the operational amplifier. In general, only the
noninverting input is tested for EMIRR for the following three reasons:
• Operational amplifier input pins are known to be the most sensitive to EMI, and typically rectify RF signals
better than the supply or output pins.
• The noninverting and inverting operational amplifier inputs have symmetrical physical layouts and exhibit
nearly matching EMIRR performance.
• EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input pin can
be isolated on a printed-circuit-board (PCB). This isolation allows the RF signal to be applied directly to the
noninverting input pin with no complex interactions from other components or connecting PCB traces.
A more formal discussion of the EMIRR IN+ definition and test method is provided in application report EMI
Rejection Ratio of Operational Amplifiers (SBOA128), available for download at www.ti.com.
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Feature Description (continued)
The EMIRR IN+ of the OPA164x is plotted versus frequency in Figure 30. If available, any dual and quad
operational amplifier device versions have nearly identical EMIRR IN+ performance. The OPA164x unity-gain
bandwidth is 11 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the
operational amplifier bandwidth.
140
120
EMIRR (dB)
100
80
60
40
20
0
10M
100M
1G
10G
Frequency (Hz)
C003
Figure 30. OPA164x EMIRR vs Frequency
Table 1 lists the EMIRR IN+ values for the OPA164x at particular frequencies commonly encountered in realworld applications. Applications listed in Table 1 can be centered on or operated near the particular frequency
shown. This information can be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
Table 1. OPA164x EMIRR IN+ for Frequencies of Interest
16
FREQUENCY
APPLICATION, ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, UHF
53.1 dB
900 MHz
GSM, radio communication and navigation, GPS (to 1.6 GHz), ISM,
aeronautical mobile, UHF
72.2 dB
1.8 GHz
GSM, mobile personal comm. broadband, satellite, L-band
80.7 dB
2.4 GHz
802.11b/g/n, Bluetooth™, mobile personal comm., ISM, amateur radio and satellite, S-band
86.8 dB
3.6 GHz
Radiolocation, aero comm./nav., satellite, mobile, S-band
91.7 dB
5 GHz
802.11a/n, aero communication and navigation, mobile communication,
space and satellite operation, C-band
96.6 dB
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7.3.3.1 EMIRR IN+ Test Configuration
Figure 31 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the
operational amplifier noninverting input pin using a transmission line. The operational amplifier is configured in a
unity-gain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A
large impedance mismatch at the operational amplifier input causes a voltage reflection; however, this effect is
characterized and accounted for when determining the EMIRR IN+. The resulting dc offset voltage is sampled
and measured by the multimeter. The LPF isolates the multimeter from residual RF signals that can interfere with
multimeter accuracy. See EMI Rejection Ratio of Operational Amplifiers (SBOA128) for more details.
Ambient temperature: 25Û&
+VS
±
50
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
Frequency Sweep: 201 pt. Log
-VS
Not shown: 0.1 µF and 10 µF
supply decoupling
Sample /
Averaging
Digital Multimeter
Figure 31. EMIRR IN+ Test Configuration Schematic
7.4 Device Functional Modes
7.4.1 Operating Voltage
The OPA1641, OPA1642, and OPA1644 series of operational amplifiers can be used with single or dual supplies
from an operating range of VS = 4.5 V (±2.25 V) and up to VS = 36 V (±18 V). These devices do not require
symmetrical supplies; only a minimum supply voltage of 4.5 V (±2.25 V) is required. For VS less than ±3.5 V, the
common-mode input range does not include midsupply. Supply voltages higher than 40 V can permanently
damage the device; see the Absolute Maximum Ratings table for more information. Key parameters are specified
over the operating temperature range, TA = –40°C to +85°C. Key parameters that vary over the supply voltage or
temperature range are illustrated in the Typical Characteristics section.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA1641, OPA1642, and OPA1644 are unity-gain stable, audio operational amplifiers with very low noise,
input bias current, and input offset voltage. Applications with noisy or high-impedance power supplies require
decoupling capacitors placed close to the device pins. In most cases, 0.1-μF capacitors are adequate. Figure 32
shows a simplified schematic of the OPA1641.
V+
Pre-Output Driver
IN-
OUT
IN+
V-
Figure 32. Simplified Internal Schematic
8.1.1 Noise Performance
Figure 33 illustrates the total circuit noise for varying source impedances with the operational amplifier in a unitygain configuration (with no feedback resistor network and therefore no additional noise contributions). The
OPA1641, OPA1642, and OPA1644 are shown with total circuit noise calculated. The operational amplifier
contributes both a voltage noise component and a current noise component. The voltage noise is commonly
modeled as a time-varying component of the offset voltage. The current noise is modeled as the time-varying
component of the input bias current and reacts with the source resistance to create a voltage component of
noise. Therefore, the lowest noise operational amplifier for a given application depends on the source
impedance. For low source impedance, current noise is negligible, and voltage noise generally dominates. The
OPA1641, OPA1642, and OPA1644 family has both low voltage noise and extremely low current noise because
of the FET input of the operational amplifier. As a result, the current noise contribution of the OPA164x series is
negligible for any practical source impedance, which makes the OPA164x series of amplifiers better choices for
applications with high source impedance.
The equation in Figure 33 illustrates the calculation of the total circuit noise, where:
• en = voltage noise
• In = current noise
• RS = source impedance
• k = Boltzmann's constant = 1.38 × 10–23 J/K
• T = temperature in degrees Kelvin (K)
For more details on calculating noise, see the Basic Noise Calculations section.
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Application Information (continued)
Votlage Noise Spectral Density, EO
10k
EO
1k
OPA1611
RS
100
OPA1641
Resistor Noise
10
2
2
2
EO = en + (in RS) + 4kTRS
1
100
1k
10k
100k
1M
Source Resistance, RS (W)
Figure 33. Noise Performance of the OPA1611 and OPA1641 in a Unity-Gain Buffer Configuration
8.1.2 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on overall operational amplifier noise performance. Total
noise of the circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. This function is plotted in Figure 33. The source impedance is usually fixed; consequently, select the
operational amplifier and the feedback resistors to minimize the respective contributions to the total noise.
Figure 34 illustrates both noninverting (A) and inverting (B) operational amplifier circuit configurations with gain.
In circuit configurations with gain, the feedback network resistors also contribute noise. In general, the current
noise of the operational amplifier reacts with the feedback resistors to create additional noise components.
However, the extremely low current noise of the OPA164x means that the device current noise contribution can
be neglected.
The feedback resistor values can generally be chosen to make these noise sources negligible. Note that low
impedance feedback resistors do load the output of the amplifier. The equations for total noise are given in
Figure 34 for both configurations.
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A) Noise in Noninverting Gain Configuration
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Noise at the output:
R2
2
2
O
E
R1
R2
= 1+
R1
2
R2
2
n
e +
2
2
2
e1 + e2 + 1 +
R1
R2
R1
es2
EO
RS
Where eS =
4kTRS = thermal noise of RS
e1 =
4kTR1 = thermal noise of R1
e2 =
4kTR2 = thermal noise of R2
VS
B) Noise in Inverting Gain Configuration
Noise at the output:
R2
2
2
EO
R1
= 1+
R2
R1 + RS
2
2
en +
R2
R 1 + RS
2
2
1
2
e + e2 +
R2
R 1 + RS
e s2
EO
RS
VS
Where eS =
4kTRS = thermal noise of RS
e1 =
4kTR1 = thermal noise of R1
e2 =
4kTR2 = thermal noise of R2
For the OPA164x series op amps at 1kHz, en = 5.1nV/ÖHz
Figure 34. Noise Calculation in Gain Configurations
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8.1.3 Total Harmonic Distortion Measurements
The OPA164x series operational amplifiers have excellent distortion characteristics. THD + noise is below
0.00005% (G = 1, VO = 3 VRMS, BW = 80 kHz) throughout the audio frequency range, 20 Hz to 20 kHz, with a
2-kΩ load (see Figure 7).
The distortion produced by the OPA164x series operational amplifiers is below the measurement limit of many
commercially available distortion analyzers. However, a special test circuit (such as shown in Figure 35) can be
used to extend the measurement capabilities.
Operational amplifier distortion can be considered an internal error source that can be referred to the input.
Figure 35 shows a circuit that causes the operational amplifier distortion to be 101 times (or approximately
40 dB) greater than that normally produced by the operational amplifier. The addition of R3 to the otherwise
standard noninverting amplifier configuration alters the feedback factor or noise gain of the circuit. The closedloop gain is unchanged, but the feedback available for error correction is reduced by a factor of 101, thus
extending the resolution by 101. Note that the input signal and load applied to the operational amplifier are the
same as with conventional feedback without R3. Keep the value of R3 small to minimize any effect on distortion
measurements.
The validity of this technique can be verified by duplicating measurements at high gain or high frequency where
the distortion is within the measurement capability of the test equipment. Measurements for this document were
made with an audio precision system two distortion and noise analyzer that greatly simplifies such repetitive
measurements. The measurement technique can, however, be performed with manual distortion measurement
instruments.
space
R1
R2
SIGNAL DISTORTION
GAIN
GAIN
R3
Signal Gain = 1+
OPA1641
VO = 3VRMS
R2
R1
Distortion Gain = 1+
R2
R1 II R3
Generator
Output
R1
R2
R3
1
101
¥
1kW
10W
11
101
100W
1kW
11W
Analyzer
Input
Audio Precision
System Two(1)
with PC Controller
(1)
Load
For measurement bandwidth, see Figure 7 through Figure 10.
Figure 35. Distortion Test Circuit
8.1.4 Source Impedance and Distortion
In traditional JFET-input operational amplifiers, the impedance applied to the positive and negative inputs in
noninverting applications must be matched for lowest distortion. Legacy methods for fabricating the JFETs in the
FET input stage exhibit a varying input capacitance with applied common-mode input voltage. In inverting
configurations, the input does not vary with input voltage because the inverting input is held at virtual ground.
However, in noninverting applications, the inputs do vary, and the gate-to-source voltage is not constant. This
effect produces increased distortion as a result of the varying capacitance for unmatched source impedances.
However, the OPA164x family of amplifiers is designed to maintain a constant input capacitance with varying
common-mode voltage to prevent this mechanism of distortion. The variation of input capacitance with commonmode voltage for a traditional amplifier is compared to the OPA164x family in Figure 36.
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Common-Mode Capacitance (pF)
7.5
7
Traditional JFET-Input Amplifier
6.5
6
OPA164x Family
5.5
5
4.5
4
±10
±8
±6
±4
±2
0
2
4
6
8
Common-Mode Voltage (V)
10
C004
Figure 36. Input Capacitance of the OPA164x Family of Amplifiers Compared to Traditional JFET-input
Amplifiers
Total Harmonic Distortion + Noise (%)
1
-40
10 k
+
-50
±
5 VRMS
0.1
-60
-70
Traditional JFET-Input Amplifier
0.01
-80
-90
OPA164x Amplifier
0.001
-100
-110
0.0001
-120
10
100
1000
Total Harmonic Distortion + Noise (dB)
By stabilizing the input capacitance, the distortion performance of the amplifier is greatly improved for
noninverting configurations with high source impedances. The measured performance of an OPA164x amplifier
is compared to a traditional JFET-input amplifier in Figure 37. The unity-gain configuration, high source
impedance, and large-signal amplitude produce additional distortion in the traditional amplifier.
10000
Frequency (Hz)
C005
Figure 37. Measured THD+N of the OPA164x Family of Amplifiers Compared to Traditional JFET-input
Amplifiers
8.1.5 Capacitive Load and Stability
The dynamic characteristics of the OPA164x are optimized for commonly encountered gains, loads, and
operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase
margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be
isolated from the output. The simplest way to achieve this isolation is to add a small resistor (ROUT equal to 50 Ω,
for example) in series with the output.
Figure 19 and Figure 20 illustrate graphs of Small-Signal Overshoot vs Capacitive Load for several values of
ROUT. Also, see Applications Bulletin AB-028, Feedback Plots Define Op Amp AC Performance (SBOA015)
available for download at www.ti.com for details of analysis techniques and application circuits.
8.1.6 Power Dissipation and Thermal Protection
The OPA164x series of operational amplifiers are capable of driving 2-kΩ loads with power-supply voltages of up
to ±18 V over the specified temperature range. In a single-supply configuration, where the load is connected to
the negative supply voltage, the minimum load resistance is 2.8 kΩ at a supply voltage of 36 V. For lower supply
voltages (either single-supply or symmetrical supplies), a lower load resistance can be used, as long as the
output current does not exceed 13 mA; otherwise, the device short-circuit current protection circuit can activate.
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Internal power dissipation increases when operating at high supply voltages. Copper leadframe construction
used in the OPA1641, OPA1642, and OPA1644 series of devices improves heat dissipation compared to
conventional materials. PCB layout can also help reduce a possible increase in junction temperature. Wide
copper traces help dissipate the heat by functioning as an additional heatsink. Temperature rise can be further
minimized by soldering the devices directly to the PCB rather than using a socket.
Although the output current is limited by internal protection circuitry, accidental shorting one or more output
channels of a device can result in excessive heating. For instance, when an output is shorted to mid-supply, the
typical short-circuit current of 36 mA leads to an internal power dissipation of over 600 mW at a supply of ±18 V.
In case of a dual OPA1642 in an VSSOP-8 package (thermal resistance θJA = 180°C/W), such a power
dissipation results in the die temperature to be 220°C above ambient temperature, when both channels are
shorted. This temperature increase will destroy the device.
To prevent such excessive heating that can destroy the device, the OPA164x series has an internal thermal
shutdown circuit that shuts down the device if the die temperature exceeds approximately 180°C. When this
thermal shutdown circuit activates, a built-in hysteresis of 15°C ensures that the die temperature must drop to
approximately 165°C before the device switches on again.
8.1.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 38 illustrates the ESD circuits contained in the OPA164x series (indicated by the dashed line
area). The ESD protection circuitry involves several current-steering diodes connected from the input and output
pins and routed back to the internal power-supply lines where an internal absorption device is connected. This
protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event produces a short duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or
more of the steering diodes. Depending on the path that the current takes, the absorption device can activate.
The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the
OPA164x but below the device breakdown voltage level. When this threshold is exceeded, the absorption device
quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit such as the one illustrated in Figure 38, the ESD protection
components are intended to remain inactive and not become involved in the application circuit operation.
However, circumstances can arise where an applied voltage exceeds the operating voltage range of a given pin.
If this condition occurs, some of the internal ESD protection circuits can be biased on and conduct current. Any
such current flow occurs through steering diode paths and rarely involves the absorption device.
Figure 38 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the datasheet specifications recommend that applications
limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
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Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies +VS and –VS are at 0 V. The amplifier behavior depends on the supply characteristic when at
0 V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current can be supplied by the input source through the current steering diodes. This state is not
a normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance,
then the current through the steering diodes can become quite high. The current level depends on the ability of
the input source to deliver current, and any resistance in the input path.
If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes can be
added to the supply pins, as shown in Figure 38. The Zener voltage must be selected such that the diode does
not turn on during normal operation. However, the Zener voltage must be low enough so that the Zener diode
conducts if the supply pin begins to rise above the safe operating supply voltage level.
(2)
TVS
RF
+V
+VS
OPA1641
RI
ESD CurrentSteering Diodes
-In
(3)
RS
+In
Op-Amp
Core
Edge-Triggered ESD
Absorption Circuit
ID
VIN
Out
RL
(1)
-V
-VS
(2)
TVS
(1)
VIN = +VS + 500 mV.
(2)
TVS: +VS(max) > VTVSBR (Min) > +VS
(3)
Suggested value is approximately 1 kΩ.
Figure 38. Equivalent Internal ESD Circuitry and the Relation to a Typical Circuit Application
24
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8.2 Typical Application
The noise and distortion performance of the OPA164x family of amplifiers is exceptional in applications with high
source impedances, which makes these devices an excellent choice in preamplifier circuits for moving magnet
phono cartridges. The high source impedance of the cartridge, and high gain required by the RIAA playback
curve at low frequency, requires an amplifier with both low input current noise and low input voltage noise.
+15 V
RC 1.5k
LC 600mH
++
R1
47k
VC
C1
150pF
OPA1642
R4
127
C5
100uF
Output
R6
100k
-15 V
Moving-Magnet Phono Cartridge
R5
100
R2
118k
R3
10k
C2
27nF
C3
7.5nF
C4
100uF
Figure 39. Preamplifier Circuit for Vinyl Record Playback With Moving-Magnet Phono Cartridges
(Single Channel Shown)
8.2.1 Design Requirements
•
•
•
Gain: 40 dB (1 kHz)
RIAA Accuracy: ±0.5 dB (100 Hz to 20 kHz)
Power Supplies: ±15 V
8.2.2 Detailed Design Procedure
Vinyl records are recorded using an equalization curve specified by the Recording Institute Association of
America (RIAA). The purpose of this equalization curve is to decrease the amount of space occupied by a grove
on the record and therefore maximize the amount of information able to be stored. Proper playback of music
stored on the record requires a preamplifier circuit that applies the inverse transfer function of the recording
equalization curve. The combination of the recording equalization and the playback equalization results in a flat
frequency response over the audio range; see Figure 40.
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Typical Application (continued)
20
15
Playback Curve
10
Gain (dB)
5
0
Combined Response
-5
-10
Recording Curve
-15
-20
10
100
1000
10000
Frequency (Hz)
C009
Figure 40. RIAA Recording and Playback Curves Normalized at 1 kHz
The basic RIAA playback curve implements three time constants: 75 μs, 380 μs, and 3180 μs. An IEC
amendment is later added to the playback curve and implements a pole in the curve at 20 Hz with the intent of
protecting loudspeakers from excessive low frequency content. Rather than strictly adhering to the IEC
amendment, this design moves this pole to a lower frequency to improve low frequency response and still
providing protection for loudspeakers.
Resistor R1 and capacitor C1 are selected to provide the proper input impedance for the moving magnet
cartridge. Cartridge loading is specified by the manufacturer in the cartridge datasheet and is absolutely crucial
for proper response at high frequency. 47 kΩ is a common value for the input resistor, and the capacitive loading
is usually specified to 200 pF to 300 pF per channel. This capacitive loading specification includes the
capacitance of the cable connecting the turntable to the preamplifier, as well as any additional parasitic
capacitances at the preamplifier input. Therefore, the value of C1 must be less than the loading specification to
account for these additional capacitances.
The output network consisting of R5, R6, and C5 serves to ac couple the preamplifier circuit to any subsequent
electronics in the signal path. The 100-Ω resistor R5 limits in-rush current into coupling capacitor C5 and
prevents parasitic capacitance from cabling from causing instability. R6 prevents charge accumulation on C5.
Capacitor C5 is chosen to be the same value as C4; for simplicity however, the value of C5 must be large
enough to avoid attenuating low frequency information.
The feedback resistor elements must be selected to provide the correct response within the audio bandwidth. In
order to achieve the correct frequency response, the passive components in Figure 39 must satisfy Equation 1,
Equation 2, and Equation 3:
R2 u C2 3180Ps
(1)
R3 u C3
75Ps
R2 || R3 u C2
(2)
C3
318Ps
(3)
R2, R3, and R4 must also be selected to meet the design requirements for gain. The gain at 1 kHz is determined
by subtracting 20 dB from gain of the circuit at very low frequency (near dc), as shown in Equation 4:
A1kHz ALF 20dB
(4)
26
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Typical Application (continued)
Therefore, the low frequency gain of the circuit must be 60 dB to meet the goal of 40 dB at 1 kHz and is
determined by resistors R2, R3, and R4 as shown in Equation 5:
R3 R 2
ALF 1
1000(60dB)
R4
(5)
Because there are multiple combinations of passive components that satisfy these equations, a spreadsheet or
other software calculation tool is the easiest method to examine resistor and capacitor combinations.
Capacitor C4 forces the gain of the circuit to unity at dc in order to limit the offset voltage at the output of the
preamplifier circuit. The high-pass corner frequency created by this capacitor is calculated by Equation 6:
1
FHP
2SR 4 C4
(6)
The circuit described in Figure 39 is constructed with 1% tolerance resistors and 5% tolerance NP0, C0G
ceramic capacitors without any additional hand sorting. The large value of C4 typically requires an electrolytic
type to be used. However, electrolytic capacitors have the potential to introduce distortion into the signal path.
This circuit is constructed using a bipolar electrolytic capacitor specifically intended for audio applications.
8.2.3 Application Curves
The deviation from the ideal RIAA transfer function curve is shown in Figure 41 and normalized to an ideal gain
of 40 dB at 1 kHz. The measured gain at 1 kHz is 0.05 dB less than the design goal, and the maximum deviation
from 100 Hz to 20 kHz is 0.18 dB. The deviation from the ideal curve can be improved by hand-sorting resistor
and capacitor values to their ideal values. The value of C4 can also be increased to reduce the deviation at low
frequency.
A spectrum of the preamplifier output signal is shown in Figure 42 for a 10 mVRMS, 1-kHz input signal (1-VRMS
output). All distortion harmonics are below the preamplifier noise floor.
0
0.5
-40
0
Amplitude (dBV)
Magnitude Deviation from Ideal (dB)
-20
-0.5
-1
-60
-80
-100
-120
-140
-1.5
-160
10
100
1000
10
10000
100
Frequency (Hz)
1000
10000
Frequency (Hz)
C006
Figure 41. Measured Deviation from Ideal RIAA Response
C010
Figure 42. Output Spectrum for a 10 mVRMS, 1 kHz Input
Signal
9 Power Supply Recommendations
The OPA164x are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed
information, see Circuit Board Layout Techniques, SLOA089.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 43, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
VS±
Ground (GND) plane on another layer
Figure 43. OPA1641 Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macromodels in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
TI Precision Designs, available online at http://www.ti.com/ww/en/analog/precision-designs/, are analog solutions
created by TI’s precision analog applications experts and offer the theory of operation, component selection,
simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful
circuits.
11.1.1.3 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets optimized filter designs to be created using a selection of TI operational amplifiers and
passive components from TI's vendor partners.
Available as a web based tool from the WEBENCH® Design Center, the WEBENCH® Filter Designer allows
complete multistage active filter solutions to be designed, optimized, and simulated within minutes.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Circuit Board Layout Techniques, SLOA089
• Op Amps for Everyone, SLOD006
• Operational amplifier gain stability, Part 3: AC gain-error analysis, SLYT383
• Operational amplifier gain stability, Part 2: DC gain-error analysis, SLYT374
• Using infinite-gain, MFB filter topology in fully differential active filters, SLYT343
• Op Amp Performance Analysis, SBOS054
• Single-Supply Operation of Operational Amplifiers, SBOA059
• Tuning in Amplifiers, SBOA067
• Shelf-Life Evaluation of Lead-Free Component Finishes, SZZA046
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11.3 Related Links
Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA1641
Click here
Click here
Click here
Click here
Click here
OPA1642
Click here
Click here
Click here
Click here
Click here
OPA1644
Click here
Click here
Click here
Click here
Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
SoundPlus, E2E are trademarks of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Blu-ray is a trademark of Blu-Ray Disc Assocation.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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28-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA1641AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
O1641A
OPA1641AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
Call TI | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
1641
OPA1641AIDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
Call TI | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
1641
OPA1641AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
O1641A
OPA1642AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
O1642A
OPA1642AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
Call TI | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
1642
OPA1642AIDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
Call TI | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
1642
OPA1642AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
O1642A
OPA1644AID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
O1644A
OPA1644AIDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
O1644A
OPA1644AIPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
O1644A
OPA1644AIPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
O1644A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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