OPA170ASDRLTEP

OPA170-EP www.ti.com SBOS598A – DECEMBER 2012 – REVISED DECEMBER 2012 36-V, SINGLE-SUPPLY, LOW-POWER OPERATIONAL AMPLIFIER Check for Samples: OPA170-EP FEATURES 1 • • • • • • • • • • • 2 Supply Range: +2.7V to +36V, ±1.35V to ±18V Low Noise: 19nV/√Hz RFI Filtered Inputs Input Range Includes the Negative Supply Input Range Operates to Positive Supply Rail-to-Rail Output Gain Bandwidth: 1.2MHz Low Quiescent Current: 110µA per Amplifier High Common-Mode Rejection: 120dB Low Bias Current: 15pA (max) microPackage: – Single in 5-Pin SOT553 APPLICATIONS • • • • • • • • • Tracking Amplifier in Power Modules Merchant Power Supplies Transducer Amplifiers Bridge Amplifiers Temperature Measurements Strain Gauge Amplifiers Precision Integrators Battery-Powered Instruments Test Equipment SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • • • • (1) DESCRIPTION The OPA170 is a 36-V, single-supply, low-noise operational amplifier that features a micro package with the ability to operate on supplies ranging from +2.7V (±1.35V) to +36V (±18V). It offers good offset, drift, and bandwidth with low quiescent current. Unlike most op amps, which are specified at only one supply voltage, the OPA170 is specified from +2.7V to +36V. Input signals beyond the supply rails do not cause phase reversal. The OPA170 is stable with capacitive loads up to 300pF. The input can operate 100mV below the negative rail and within 2V of the positive rail for normal operation. Note that these devices can operate with full rail-to-rail input 100mV beyond the positive rail, but with reduced performance within 2V of the positive rail. The OPA170 is available in the SOT553-5 package and is specified from –40°C to +150°C. Package Footprint (to Scale) Package Height (to Scale) DRL (SOT553) Smallest Packaging for 36V Op Amps Controlled Baseline One Assembly or Test Site One Fabrication Site Available in Extended (–40°C to 150°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability Additional temperature ranges available - contact factory 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated OPA170-EP SBOS598A – DECEMBER 2012 – REVISED DECEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER –40°C to 150°C SOT553-5 - DRL OPA170ASDRLTEP SHN V62/12627-01XE (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. PIN CONFIGURATIONS DRL PACKAGE SOT553-5 (TOP VIEW) IN+ 1 V- 2 IN- 3 5 V+ 4 OUT ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. UNIT Supply voltage Signal input terminals Voltage ±20, +40 (single supply) V (V–) – 0.5 to (V+) + 0.5 V ±10 mA Current Output short circuit (2) Continuous Operating temperature –40 to +150 °C Storage temperature –65 to +150 °C Junction temperature +150 °C 4 kV 750 V ESD ratings (1) (2) Human body model (HBM) Charged device model (CDM) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Short-circuit to ground, one amplifier per package. THERMAL INFORMATION OPA170 THERMAL METRIC (1) DRL (SOT553) UNITS 5 PINS θJA Junction-to-ambient thermal resistance 226.8 θJC(top) Junction-to-case(top) thermal resistance 80.3 θJB Junction-to-board thermal resistance 42.9 ψJT Junction-to-top characterization parameter 3.2 ψJB Junction-to-board characterization parameter 42.5 θJC(bottom) Junction-to-case(bottom) thermal resistance N/A (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: OPA170-EP OPA170-EP www.ti.com SBOS598A – DECEMBER 2012 – REVISED DECEMBER 2012 ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range, TA = –40°C to +150°C. At TA = +25°C, VCM = VOUT = VS/2, and RL = 10kΩ connected to VS/2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.25 ±1.8 mV ±2.5 mV OFFSET VOLTAGE Input offset voltage VOS Over temperature Drift vs power supply TA = –40°C to +150°C dVOS/dT PSRR Channel separation, dc ±0.3 VS = +4V to +36V 1 dc 5 µV/°C ±5 µV/V µV/V INPUT BIAS CURRENT Input bias current IB Over temperature Input offset current ±8 TA = –40°C to +150°C IOS Over temperature ±4 TA = –40°C to +150°C ±15 pA ±8 nA ±15 pA ±8 nA NOISE Input voltage noise Input voltage noise density en f = 0.1Hz to 10Hz 2 µVPP f = 100Hz 22 nV/√Hz f = 1kHz 19 nV/√Hz INPUT VOLTAGE Common-mode voltage range (1) Common-mode rejection ratio VCM CMRR (V–) – 0.1V (V+) – 2V V VS = ±2V, (V–) – 0.1V < VCM < (V+) – 2V 87 104 dB VS = ±18V, (V–) – 0.1V < VCM < (V+) – 2V 100 120 dB INPUT IMPEDANCE Differential 100 || 3 Common-mode MΩ || pF 6 || 3 1012 Ω || pF 130 dB OPEN-LOOP GAIN Open-loop voltage gain AOL VS = +4V to +36V, (V–) + 0.35V < VO < (V+) – 0.35V 107 FREQUENCY RESPONSE Gain bandwidth product Slew rate Settling time GBP SR tS Overload recovery time Total harmonic distortion + noise (1) THD+N 1.2 MHz G = +1 0.4 V/µs To 0.1%, VS = ±18V, G = +1, 10V step 20 µs To 0.01% (12 bit), VS = ±18V, G = +1, 10V step 28 µs VIN × Gain > VS 2 µs 0.0002 % G = +1, f = 1kHz, VO = 3VRMS The input range can be extended beyond (V+) – 2V up to V+. See the Typical Characteristics and Application Information sections for additional information. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: OPA170-EP 3 OPA170-EP SBOS598A – DECEMBER 2012 – REVISED DECEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +150°C. At TA = +25°C, VCM = VOUT = VS/2, and RL = 10kΩ connected to VS/2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT Voltage output swing from rail VO Positive rail Negative Rail Over temperature Short-circuit current IL = 0mA, VS = +4V to +36V 10 IL sourcing 1mA, VS = +4V to +36V 130 8 mV IL sinking 1mA, VS = +4V to +36V 72 mV VS = 5V, RL = 10kΩ (V–) + 0.03 (V+) – 0.05 RL = 10kΩ, AOL ≥ 107dB (V–) + 0.35 (V+) – 0.35 +17/–20 CLOAD Open-loop output resistance mV IL = 0mA, VS = +4V to +36V ISC Capacitive load drive mV f = 1MHz, IO = 0A V mA See Typical Characteristics RO V pF Ω 900 POWER SUPPLY Specified voltage range VS Quiescent current per amplifier IQ +2.7 IO = 0A Over temperature 110 IO = 0A +36 V 145 µA 160 µA TEMPERATURE Specified range –40 +125 °C Operating range –40 +150 °C 10000.00 1000.00 Estimated Life (Years) Electromigration Fail Mode 100.00 Wirebond Voiding Fail Mode 10.00 1.00 0.10 80 100 120 140 160 180 200 Continuous T J (°C) (1) See datasheet for absolute maximum and minimum recommended operating conditions. (2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). (3) Enhanced plastic product disclaimer applies. Figure 1. OPA170-EP Operating Life Derating Chart 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: OPA170-EP OPA170-EP www.ti.com SBOS598A – DECEMBER 2012 – REVISED DECEMBER 2012 TYPICAL CHARACTERISTICS VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted. OFFSET VOLTAGE PRODUCTION DISTRIBUTION OFFSET VOLTAGE DRIFT DISTRIBUTION 25 20 Distribution Taken From 400 Amplifiers Distribution Taken From 104 Amplifiers Percentage of Amplifiers (%) Percentage of Amplifiers (%) 18 16 14 12 10 8 6 4 20 15 10 5 2 0 −1200 −1100 −1000 −900 −800 −700 −600 −500 −400 −300 −200 −100 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 0 Offset Voltage (µV) Offset Voltage Drift (µV/°C) G001 G002 Figure 2. Figure 3. OFFSET VOLTAGE vs TEMPERATURE OFFSET VOLTAGE vs COMMON-MODE VOLTAGE 800 400 Offset Voltage (mV) Offset Voltage (µV) 600 5 Typical Units Shown VS = ±18V 200 0 −200 −400 VCM = - 18.1V −600 −800 −50 −25 0 25 50 75 Temperature (°C) 100 125 150 Common-Mode Voltage (V) G003 Figure 4. Figure 5. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE (Upper Stage) OFFSET VOLTAGE vs POWER SUPPLY 500 VSUPPLY = ±1.35V to ± 18V 5 Typical Units Shown 5 Typical Units Shown Offset Voltage (µV) Offset Voltage (mV) 300 Normal Operation 100 −100 −300 −500 0 Common-Mode Voltage (V) Figure 6. 2 4 6 8 10 12 VSUPPLY (V) 14 16 18 20 G006 Figure 7. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: OPA170-EP 5 OPA170-EP SBOS598A – DECEMBER 2012 – REVISED DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted. IB AND IOS vs COMMON-MODE VOLTAGE INPUT BIAS CURRENT vs TEMPERATURE 3000 12 10 Input Bias Current (pA) +IB 8 IB and IOS (pA) IB+ IB− IOS 2500 6 IOS 4 -IB 2000 1500 1000 500 0 2 −500 VCM = 16.1V VCM = -18.1V 0 -20 -15 -10 0 -5 5 10 15 20 −1000 −50 −25 0 VCM (V) 150 G008 OUTPUT VOLTAGE SWING vs OUTPUT CURRENT (Maximum Supply) CMRR AND PSRR vs FREQUENCY (Referred-to Input) 140 Common-Mode Rejection Ratio (dB), Power-Supply Rejection Ratio (dB) Output Voltage (V) 125 Figure 9. 17 16 15 14.5 –14.5 –15 –40°C +25°C +125°C +150°C –16 –17 –18 120 100 80 60 40 +PSRR -PSRR CMRR 20 0 0 1 2 3 4 5 6 7 8 9 Output Current (mA) 10 1 10 100 CMRR vs TEMPERATURE 1M PSRR vs TEMPERATURE 3 Power-Supply Rejection Ratio (µV/V) VS = ±1.35V VS = ±2V VS = ±18V 20 15 10 5 0 −50 100k 10k Figure 11. 30 25 1k Frequency (Hz) G009 Figure 10. Common-Mode Rejection Ratio (µV/V) 100 Figure 8. 18 −25 0 25 50 75 Temperature (°C) 100 125 150 2 VS = 2.7V to 36V VS = 4V to 36V 1 0 −1 −2 −3 −50 G011 Figure 12. 6 25 50 75 Temperature (°C) −25 0 25 50 75 Temperature (°C) 100 125 150 G012 Figure 13. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: OPA170-EP OPA170-EP www.ti.com SBOS598A – DECEMBER 2012 – REVISED DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 0.1Hz TO 10Hz NOISE 1mV/div Voltage Noise Density (nV/ Hz) 1000 100 10 1 1 10 100 Figure 14. -120 -140 100k 10k Total Harmonic Distortion + Noise (%) Total Harmonic Distortion + Noise (%) 0.0001 1k G014 BW = 80kHz G = +1 RL = 10kW -60 0.01 -80 0.001 -100 0.0001 -120 0.00001 0.01 0.1 1 10 Total Harmonic Distortion + Noise (dB) -100 0.1 Total Harmonic Distortion + Noise (dB) 0.001 100 1M THD+N vs OUTPUT AMPLITUDE -80 VOUT = 3VRMS BW = 80kHz G = +1 RL = 10kW 0.00001 10 100k Figure 15. THD+N RATIO vs FREQUENCY 0.01 1k 10k Frequency (Hz) -140 20 Output Amplitude (VRMS) Frequency (Hz) Figure 16. Figure 17. QUIESCENT CURRENT vs TEMPERATURE QUIESCENT CURRENT vs SUPPLY VOLTAGE 140 130 VS = ±1.35V VS = ±18V 120 IQ (mA) 110 100 90 80 70 60 50 40 −50 −25 0 25 50 75 Temperature (°C) 100 125 150 G017 Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: OPA170-EP 7 OPA170-EP SBOS598A – DECEMBER 2012 – REVISED DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted. OPEN-LOOP GAIN AND PHASE vs FREQUENCY 140 120 Gain 100 50 90 40 45 30 0 -45 40 -90 20 -135 0 -180 -20 -225 -40 0.1 1 10 100 1k 10k 100k Phase (°) Phase 60 Gain (dB) 80 Gain (dB) CLOSED-LOOP GAIN vs FREQUENCY 135 10 0 G = −1 G=1 G = 10 −10 −20 -270 10M 1M 20 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) Figure 20. 10M 100M G020 Figure 21. OPEN-LOOP GAIN vs TEMPERATURE OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY 10k 3 VS = 2.7V VS = 4V 2.5 1k VS = 36V ZO (W) AOL (mV/V) 2 1.5 100 10 1 1 0.5 1m 0 -75 -50 -25 0 25 50 75 100 125 150 1 10 100 1k 10k 100k 10M Figure 22. Figure 23. SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100mV Output Step) SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100mV Output Step) W W G = +1 +18V RI = 10kW RF = 10kW ROUT W W W G = -1 +18V OPA170 RL CL -18V Figure 24. 8 1M Frequency (Hz) Temperature (°C) W W W ROUT OPA170 CL -18V Figure 25. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: OPA170-EP OPA170-EP www.ti.com SBOS598A – DECEMBER 2012 – REVISED DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted. NO PHASE REVERSAL POSITIVE OVERLOAD RECOVERY +18V OPA170 20kW 5V/div 5V/div -18V 37VPP Sine Wave (±18.5V) +18V 2kW OPA170 VOUT VIN -18V G = -10 Time (10ms/div) Time (100ms/div) Figure 26. Figure 27. NEGATIVE OVERLOAD RECOVERY SMALL-SIGNAL STEP RESPONSE (100mV) 20kW 2kW RL = 10kW CL = 10pF +18V OPA170 VOUT VIN 5V/div G = -10 20mV/div -18V +18V OPA170 -18V Time (10ms/div) RL CL Time (5ms/div) Figure 28. Figure 29. SMALL-SIGNAL STEP RESPONSE (100mV) LARGE-SIGNAL STEP RESPONSE G = +1 RL = 10kW CL = 10pF RI = 2kW RF 2V/div RL = 10kW CL = 10pF 20mV/div G = +1 = 2kW +18V OPA170 CL -18V G = -1 Time (50ms/div) Time (5ms/div) Figure 30. Figure 31. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: OPA170-EP 9 OPA170-EP SBOS598A – DECEMBER 2012 – REVISED DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted. LARGE-SIGNAL SETTLING TIME (10V Positive Step) LARGE-SIGNAL STEP RESPONSE 10 G = -1 RL = 10kW CL = 10pF 8 2V/div D From Final Value (mV) 6 4 12-Bit Settling 2 0 -2 (±1/2LSB = ±0.012%) -4 -6 -8 -10 Time (50ms/div) 0 10 20 30 40 50 60 70 80 90 100 Time (ms) Figure 32. Figure 33. LARGE-SIGNAL SETTLING TIME (10V Negative Step) 10 SHORT-CIRCUIT CURRENT vs TEMPERATURE G = -1 8 D From Final Value (mV) 6 4 12-Bit Settling ISC (mA) 2 0 -2 (±1/2LSB = ±0.012%) -4 -6 -8 -10 0 10 20 30 40 50 60 30 25 20 15 10 5 0 −5 −10 −15 −20 −25 −30 −50 ISC, Source ISC, Sink −25 0 25 50 75 Temperature (°C) 100 125 150 G034 Time (ms) Figure 34. Figure 35. MAXIMUM OUTPUT VOLTAGE vs FREQUENCY EMIRR IN+ vs FREQUENCY 15 140 VS = ±15 V 120 Maximum output range without slew−rate induced distortion 10 EMIRR IN+ (dB) Output Voltage (VPP ) 12.5 7.5 VS = ±5 V 5 2.5 0 VS = ±1.35 V 1k 10k 100 80 60 40 100k Frequency (Hz) 1M 10M 0 10M G035 Figure 36. 10 PRP = -10dBm VS = ±18V VCM = 0V 20 100M 1G 10G Frequency (Hz) Figure 37. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: OPA170-EP OPA170-EP www.ti.com SBOS598A – DECEMBER 2012 – REVISED DECEMBER 2012 APPLICATION INFORMATION The OPA170 operational amplifier provides high overall performance. This device is ideal for many general-purpose applications. The excellent offset drift of only 2µV/°C provides excellent stability over the entire temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors placed close to the device pins. In most cases, 0.1µF capacitors are adequate. OPERATING CHARACTERISTICS The OPA170 is specified for operation from 2.7V to 36V (±1.35V to ±18V). Many of the specifications apply from –40°C to +150°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. This device can operate with full rail-to-rail input 100mV beyond the positive rail, but with reduced performance within 2V of the positive rail. The typical performance in this range is summarized in Table 1. PHASE-REVERSAL PROTECTION The OPA170 has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear commonmode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input of the OPA170 prevents phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 38. +18V OPA170 GENERAL LAYOUT GUIDELINES -18V 37VPP Sine Wave (±18.5V) 5V/div For best operational performance of the device, good printed circuit board (PCB) layout practices are recommended. Low-loss, 0.1µF bypass capacitors should be connected between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to single-supply applications. Time (100ms/div) COMMON-MODE VOLTAGE RANGE The input common-mode voltage range of the OPA170 extends 100mV below the negative rail and within 2V of the positive rail for normal operation. Figure 38. No Phase Reversal Table 1. Typical Performance Range PARAMETER Input Common-Mode Voltage MIN TYP (V+) – 2 Offset voltage MAX (V+) + 0.1 UNIT V 7 mV vs Temperature 12 µV/°C Common-mode rejection 65 dB Open-loop gain 60 dB Gain-bandwidth product 0.3 MHz Slew rate 0.3 V/µs Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: OPA170-EP 11 OPA170-EP SBOS598A – DECEMBER 2012 – REVISED DECEMBER 2012 www.ti.com CAPACITIVE LOAD AND STABILITY ELECTRICAL OVERSTRESS The dynamic characteristics of the OPA170 have been optimized for common operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50Ω) in series with the output. Figure 39 and Figure 40 illustrate graphs of small-signal overshoot versus capacitive load for several values of ROUT. Also, refer to Applications Bulletin AB-028, Feedback Plots Define Op Amp AC Performance (literature number SBOA015, available for download from the TI website), for details of analysis techniques and application circuits. Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. W These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to 10mA as stated in the Absolute Maximum Ratings. Figure 41 shows how a series input resistor may be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and its value should be kept to a minimum in noise-sensitive applications. V+ G = +1 +18V IOVERLOAD 10mA max ROUT OPA170 RL W W W CL -18V OPA170 VOUT VIN 5kW Figure 41. Input Current Protection Figure 39. Small-Signal Overshoot versus Capacitive Load (100mV Output Step, G = +1) W RI = 10kW RF = 10kW G = -1 +18V W W W ROUT OPA170 CL -18V Figure 40. Small-Signal Overshoot versus Capacitive Load (100mV Output Step, G = –1) 12 An ESD event produces a short duration, highvoltage pulse that is transformed into a short duration, high-current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent it from being damaged. The energy absorbed by the protection circuitry is then dissipated as heat. When the operational amplifier connects into a circuit, the ESD protection components are intended to remain inactive and not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow occurs through ESD cells and rarely involves the absorption device. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: OPA170-EP OPA170-EP www.ti.com SBOS598A – DECEMBER 2012 – REVISED DECEMBER 2012 If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be added to the supply pins. The zener voltage must be selected such that the diode does not turn on during normal operation. However, its zener voltage should be low enough so that the zener diode conducts if the supply pin begins to rise above the safe operating supply voltage level. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: OPA170-EP 13 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) OPA170ASDRLTEP ACTIVE SOT-5X3 DRL 5 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 150 DAQ V62/12627-01XE ACTIVE SOT-5X3 DRL 5 250 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 150 DAQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of