OPA177GP

® OPA 177 OPA177 OPA 177 Precision OPERATIONAL AMPLIFIER FEATURES q LOW OFFSET VOLTAGE: 25µV max q LOW DRIFT: 0.3µV/°C q HIGH OPEN-LOOP GAIN: 130dB min q LOW QUIESCENT CURRENT: 1.5mA typ q REPLACES INDUSTRY-STANDARD OP AMPS: OP-07, OP-77, OP-177, AD707, ETC. APPLICATIONS q PRECISION INSTRUMENTATION q DATA ACQUISITION q TEST EQUIPMENT q BRIDGE AMPLIFIER q THERMOCOUPLE AMPLIFIER DESCRIPTION The OPA177 precision bipolar op amp feature very low offset voltage and drift. Laser-trimmed offset, drift and input bias current virtually eliminate the need for costly external trimming. The high performance and low cost make them ideally suited to a wide range of precision instrumentation. The low quiescent current of the OPA177 dramatically reduce warm-up drift and errors due to thermoV+ 7 Trim 1 14kΩ Trim 8 electric effects in input interconnections. It provides an effective alternative to chopper-stabilized amplifiers. The low noise of the OPA177 maintains accuracy. OPA177 performance gradeouts are available. Packaging options include 8-pin plastic DIP and SO-8 surface-mount packages. 25Ω 30Ω +In 3 500Ω VO 6 –In 2 500Ω 20µA V– 4 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1990 Burr-Brown Corporation PDS-1081E Printed in U.S.A. August, 1997 SBOS008 OPA177 SPECIFICATIONS At VS = ±15V, TA = +25°C, unless otherwise noted. OPA177F PARAMETER OFFSET VOLTAGE Input Offset Voltage Long-Term Input Offset(1) Voltage Stability Offset Adjustment Range Power Supply Rejection Ratio INPUT BIAS CURRENT Input Offset Current Input Bias Current NOISE Input Noise Voltage Input Noise Current INPUT IMPEDANCE Input Resistance INPUT VOLTAGE RANGE Common-Mode Input Range(4) Common-Mode Rejection OPEN-LOOP GAIN Large Signal Voltage Gain OUTPUT Output Voltage Swing 1Hz to 100Hz(2) 1Hz to 100Hz Differential Mode(3) Common-Mode 26 CONDITION MIN TYP 10 0.3 RP = 20kΩ VS = ±3V to ±18V ±3 125 0.3 0.5 85 4.5 45 200 ±14 140 12,000 ±14 ±13 ±12.5 60 0.3 0.6 40 3.5 1.3 60 4.5 2 1.5 ±2 150 MAX 25 MIN OPA177G TYP 20 0.4 T 120 T T T T 18.5 T T T T 6000 T T T T T T T T T T T T 2.8 ±2.8 T MAX 60 UNITS µV µV/Mo mV dB nA nA nVrms pArms MΩ GΩ V dB V/mV V V V Ω V/µs MHz mW mW mA 115 110 VCM = ±13V RL ≥ 2kΩ VO = ±10V(5) RL ≥ 10kΩ RL ≥ 2kΩ RL ≥ 1kΩ ±13 130 5110 ±13.5 ±12.5 ±12 T 115 2000 T T T Open-Loop Output Resistance FREQUENCY RESPONSE Slew Rate Closed-Loop Bandwidth POWER SUPPLY Power Consumption Supply Current RL ≥ 2kΩ G = +1 VS = ±15V, No Load VS = ±3V, No Load VS = ±15V, No Load 0.1 0.4 T T At VS = ±15V, –40°C ≤ TA ≤ +85°C, unless otherwise noted. OFFSET VOLTAGE Input Offset Voltage Average Input Offset Voltage Drift Power Supply Rejection Ratio INPUT BIAS CURRENT Input Offset Current Average Input Offset Current Drift(6) Input Bias Current Average Input Bias Current Drift(6) INPUT VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection OPEN-LOOP GAIN Large Signal Voltage Gain OUTPUT Output Voltage Swing POWER SUPPLY Power Consumption Supply Current T Same as specification for product to left. NOTES: (1) Long-Term Input Offset Voltage Stability refers to the averaged trend line of VOS vs time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically less than 2µV. (2) Sample tested. (3) Guaranteed by design. (4) Guaranteed by CMRR test condition. (5) To insure high open-loop gain throughout the ±10V output range, AOL is tested at –10V ≤ VO ≤ 0V, 0V ≤ VO ≤ +10V, and –10V ≤ VO ≤ +10V. (6) Guaranteed by end-point limits. ±13 120 2000 ±12 15 0.1 VS = ±3V to ±18V 110 120 0.5 1.5 0.5 8 2.2 40 ±4 40 40 0.3 106 20 0.7 115 T T T 15 4.5 85 ±6 60 100 1.2 µV µV/°C dB nA pA/°C nA pA/°C VCM = ±13V RL ≥ 2kΩ, VO = ±10V RL ≥ 2kΩ VS = ±15V, No Load VS = ±15V, No Load ±13.5 140 6000 ±13 60 2 75 25 T 110 1000 T T T 4000 T T T T T V dB V/mV V mW mA ® OPA177 2 PIN CONFIGURATION Top View DIP/SOIC ABSOLUTE MAXIMUM RATINGS Power Supply Voltage ....................................................................... ±22V Differential Input Voltage ................................................................... ±30V Input Voltage ....................................................................................... ±VS Output Short Circuit ................................................................. Continuous Operating Temperature: Plastic DIP (P), SO-8 (S) .............................................. –40°C to +85°C θJA (PDIP) ................................................................................. 100°C/W θJA (SOIC) ................................................................................. 160°C/W Storage Temperature: Plastic DIP (P), SO-8 (S) ............................................ –65°C to +125°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 10s) P packages ........................... +300°C (soldering, 3s) S package ............................... +260°C Offset Trim –In +In V– 1 2 3 4 8 7 6 5 Offset Trim V+ VO No Internal Connection PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) 006 006 182 TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C PRODUCT OPA177FP OPA177GP OPA177GS PACKAGE 8-Pin Plastic DIP 8-Pin Plastic DIP SO-8 Surface-Mount ELECTROSTATIC DISCHARGE SENSITIVITY Any integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. ESD can cause damage ranging from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. Burr-Brown’s standard ESD test method consists of five 1000V positive and negative discharges (100pF in series with 1.5kΩ) applied to each pin. Failure to observe proper handling procedures could result in small changes to the OPA177’s input bias current. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA177 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = ±15V, unless otherwise noted. TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY MAXIMUM VOUT vs IOUT (Negative Swing) –17.5 VS = ±18V VS = ±15V VS = ±12V 1 A = 20dB, 3Vrms, 10kΩ load –15 –12.5 THD + N (%) 0.1 VOUT (V) –10 –7.5 –5 –2.5 Noninverting Inverting 0.01 VS = ±15V 30kHz low pass filtered 0.001 1k 10k Frequency (Hz) 100k 0 0 –2 –4 –6 –IOUT (mA) –8 –10 –12 MAXIMUM VOUT vs IOUT (Positive Swing) 17.5 WARM-UP OFFSET VOLTAGE DRIFT 3 VS = ±18V 12.5 VS = ±15V 10 7.5 5 2.5 VS = ±15V 0 0 6 12 18 IOUT (mA) 24 30 36 VS = ±12V Offset Voltage Change (µV) 15 2 1 0 –1 –2 –3 0 15 30 45 60 75 90 105 120 Time from Power Supply Turn-On (s) VOUT (V) OFFSET VOLTAGE CHANGE DUE TO THERMAL SHOCK 30 Device Immersed in 70°C Inert Liquid 25 CLOSED-LOOP RESPONSE vs FREQUENCY 100 80 Closed-Loop Gain (dB) Absolute Change in Input Offset Voltage (µV) 20 15 10 Plastic DIP 5 0 0 10 20 30 40 Time (s) 50 60 70 80 60 40 20 0 –20 10 100 1k 10k 100k 1M 10M Frequency (Hz) ® OPA177 4 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±15V, unless otherwise noted. OPEN-LOOP GAIN/PHASE vs FREQUENCY 160 140 Open-Loop Gain (dB) CMRR vs FREQUENCY 0 Gain 45 Phase Shift (Degrees) 150 140 130 120 100 Phase 80 60 40 20 0 0.01 CMRR (dB) 120 110 100 90 90 135 180 0.1 1 10 100 1k 10k 100k 1M Frequency (Hz) 80 1 10 100 1k 10k 100k Frequency (Hz) POWER SUPPLY REJECTION vs FREQUENCY INPUT BIAS AND INPUT OFFSET CURRENT vs TEMPERATURE 130 Input Bias and Input Offset Current (nA) 150 2 Power Supply Rejection (dB) 1 IB I OS 110 0 90 –1 70 50 0.1 1 10 100 1k 10k Frequency (Hz) –2 –40 –15 10 35 60 85 Temperature (°C) TOTAL NOISE vs BANDWIDTH (0.1Hz to Frequency Indicated) 10 INPUT NOISE VOLTAGE DENSITY vs FREQUENCY 1k Input Noise Voltage (nV/√Hz) RS1 = RS2 = 200kΩ Thermal noise of source resistors included. RMS Noise (µV) 1 100 0.1 10 RS = 0 0.01 100 1k Bandwidth (Hz) 10k 100k 1 1 10 100 Frequency (Hz) 1k 10k ® 5 OPA177 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±15V, unless otherwise noted. MAXIMUM OUTPUT SWING vs FREQUENCY POWER CONSUMPTION vs POWER SUPPLY 100 32 Peak-to-Peak Amplitude (V) 28 24 20 16 12 8 4 0 1k 10k 100k Frequency (Hz) Power Consumption (mW) G = +1 R L = 2kΩ 10 1 1M 0 10 20 Total Supply Voltage (V) 30 40 MAXIMUM OUTPUT VOLTAGE vs LOAD RESISTANCE 20 Positive Output Negative Output Output Short-Circuit Current (mA) 40 OUTPUT SHORT-CIRCUIT CURRENT vs TIME 35 Maximum Output (V) 15 30 ISC + 10 25 5 20 ISC – 0 100 1k Load Resistance to Ground ( Ω) 10k 15 0 1 2 3 4 Time from Output Being Shorted (min) ® OPA177 6 APPLICATIONS INFORMATION The OPA177 is unity-gain stable, making it easy to use and free from oscillations in the widest range of circuitry. Applications with noisy or high impedance power supply lines may require decoupling capacitors close to the device pins. In most cases 0.1µF ceramic capacitors are adequate. The OPA177 has very low offset voltage and drift. To achieve highest performance, circuit layout and mechanical conditions must be optimized. Offset voltage and drift can be degraded by small thermoelectric potentials at the op amp inputs. Connections of dissimilar metals will generate thermal potential which can mask the ultimate performance of the OPA177. These thermal potentials can be made to cancel by assuring that they are equal in both input terminals. 1. Keep connections made to the two input terminals close together. 2. Locate heat sources as far as possible from the critical input circuitry. 3. Shield the op amp and input circuitry from air currents such as cooling fans. OFFSET VOLTAGE ADJUSTMENT The OPA177 has been laser-trimmed for low offset voltage and drift so most circuits will not require external adjustment. Figure 1 shows the optional connection of an external potentiometer to adjust offset voltage. This adjustment should not be used to compensate for offsets created elsewhere in a system since this can introduce excessive temperature drift. INPUT PROTECTION The inputs of the OPA177 are protected with 500Ω series input resistors and diode clamps as shown in the simplified circuit diagram. The inputs can withstand ±30V differential inputs without damage. The protection diodes will, of course, conduct current when the inputs are overdriven. This may disturb the slewing behavior of unity-gain follower applications, but will not damage the op amp. 2 VIN 3 OPA177 V+ 1 8 20kΩ VOUT Trim Range is approximately ±3.0mV FIGURE 1. Optional Offset Nulling Circuit. NOISE PERFORMANCE The noise performance of the OPA177 is optimized for circuit impedances in the range of 2kΩ to 50kΩ. Total noise in an application is a combination of the op amp’s input voltage noise and input bias current noise reacting with circuit impedances. For applications with higher source impedance, the OPA627 FET-input op amp will generally provide lower noise. For very low impedance applications, the OPA27 will provide lower noise. INPUT BIAS CURRENT CANCELLATION The input stage base current of the OPA177 is internally compensated with an equal and opposite cancellation current. The resulting input bias current is the difference between the input stage base current and the cancellation current. This residual input bias current can be positive or negative. When the bias current is cancelled in this manner, the input bias current and input offset current are approximately the same magnitude. As a result, it is not necessary to balance the DC resistance seen at the two input terminals (Figure 2). A resistor added to balance the input resistances may actually increase offset and noise. R2 R2 R1 Op Amp R1 OPA177 RB = R2 || R1 No bias current cancellation resistor needed (a) (b) Conventional op amp with external bias current cancellation resistor. OPA177 with no external bias current cancellation resistor. FIGURE 2. Input Bias Current Cancellation. ® 7 OPA177 PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 PACKAGING INFORMATION Orderable Device OPA177FP OPA177FPG4 OPA177GP OPA177GPG4 OPA177GS OPA177GS/2K5 OPA177GS/2K5E4 OPA177GSE4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type PDIP PDIP PDIP PDIP SOIC SOIC SOIC SOIC Package Drawing P P P P D D D D Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 8 50 50 50 50 100 2500 2500 100 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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