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Design
OPA187, OPA2187, OPA4187
SBOS807E – DECEMBER 2016 – REVISED MAY 2020
OPAx187 0.001-µV/°C Drift, Low Power, Rail-to-Rail Output
36-V Operational Amplifiers Zero-Drift Series
1 Features
3 Description
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The OPAx187 series operational amplifiers use autozeroing techniques to simultaneously provide lowoffset voltage (1 µV), and near zero drift over time
and temperature. These miniature, high-precision,
low-quiescent current amplifiers offer high-input
impedance and rail-to-rail output swing within 5 mV of
the rails into high-impedance loads. The input
common-mode range includes the negative rail.
Either single or dual supplies can be used in the
range of 4.5 V to 36 V (±2.25 V to ±18 V).
1
Low offset voltage: 10 µV (maximum)
Zero drift: 0.001 µV/°C
Low noise: 15 nV/√Hz
PSRR: 160 dB
CMRR: 140 dB
AOL: 160 dB
Quiescent Current: 100 µA
Wide supply voltage: ±2.25 V to ±18 V
Rail-to-rail output operation
Input includes negative rail
Low bias current: 100 pA (typical)
EMI filtered inputs
Microsize packages
The single version OPAx187 device is available in
microsize 8-pin VSSOP, 5-pin SOT-23, and 8-pin
SOIC packages. The dual version is offered in 8-pin
VSSOP and 8-pin SOIC packages. The quad version
is offered in 14-pin SOIC, 14-pin TSSOP, and 16-pin
WQFN packages. All versions are specified for
operation from –40°C to +125°C.
2 Applications
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Device Information(1)
Analog input module
Mixed module (AI, AO, DI, DO)
Flow transmitter
Pressure transmitter
Test and measurement
Semiconductor test
Semiconductor manufacturing
Process analytics (pH, gas, concentration, force,
and humidity)
PART NUMBER
OPA187
OPA2187
OPA4187
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SOT-23 (5)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.70 mm × 3.90 mm
TSSOP (14)
5.00 mm × 4.40 mm
WQFN (16)
4.00 mm × 4.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
OPAx187 Offers Precision Low-Side Current Measurement Capability
VSUPPLY
+
Load
100 k
GND
VSUPPLY
±
100
+
RSHUNT
VOUT
OPA187
100
±
GND
I
I
100 k
GND
G = 1000 ‡ 5SHUNT ‡ ,
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
OPA187, OPA2187, OPA4187
SBOS807E – DECEMBER 2016 – REVISED MAY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information: OPA187 .................................. 7
Thermal Information: OPA2187 ................................ 7
Thermal Information: OPA4187 ................................ 7
Electrical Characteristics: High-Voltage Operation .. 8
Electrical Characteristics: Low-Voltage Operation... 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 21
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Applications ................................................ 22
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
29
29
29
29
29
29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2018) to Revision E
•
Page
Changed OPA4187 RUM (WQFN) package from preview to production data (active) ......................................................... 1
Changes from Revision C (December 2018) to Revision D
Page
•
Changed OPA4187 SOIC and TSSOP packages from product preview to production data ................................................. 1
•
Changed offset drift (high and low supply) max to ±15nV/°C................................................................................................. 9
Changes from Revision B (October 2018) to Revision C
•
Page
First release of production OPA187 SOIC device .................................................................................................................. 1
Changes from Revision A (July 2017) to Revision B
Page
•
Changed OPA187 SOIC status to preview ............................................................................................................................ 1
•
Changed OPA4187 SOIC, TSSOP and WQFN status to preview ......................................................................................... 1
•
Changed offset drift (high supply) typical from ±5 nV/℃ to ±1 nV/℃ and max from ±50 nV/℃ to ±20 nV/℃ ...................... 8
•
Changed input bias current max (high supply) from ±5 nA to ±7.5 nA .................................................................................. 8
•
Changed input offset current max (high supply) from ±5 nA to ±14.5 nA .............................................................................. 8
•
Changed offset drift (low supply) typical from ±5 nV/℃ to ±1 nV/℃ and max from ±50 nV/℃ to ±20 nV/℃ ........................ 9
•
Changed Offset Voltage Production Distribution figure........................................................................................................ 11
2
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SBOS807E – DECEMBER 2016 – REVISED MAY 2020
Changes from Original (December 2016) to Revision A
Page
•
Deleted VSON package option from the Description ............................................................................................................. 1
•
Deleted VSON package option from the Device Information table ........................................................................................ 1
•
Added WQFN package option to the Device Information table.............................................................................................. 1
•
Deleted OPA187 DRG package option from Pin Configuration and Functions ..................................................................... 4
•
Added WQFN package to Pin Configuration and Functions .................................................................................................. 5
Copyright © 2016–2020, Texas Instruments Incorporated
Product Folder Links: OPA187 OPA2187 OPA4187
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OPA187, OPA2187, OPA4187
SBOS807E – DECEMBER 2016 – REVISED MAY 2020
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5 Pin Configuration and Functions
OPA187: DBV Package
5-Pin SOT-23
Top View
OUT
1
V±
2
5
3
NC
1
±IN
2
+IN
3
V±
4
8
NC
±
7
V+
+
6
OUT
5
NC
V+
±
+
+IN
OPA187: D and DGK Packages
8-Pin SOIC and 8-pin VSSOP
Top View
4
±IN
Not to scale
Not to scale
Pin Functions: OPA187
PIN
NAME
I/O
DESCRIPTION
DBV
D and DGK
+IN
3
3
I
Non-inverting input
–IN
4
2
I
Inverting input
NC
—
1, 5, 8
—
No connection (can be left floating)
OUT
1
6
O
Output signal
V+
5
7
—
Positive (highest) supply voltage
V–
2
4
—
Negative (lowest) supply voltage
OPA2187: D and DGK Packages
8-Pin SOIC and 8-Pin VSSOP
Top View
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
Not to scale
Pin Functions: OPA2187
PIN
I/O
DESCRIPTION
NAME
D and DGK
+IN A
3
I
Non-inverting input, channel A
–IN A
2
I
Inverting input, channel A
+IN B
5
I
Non-inverting input, channel B
–IN B
6
I
Inverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V+
8
—
Positive (highest) supply voltage
V–
4
—
Negative (lowest) supply voltage
4
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SBOS807E – DECEMBER 2016 – REVISED MAY 2020
OPA4187: D and PW Packages
14-pin SOIC and 14-Pin TSSOP
Top View
OPA4187: RUM Package
16-pin WQFN
Top View
OUT A
1
14
OUT D
±IN A
2
13
±IN D
+IN A
3
12
+IN D
V+
4
11
V±
+IN B
5
10
+IN C
±IN B
6
9
±IN C
OUT B
7
8
OUT C
Not to scale
Pin Functions: OPA4187
PIN
I/O
DESCRIPTION
NAME
D and PW
RUM
+IN A
3
2
I
Non-inverting input, channel A
–IN A
2
1
I
Inverting input, channel A
+IN B
5
4
I
Non-inverting input, channel B
–IN B
6
5
I
Inverting input, channel B
+IN C
10
9
I
Non-inverting input, channel C
–IN C
9
8
I
Inverting input, channel C
+IN D
12
11
I
Non-inverting input, channel D
–IN D
13
12
I
Inverting input, channel D
OUT A
1
15
O
Output, channel A
OUT B
7
6
O
Output, channel B
OUT C
8
7
O
Output, channel C
OUT D
14
14
O
Output, channel D
V+
4
3
—
Positive (highest) supply voltage
V–
11
10
—
Negative (lowest) supply voltage
NC
—
13, 16
—
No internal connection (can be left floating)
Copyright © 2016–2020, Texas Instruments Incorporated
Product Folder Links: OPA187 OPA2187 OPA4187
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OPA187, OPA2187, OPA4187
SBOS807E – DECEMBER 2016 – REVISED MAY 2020
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Supply, VS = (V+) – (V–)
Signal input pin (2)
Voltage
Signal output pin
Current
(V–) – 0.5
(3)
–
(V ) + 0.5
–10
10
mA
Signal output pin (3)
–55
55
mA
Continuous
Continuous
–55
150
Junction, TJ
150
Storage, Tstg
(2)
(3)
(4)
V
+
(V ) – 0.5
Operating range, TA
(1)
(V+) + 0.5
Signal input pin (2)
Output short-circuit (4)
Temperature
UNIT
40
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to ±10 mA or less.
Output terminals are diode-clamped to the power-supply rails. Output signals that can swing more than 0.5 V beyond the supply rails
should be current limited to ±55 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
(V+) – (V–)
Supply voltage
TA
Operating temperature
6
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NOM
MAX
UNIT
4.5 (±2.25)
36 (±18)
V
–40
150
°C
Copyright © 2016–2020, Texas Instruments Incorporated
Product Folder Links: OPA187 OPA2187 OPA4187
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SBOS807E – DECEMBER 2016 – REVISED MAY 2020
6.4 Thermal Information: OPA187
OPA187
THERMAL METRIC (1)
5 PINS
8 PINS
UNIT
DBV (SOT-23)
DGK (VSSOP)
D (SOIC)
RθJA
Junction-to-ambient thermal resistance
273.8
159
100.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
126.8
37
42.4
°C/W
RθJB
Junction-to-board thermal resistance
85.9
49
41.0
°C/W
ψJT
Junction-to-top characterization parameter
10.9
1.2
4.8
°C/W
ψJB
Junction-to-board characterization parameter
84.9
77.1
40.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2187
OPA2187
THERMAL METRIC (1)
8 PINS
UNIT
DGK (VSSOP)
D (SOIC)
RθJA
Junction-to-ambient thermal resistance
159
100.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
37
42.4
°C/W
RθJB
Junction-to-board thermal resistance
49
41.0
°C/W
ψJT
Junction-to-top characterization parameter
1.2
4.8
°C/W
ψJB
Junction-to-board characterization parameter
77.1
40.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4187
OPA4187
THERMAL METRIC
(1)
14 PINS
16 PINS
PW (TSSOP)
D (SOIC)
RUM (WQFN)
UNIT
RθJA
Junction-to-ambient thermal resistance
107.8
83.8
35.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.6
70.7
32.7
°C/W
RθJB
Junction-to-board thermal resistance
52.6
59.5
12.9
°C/W
ψJT
Junction-to-top characterization parameter
1.5
11.6
0.3
°C/W
ψJB
Junction-to-board characterization parameter
51.6
37.7
12.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
3.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2016–2020, Texas Instruments Incorporated
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OPA187, OPA2187, OPA4187
SBOS807E – DECEMBER 2016 – REVISED MAY 2020
6.7
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Electrical Characteristics: High-Voltage Operation
at TA = +25°C, VS = ±4 V to ±18 V (VS = +8 V to +36 V), RL = 10 kΩ connected to VS / 2 (1), and VCM = VOUT = VS / 2 (1) (unless
otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
PSRR
Power-supply rejection ratio
TA = –40°C to +125°C
±1
±10
±0.001
±0.015
μV/°C
±1
μV/V
VS = 4.5 V to 36 V, TA = –40°C to
+125°C
±0.01
VCM = VS / 2
±100
μV
INPUT BIAS CURRENT
IB
Input bias current
IOS
TA = –40°C to +125°C
±100
Input offset current
TA = –40°C to +125°C
±350
pA
±7.5
nA
±500
pA
±14.5
nA
NOISE
en
Input voltage noise
in
f = 0.1 Hz to 10 Hz
0.4
µVPP
f = 0.1 Hz to 10 Hz
60
nVrms
Input voltage noise density
f = 1 kHz
20
nV/√Hz
Input current noise density
f = 1 kHz
160
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(V–) – 0.1
(V+) – 2
V
(V–) – 0.1 V < VCM < (V+) – 2 V, VS =
±18 V
126
140
dB
(V–) < VCM < (V+) – 2 V, VS = ±18 V,
TA = –40°C to +125°C
130
145
dB
INPUT IMPEDANCE
ZID
Differential
100 || 6
MΩ || pF
ZIC
Common-mode
6 || 4.2
1012 Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
TA = –40°C to +125°C, VS = ±4 V to ±18
V, (V–) + 0.3 V < VO < (V+) – 0.3 V, RL =
10 kΩ
132
160
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
Settling time
tOR
Overload recovery time
VIN × G = VS
Total harmonic distortion + noise
1 kHz, G = +1, VOUT = 3.5 VRMS, No
Load
THD+N
550
kHz
VO = 10-V step, G = +1
0.2
V/μs
0.1%
VS = ±18 V, G = 1, 10-V step
46
μs
0.01%
VS = ±18 V, G = 1, 10-V step
48
μs
8
μs
0.035%
OUTPUT
VS = ±4 V to ±18 V, No Load
Voltage output swing from rail
VS = ±4 V to ±18 V, RL = 10 kΩ
VS = ±4 V to ±18 V, RL = 10 kΩ, TA =
–40°C to +125°C
ISC
Short-circuit current
RO
Open-loop output resistance
CLOAD
Capacitive load drive
5
15
75
100
100
125
mV
VS = ±18 V, Sinking
–30
mA
VS = ±18 V, Sourcing
+30
mA
1.4
kΩ
f = 550 kHz, IO = 0, See Figure 21
See Typical Characteristics
POWER SUPPLY
IQ
(1)
8
Quiescent current (per amplifier)
VS = ±4 V to VS = ±18 V
100
IO = 0 mA, TA = –40°C to +125°C
145
μA
150
μA
VS / 2 = midsupply.
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6.8
SBOS807E – DECEMBER 2016 – REVISED MAY 2020
Electrical Characteristics: Low-Voltage Operation
at TA = +25°C, VS = ±2.25 V to < ±4 V (VS = +4.5 V to < +8 V), RL = 10 kΩ connected to VS / 2 (1), and VCM = VOUT = VS / 2 (1)
(unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
PSRR
Power-supply rejection ratio
±1
±15
±0.001
±0.015
μV/°C
VS = 4.5 V to 36 V,
TA = –40°C to +125°C
±0.01
±1
μV/V
VCM = VS / 2
±100
±350
pA
±5
nA
±500
pA
±5
nA
TA = –40°C to +125°C
μV
INPUT BIAS CURRENT
IB
Input bias current
IOS
TA = –40°C to +125°C
±100
Input offset current
TA = –40°C to +125°C
NOISE
en
Input voltage noise
in
f = 0.1 Hz to 10 Hz
0.4
µVPP
f = 0.1 Hz to 10 Hz
60
nVrms
Input voltage noise density
f = 1 kHz
20
nV/√Hz
Input current noise density
f = 1 kHz
160
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
(V–) – 0.1
Common-mode rejection ratio
(V+) – 2
V
(V–) – 0.1 V < VCM < (V+) – 2 V, VS =
±2.25 V
114
130
dB
(V–) < VCM < (V+) – 2 V, VS = ±2.25 V,
TA = –40°C to +125°C
120
137
dB
INPUT IMPEDANCE
ZID
Differential
100 || 6
MΩ || pF
ZIC
Common-mode
6 || 4.2
1012 Ω || pF
OPEN-LOOP GAIN
AOL
TA = –40°C to +125°C, VS = ±2.25 V
to ±4 V, (V–) + 0.3 V < VO < (V+) – 0.3
V, RL = 10 kΩ
Open-loop voltage gain
120
140
dB
550
kHz
0.2
V/μs
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
VO = 1-V step, G = +1
tOR
Overload recovery time
VIN × G = VS
THD+N
Total harmonic distortion + noise
1 kHz, G = +1, VOUT = 1 Vrms, No Load
8
μs
0.05%
OUTPUT
VS = ±2.25 V to ±4 V, No Load
Voltage output swing from rail
ISC
Short-circuit current
RO
Open-loop output resistance
CLOAD
Capacitive load drive
5
15
VS = ±2.25 V to ±4 V, RL = 10 kΩ
15
25
VS = ±2.25 V to ±4 V, RL = 10 kΩ, TA =
–40°C to +125°C
15
30
mV
VS = ±2.25, Sinking
–20
mA
VS = ±2.25, Sourcing
+20
mA
1.4
kΩ
f = 550 kHz, IO = 0, See Figure 21
See Typical Characteristics
POWER SUPPLY
IQ
(1)
VS = ±2.25 V to VS = ±4 V
Quiescent current (per amplifier)
IO = 0 mA, TA = –40°C to +125°C
100
145
μA
150
μA
VS / 2 = midsupply.
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6.9 Typical Characteristics
Table 1. Typical Characteristic Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature
Figure 3
Offset Voltage vs Common-Mode Voltage
Figure 4
Offset Voltage vs Power Supply
Figure 5
Open-Loop Gain and Phase vs Frequency
Figure 6
Closed-Loop Gain vs Frequency
Figure 7
IB vs Common-Mode Voltage
Figure 8
Input Bias Current vs Temperature
Figure 9
Output Voltage Swing vs Output Current
Figure 10
CMRR and PSRR vs Frequency (Referred-to-Input)
Figure 11
CMRR vs Temperature
Figure 12
PSRR vs Temperature
Figure 13
0.1-Hz to 10-Hz Noise
Figure 14
Input Voltage Noise Spectral Density vs Frequency
Figure 15
THD+N Ratio vs Frequency
Figure 16
THD+N vs Output Amplitude
Figure 17
Quiescent Current vs Supply Voltage
Figure 18
Quiescent Current vs Temperature
Figure 19
Open-Loop Gain vs Temperature
Figure 20
Open-Loop Output Impedance vs Frequency
Figure 21
Small-Signal Overshoot vs Capacitive Load (G = 1) (10-mV Output Step)
Figure 22
No Phase Reversal
Figure 23
Positive Overload Recovery
Figure 24
Negative Overload Recovery
Figure 25
Small-Signal Step Response (10 mV)
Figure 26, Figure 27
Large-Signal Step Response
Figure 28, Figure 29
Large-Signal Settling Time (10-V Positive Step)
Figure 30
Large-Signal Settling Time (10-V Negative Step)
Figure 31
Short-Circuit Current vs Temperature
Figure 32
Maximum Output Voltage vs Frequency
Figure 33
Crosstalk vs Frequency
Figure 34
EMIRR IN+ vs Frequency
Figure 35
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
15%
20
18
Total Amplifiers (%)
Amplifiers (%)
16
14
12
10
8
6
10%
5%
4
2
0
-0.015
10
8
5
3
0
-3
-5
-8
-10
0
-0.01
-0.005
0
0.005
Offset Voltage Drift (PV/qC)
0.01
0.015
Offset Voltage (µV)
C002
Figure 2. Offset Voltage Drift Distribution
10
8
8
6
6
4
4
2
2
VOS ( V)
VOS ( V)
Figure 1. Offset Voltage Production Distribution
10
0
±2
0
±2
±4
±4
±6
±6
±8
±8
±10
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
±20
Open-loop Gain (dB)
100
VOS ( V)
2
1
0
±1
10
15
20
C003
VS = ± 2.25 V
135
Open-loop Gain
90
60
40
45
20
0
±20
±4
±40
0
1
±5
Phase
80
±3
10
100
8.0 10.0 12.0 14.0 16.0 18.0 20.0
VSUPPLY (V)
5
Open-loop Phase (ƒ)
120
3
6.0
0
±5
Figure 4. Offset Voltage vs Common-Mode Voltage
4
4.0
±10
VCM (V)
140
2.0
±15
C001
Figure 3. Offset Voltage vs Temperature
0.0
VCM = 16 V
±10
150
5
±2
VCM = ±18.1 V
1k
10k
100k
1M
-45
10M
Frequency (Hz)
C001
C001
Figure 5. Offset Voltage vs Power Supply
Figure 6. Open-Loop Gain and Phase vs Frequency
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
350
G = +1
G= +10
G= -1
20
250
Input Bias Current (pA)
Closed-loop Gain (dB)
40
0
-20
150
50
±50
±150
±250
-40
±350
100
1k
10k
100k
1M
10M
Frequency (Hz)
±20
±15
±10
0
±5
5
10
15
VCM (V)
C004
Figure 7. Closed-Loop Gain vs Frequency
20
C001
Figure 8. IB vs Common-Mode Voltage
15.0
3
2.5
Input Bias Current (nA)
12.5
2
1.5
10.0
VO (V)
1
7.5
5.0
0.5
125°C
0
25°C
±40°C
-0.5
-1
-1.5
2.5
-2
ios
-2.5
0.0
-3
±75
±50
0
±25
25
50
75
100
125
Temperature (ƒC)
150
0
30
40
50
Figure 10. Output Voltage Swing vs Output Current
0.001
Common-Mode Rejection Ratio (dB)
140
120
100
80
60
CMRR
40
+PSRR
20
±PSRR
170
0.01
160
150
0.1
140
130
120
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Figure 11. CMRR and PSRR vs Frequency
(Referred-to-Input)
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10M
Common-Mode Rejection Ratio ( V/V)
160
0
60
C001
180
180
Common-Mode Rejection Ratio (dB)
20
IO (mA)
Figure 9. Input Bias Current vs Temperature
12
10
C001
1
±75 ±50 ±25
0
25
50
75
100 125 150
Temperature (ƒC)
C004
C001
Figure 12. CMRR vs Temperature
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
0.001
170
0.01
160
150
0.1
140
130
120
Voltage (100 nV/div)
Power-Supply Rejection Ratio (µV/V)
Power-Supply Rejection Ratio (dB)
180
Time (1 s/div)
1
±75 ±50 ±25
0
25
50
75
C017
100 125 150
Temperature (ƒC)
C001
Figure 14. 0.1-Hz to 10-Hz Noise
Total Harmonic Distortion + Noise (%)
1000
10
100
10
-40
G = -1, 10k- Load
G = -1, 2k- Load
G = -1, 600- Load
G = +1, 10k- Load
G = +1, 2k- Load
G = +1, 600- Load
1
-60
-80
0.1
-100
0.01
-120
-140
20k
0.001
20
1
1
10
100
1k
10k
Figure 16. THD+N Ratio vs Frequency
-80
0.01
G = -1, 10k- Load
G = -1, 2k- Load
G = -1, 600- Load
G = +1, 10k- Load
G = +1, 2k- Load
G = +1, 600- Load
0.1
-100
-120
1
10
Output Amplitude (VRMS)
120
100
IQ (µA)
0.1
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
140
-60
1
0.01
C004
C002
Figure 15. Input-Referred Voltage Noise Spectral Density vs
Frequency (G = +101)
0.0001
0.001
2k
Frequency (Hz)
100k
Frequency (Hz)
0.001
200
Total Harmonic Distortion + Noise (dB)
Voltage Noise Spectral Density (nV/¥Hz)
Figure 13. PSRR vs Temperature
80
60
40
20
0
C004
0
2
4
6
8
10
12
14
16
18
Supply Voltage (V)
Figure 17. THD+N vs Output Amplitude
20
C001
Figure 18. Quiescent Current vs Supply Voltage
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
150
0.0001
200
VS = ± 2.25 V
DC Open-Loop Gain (dB)
IQ (µA)
90
60
30
0
190
VS = ± 18 V
0.001
180
170
160
0.01
150
140
±75
±50
0
±25
25
50
75
100
125
Temperature (ƒC)
150
0.1
±75 ±50 ±25
0
25
50
75
100 125 150
Temperature (ƒC)
C001
Figure 19. Quiescent Current vs Temperature
C001
Figure 20. Open-Loop Gain vs Temperature
10000
70
1000
60
RISO = 0 Ÿ
Overshoot (%)
Open-loop Output Impedance (Ÿ)
DC Open-Loop Gain (µV/V)
120
100
10
1
RISO = 25 Ÿ
RISO = 50 Ÿ
50
40
30
20
10
0.1
10
100
1k
10k
100k
1M
Frequency (Hz)
10M
10
100M
100
Capacitive Load (pF)
C001
Figure 21. Open-Loop Output Impedance vs Frequency
C004
Figure 22. Small-Signal Overshoot vs
Capacitive Load (G = +1) (10-mV Output Step)
VIN
1 V/div
Voltage (5 V/div)
VOUT
VIN
VOUT
Time (40 ms/div)
Time (2 µs/div)
C017
Figure 23. No Phase Reversal
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Figure 24. Positive Overload Recovery
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
5 V/div
2 mV/div
VIN
VOUT
VOUT
VIN
Time (2 µs/div)
Time (1 µs/div)
C017
C017
Figure 25. Negative Overload Recovery
Figure 26. Small-Signal Step Response
(100 mV)
2 mV/div
2.5 V/div
VOUT
VIN
VOUT
VIN
Time (2.5 µs/div)
Time (25 µs/div)
C017
C017
Figure 27. Small-Signal Step Response
(100 mV)
Figure 28. Large-Signal Step Response
VOUT
VIN
2.5 V/div
Output Voltage (1 mV/div)
0.01% Settling = “1mV
t0 = 45 µs
Time (25 µs/div)
45
50
Figure 29. Large-Signal Step Response
55
60
Time (5 µs/div)
C017
65
C017
Figure 30. Large-Signal Settling Time
(10-V Positive Step)
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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
60
0.01% Settling = “1mV
Output Voltage (1 mV/div)
50
ISC (mA)
30
10
t0 = 45 µs
50
0
55
60
65
Time (5 µs/div)
±75
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C001
Figure 32. Short-Circuit Current vs Temperature
40
-60
Maximum output voltage without
slew-rate induced distortion.
35
±50
C017
Figure 31. Large-Signal Settling Time
(10-V Negative Step)
VS = ±18V
-80
Crosstalk (dB)
Output Voltage (VPP)
ISC, Source
20
45
30
ISC, Sink
40
25
20
15
VS = ±4V
-100
-120
10
-140
5
0
VS = ±2.25V
100
1k
10k
100k
Frequency (Hz)
-160
1M
1k
10k
100k
Frequency (Hz)
C001
Figure 33. Maximum Output Voltage vs Frequency
1M
C004
Figure 34. Crosstalk vs Frequency
180
160
EMIRR IN+ (dB)
140
120
100
80
60
40
20
0
10M
100M
1000M
Frequency (Hz)
C004
Figure 35. EMIRR IN+ vs Frequency
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7 Detailed Description
7.1 Overview
The OPA187, OPA2187, and OPA4187 (OPAx187) operational amplifiers combine precision offset and drift with
excellent overall performance, making these devices an an excellent choice for many precision applications. The
precision offset drift of only 0.001 µV/°C provides stability over the entire temperature range. In addition, these
devices offer excellent overall performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications
with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most
cases, 0.1-µF capacitors are adequate.
The OPAx187 is part of a family of zero-drift, low-power, rail-to-rail output operational amplifiers. These devices
operate from 4.5 V to 36 V, are unity-gain stable, and are designed for a wide range of general-purpose
applications. The zero-drift architecture provides ultra-low input offset voltage, and near-zero input offset voltage
drift over temperature and time. This choice of architecture also offers outstanding ac performance, such as ultralow broadband noise and zero flicker noise.
7.2 Functional Block Diagram
The functional block diagram shows a representation of the proprietary OPAx187 architecture. Functional blocks
CHOP1 and CHOP2 operate such that the non-idealities of GM1 are cancelled while the input signal is left inphase. The integrated notch filter of the OPAx187 family suppresses most of the auto-zero amplifier carrier.
V+
C2
CHOP1
GM1
Notch
Filter
CHOP2
GM2
GM3
OUT
+IN
-IN
C1
GM_FF
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7.3 Feature Description
The OPAx187 are unity-gain stable and free from unexpected output phase reversal. These devices use a
proprietary, periodic autocalibration technique to provide ultra-low input offset voltage and near zero input offset
voltage drift over temp and temperature. For lowest offset voltage and precision performance, optimize circuit
layout and mechanical conditions. Avoid temperature gradients that create thermoelectric (Seebeck) effects in
the thermocouple junctions formed from connecting dissimilar conductors. Cancel these thermally-generated
potentials by making sure they are equal on both input pins. Other layout and design considerations include:
Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
Thermally isolate components from power supplies or other heat sources.
Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Follow these guidelines to reduce the likelihood of junctions being at different temperatures, which may cause
thermoelectric voltages of 0.1 µV/°C or higher, depending on the materials used.
7.3.1 Operating Characteristics
The OPAx187 are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
7.3.2 Phase-Reversal Protection
The OPAx187 have an internal phase-reversal protection. Many op amps exhibit a phase reversal when the input
is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPAx187 input prevents phase reversal with excessive common-mode
voltage. Instead, the output limits into the appropriate rail. Figure 36 shows this performance.
Voltage (5 V/div)
VIN
VOUT
Time (40 ms/div)
C017
Figure 36. No Phase Reversal
7.3.3 Input Bias Current Clock Feedthrough
Zero-drift amplifiers, such as the OPAx187, use switching on the inputs to correct for the intrinsic offset and drift
of the amplifier. Charge injection from the integrated switches on the inputs can introduce very short transients in
the input bias current of the amplifier. An extremely short duration prevents these pulses from being amplified;
however, the pulses may be coupled to the output of the amplifier through the feedback network. The most
effective method to prevent transients in the input bias current from producing additional noise at the amplifier
output is to use a low-pass filter such as an RC network.
7.3.4 Internal Offset Correction
The OPAx187 op amps use an auto-calibration technique with a time-continuous 125-kHz op amp in the signal
path. This amplifier is zero-corrected every 22 μs using a proprietary technique. At power-up, the amplifier
requires approximately 100 μs to achieve the specified VOS accuracy. This design has no aliasing or flicker noise.
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Feature Description (continued)
7.3.5 EMI Rejection
The OPAx187 devices use integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
from sources such as wireless communications and densely-populated boards with a mix of analog signal chain
and digital components. EMI immunity can be improved with circuit design techniques; the OPAx187 benefit from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 37 shows the results of this testing on the OPAx187. Table 2 lists the EMIRR IN+ values for the OPAx187
at particular frequencies commonly encountered in real-world applications. Applications listed in Table 2 may be
centered on or operated near the particular frequency shown. Detailed information can also be found in the EMI
Rejection Ratio of Operational Amplifiers application report, available for download from www.ti.com.
180
160
EMIRR IN+ (dB)
140
120
100
80
60
40
20
0
10M
100M
1000M
Frequency (Hz)
C004
Figure 37. EMIRR Testing
Table 2. OPAx187 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
81.8 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
102.7 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
115.4 dB
®
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth , mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
150.7 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
142.0 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
173.8 dB
5 GHz
7.3.6 Capacitive Load and Stability
The dynamic characteristics of the OPAx187 are optimized for a range of common operating conditions. The
combination of low closed-loop gain and high capacitive loads decreases the amplifier phase margin and can
lead to gain peaking or oscillations. As a result, larger capacitive loads must be isolated from the output. The
simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with
the output. Figure 38 illustrates small-signal overshoot versus capacitive load for several values of ROUT. Also, for
details of analysis techniques and application circuits, refer to the Feedback Plots Define Op Amp AC
Performance application report, available for download from www.ti.com.
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G = 1, RL = 10 kΩ, 10-mV Output Step
70
RISO = 0 Ÿ
Overshoot (%)
60
RISO = 25 Ÿ
RISO = 50 Ÿ
50
40
30
20
10
10
100
Capacitive Load (pF)
C004
Figure 38. Small-Signal Overshoot vs Capacitive Load
7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful.
See Figure 39 for an illustration of the ESD circuits contained in the OPAx187 (indicated by the dashed-line
area). The ESD protection circuitry involves several current-steering diodes connected from the input and output
pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device internal
to the op amp. This protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the op amp core to prevent damage. The energy absorbed by the protection
circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device may activate. The
absorption device has a trigger, or threshold voltage, that is greater than the normal operating voltage of the
OPAx187, but less than the device breakdown voltage level. When this threshold is exceeded, the absorption
device quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (see Figure 39), the ESD protection components are
intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits may be biased on, and conduct
current. Any such current flow occurs through steering-diode paths, and rarely involves the absorption device.
Figure 39 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data-sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
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Another common question involves what happens to the amplifier if an input signal is applied to the input while
power supply +VS or –VS is at 0 V. Again, this question depends on the supply characteristic while at 0 V, or at a
level less than the input signal amplitude. If the supplies are high impedance, then the operational amplifier
supply current may be supplied by the input source through the current-steering diodes. This state is not a
normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance, then
the current through the steering diodes can become quite high. The current level depends on the ability of the
input source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external transient voltage
suppressor (TVS) diodes to the supply pins, as shown in Figure 39. Select the TVS voltage so that the diode
does not turn on during normal operation. However, make sure that the TVS voltage is low enough so that the
TVS diode conducts if the supply pin exceeds the safe operating supply voltage level.
TVS
(See Note 2)
RF
V+
RI
+VS
ESD CurrentSteering Diodes
IN
(See Note 3)
RS
+IN
Op Amp
Core
OUT
Edge-Triggered ESD
Absorption Circuit
ID
VIN
(See
Note 1)
RL
V±
VS
TVS
(See Note 2)
Copyright © 2016, Texas Instruments Incorporated
NOTE 1: VIN = +VS + 500 mV.
NOTE 2: TVS: +VS(max) > VTVSBR (min) > +VS.
NOTE 3: Suggested value is approximately 1 kΩ.
Figure 39. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
The OPAx187 input pins are protected from excessive differential voltage with back-to-back diodes, as shown in
Figure 39. In most circuit applications, the input protection circuitry has no consequence. However, in low-gain or
G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier
cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias
condition, the input signal current must be limited to 10 mA or less. If the input signal current is not inherently
limited, an input series resistor can be used to limit the signal input current. This input series resistor degrades
the low-noise performance of the OPAx187. Figure 39 shows an example configuration that implements a
current-limiting feedback resistor.
7.4 Device Functional Modes
The OPAx187 have a single functional mode and are operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx187 is 36 V (±18 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx187 operational amplifier family combines precision offset and drift with excellent overall performance,
making this device an excellent choice for many precision applications. The precision offset drift of only 0.001
µV/°C provides stability over the entire temperature range. In addition, the device pairs excellent CMRR, PSRR,
and AOL dc performance with outstanding low-noise operation. As with all amplifiers, applications with noisy or
high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF
capacitors are adequate.
The following application examples highlight only a few of the circuits where the OPAx187 can be used.
8.2 Typical Applications
8.2.1 High-Side Voltage-to-Current (V-I) Converter
The circuit shown in Figure 40 is a high-side voltage-to-current (V-I) converter. The converter translates an input
voltage of 0 V to 2 V into an output current of 0 mA to 100 mA. Figure 41 shows the measured transfer function
for this circuit. The low offset voltage and offset drift of the OPA2187 facilitate excellent dc accuracy for the
circuit.
V+
RS2
470
RS3
4.7
IRS2
IRS3
R4
10 k
VRS2
VRS3
C7
2200 pF
R5
330
Q2
+
R3
200
+
Q1
C6
1000 pF
VIN
+
R2
10
±
VRS1
RS1
2k
VLOAD
RLOAD
IRS1
ILOAD
Copyright © 2016, Texas Instruments Incorporated
Figure 40. High-Side Voltage-to-Current (V-I) Converter
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Typical Applications (continued)
8.2.1.1 Design Requirements
The design requirements are:
• Supply voltage: 5 V DC
• Input: 0 V to 2 V DC
• Output: 0 mA to 100 mA DC
8.2.1.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three
current sensing resistors, RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that
flows through the first stage of the design. The current gain from the first stage to the second stage is based on
the relationship between RS2 and RS3.
This application benefits from an operational amplifier with low offset voltage, low temperature drift, and rail-torail output. The OPAx187 CMOS operational amplifiers are high-precision, ultra-low offset, ultra-low drift
amplifier, optimized for wide-voltage, single-supply operation, with an output swing to within 5 mV of the positive
rail. The OPAx187 family uses chopping techniques to provide low initial offset voltage and near-zero drift over
time and temperature. Low offset voltage and low drift reduce the offset error in the system, making this device
appropriate for precise dc control. The rail-to-rail output stage of the OPAx187 makes sure that the output swing
of the operational amplifier is able to fully control the gate of the MOSFET devices within the supply rails.
A detailed error analysis, design procedure, and additional measured results are given in reference design
TIPD102, a step-by-step process to design a High-Side Voltage-to-Current (V-I) Converter.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision
Design TIPD102, High-Side Voltage-to-Current (V-I) Converter.
8.2.1.3 Application Curve
Figure 41 shows the measured transfer function for the high-side voltage-to-current converter shown in
Figure 40.
0.1
Load
Output Current (A)
0.075
0.05
0.025
0
0
0.5
1
Input Voltage (V)
1.5
2
D001
Figure 41. Measured Transfer Function for High-Side V-I Converter
8.2.2 Discrete INA + Attenuation for ADC With 3.3-V Supply
NOTE
The TINA-TI files shown in the following sections require that either the TINA software
(from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software
from the TINA-TI web folder.
Copyright © 2016–2020, Texas Instruments Incorporated
Product Folder Links: OPA187 OPA2187 OPA4187
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Figure 42 shows an example of how the OPA187 is used as a high-voltage, high-impedance front-end for a
precision, discreet instrumentation amplifier with attenuation. The INA159 provides the attenuation that allows
this circuit to easily interface with 3.3-V or 5-V analog-to-digital converters (ADCs). Click the following link to
download the TINA-TI file: Discrete INA.
15 V
VOUTP
OPA187
5V
VDIFF / 2
- 15 V
RP
10 NŸ
Ref 1
VCM
10V
Ref 2
RG
500 Ÿ
+
INA159
VOUT(1)
Sense
15 V
±VDIFF / 2
OPA187
RN
10 NŸ
VOUTN
15 V
Copyright © 2016, Texas Instruments Incorporated
(1)
VOUT = VDIFF × (41 / 5) + (Ref 1) / 2.
Figure 42. Discrete INA + Attenuation for ADC With a 3.3-V Supply
8.2.3 Bridge Amplifier
Figure 43 shows the basic configuration for a bridge amplifier. Click the following link to download the TINA-TI
file: Bridge Amplifier Circuit.
15 V
R
15 V
R
R
R
R
±
VOUT
OPA187
+
R
VREF
Copyright © 2016, Texas Instruments Incorporated
Figure 43. Bridge Amplifier
8.2.4 Low-Side Current Monitor
Figure 44 shows the OPA187 configured in a low-side, current-sensing application. The load current (ILOAD)
creates a voltage drop across the shunt resistor (RSHUNT). This voltage is amplified by the OPA187, with a gain of
201. The load current is set from 0 A to 500 mA, and corresponds to an output voltage range from 0 V to 10 V.
The output range can be adjusted by changing the shunt resistor or gain of the configuration. Click the following
link to download the TINA-TI file: Current-Sensing Circuit.
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SBOS807E – DECEMBER 2016 – REVISED MAY 2020
V
Load
15 V
+
VOUT = ILOAD * RSHUNT(1 + RF / RIN)
VOUT
OPA187
±
ILOAD
RSHUNT
100 m
RIN
VOUT / ILOAD= 1 V / 49.75 mA
RF
100
20 k
CF
150
pF
Copyright © 2016, Texas Instruments Incorporated
Figure 44. Low-Side Current Monitor
8.2.5 Programmable Power Supply
Figure 45 shows the OPA187 configured as a precision, programmable power supply using the 16-bit, voltage
output DAC8581 and the OPA548 high-current amplifier. This application amplifies the digital-to-analog converter
(DAC) voltage by a value of five, and handles a large variety of capacitive and current loads. The OPA187 in the
front-end provides precision and low drift across a wide range of inputs and conditions. Click the following link to
download the TINA-TI file: Programmable Power-Supply Circuit.
C1
500 nF
R1
10 k
R4
40 k
R2
1k
GND
C2
500 nF
+30V
+15V
±
OPA187
+
DAC8581
±
R3
10 k
OPA548
+
VOUT
Output = ± 25V
±30V
±15V
Input = ± 5V
Copyright © 2016, Texas Instruments Incorporated
Figure 45. Programmable Power Supply
Copyright © 2016–2020, Texas Instruments Incorporated
Product Folder Links: OPA187 OPA2187 OPA4187
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8.2.6 RTD Amplifier With Linearization
See the Analog Linearization Of Resistance Temperature Detectors technical brief, for an in-depth analysis of
Figure 46. Click the following link to download the TINA-TI file: RTD Amplifier With Linearization.
15 V
(5 V)
Out
REF5050
In
1 µF
1 µF
R2
49.1 kŸ
R3
60.4 kŸ
R1
4.99 kŸ
OPA187
V OUT
0°C = 0 V
200°C = 5 V
R5
(1)
105.8 kŸ
RTD
Pt100
R4
1 kŸ
Copyright © 2016, Texas Instruments Incorporated
(1)
R5 provides positive-varying excitation to linearize output.
Figure 46. RTD Amplifier With Linearization
9 Power Supply Recommendations
The OPAx187 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. The Typical Characteristics presents parameters that can exhibit significant variance with
regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 40 V can permanently damage the device (see the
Absolute Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Low-ESR, 0.1-µF ceramic bypass capacitors must be connected between each supply pin and ground; place
the capacitors as close to the device as possible. A single bypass capacitor from V+ to ground is applicable
to single-supply applications.
• To reduce parasitic coupling, run the input traces as far away from the supply lines as possible.
• A ground plane helps distribute heat and reduces EMI noise pickup.
• Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VOUT
VS±
GND
VOUT
Use low-ESR, ceramic
bypass capacitor
Ground (GND) plane on another layer
Copyright © 2017, Texas Instruments Incorporated
Figure 47. Layout Example
Copyright © 2016–2020, Texas Instruments Incorporated
Product Folder Links: OPA187 OPA2187 OPA4187
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models, in addition to a
range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that lets users format results various ways. Virtual instruments offer users the ability to select input
waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts which offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
11.1.1.3 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets users create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web-based tool from the WEBENCH Design Center, WEBENCH® Filter Designer lets users
design, optimize, and simulate complete multistage active filter solutions within minutes.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Operational Amplifier Gain Stability, Part 3: AC Gain-Error Analysis technical brief
• Texas Instruments, Operational Amplifier Gain Stability, Part 2: DC Gain-Error Analysis technical brief
• Texas Instruments, Using Infinite-Gain, MFB Filter Topology In Fully Differential Active Filters technical brief
• Texas Instruments, Op Amp Performance Analysis application bulletin
• Texas Instruments, Single-Supply Operation of Operational Amplifiers application bulletin
• Texas Instruments, Tuning in Amplifiers application bulletin
• Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes application report
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SBOS807E – DECEMBER 2016 – REVISED MAY 2020
11.3 Related Links
Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE AND BUY
TECHNICAL
DOCUMENTS
TOOLS AND
SOFTWARE
SUPPORT AND
COMMUNITY
OPA187
Click here
Click here
Click here
Click here
Click here
OPA2187
Click here
Click here
Click here
Click here
Click here
OPA4187
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on the Alert me button to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
DesignSoft, TINA are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2016–2020, Texas Instruments Incorporated
Product Folder Links: OPA187 OPA2187 OPA4187
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA187ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA187
OPA187IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1CUV
OPA187IDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1CUV
OPA187IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1D96
OPA187IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1D96
OPA187IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA187
OPA2187ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2187
OPA2187IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
16TV
OPA2187IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
16TV
OPA2187IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2187
OPA4187ID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4187
OPA4187IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4187
OPA4187IPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4187
OPA4187IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4187
OPA4187IRUMR
ACTIVE
WQFN
RUM
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OPA
4187
OPA4187IRUMT
ACTIVE
WQFN
RUM
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OPA
4187
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2021
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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