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OPA188
SBOS642C – MARCH 2013 – REVISED JANUARY 2020
OPA188 Precision, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift
Operational Amplifier
1 Features
3 Description
•
•
•
The OPA188 operational amplifier uses TI's
proprietary auto-zeroing techniques to provide low
offset voltage (25-μV maximum) and near zero-drift
over time and temperature. This miniature, highprecision, low-quiescent current amplifier offers high
input impedance and rail-to-rail output swing within 15
mV of the rails. The input common-mode range
includes the negative rail. Either single or dual
supplies can be used in the range from 4 V to 36 V
(±2 V to ±18 V).
1
•
•
•
•
•
•
•
•
Low offset voltage: 25 μV (maximum)
Zero drift: 0.03 μV/°C
Low noise: 8.8 nV/√Hz
– 0.1-Hz to 10-Hz Noise: 0.25 µVPP
Excellent dc precision:
– PSRR: 142 dB
– CMRR: 146 dB
– Open-loop gain: 136 dB
Gain bandwidth: 2 MHz
Quiescent current: 510 μA (Maximum)
Wide supply range: ±2 V to ±18 V
Rail-to-rail output
Input includes negative rail
RFI filtered inputs
MicroSIZE packages
The single version is available in the MicroSIZE SOT23-5, MSOP-8, and SO-8 packages. All versions are
specified for operation from –40°C to +125°C.
Device Information(1)
PART NUMBER
OPA188
2 Applications
•
•
•
•
•
•
•
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SOT-23 (5)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Weight scale
Analog input module
Flow transmitter
Battery test
DC power supply, ac source, electronic load
Data acquisition (DAQ)
Semiconductor test
Auto-Zero Technology Provides Ultra-Low Temperature Drift
145
OPA188 Zero-Drift Architecture
Precision Laser Trim Architecture
Offset Voltage (mV)
125
105
85
65
45
25
5
-55
-35
-15
5
25
45
65
85
105
125
Temperature (°C)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA188
SBOS642C – MARCH 2013 – REVISED JANUARY 2020
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
1
1
1
2
3
6
7
Pin Configuration and Functions ......................... 3
Specifications......................................................... 4
5.1 Portfolio Comparison................................................. 3
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: High-Voltage Operation ..
Electrical Characteristics: Low-Voltage Operation...
Typical Characteristics: Table of Graphs ..................
Typical Characteristics ..............................................
4
4
4
4
5
6
7
8
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 19
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Applications ................................................ 20
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2016) to Revision C
•
Page
Deleted automotive (Q1) device test conditions from plots in this commercial device data sheet ....................................... 8
Changes from Revision A (March 2013) to Revision B
Page
•
Added Device Information, Device Comparison, ESD Ratings, and Recommended Operating Conditions tables, and
Detailed Description, Applications and Implementation, Power Supply Recommendations, Layout, Device and
Documentation Support, and Mechanical, Packaging, and Orderable Information sections ................................................. 1
•
Deleted Package Information table; all information now available in the package option addendum at the end of the
data sheet .............................................................................................................................................................................. 3
•
Changed input bias current maximum value for over-temperature test condition in Electrical Characteristics ..................... 5
•
Changed input offset current maximum value for over-temperature test condition in Electrical Characteristics ................... 5
•
Changed quiescent current values in Electrical Characteristics............................................................................................. 5
•
Changed input bias current maximum value for over-temperature test condition in Electrical Characteristics ..................... 6
•
Changed input offset current maximum value for over-temperature test condition in Electrical Characteristics ................... 6
•
Changed quiescent current maximum values in Electrical Characteristics ............................................................................ 6
Changes from Original (March 2013) to Revision A
•
2
Page
Changed document status to Production Data....................................................................................................................... 1
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SBOS642C – MARCH 2013 – REVISED JANUARY 2020
5 Device Comparison Table
5.1 Portfolio Comparison
Table 1. Zero-Drift Amplifier Portfolio
PRODUCT
OFFSET VOLTAGE
(µV, maximum)
OFFSET VOLTAGE DRIFT
(µV/°C, maximum)
BANDWIDTH
(MHz)
INPUT VOLTAGE NOISE
(µVPP, f = 0.1 Hz to 10 Hz)
OPA188 (4 V to 36 V)
±25
±0.085
2
0.25
OPA333 (5 V)
±10
±0.05
0.35
1.1
OPA378 (5 V)
±50
±0.25
0.9
0.4
OPA735 (12 V)
±5
±0.05
1.6
2.5
OPA2188 (4 V to 36 V)
±25
±0.085
2
0.25
OPA2333 (5 V)
±10
±0.05
0.35
1.1
OPA2378 (5 V)
±50
±0.25
0.9
0.4
OPA2735 (12 V)
±5
±0.05
1.6
2.5
OPA4330 (5 V)
±50
±0.25
0.35
1.1
VERSION
Single
Dual
Quad
6 Pin Configuration and Functions
OPA188 D and DGK Packages
8-Pin SOIC and 8-Pin VSSOP
Top View
1
8
NC
-IN
2
7
V+
+IN
3
6
OUT
V-
4
5
NC
NC
(1)
(1)
OPA188 DBV Package
5-Pin SOT-23
Top View
OUT
1
V-
2
+IN
3
5
V+
4
-IN
NC = no connection.
Pin Functions
PIN
NAME
I/O
DESCRIPTION
D, DGK
DBV
+IN
3
3
I
Noninverting input
–IN
2
4
I
Inverting input
NC
1, 5, 8
—
—
No internal connection (can be left floating)
OUT
6
1
O
Output
V+
7
5
—
Positive (highest) power supply
V–
4
2
—
Negative (lowest) power supply
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SBOS642C – MARCH 2013 – REVISED JANUARY 2020
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply
Signal input pins
(2)
Signal input pins
(2)
40
(V–) – 0.5
±0.7
±10
–55
(3)
(4)
150
Junction, TJ
150
Storage, Tstg
(2)
mA
Continuous
Operating (4), TA
(1)
V
(V+) + 0.5
Differential
Output short-circuit (3)
Temperature
UNIT
±20
Single supply
Voltage
Current
MAX
Split supply
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current-limited to 10 mA or less.
Short-circuit to ground, V-, or V+.
Provided device does not exceed maximum junction temperature (TJ) at any time.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Operating voltage range
TA
Specified temperature range
Split supply
Single supply
NOM
MAX
±2
±18
4
36
–40
125
UNIT
V
°C
7.4 Thermal Information
OPA188
THERMAL METRIC (1)
D (SO)
DBV (SOT23)
DGK (MSOP)
UNIT
8 PINS
5 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
122.0
158.8
180.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
68.5
60.7
67.9
°C/W
RθJB
Junction-to-board thermal resistance
63.5
44.8
102.1
°C/W
ψJT
Junction-to-top characterization parameter
13.7
1.6
10.4
°C/W
ψJB
Junction-to-board characterization parameter
62.8
44.2
100.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5
SBOS642C – MARCH 2013 – REVISED JANUARY 2020
Electrical Characteristics: High-Voltage Operation
at TA = +25°C, VS = ±4 V to ±18 V (VS = 8 V to 36 V), RL = 10 kΩ connected to VS / 2 (1), and VCM = VOUT = VS / 2 (1) (unless
otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
PSRR
Power-supply rejection ratio
TA = –40°C to +125°C
VS = 4 V to 36 V, TA = –40°C to +125°C
Long-term stability (2)
±6
±25
±0.03
±0.085
μV/°C
±0.075
±0.3
μV/V
μV
4
μV
INPUT BIAS CURRENT
IB
VCM = VS / 2
Input bias current
IOS
±160
TA = –40°C to +125°C
±320
Input offset current
TA = –40°C to +125°C
±1400
pA
±18
nA
±2800
pA
±6
nA
NOISE
en
f = 0.1 Hz to 10 Hz
250
nVPP
f = 0.1 Hz to 10 Hz
40
nVrms
Input voltage noise density
f = 1 kHz
8.8
nV/√Hz
Input current noise density
f = 1 kHz
7
fA/√Hz
Input voltage noise
in
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
TA = –40°C to +125°C
V–
(V+) – 1.5
V
(V–) < VCM < (V+) – 1.5 V
120
134
dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V,
VS = ±18 V
130
146
dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V,
VS = ±18 V, TA = –40°C to +125°C
120
126
dB
INPUT IMPEDANCE
ZID
Differential
100 || 6
MΩ || pF
ZIC
Common-mode
6 || 9.5
1012 Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 0.5 V < VO < (V+) – 0.5 V
130
136
dB
(V–) + 0.5 V < VO < (V+) – 0.5 V,
TA = –40°C to +125°C
120
126
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
2
MHz
G = +1
0.8
V/μs
0.1%
VS = ±18 V, G = 1, 10-V step
20
μs
0.01%
VS = ±18 V, G = 1, 10-V step
27
μs
1
μs
tS
Settling time
tOR
Overload recovery time
VIN × G = VS
THD+N
Total harmonic distortion + noise
1 kHz, G = 1, VOUT = 1 Vrms
0.0001%
OUTPUT
No load
Voltage output swing from rail
ISC
Short-circuit current
RO
Open-loop output resistance
CLOAD
Capacitive load drive
6
15
mV
RL = 10 kΩ
220
250
mV
TA = –40°C to +125°C
310
350
mV
Sinking
–18
mA
16
mA
Sourcing
f = 1 MHz, IO = 0
120
Ω
1
nF
POWER SUPPLY
IQ
(1)
(2)
Quiescent current (per amplifier)
VS = ±4 V to VS = ±18 V
IO = 0 mA, TA = –40°C to +125°C
450
510
μA
600
μA
VS / 2 = midsupply.
1000-hour life test at 125°C demonstrated randomly distributed variation in the range of measurement limits—approximately 4 μV.
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SBOS642C – MARCH 2013 – REVISED JANUARY 2020
7.6
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Electrical Characteristics: Low-Voltage Operation
at TA = 25°C, VS = ±2 V to < ±4 V (VS = 4 V to < 8 V), RL = 10 kΩ connected to VS / 2 (1), and VCM = VOUT = VS / 2 (1) (unless
otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
PSRR
Power-supply rejection ratio
Long-term stability
±6
±25
TA = –40°C to +125°C
±0.03
±0.085
μV/°C
VS = 4 V to 36 V,
TA = –40°C to +125°C
0.075
0.3
μV/V
(2)
4
μV
μV
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
±160
TA = –40°C to +125°C
±320
TA = –40°C to +125°C
±1400
pA
±18
nA
±2800
pA
±6
nA
NOISE
en
f = 0.1 Hz to 10 Hz
250
nVPP
f = 0.1 Hz to 10 Hz
40
nVrms
Input voltage noise density
f = 1 kHz
8.8
nV/√Hz
Input current noise density
f = 1 kHz
7
fA/√Hz
Input voltage noise
in
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
TA = –40°C to +125°C
V–
(V+) – 1.5
V
(V–) < VCM < (V+) – 1.5 V
106
114
dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V,
VS = ±2 V
114
120
dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V,
VS = ±2 V, TA = –40°C to +125°C
110
120
dB
INPUT IMPEDANCE
ZID
Differential
100 || 6
MΩ || pF
ZIC
Common-mode
6 || 9.5
1012 Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 0.5 V < VO < (V+) – 0.5 V,
RL = 5 kΩ
110
120
dB
(V–) + 0.5 V < VO < (V+) – 0.5 V
120
130
dB
(V–) + 0.5 V < VO < (V+) – 0.5 V,
TA = –40°C to +125°C
110
120
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
G = +1
tOR
Overload recovery time
VIN × G = VS
THD+N
Total harmonic distortion + noise
1 kHz, G = 1, VOUT = 1 Vrms
2
MHz
0.8
V/μs
1
μs
0.0001%
OUTPUT
No load
Voltage output swing from rail
ISC
Short-circuit current
RO
Open-loop output resistance
CLOAD
Capacitive load drive
6
15
mV
RL = 10 kΩ
220
250
mV
TA = –40°C to +125°C
310
350
mV
Sinking
–18
mA
16
mA
Sourcing
f = 1 MHz, IO = 0
120
Ω
1
nF
POWER SUPPLY
IQ
(1)
(2)
6
Quiescent current (per amplifier)
VS = ±2 V to VS = ±4 V
IO = 0 mA, TA = –40°C to +125°C
425
485
μA
575
μA
VS / 2 = midsupply.
1000-hour life test at 125°C demonstrated randomly distributed variation in the range of measurement limits—approximately 4 μV.
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7.7 Typical Characteristics: Table of Graphs
7.7.1 Table of Graphs
Table 2. Typical Characteristic Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature
Figure 3
Offset Voltage vs Common-Mode Voltage
Figure 4, Figure 5
Offset Voltage vs Power Supply
Figure 6
Open-Loop Gain and Phase vs Frequency
Figure 7
Closed-Loop Gain vs Frequency
Figure 8
IB and IOS vs Common-Mode Voltage
Figure 9
Input Bias Current vs Temperature
Figure 10
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 11
CMRR and PSRR vs Frequency (Referred-to-Input)
Figure 12
CMRR vs Temperature
Figure 13, Figure 14
PSRR vs Temperature
Figure 15
0.1-Hz to 10-Hz Noise
Figure 16
Input Voltage Noise Spectral Density vs Frequency
Figure 17
THD+N Ratio vs Frequency
Figure 18
THD+N vs Output Amplitude
Figure 19
Quiescent Current vs Supply Voltage
Figure 20
Quiescent Current vs Temperature
Figure 21
Open-Loop Gain vs Temperature
Figure 22
Open-Loop Output Impedance vs Frequency
Figure 23
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 24, Figure 25
No Phase Reversal
Figure 26
Positive Overload Recovery
Figure 27
Negative Overload Recovery
Figure 28
Small-Signal Step Response (100 mV)
Figure 29, Figure 30
Large-Signal Step Response
Figure 31, Figure 32
Large-Signal Settling Time (10-V Positive Step)
Figure 33
Large-Signal Settling Time (10-V Negative Step)
Figure 34
Short-Circuit Current vs Temperature
Figure 35
Maximum Output Voltage vs Frequency
Figure 36
EMIRR IN+ vs Frequency
Figure 37
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7.8 Typical Characteristics
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
40
Data Taken From 3 Unique Fab Lots
Data Taken From 3 Unique Fab Lots
Percentage of Amplifiers (%)
16
14
12
10
8
6
4
35
30
25
20
15
10
5
2
Figure 1. Offset Voltage Production Distribution
5 Typical Units Shown
VS = ±18 V
VOS (mV)
-10
-10
-55
-35
-15
5
25
45
65
85
105
-15
-2.5
125
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
VCM (V)
Temperature (°C)
Figure 3. Offset Voltage vs Temperature
Figure 4. Offset Voltage vs Common-Mode Voltage
15
5 Typical Units Shown
VS = ±18 V
5 Typical Units Shown
VSUPPLY = ±2 V to ±18 V
10
5
VOS (mV)
5
VOS (mV)
0.09
0
-5
-15
0
0
-5
-5
-10
-10
-15
-15
-20
-15
-10
-5
0
5
10
15
20
0
VCM (V)
2
4
6
8
10
12
14
16
18
20
VSUPPLY (V)
Figure 5. Offset Voltage vs Common-Mode Voltage
8
0.08
5
-5
10
0.07
5 Typical Units Shown
VS = ±2 V
10
0
15
0.06
Figure 2. Offset Voltage Drift Distribution
15
5
VOS (mV)
0.05
Offset Voltage Drift (mV/°C)
15
10
0.04
0.01
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
18
20
Offset Voltage (mV)
0.1
0
0
0.03
Percentage of Amplifiers (%)
18
0.02
20
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Figure 6. Offset Voltage vs Power Supply
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Typical Characteristics (continued)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
140
25
0
GBW = 2MHz
Dominant Pole @7mHz
120
Gain
20
Phase
90
60
40
10
Gain (dB)
80
Phase (ƒ)
Gain (dB)
15
45
100
5
0
-5
135
20
-10
0
180
10M
±20
1
10
100
1k
10k
100k
1M
G = 10
G = +1
G = -1
-15
-20
10k
C007
100k
1M
10M
Frequency (Hz)
Figure 7. Open-Loop Gain and Phase vs Frequency
Figure 8. Closed-Loop Gain vs Frequency
4000
500
IB+
IB-
300
IOS
IB-
3000
IOS
Input Bias Current (pA)
IB and IOS (pA)
IB+
400
200
100
0
-100
2000
1000
0
-1000
-200
-2000
-300
-20
-15
-10
0
-5
5
10
15
-55
20
-35
-15
25
45
65
85
105
125
Figure 10. Input Bias Current vs Temperature
Figure 9. IB and IOS vs Common-Mode Voltage
160
(V+) + 2
(V+) + 1
(V+)
(V+) - 1
(V+) - 2
(V+) - 3
(V+) - 4
(V-) + 4
(V-) + 3
(V-) + 2
(V-) + 1
(V-)
(V-) - 1
(V-) - 2
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
Output Voltage (V)
5
Temperature (°C)
VCM (V)
-40°C
+25°C
+125°C
140
120
100
80
60
40
+PSRR
-PSRR
CMRR
20
0
0
2
4
6
8
10
12
14
16
18
20
22
24
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Output Current (mA)
Figure 11. Output Voltage Swing vs
Output Current (Maximum Supply)
Figure 12. CMRR and PSRR vs Frequency
(Referred-to-Input)
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Typical Characteristics (continued)
40
Common-Mode Rejection Ratio (mV/V)
Common-Mode Rejection Ratio (mV/V)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
(V-) < VCM < (V+) - 1.5 V
35
(V-) + 0.5 V < VCM < (V+) - 1.5 V
30
VSUPPLY = ±2 V
25
20
15
10
5
0
8
(V-) < VCM < (V+) - 1.5 V
7
(V-) + 0.5 V < VCM < (V+) - 1.5 V
6
VSUPPLY = ±18 V
5
4
3
2
1
0
-55
-35
-15
5
25
45
65
85
105
125
-55
-35
-15
5
25
45
65
85
105
Temperature (°C)
Temperature (°C)
Figure 13. CMRR vs Temperature
Figure 14. CMRR vs Temperature
125
5 Typical Units Shown
VSUPPLY = ±2 V to ±18 V
0.8
0.6
+3*sigma
0.4
50 nV/div
Power-Supply Rejection Ratio (mV/V)
1
0.2
0
-0.2
-0.4
-0.6
-3*sigma
-0.8
3*Sigma Noise = 172 nVPP
Peak-to-Peak Noise = 250 nV
-1
-55
-35
-15
5
25
45
65
85
105
Time (1 s/div)
125
Temperature (°C)
C016
Figure 15. PSRR vs Temperature
Figure 16. 0.1-Hz to 10-Hz Noise
Total Harmonic Distortion + Noise (%)
0.01
10
1
0.1
1
10
100
1k
10k
100k
0.001
-100
0.0001
-120
G = +1, RL = 10 kW
G = -1, RL = 10 kW
0.00001
10
Frequency (Hz)
100
1k
10k
-140
20k
Frequency (Hz)
Figure 17. Input Voltage Noise Spectral Density vs
Frequency
10
-80
VOUT = 1 VRMS
BW = 80 kHz
Total Harmonic Distortion + Noise (dB)
Voltage Noise Density (nV/ÖHz)
100
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Figure 18. THD+N Ratio vs Frequency
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Typical Characteristics (continued)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
0.01
-80
0.001
-100
0.0001
-120
G = +1, RL = 10 kW
G = -1, RL = 10 kW
0.00001
0.01
0.5
0.48
0.46
0.44
IQ (mA)
Total Harmonic Distortion + Noise (%)
-60
BW = 80 kHz
Total Harmonic Distortion + Noise (dB)
0.1
1
10
0.4
0.38
0.36
0.34
0.32
-140
0.1
0.42
Specified Supply-Voltage Range
0.3
0
20
4
8
12
3
0.5
VS = ±2 V
28
32
36
VSUPPLY = 36 V, RL = 10 kW
2.5
0.44
2
AOL (mV/V)
IQ (mA)
24
VSUPPLY = 4 V, RL = 10 kW
VS = ±18 V
0.46
20
Figure 20. Quiescent Current vs Supply Voltage
Figure 19. THD+N vs Output Amplitude
0.48
16
Supply Voltage (V)
Output Amplitude (VRMS)
0.42
0.4
0.38
1.5
1
0.36
0.34
0.5
0.32
0
0.3
-55
-35
-15
5
25
45
65
85
105
125
-55
-35
-15
5
25
45
65
85
105
125
Temperature (°C)
Temperature (°C)
Figure 21. Quiescent Current vs Temperature
Figure 22. Open-Loop Gain vs Temperature
40
10k
RL = 10 kW
35
RISO = 0 W
30
Overshoot (%)
ZO (W)
1k
100
10
RISO = 25 W
25
RISO = 50 W
20
15
G = +1
+18 V
RISO
10
Device
1
-18 V
5
RL
CL
0
0.1
1
10
100
1k
10k
100k
1M
10M
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Frequency (Hz)
Figure 23. Open-Loop Output Impedance vs Frequency
Figure 24. Small-Signal Overshoot vs
Capacitive Load (100-mV Output Step)
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Typical Characteristics (continued)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
40
RISO = 0 W
35
Device
RISO = 50 W
30
25
-18 V
37 VPP
Sine Wave
(±18.5 V)
5 V/div
Overshoot (%)
+18 V
RISO = 25 W
20
15
RI = 10 kW
10
RF = 10 kW
G = -1
+18 V
RISO
VIN
VOUT
Device
5
CL
RL = RF = 10 kW
-18 V
0
0
100 200 300 400 500 600 700 800 900 1000
Time (100 ms/div)
Capacitive Load (pF)
Figure 25. Small-Signal Overshoot vs
Capacitive Load (100-mV Output Step)
Figure 26. No Phase Reversal
VIN
VOUT
20 kW
20 kW
+18 V
Device
5 V/div
5 V/div
2 kW
VOUT
VIN
TOR
-18 V
2 kW
+18 V
TOR
VOUT
Device
VIN
G = -10
-18 V
G = -10
VOUT
VIN
Time (5 ms/div)
Time (5 ms/div)
Figure 27. Positive Overload Recovery
Figure 28. Negative Overload Recovery
+18 V
RL = RF = 2 kW
CL = 10 pF
20 mV/div
20 mV/div
RL = 10 kW
CL = 10 pF
G = +1
RI
= 2 kW
RF
= 2 kW
+18 V
Device
Device
-18 V
RL
CL
CL
-18 V
G = -1
Time (20 ms/div)
Time (1 ms/div)
Figure 29. Small-Signal Step Response
(100 mV)
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Figure 30. Small-Signal Step Response
(100 mV)
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Typical Characteristics (continued)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
G = +1
RL = 10 kW
CL = 10 pF
5 V/div
5 V/div
G = -1
RL = 10 kW
CL = 10 pF
Time (50 ms/div)
Time (50 ms/div)
Figure 31. Large-Signal Step Response
Figure 32. Large-Signal Step Response
10
G = -1
8
6
4
12-Bit Settling
2
0
-2
(±1/2 LSB = ±0.024%)
-4
-6
-8
Output D From Final Value (mV)
Output D From Final Value (mV)
10
-10
G = -1
8
6
4
12-Bit Settling
2
0
-2
(±1/2 LSB = ±0.024%)
-4
-6
-8
-10
0
10
20
30
40
50
60
0
10
20
Time (ms)
30
40
50
60
Time (ms)
Figure 33. Large-Signal Settling Time
(10-V Positive Step)
Figure 34. Large-Signal Settling Time
(10-V Negative Step)
30
15
20
12.5
Output Voltage (VPP)
VS = ±15 V
ISC (mA)
10
ISC, Source
0
ISC, Sink
-10
10
Maximum output voltage without
slew-rate induced distortion.
7.5
VS = ±5 V
5
2.5
-20
VS = ±2.25 V
0
-30
-55
-35
-15
5
25
45
65
85
105
125
1k
10k
100k
1M
10M
Frequency (Hz)
Temperature (°C)
Figure 35. Short-Circuit Current vs Temperature
Figure 36. Maximum Output Voltage vs Frequency
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Typical Characteristics (continued)
at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
160
140
EMIRR IN+ (dB)
120
100
80
60
40
20
0
10M
100M
1G
10G
Frequency (Hz)
Figure 37. EMIRR IN+ vs Frequency
14
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8 Detailed Description
8.1 Overview
The OPA188 operational amplifier combines precision offset and drift with excellent overall performance, making
this device an excellent choice for many precision applications. The precision offset drift of only 0.085 µV/°C
provides stability over the entire temperature range. In addition, this device offers excellent overall performance
with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power
supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
The OPA188 device is part of a family of zero-drift, low-power, rail-to-rail output operational amplifiers. These
devices operate from 4 V to 36 V, are unity-gain stable, and are designed for a wide range of general-purpose
applications. The zero-drift architecture provides ultra-low input offset voltage and near-zero input offset voltage
drift over temperature and time. This choice of architecture also offers outstanding ac performance, such as ultralow broadband noise and zero flicker noise.
8.2 Functional Block Diagram
Figure 38 shows a representation of the proprietary OPA188 architecture. Table 3 lists the active and passive
component counts for this device. The component count allows for accurate reliability calculations.
V+
C2
CHOP1
GM1
Notch
Filter
CHOP2
GM2
GM3
OUT
+IN
-IN
C1
GM_FF
Copyright © 2017, Texas Instruments Incorporated
V-
Figure 38. Functional Block Diagram
Table 3. Component Count
COMPONENT
COUNT
Transistors
636
Diodes
5
Resistors
41
Capacitors
72
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8.3 Feature Description
The OPA188 is unity-gain stable and free from unexpected output phase reversal. This device uses a
proprietary, periodic zero-drift technique to provide low input offset voltage and very low input offset voltage drift
over temperature. For lowest offset voltage and precision performance, optimize circuit layout and mechanical
conditions. Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple
junctions formed from connecting dissimilar conductors. Cancel these thermally-generated potentials by ensuring
the potentials are equal on both input pins. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield the operational amplifier and input circuitry from air currents, such as cooling fans.
Follow these guidelines to reduce the likelihood of junctions being at different temperatures, which may cause
thermoelectric voltages of 0.1 µV/°C or higher, depending on the materials used.
8.3.1 Operating Characteristics
The OPA188 is specified for operation from 4 V to 36 V (±2 V to ±18 V). Many specifications apply from –40°C to
+125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are
presented in Typical Characteristics.
8.3.2 Phase-Reversal Protection
The OPA188 has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is
driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits
when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into
the opposite rail. The OPA188 input prevents phase reversal with excessive common-mode voltage. Instead, the
output limits into the appropriate rail; Figure 39 shows this performance.
+18 V
Device
5 V/div
-18 V
37 VPP
Sine Wave
(±18.5 V)
VIN
VOUT
Time (100 ms/div)
Figure 39. No Phase Reversal
8.3.3 Input Bias Current Clock Feedthrough
Zero-drift amplifiers (such as the OPA188) use switching on the inputs to correct for the intrinsic offset and drift of
the amplifier. Charge injection from the integrated switches on the inputs can introduce very short transients in
the input bias current of the amplifier. The extremely short duration of these pulses prevents the device from
being amplified. However, the devices may be coupled to the output of the amplifier through the feedback
network. The most effective method to prevent transients in the input bias current from producing additional noise
at the amplifier output is to use a low-pass filter such as an RC network.
8.3.4 Internal Offset Correction
The OPA188 op amp uses an auto-calibration technique with a time-continuous 750-kHz op amp in the signal
path. This amplifier is zero-corrected every 3 μs using a proprietary technique. Upon power up, the amplifier
requires approximately 100 μs to achieve the specified VOS accuracy. This design has no aliasing or flicker noise.
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Feature Description (continued)
8.3.5 EMI Rejection
The OPA188 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI interference
from sources such as wireless communications and densely-populated boards with a mix of analog signal chain
and digital components. EMI immunity can be improved with circuit design techniques; the benefits from these
design improvements. Texas Instruments™ has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 40 shows the results of this testing on the OPA188 . Table 4 lists the EMIRR IN+ values for theOPA188 at
particular frequencies commonly encountered in real-world applications. Applications listed in Table 4 may be
centered on or operated near the particular frequency shown. Detailed information can also be found in EMI
Rejection Ratio of Operational Amplifiers, available for download from www.ti.com.
160
140
EMIRR IN+ (dB)
120
100
80
60
40
20
0
10M
100M
1G
10G
Frequency (Hz)
Figure 40. EMIRR Testing
Table 4. OPA188 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency
(UHF) applications
62.2 dB
900 MHz
Global system for mobile communications (GSM) applications, radio
communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF
applications
74.7 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band
(1 GHz to 2 GHz)
100.7 dB
®
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth , mobile personal communications,
industrial, scientific and medical (ISM) radio band, amateur radio and satellite, Sband (2 GHz to 4 GHz)
102.4 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
104.8 dB
802.11a, 802.11n, aero communication and navigation, mobile communication,
space and satellite operation, C-band (4 GHz to 8 GHz)
100.3 dB
5 GHz
8.3.6 Capacitive Load and Stability
The device dynamic characteristics are optimized for a range of common operating conditions. The combination
of low closed-loop gain and high capacitive loads decreases the amplifier phase margin and can lead to gain
peaking or oscillations. As a result, larger capacitive loads must be isolated from the output. The simplest way to
achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output.
Figure 41 and Figure 42 show graphs of small-signal overshoot versus capacitive load for several values of
ROUT. For details of analysis techniques and application circuits, see Feedback Plots Define Op Amp AC
Performance, available for download from www.ti.com.
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40
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40
RL = 10 kW
RISO = 0 W
35
35
RISO = 0 W
RISO = 25 W
25
RISO = 25 W
RISO = 50 W
30
RISO = 50 W
20
15
G = +1
+18 V
RISO
10
-18 V
25
20
15
RI = 10 kW
10
Device
5
Overshoot (%)
Overshoot (%)
30
RL
RF = 10 kW
G = -1
+18 V
RISO
CL
Device
5
CL
RL = RF = 10 kW
-18 V
0
0
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
G=1
RL = 10 kΩ
Capacitive Load (pF)
100-mV Output
Step
Figure 41. Small-Signal Overshoot vs Capacitive Load
G = –1
RL = RF = 10 kΩ
100-mV Output
Step
Figure 42. Small-Signal Overshoot vs Capacitive Load
8.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or the output pin.
Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. See Figure 43 for an illustration of the ESD circuits contained in the OPA188 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an internal absorption
device of the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit
operation.
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device may activate. The
absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA188
but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly
activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (such as Figure 43 shows), the ESD protection
components are intended to remain inactive and do not become involved in the operation of the application
circuit. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a
given pin. If this condition occurs, there is a risk that some internal ESD protection circuits may be biased on and
conduct current. Any such current flow occurs through steering-diode paths and rarely involves the absorption
device.
Figure 43 shows a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper-input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the absolute maximum ratings of the operational amplifier.
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Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies (+VS or –VS) are at 0 V. Again, this question depends on the supply characteristic while at 0
V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current may be supplied by the input source through the current-steering diodes. This state is not
a normal bias condition; the amplifier will not operate normally. If the supplies are low impedance, then the
current through the steering diodes can become quite high. The current level depends on the ability of the input
source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, external zener diodes may be
added to the supply pins, as shown in Figure 43. The zener voltage must be selected such that the diode does
not turn on during normal operation. However, the zener voltage must be low enough so that the zener diode
conducts if the supply pin begins to rise above the safe operating supply voltage level.
(2)
TVS
RF
V+
+VS
OPA188
RI
ESD CurrentSteering Diodes
IN
(3)
RS
+IN
Op Amp
Core
Edge-Triggered ESD
Absorption Circuit
ID
VIN
OUT
RL
(1)
V±
VS
(2)
TVS
Copyright © 2016, Texas Instruments Incorporated
(1)
VIN = +VS + 500 mV.
(2)
TVS: +VS(max) > VTVSBR(min) > +VS.
(3)
Suggested value is approximately 1 kΩ.
Figure 43. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
The OPA188 input terminals are protected from excessive differential voltage with back-to-back diodes, as
shown in Figure 43. In most circuit applications, the input protection circuitry has no consequence. However, in
low-gain and G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the
amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this
forward-bias condition, the input signal current must be limited to 10 mA or less. If the input signal current is not
inherently limited, an input series resistor can be used to limit the signal input current. This input series resistor
degrades the low-noise performance of the OPA188 . Figure 43 shows an example configuration that implements
a current-limiting feedback resistor.
8.4 Device Functional Modes
The OPA188 has a single functional mode, and is operational when the power-supply voltage is greater than 4.5
V (±2.25 V). The maximum power supply voltage for the OPA188 is 36 V (±18 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPA188 operational amplifier combines precision offset and drift with excellent overall performance, making
this device an excellent choice for many precision applications. The precision offset drift of only 0.085 µV/°C
provides stability over the entire temperature range. In addition, the device pairs excellent CMRR, PSRR, and
AOL dc performance with outstanding low-noise operation. As with all amplifiers, applications with noisy or highimpedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF
capacitors are adequate.
The following application examples highlight only a few of the circuits where the OPA188 can be used.
9.2 Typical Applications
9.2.1 High-Side Voltage-to-Current (V-I) Converter
The circuit shown in Figure 44 is a high-side voltage-to-current (V-I) converter. The converter translates an input
voltage of 0 V to 2 V to an output current of 0 mA to 100 mA. Figure 45 shows the measured transfer function for
this circuit. The low offset voltage and offset drift of the OPA188 facilitate excellent dc accuracy for the circuit.
V+
RS2
470
RS3
4.7
IRS2
IRS3
R4
10 k
VRS2
VRS3
C7
2200 pF
R5
330
Q2
+
R3
200
+
Q1
C6
1000 pF
VIN
+
R2
10
±
VRS1
RS1
2k
IRS1
VLOAD
RLOAD
ILOAD
Copyright © 2016, Texas Instruments Incorporated
Figure 44. High-Side Voltage-to-Current (V-I) Converter
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Typical Applications (continued)
9.2.1.1 Design Requirements
The design requirements are:
• Supply voltage: 5 V dc
• Input: 0 V to 2 V dc
• Output: 0 mA to 100 mA dc
9.2.1.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three
current sensing resistors, RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that
flows through the first stage of the design. The current gain from the first stage to the second stage is based on
the relationship between RS2 and RS3.
For a successful design, pay close attention to the dc characteristics of the operational amplifier chosen for the
application. To meet the performance goals, this application benefits from an operational amplifier with low offset
voltage, low temperature drift, and rail-to-rail output. The OPA188 CMOS operational amplifier is a highprecision, ultra-low offset, ultra-low drift amplifier, optimized for low-voltage, single-supply operation, with an
output swing to within 15 mV of the positive rail. The devices in the OPA188 family use chopping techniques to
provide low initial offset voltage and near-zero drift over time and temperature. Low offset voltage and low drift
reduce the offset error in the system, making this device appropriate for precise dc control. The rail-to-rail output
stage of the OPA188 makes sure that the output swing of the operational amplifier is able to fully control the gate
of the MOSFET devices within the supply rails.
A detailed error analysis, design procedure, and additional measured results are given in reference design
TIPD102, a step-by-step process to design a High-Side Voltage-to-Current (V-I) Converter.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to Precision
Design Guide TIPD102, High-Side Voltage-to-Current (V-I) Converter.
9.2.1.3 Application Curves
Figure 45 shows the measured transfer function for the high-side voltage-to-current converter shown in
Figure 44 .
0.1
Load
Output Current (A)
0.075
0.05
0.025
0
0
0.5
1
Input Voltage (V)
1.5
2
D001
Figure 45. Measured Transfer Function for High-Side V-I Converter
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9.2.2 Discrete INA + Attenuation for ADC With 3.3-V Supply
NOTE
The TINA-TI files shown in the following sections require that either the TINA software
(from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software
from the TINA-TI folder.
Figure 46 shows an example of how the OPA188 is used as a high-voltage, high-impedance front-end for a
precision, discrete instrumentation amplifier with attenuation. The INA159 provides the attenuation that allows
this circuit to easily interface with 3.3-V or 5-V analog-to-digital converters (ADCs). Click the following link to
download the TINA-TI file: Discrete INA.
15 V
U2
VOUTP
OPA188
5V
VDIFF / 2
VCM
10
-15 V
Ref 1
Ref 2
RG
500 W
+
R5
10 kW
R7
10 kW
U1
INA159
(1)
VOUT
Sense
-15 V
-VDIFF / 2
U3
OPA188
VOUTN
15 V
(1)
VOUT = VDIFF × (41 / 5) + (Ref 1) / 2.
Figure 46. Discrete INA + Attenuation for ADC With 3.3-V Supply
9.2.3 Bridge Amplifier
Figure 47 shows the basic configuration for a bridge amplifier. Click the following link to download the TINA-TI
file: Bridge Amplifier Circuit.
15 V
R1
15 V
R
R
R
OPA188
+
R
VOUT
R1
VREF
Copyright © 2016, Texas Instruments Incorporated
Figure 47. Bridge Amplifier
22
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9.2.4 Low-Side Current Monitor
Figure 48 shows the OPA188 configured in a low-side current-sensing application. The load current (ILOAD)
creates a voltage drop across the shunt resistor (RSHUNT). This voltage is amplified by the OPA188, with a gain of
201. The load current is set from 0 A to 500 mA, which corresponds to an output voltage range from 0 V to 10 V.
The output range can be adjusted by changing the shunt resistor or gain of the configuration. Click the following
link to download the TINA-TI file: Current-Sensing Circuit.
V
Load
15 V
+
VOUT = ILOAD * RSHUNT(1 + RF / RIN)
VOUT
OPA188
ILOAD
RSHUNT
100 m
VOUT / ILOAD= 1 V / 49.75 mA
RIN
100
RF
20 k
CF
150
pF
Copyright © 2016, Texas Instruments Incorporated
Figure 48. Low-Side Current Monitor
9.2.5 Programmable Power Supply
Figure 49 shows the OPA188 configured as a precision programmable power supply using the 16-bit, voltage
output DAC8581 and the OPA548 high-current amplifier. This application amplifies the digital-to-analog converter
(DAC) voltage by a value of five, and handles a large variety of capacitive and current loads. The OPA188 in the
front-end provides precision and low drift across a wide range of inputs and conditions. Click the following link to
download the TINA-TI file: Programmable Power-Supply Circuit.
C1
150pF
R1
10k
R2
1k
R4
40k
C2
500nF
30V
15V
OPA188
+
DAC8581
OPA548
+
R3
10k
VOUT
VOUT = ± 25V
-30V
-15V
Input = ± 5V
Figure 49. Programmable Power Supply
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9.2.6 RTD Amplifier With Linearization
See Analog Linearization Of Resistance Temperature Detectors for an in-depth analysis of Figure 50 . Click the
following link to download the TINA-TI file: RTD Amplifier with Linearization.
15 V
(5 V)
Out
REF5050
In
1 µF
1 µF
R2
49.1 kŸ
R3
60.4 kŸ
R1
4.99 kŸ
OPA188
V OUT
0°C = 0 V
200°C = 5 V
R5
(1)
105.8 kŸ
RTD
Pt100
R4
1 kŸ
Copyright © 2016, Texas Instruments Incorporated
(1)
R5 provides positive-varying excitation to linearize output.
Figure 50. RTD Amplifier With Linearization
24
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10 Power Supply Recommendations
The OPA188 is specified for operation from 4 V to 36 V (±2 V to ±18 V); many specifications apply from –40°C to
+125°C. Typical Characteristics presents parameters that can exhibit significant variance with regard to operating
voltage or temperature.
CAUTION
Supply voltages larger than 40 V can permanently damage the device (see the
Absolute Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Layout.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Connect Low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable to single-supply
applications.
• To reduce parasitic coupling, run the input traces as far away from the supply lines as possible.
• Use a ground plane to help distribute heat and reduces EMI noise pickup.
• Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
VOUT
GND
VOUT
Use low-ESR, ceramic
bypass capacitor
Ground (GND) plane on another layer
Copyright © 2017, Texas Instruments Incorporated
Figure 51. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 TINA-TI™ (Free Download Software)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macromodels in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE as well as additional design capabilities.
Available as a free download, TINA-TI offers extensive post-processing capability that allows users to format
results in a variety of ways. Virtual instruments offer users the ability to select input waveforms and probe circuit
nodes, voltages, and waveforms, creating a dynamic quick-start tool.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
• Texas Instruments, Feedback Plots Define Op Amp AC Performance application report
• Texas Instruments, Analog Linearization Of Resistance Temperature Detectors technical brief
• Texas Instruments, High-Side Voltage-to-Current (V-I) Converter design guide
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
Texas Instruments, E2E are trademarks of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
DesignSoft, TINA are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
26
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA188AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA188
OPA188AIDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QXZ
OPA188AIDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QXZ
OPA188AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QXX
OPA188AIDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QXX
OPA188AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA188
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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