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OPA207
SBOS826D – DECEMBER 2017 – REVISED OCTOBER 2019
OPA207 Low-Power, High-Precision, Low-Noise, Rail-to-Rail Output
Operational Amplifier
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The OPA207 precision operational amplifier (op amp)
replaces the industry standard OP-07, OP-77 and
OP–177 amplifiers. The OPA207 offers improved
noise, wider output voltage swing, and is twice as fast
with half the quiescent current of the industry
standard alternatives. Features include ultra-low input
offset voltage and drift, low input bias current, high
common-mode rejection ratio, and high power-supply
rejection ratio.
1
Ultra-low offset voltage: 150 μV (maximum)
Ultra-low drift: ±1 μV/°C (maximum)
Gain bandwidth: 1 MHz (typical)
Slew rate: 3.6 V/μs (typical)
High open-loop gain: 130 dB (minimum)
High common-mode rejection: 115 dB (minimum)
High power-supply rejection: 5µV/V (maximum)
Low bias current: 2.8 nA (maximum)
Wide supply range: ±2.25 V to ±18 V
Low quiescent current: 375 μA (maximum)
Replaces OP-07, OP-77, and OP-177
The OPA207 operational amplifier is easy to use and
free from phase inversion and the overload problems
found in some other operational amplifiers. The
OPA207 is stable in unity gain and provide excellent
dynamic behavior over a wide range of load
conditions.
2 Applications
•
•
•
•
•
The OPA207 op amp operates over a wide powersupply-voltage range, from ±2.25 V to ±18 V, with
excellent performance. High performance is
maintained as the amplifiers swing to their specified
limits.
Analog input module
Battery test
Data acquisition (DAQ)
Pressure transmitter
Temperature transmitter
Device Information(1)
PART NUMBER
OPA207
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOT-23 (5)
2.90 mm × 1.60 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Input Referred Voltage Noise (100 nV/div)
Ultra-Low 0.1-Hz to 10-Hz Noise
Time (1 s/div)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA207
SBOS826D – DECEMBER 2017 – REVISED OCTOBER 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Applications ................................................ 20
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
25
25
25
25
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2019) to Revision D
Page
•
Changed SOT-23 (DBV) package from preview to production data (active) ......................................................................... 1
•
Added specifications for new DBV package........................................................................................................................... 4
Changes from Revision B (March 2019) to Revision C
Page
•
Added input offset voltage specification for OPA207DGK ..................................................................................................... 5
•
Added input offset voltage drift specification for OPA207DGK .............................................................................................. 5
Changes from Revision A (December 2018) to Revision B
•
Added content for first release of production-data data sheet for VSSOP (DGK) package................................................... 1
Changes from Original (December 2017) to Revision A
•
2
Page
Page
Added content re: 5-pin SOT-23 package for Advance Information ..................................................................................... 1
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SBOS826D – DECEMBER 2017 – REVISED OCTOBER 2019
5 Pin Configuration and Functions
D and DGK Packages
8-Pin SOIC and 8-Pin VSSOP
Top View
DBV Package
5-Pin SOT-23
Top View
V±
2
+IN
3
5
V+
4
±IN
±
1
+
OUT
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
D (SOIC),
DGK(VSSOP)
DBV (SOT-23)
–IN
2
4
I
Inverting input
+IN
3
3
I
Non-inverting input
NC
1, 5, 8
—
—
No internal connection (can be left floating or connected to ground)
OUT
6
1
O
Output
V–
4
2
—
Negative (lowest) power supply
V+
7
5
—
Positive (highest) power supply
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OPA207
SBOS826D – DECEMBER 2017 – REVISED OCTOBER 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
Supply voltage, Vs = (V+) – (V–)
Input voltage - Common-mode (2)
V
(V–) -0.7
(V+) +0.7
V
–1
1
V
125
°C
150
°C
150
°C
Input voltage - Differential
Output short-circuit (3)
Continuous
Operating temperature
–55
Junction temperature
Storage temperature, Tstg
(1)
(2)
(3)
UNIT
36
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input current must be limited to 10 mA.
Short circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
4.5
30
36
±2.25
±15
±18
V
125
°C
Single Supply
Supply voltage, Vs = (V+) – (V–)
Dual Supply
–40
Specified temperature
UNIT
V
6.4 Thermal Information
OPA207
THERMAL METRIC (1)
DGK (VSSOP)
D (SOIC)
DBV (SOT-23)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
176.7
121.5
166.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
63.9
64.3
116.9
°C/W
RθJB
Junction-to-board thermal resistance
99.4
65.0
63.2
°C/W
ψJT
Junction-to-top characterization parameter
8.8
18.2
45
°C/W
ψJB
Junction-to-board characterization parameter
97.6
64.3
62.9
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package ThermalMetrics application
report.
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6.5 Electrical Characteristics
at VS = ±15 V, TA = 25°C, RL = 2 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
15
±100
UNIT
OFFSET VOLTAGE
Input offset voltage
OPA207D
TA = –40°C to 85°C
±150
TA = –40°C to 125°C
±200
15
VOS
Input offset voltage
OPA207DGK
±170
TA = –40°C to 125°C
±225
15
Input offset voltage
OPA207DBV
dVOS/dT
PSRR
±125
TA = 0°C to 85°C
±130
TA = 0°C to 85°C
±170
TA = –40°C to 125°C
±225
Input offset voltage drift
OPA207D
TA = –40°C to 85°C
±0.2
TA = –40°C to 125°C
±0.2
±.8
Input offset voltage drift
OPA207DGK
and OPA207DBV
TA = 0°C to 85°C
±0.2
±1.1
TA = –40°C to 125°C
±0.2
±1.1
VS = ±2.25 V to ±18 V
±0.5
Input offset voltage versus
power supply
VS = ±2.25 V to ±18 V, TA = –40°C to 85°C
±.8
μV/°C
±3
±4.2
VS = ±2.25 V to ±18 V, TA = –40°C to 125°C
μV
μV/V
±5
INPUT BIAS CURRENT
±0.2
IB
Input bias current
±2
TA = –40°C to 125°C
±7
±0.13
IOS
Input offset current
±1.5
TA = –40°C to 85°C
nA
±1.5
TA = –40°C to 85°C
±2
TA = –40°C to 125°C
±7
nA
NOISE
Input voltage noise
eN
iN
Input voltage noise density
Input current noise
f = 0.1 Hz to 10 Hz
0.16
μVPP
0.024
µVRMS
f = 1 Hz
9.5
f = 10 Hz
7.5
f = 100 Hz
7.5
f = 1 kHz
7.5
f = 1 kHz
0.18
nV/√Hz
pA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
range
CMRR
Common-mode rejection
ratio
(V–) + 1.25
(V+) – 1.25
(V–) + 1.25 V < VCM < (V+) – 1.25 V
120
140
(V–) + 1.25 V < VCM < (V+) – 1.25 V, TA = –40°C to
125°C
115
140
V
dB
INPUT CAPACITANCE
ZID
Differential
ZICM
Common-mode
3 || 14
MΩ || pF
1 || 1
GΩ || pF
OPEN-LOOP GAIN
(V–) + 200 mV < VO <
(V+) – 200 mV, RL = 10 kΩ TA = –40°C to 125°C
AOL
Open-loop voltage gain
130
140
126
(V–) + 200 mV < VO <
(V+) – 200 mV, RL = 2 kΩ
OPA207D, OPA207DGK
120
140
(V–) + 300 mV < VO <
(V+) – 300 mV, RL = 2 kΩ
OPA207DBV
130
140
(V–) + 200 mV < VO <
(V+) – 200 mV, RL = 2 kΩ
TA = –40°C to 125°C,
OPA207D, OPA207DGK
114
(V–) + 300 mV < VO <
(V+) – 300 mV, RL = 2 kΩ
TA = –40°C to 125°C,
OPA207DBV
120
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OPA207
SBOS826D – DECEMBER 2017 – REVISED OCTOBER 2019
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Electrical Characteristics (continued)
at VS = ±15 V, TA = 25°C, RL = 2 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
1.3
MHz
10-V step, G = 1
2.7
V/μs
To 0.1%, 10-V step , G = 1
4.8
To 0.01%, 10-V step , G = 1
5.4
To 0.001%, 10-V step , G = 1
8.1
Overload recovery time
VIN × gain > VS
1.1
μs
Total harmonic distortion +
noise (THD+N)
VO = 3 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ
–114
dB
Settling time
μs
OUTPUT
Voltage output swing from
rail
ISC
Short-circuit current
CLOAD
Capacitive load drive
RO
Open-loop output
impedance
TA = 25°C, no load, OPA207DBV
15
TA = 25°C, RL = 10 kΩ, OPA207DBV
40
60
TA = 25°C, RL = 2 kΩ, OPA207DBV
80
140
TA = 25°C, no load, OPA207D, OPA207DGK
15
30
TA = 25°C, RL = 10 kΩ, OPA207D, OPA207DGK
40
50
TA = 25°C, RL = 2 kΩ, OPA207D, OPA207DGK
80
125
TA = –40°C to 125°C, RL = 10 kΩ
75
200
Sinking
40
–40
Sourcing
mA
40
f = 1 MHz
mV
200
pf
45
Ω
POWER SUPPLY
IQ
6
Quiescent current per
amplifier
IO = 0 A
350
Turnon time
At TA = 25°C, VS = 36 V, VS ramp rate > 0.3 V/µs
IO = 0 A, TA = –40°C to 125°C
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375
450
27
μA
μs
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6.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
25
20
15
Amplifiers (%)
15
10
10
5
5
C001
C002
Figure 1. Input Referred Offset Voltage Distribution
140
300
120
Gain
Phase 250
100
200
80
150
60
100
40
50
20
0
Figure 2. Input Referred Offset Voltage Drift Distribution
30
G= +1
G= –1
G= +11
Phase (°)
0
Gain (dB)
20
Gain (dB)
1
Input Offset Voltage Drift (µV/ƒC)
Offset Voltage (µV)
10
0
-10
-50
-20
100m
1
10
100
1k
10k
Frequency (Hz)
100k
1M
-20
100
-100
10M
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 4. Closed Loop Gain vs Frequency
Figure 3. Open-Loop Gain and Phase vs Frequency
140
100
PSRR–
PSRR+
CMRR
120
80
70
60
100
Impedance (:)
Rejection Ratio (dB)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0
100
60
20
-20
-60
-100
0.2
0
0
0.1
Amplifiers (%)
20
80
60
50
40
30
20
40
20
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
Figure 5. Power Supply Rejection Ratio and Common-Mode
Rejection Ratio vs Frequency
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
Open
Figure 6. Open-Loop Output Impedance vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
40
Output Voltage (VPP)
35
30
25
20
15
10
5
Voltage Noise Density (nV/—Hz)
20
Vs=±18 V
Vs=±15 V
Vs=±2.25 V
0
1
10
100
1k
10k
Frequency (Hz)
100k
15
10
5
0
100m
1M
Figure 7. Full Power Bandwidth
10
100
1k
Frequency (Hz)
10k
100k
1M
OPA2
Figure 8. Input Voltage Noise Spectral Density vs Frequency
Current Noise Density (pA/√Hz)
Input Referred Voltage Noise (100 nV/div)
10
1
0.1
100m
Time (1 s/div)
G = –1 V/V, RL = 2 kΩ
G = –1 V/V, RL = 10 kΩ
0.05 0.1
G = 1 V/V, RL = 2 kΩ
G = 1 V/V, RL = 10 kΩ
0.20.3 0.5 1
2 3 4 5 7 10
Output Amplitude (VPP)
20 30 50
Total Harmonic Distortion + Noise (dB)
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
-125
0.02
1
10
100
1k
Frequency (Hz)
10k
100k
Figure 10. Input Current Noise vs Frequency
Figure 9. 0.1-Hz to 10-Hz Noise Voltage
Total Harmonic Distortion + Noise (dB)
1
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
-125
G = –1 V/V, RL = 2 kΩ
G = –1 V/V, RL = 10 kΩ
20
50
100
200
G = 1 V/V, RL = 2 kΩ
G = 1 V/V, RL = 10 kΩ
500 1k
2k
Frequency (Hz)
5k
10k 20k
VOUT = 3 VRMS
Figure 11. Total Harmonic Distortion + Noise vs Output
Amplitude
8
Figure 12. Total Harmonic Distortion + Noise vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
80
40
RISO = 0 Ω
RISO = 25 Ω
RISO = 50 Ω
60
30
Overshoot (%)
Overshoot (%)
RISO = 0 :
RISO = 25 :
RISO = 50 :
35
40
20
25
20
15
10
5
0
20
30 40 50
70 100
200 300
Capacitive Load (pF)
500 700 1000
0
20
30 40 50
G = +1 V/V
70 100
200 300
Capacitive Load (pF)
500 700 1000
OPA2
G = –1 V/V
Figure 14. Overshoot vs Capacitive Load
Figure 13. Overshoot vs Capacitive Load
Vin
Cload = 10 pF
Cload = 100 pF
Cload = 200 pF
Cload = 400 pF
Voltage (5 V/div)
Voltage (5 mV/div)
Vin
Cload = 10 pF
Cload = 100 pF
Cload = 200 pF
Cload = 400 pF
Time (1 Ps/div)
Time (2 Ps/div)
Smal
Larg
G = +1 V/V
G = +1 V/V
Figure 15. Small-Signal Step Response
Voltage (5 V/div)
Voltage (5 mV/div)
Figure 16. Large-Signal Step Response
Vin
Cload = 10 pF
Cload = 100 pF
Cload = 200 pF
Vin
Cload = 10 pF
Cload = 400 pF
Time (1 Ps/div)
Cload = 100 pF
Cload = 200 pF
Cload = 400 pF
Time (2 Ps/div)
Smal
G = –1 V/V
Larg
G = –1 V/V
Figure 17. Small-Signal Step Response
Figure 18. Large-Signal Step Response
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
Voltage (5 V/div)
Voltage (5 V/div)
VOUT
VIN
VOUT
VIN
Time (2 Ps/div)
Time (2 Ps/div)
Figure 19. Overload Recovery From Positive Overload
Figure 20. Overload Recovery from Negative Overload
Vin (V)
Vout (V)
Voltage (5 V/div)
Output (1 mV/div)
Rising
Falling
Time (5 Ps/div)
Time (100 ms/div)
Sett
VOUT = 3 VRMS
VOUT = 3 VRMS
Figure 21. Settling Time
Figure 22. No Phase Reversal
2
60
1
VCM = 13.75 V
VCM = ± 13.75 V
Input Bias Current (nA)
Input-referred Offset Voltage ( V)
80
40
20
0
±20
±40
0
±1
±1
±2
±60
±80
±2
±15
±10
±5
0
5
Input Common-mode Voltage (V)
10
15
±20
±15
±10
±5
0
5
10
Input Common-mode Voltage (V)
C003
Figure 23. Input Offset Voltage vs Input Common-mode
Voltage
10
1
15
20
C001
Figure 24. Input Bias Current vs Input Common-mode
Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
400
Input-referred Offset Voltage ( V)
100.0
Quiescent Current ( A)
350
300
250
200
VS = 4.5 V
150
100
50
0
75.0
50.0
25.0
0.0
±25.0
±50.0
VS = 4.5 V
±75.0
±100.0
0
9
18
27
36
Supply Voltage (V)
0
9
18
Figure 25. Quiescent Current vs Power Supply Voltage
27
36
Supply Voltage (V)
C001
C001
Figure 26. Input Offset Voltage vs Power Supply Voltage
15
-10
14
-11
13
-12
125°C
VO (V)
VO (V)
±40°C
25°C
12
125°C
85°C
-13
25°C
85°C
11
-14
±40°C
-15
10
0
5
10
15
20
25
30
35
40
45
0
50
5
10
15
20
25
30
35
40
45
IO (mA)
C001
50
C001
Figure 27. Output Voltage vs Output Current (Sourcing)
Figure 28. Output Voltage vs Output Current (Sinking)
100
2.0
75
1.0
Input Current (nA)
Input-referred Offset Voltage ( V)
IO (mA)
50
25
IBP
IBN
IOS
0.0
±1.0
0
±2.0
±3.0
±25
±50
±4.0
±75
±5.0
±6.0
±100
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±75
Figure 29. Input Offset Voltage vs Temperature
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
150
C001
Figure 30. Input Bias Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
180
0.001
Common-Mode Rejection Ratio (dB)
Open-loop Gain (dB)
150
VS = ± 18 V
140
0.1
Open-loop Gain (µV/V)
0.01
130
VS = ± 2.25 V
120
±25
0
25
50
75
100
150
0.1
130
120
Quiescent Current ( A)
Power Supply Rejection Ratio (dB)
0.01
140
100
125
50
75
100 125 150
C001
400
VS = ± 18 V
VS = ± 2.25 V
350
300
250
1
75
25
450
Power Supply Rejection Ratio (µV/V)
160
50
1
0
Figure 32. Common-Mode Rejection Ratio vs Temperature
170
25
130
Temperature (ƒC)
0.001
0
0.1
±75 ±50 ±25
Figure 31. Open Loop Gain vs Temperature
±25
140
C001
180
±50
150
125
Temperature (ƒC)
±75
0.01
160
120
1
±50
170
Common-mode Rejection Ratio (µV/V)
170
160
0.001
180
±75
150
Temperature (ƒC)
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
150
C001
Figure 34. Quiescent Current vs Temperature
Figure 33. Power Supply Rejection Ratio vs Temperature
Short Circuit Current (mA)
45
Sinking
40
35
Sourcing
30
25
±75
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
C001
Figure 35. Output Short Circuit Current vs Temperature
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7 Detailed Description
7.1 Overview
The OPA207 precision operational amplifier replaces the industry standard OP-177. The OPA207 offers
improved noise, wider output voltage swing, has twice the bandwidth, ten times the slew rate and consumes only
half the quiescent current as the OP-177. Additional features include ultralow offset voltage and drift, low bias
current, high common-mode rejection, and high power supply rejection.
7.2 Functional Block Diagram
V+
+IN
_
gm3
gm2
gm1
OUT
IN
V_
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7.3 Feature Description
The OPA207 is unity-gain stable and free from unexpected output phase reversal, making it easy to use in a
wide range of applications. Applications with noisy or high-impedance power supplies may require decoupling
capacitors close to the device pins. In most cases 0.1-μF capacitors are adequate.
7.3.1 Operating Voltage
The OPA207 operates from ±2.25 V to ±18 V supplies with excellent performance. Key parameters are assured
over the specified temperature range, –40°C to 125°C. Most behavior remains unchanged through the full
operating voltage range (±2.25 V to ±18 V). Parameters which vary significantly with operating voltage or
temperature are shown in Typical Characteristics.
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Feature Description (continued)
7.3.2 Input Protection
The input stage of the OPA207 is internally protected with resistors in series with diode clamps as shown in
Figure 36. The inputs can withstand ±10 V differential inputs without damage and the maximum input current
should be limited to 10 mA or less.. The protection diodes conduct current when the inputs are over-driven such
as when the opamp output is slewing. This may disturb the slewing behavior of unity-gain follower applications,
but will not damage the operational amplifier.
500
+IN
+
OUT
±
-IN
500
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Figure 36. Simplified OPA207 Input Protection Circuit
7.3.3 ESD Protection
The OPA207 is internally protected against ESD events that can occur during manufacturing, handling, or
printed-circuit-board assembly. The internal ESD protection diodes are not intended to protect the OPA207
during normal operation when the device is operating under power. In cases where the inputs or output can be
driven above the positive power supply or below the negative power supply care must be taken to limit the
current through the internal diodes to 10 mA or less. In harsh electrical environments external protection circuitry
may be required and is dependant upon the application requirements and environmental conditions.
V+
+IN
+
-IN
±
OUT
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Figure 37. Simplified OPA207 ESD Protection Circuit
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Feature Description (continued)
7.3.4 Input Stage Linearization
The OPA207 uses linearization techniques to reduce the total harmonic distortion. Figure 38 illustrates the
linearization concept, and Figure 38 illustrates the total harmonic distortion performance of the OPA207.
-IN
+IN
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Total Harmonic Distortion + Noise (dB)
Figure 38. Simplified Input Stage Linearization Circuit
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
-125
G = –1 V/V, RL = 2 kΩ
G = –1 V/V, RL = 10 kΩ
20
50
100
200
G = 1 V/V, RL = 2 kΩ
G = 1 V/V, RL = 10 kΩ
500 1k
2k
Frequency (Hz)
5k
10k 20k
Figure 39. Total Harmonic Distortion
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Feature Description (continued)
7.3.5 Rail-to-Rail Output
The OPA207 uses a rail-to-rail output stage capable of swinging within a few millivolts from either power supply
rail while maintaining high open-loop gain. Figure 40 shows a simplified drawing of the output stage circuit.
Resistors connected in series with each output transistor ensure a consistent output current limit. Limiting the
output current in this way ensures reliable operation of the OPA207 under short circuited conditions and protects
sensitive loads from being damaged by excessive current. Figure 41 and Figure 42 illustrate the maximum output
current available from the OPA207 at various temperatures.
V+
OUT
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Figure 40. Simplified Rail-to-Rail Output Stage Circuit
15
-10
14
-11
13
-12
125°C
VO (V)
VO (V)
±40°C
25°C
12
125°C
85°C
-13
25°C
85°C
11
-14
±40°C
-15
10
0
5
10
15
20
25
IO (mA)
30
35
40
45
50
Figure 41. Output Swing to Rail While Sourcing Current
16
0
5
10
15
20
25
IO (mA)
C001
30
35
40
45
50
C001
Figure 42. Output Swing to Rail While Sinking Current
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Feature Description (continued)
7.3.6 Low Input Bias Current
The OPA207 uses super-beta bipolar transistors and employs an input bias current cancellation technique. This
combination results in very low input bias currents that remain low over the full specified temperature range from
–40°C to + 125°C unlike CMOS or JFET amplifiers whose input bias currents typically double every 10°C and
can be extremely high at 125°C. Figure 43 illustrates the comparison between the OPA207 and typical CMOS or
JFET amplifiers.
6000
Input Bias Current (pA)
5000
OPA207
Typical CMOS/JFET
4000
3000
2000
1000
0
-1000
-50
-25
0
25
50
Temperature (qC)
75
100
125
OPA2
Figure 43. Input Bias Current vs Temperature
It is common practice to place a bias current cancellation resistor as illustrated in Figure 42. This approach works
well with amplifiers that do not employ an internal input bias current cancellation technique. Because the
OPA207 uses an internal bias current cancellation technique, TI does not recommend the bias cancellation
resistor.
R2
R1
IBN
±
+
+
IBP
±
GND
IBN ~ IBP = IB
IBN ± IBP = IOS
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