®
OPA2111
Dual Low Noise Precision Difet ® OPERATIONAL AMPLIFIER
FEATURES
q LOW NOISE: 100% Tested, 8nV/√Hz max at 10kHz q q q q q LOW BIAS CURRENT: 4pA max LOW OFFSET: 500µV max LOW DRIFT: 2.8µV/°C HIGH OPEN-LOOP GAIN: 114dB min HIGH COMMON-MODE REJECTION: 96dB min
APPLICATIONS
q PRECISION INSTRUMENTATION q DATA ACQUISITION q TEST EQUIPMENT q PROFESSIONAL AUDIO EQUIPMENT q MEDICAL EQUIPMENT q DETECTOR ARRAYS
DESCRIPTION
The OPA2111 is a high precision monolithic dielectrically isolated FET (Difet ) operational amplifier. Outstanding performance characteristics allow its use in the most critical instrumentation applications. Noise, bias current, voltage offset, drift, open-loop gain, common-mode rejection, and power supply rejection are superior to BIFET® amplifiers. Very low bias current is obtained by dielectric isolation with on-chip guarding. Laser trimming of thin-film resistors gives very low offset and drift. Extremely low noise is achieved with patented circuit design techniques. A cascode design allows high precision input specifications and reduced susceptibility to flicker noise. Standard dual op amp pin configuration allows upgrading of existing designs to higher performance levels.
BIFET® National Semiconductor Corp., Difet ® Burr-Brown Corp.
*Patented OPA2111 Simplified Circuit (Each Amplifier) +VCC 8
–In
+In
Noise-Free Cascode*
Output
–VCC 4
International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1984 Burr-Brown Corporation
• Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-540E Printed in U.S.A. October, 1993
SPECIFICATIONS
ELECTRICAL
At VCC = ±15VDC and TA = +25°C unless otherwise noted . PARAMETER INPUT NOISE Voltage, fO = 10Hz fO = 100Hz fO = 1kHz fO = 10kHz fB = 10Hz to 10kHz fB = 0.1Hz to 10Hz Current, fB = 0.1Hz to 10Hz fO = 0.1Hz to 20kHz OFFSET VOLTAGE(2) Input Offset Voltage Average Drift Match Supply Rejection Channel Separation BIAS CURRENT(2) Input Bias Current Match OFFSET CURRENT(2) Input Offset Current IMPEDANCE Differential Common-Mode VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection OPEN-LOOP GAIN, DC Open-Loop Voltage Gain Match FREQUENCY RESPONSE Unity Gain, Small Signal Full Power Response Slew Rate Settling Time, 0.1% 0.01% Overload Recovery, 50% Overdrive(3) RATED OUTPUT Voltage Output Current Output Output Resistance Load Capacitance Stability Short Circuit Current POWER SUPPLY Rated Voltage Voltage Range, Derated Performance Current, Quiescent TEMPERATURE RANGE Specification Operating “M” Package “P” Package Storage “M” Package “P” Package θ Junction-Ambient Ambient Temp. Ambient Temp. Ambient Temp. –25 –55 –65 200 +85 +125 +150 –25 –55 –65 200 +85 +125 +150 –55 –55 –65 200 +125 +125 +150 0 –55 –40 –65 –40 200(4) +70 +125 +85 +150 +85 °C °C °C °C °C °C/W ±10 90 110 CONDITION 100% Tested 100% Tested 100% Tested
(1) (1) (1) (1) (1)
OPA2111AM MIN TYP 40 15 8 6 0.7 1.6 15 0.8 ±0.1 ±2 ±1 110 ±3 136 ±2 ±1 ±1.2 1013 || 1 1014 || 3 ±11 110 125 3 2 32 2 6 10 5 ±10 ±5 ±11 ±10 100 1000 40 ±15 ±5 IO = 0mADC 5 ±18 7 ±5 MAX 80 40 15 8 1.2 3.3 24 1.3 ±0.75 ±6 96 ±31
OPA2111BM MIN TYP 30 11 7 6 0.6 1.2 12 0.6 ±0.05 ±0.5 ±0.5 110 ±3 136 ±1.2 ±0.5 ±0.6 1013 || 1 1014 || 3 ±10 96 114 ±11 110 125 2 2 32 2 6 10 5 ±10 ±5 ±11 ±10 100 1000 40 ±15 ±18 7 ±5 MAX 60 30 12 8 1 2.5 19 1 ±0.5 ±2.8 90 ±16
OPA2111SM MIN TYP 40 15 8 6 0.7 1.6 15 0.8 ±0.1 ±2 2 110 ±3 136 ±2 ±1 ±1.2 1013 || 1 1014 || 3 ±10 90 110 ±11 110 125 3 2 32 2 6 10 5 ±10 ±5 ±11 ±10 100 1000 40 ±15 ±18 7 MAX 80 40 15 8 1.2 3.3 24 1 ±0.75 ±6
OPA2111KM, KP MIN TYP 40 15 8 6 0.7 1.6 15 0.8 ±0.3 ±8 2 110 ±3 136 ±3 2 ±3 1013 || 1 1014 || 3 ±10 82 106 ±11 110 125 3 2 32 2 6 10 5 ±10 ±5 ±11 ±10 100 1000 40 ±15 ±5 5 ±18 9 ±2 ±15 MAX UNITS nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms µVp-p fAp-p fA/√Hz mV µV/°C µV/°C dB µV/V dB pA pA pA Ω || pF Ω || pF V dB dB dB MHz kHz V/µs µs µs µs V mA Ω pF mA VDC VDC mA
VCM = 0VDC TA = TMIN to TMAX 90 100Hz, R L = 2kΩ VCM = 0VDC
86 ±31
±50
±8
±4
±8
±15
VCM = 0VDC
±6
±3
±6
±12
VIN = ±10VDC RL ≥ 2kΩ
20Vp-p, RL = 2kΩ VO = ±10V, RL = 2kΩ Gain = –1, RL = 2kΩ 10V Step Gain = –1 RL = 2kΩ VO = ±10VDC DC, Open-Loop Gain = +1
16 1
16 1
16 1
10
10
10
10
5
5
NOTES: (1) Sample tested—this parameter is guaranteed. (2) Offset voltage, offset current, and bias current are measured with the units fully warmed up. (3) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. (4) Typical θJ-A = 150°C/W for plastic DIP.
®
OPA2111
2
ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS)
At VCC = ±15VDC and TA = TMIN to TMAX unless otherwise noted. OPA2111AM PARAMETER TEMPERATURE RANGE Specification Range INPUT OFFSET VOLTAGE(1) Input Offset Voltage Average Drift Match Supply Rejection BIAS CURRENT(1) Input Bias Current Match OFFSET CURRENT(1) Input Offset Current VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection OPEN-LOOP GAIN, DC Open-Loop Voltage Gain Match RATED OUTPUT Voltage Output Current Output Short Circuit Current POWER SUPPLY Current, Quiescent IO = 0mADC 5 8 5 8 5 8 5 10 mA CONDITION Ambient Temp. VCM = 0VDC MIN –25 ±0.22 ±2 1 100 ±10 ±125 60 ±75 ±10 86 106 ±11 100 120 5 ±11 ±10 40 TYP MAX +85 ±1.2 ±6 90 ±50 ±1nA OPA2111BM MIN –25 TYP MAX +85 ±0.08 ±0.75 ±0.5 ±2.8 0.5 100 ±10 ±32 ±75 30 ±38 ±10 90 110 ±11 100 120 3 ±11 ±10 40 ±500 OPA2111SM MIN –55 ±0.3 ±2 2 100 ±10 TYP MAX +125 ±1.5 ±6 82 ±50 OPA2111KM, KP MIN 0 ±0.9 ±8 2 100 ±10 ±125 TYP MAX +70 ±5 ±15 UNITS °C mV µV/°C µV/°C dB µV/V pA pA pA V dB dB dB V mA mA
86
86
±80 ±500
VCM = 0VDC
±2nA ±16.3nA 1nA ±1.3nA ±12nA ±10 86 106 ±11 100 120 5 ±11 ±10 40 ±10 80 100
VCM = 0VDC
±750
±375
±75 ±11 100 120 5 ±11 ±10 40
±375
VIN = ±10VDC RL ≥ 2kΩ
RL = 2kΩ VO = ±10VDC VO = 0VDC
±10.5 ±5 10
±10.5 ±5 10
±10.5 ±5 10
±10.5 ±5 10
NOTES: (1) Offset voltage, offset current, and bias current are measured with the units fully warmed up.
CONNECTION DIAGRAMS
Top View DIP
ABSOLUTE MAXIMUM RATINGS
Supply ........................................................................................... ±18VDC Internal Power Dissipation (TJ ≤ +175°C) .................................... 500mW Differential Input Voltage ............................................................ Total VCC Input Voltage Range .......................................................................... ±VCC Storage Temperature Range: “M” Package .................. –65°C to +150°C “P” Package .................... –40°C to +85°C Operating Temperature Range: “M” Package ............... –55°C to +125°C “P” Package ................. –40°C to +85°C Lead Temperature (soldering, 10s) ............................................... +300°C Output Short Circuit to Ground (+25°C) ................................. Continuous Junction Temperature .................................................................... +175°C
Out A –In A +In A –VCC
1 2 3 4 A B
8 7 6 5
+VCC Out B –In B +In B
PACKAGE INFORMATION
MODEL Top View TO-99 OPA2111AM OPA2111BM OPA2111KM OPA2111SM OPA2111KP PACKAGE TO-99 TO-99 TO-99 TO-99 8-Pin Plastic DIP PACKAGE DRAWING NUMBER(1) 001 001 001 001 006
+VCC and Case 8 Out A 1 A –In A 2 B 6 –In B 7 Out B
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.
+In A
3 4 –VCC
5 +In B
ORDERING INFORMATION
TEMPERATURE MODEL OPA2111AM OPA2111BM OPA2111KM OPA2111SM OPA2111KP PACKAGE RANGE TO-99 –25°C to +85°C TO-99 –25°C to +85°C TO-99 0°C to +70°C TO-99 –55°C to +125°C 8-Pin Plastic DIP 0°C to +70°C OFFSET VOLTAGE, max (mV) ±0.75 ±0.5 ±2 ±0.75 ±2
®
1–24
$12.50 21.60 25.55
3
OPA2111
DICE INFORMATION
PAD 1 2 3 4 5 6 7 8 NC
FUNCTION Out A –In A +In A –VS +In B –In B Out B +VS No Connection
Substrate Bias: No Connection
MECHANICAL INFORMATION
MILS (0.001") Die Size Die Thickness Min. Pad Size Backing Transistor Count 138 x 84 ±5 20 ±3 4x4 MILLIMETERS 3.51 x 2.13 ±0.13 0.51 ±0.08 0.10 x 0.10 None 102
OPA2111AD DIE TOPOGRAPHY
TYPICAL PERFORMANCE CURVES
TA = +25°C, and VCC = ±15VDC unless otherwise noted.
INPUT CURRENT NOISE SPECTRAL DENSITY 100
VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs TEMPERATURE 12 fO = 1kHz 100
Current Noise (fA/ Hz)
Voltage Noise (nV/ Hz)
10
10
10
8
1
1 BM
6
0.1
0.1 1 10 100 1k Frequency (Hz) 10k 100k 1M
4 –75 –50 –25 0 25 50 75 100
0.01 125
Temperature (°C)
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OPA2111
4
Current Noise (fA/ Hz)
TYPICAL PERFORMANCE CURVES
TA = +25°C, and VCC = ±15VDC unless otherwise noted.
TOTAL(1) INPUT VOLTAGE NOISE SPECTRAL DENSITY vs SOURCE RESISTANCE 1k RS = 10MΩ RS = 1MΩ 100 RS = 100kΩ
(CONT)
INPUT OFFSET VOLTAGE WARM-UP DRIFT 40
Offset Voltage Change (µV)
Voltage Noise (nV/ Hz)
20
0
10
BM NOTE: (1) Includes contribution from source resistance.
RS = 100Ω
–20
1 0.1 1 10 100 Frequency (Hz) 1k 10k 100k
–40 0 1 2 3 4 5 6 Time From Power Turn-On (Minutes)
INPUT VOLTAGE NOISE SPECTRAL DENSITY 1k
BIAS AND OFFSET CURRENT vs TEMPERATURE 1k 1k
Voltage Noise (nV/ Hz)
100
100
Bias Current (pA)
100
Offset Current (pA)
®
10
10
AM, SM BM 10
1
1
0.1
1 1 10 100 1k Frequency (Hz) 10k 100k 1M
0.1 0.01 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C)
0.01
TOTAL(1) INPUT VOLTAGE NOISE (PEAK-TO-PEAK) vs SOURCE RESISTANCE 1k 140
POWER SUPPLY REJECTION vs FREQUENCY
Voltage Noise (µVp-p)
100
NOTE: (1) Includes contribution from source resistance.
Power Supply Rejection (dB)
10
120 100 80 60 40 20 0
10
BM fB = 0.1Hz to 10Hz
1 10
4
10 5
10
6
10
7
10
8
10
9
10
1
10
100
1k
10k
100k
1M
10M
Source Resistance (Ω)
Frequency (Hz)
5
OPA2111
TYPICAL PERFORMANCE CURVES
TA = +25°C, and VCC = ±15VDC unless otherwise noted.
(CONT)
TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY AT 1kHz vs SOURCE RESISTANCE 1k
COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE 120
Common-Mode Rejection (dB)
Voltage Noise, EO (nV/ Hz)
EO
110
100
RS
BM
100
10
OPA2111 + Resistor
90
Resistor Noise Only 1 100 1k 10k 100k 1M 10M 100M Source Resistance (Ω)
80 70 –15 –10 –5 0 5 10 15 Common-Mode Voltage (V)
INPUT OFFSET VOLTAGE CHANGE DUE TO THERMAL SHOCK 150
4
GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE 4
Offset Voltage Change (µV)
AM 75 BM 0 25°C 85°C TA = 25°C to TA = 85°C Air Environment –75
Gain Bandwidth (MHz)
3
3
2
2
1
1
–150 –1 0 1 2 3 4 5 Time From Thermal Shock (Minutes)
0 –75 –50 –25 0 25 50 75 100 Ambient Temperature (°C)
0 125
BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE 10 10
OPEN-LOOP GAIN vs TEMPERATURE 140
Offset Current (pA)
Bias Current (pA)
1 Offset Current 0.1
1
Voltage Gain (dB)
Bias Current
130
120
0.1
110
0.01 –15 –10 –5 0 5 10 15
0.01 Common-Mode Voltage (V)
100 –75 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C)
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OPA2111
6
Slew Rate (V/µs)
TYPICAL PERFORMANCE CURVES
TA = +25°C, VCC = ±15VDC unless otherwise noted.
(CONT)
COMMON-MODE REJECTION vs FREQUENCY 140
LARGE SIGNAL TRANSIENT RESPONSE
Common-Mode Rejection (dB)
120
15
Output Voltage (V)
100 80 60 40 20 0 1 10 100 1k 10k 100k 1M 10M
0
–15
0
25 Time (µs)
50
Frequency (Hz)
OPEN-LOOP FREQUENCY RESPONSE 140 120
Voltage Gain (dB)
SETTLING TIME vs CLOSED-LOOP GAIN 100
–45
Phase Shift (Degrees)
80
Gain
80 60 40 20 0 1 10 100 1k 10k 100k Phase Margin ≈ 65°
φ
Settling Time (µs)
100
–90
60 0.01% 0.1%
40
–135
20
–180 1M 10M Frequency (Hz)
0 1 10 100 1k Closed-Loop Gain (V/V)
GAIN-BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE 3 3
150
CHANNEL SEPARATION vs FREQUENCY
Channel Separation (dB)
Gain Bandwidth (MHz)
140
RL = ∞ RL = 2kΩ RL = 560Ω
2
2
Slew Rate (V/µs)
130
120
1
1
110 100 10 100 1k Frequency (Hz) 10k 100k
0 0 5 10 Supply Voltage (±VCC ) 15 20
0
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7
OPA2111
TYPICAL PERFORMANCE CURVES
TA = +25°C, VCC = ±15VDC unless otherwise noted.
(CONT)
MAXIMUM UNDISTORTED OUTPUT VOLTAGE vs FREQUENCY 30
SUPPLY CURRENT vs TEMPERATURE 8
Output Voltage (Vp-p)
20
Supply Current (mA)
6
4
10
2
0 1k 10k Frequency (Hz) 100k 1M
0 –75 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C)
SMALL SIGNAL TRANSIENT RESPONSE 60 40
Output Voltage (mV)
TOTAL HARMONIC DISTORTION vs FREQUENCY 1
Total Harmonic Distortion (%)
10kΩ 10kΩ EO 2kΩ EO = 700mV EO = 7V
20 0 –20 –40 –60 0 1 2 Time (µs) 3 4 5
0.1
0.01
0.001 0.1 1 10 100 Frequency (Hz)
THD + Noise Residual Test Limit 1K 10K 100K
APPLICATIONS INFORMATION
OFFSET VOLTAGE ADJUSTMENT The OPA2111 offset voltage is laser-trimmed and will require no further trim for most applications. Offset voltage can be trimmed by summing (see Figure 1). With this trim method there will be no degradation of input offset drift. INPUT PROTECTION Conventional monolithic FET operational amplifiers require external current-limiting resistors to protect their inputs against destructive currents that can flow when input FET gate-to-substrate isolation diodes are forward-biased. Most BIFET amplifiers can be destroyed by the loss of –VCC. Because of its dielectric isolation, no special protection is needed on the OPA2111. Of course, the differential and common-mode voltage limits should be observed. Static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers (both bipolar and FET types), this may cause a noticeable degradation of offset voltage and drift. Static protection is recommended when handling any precision IC operational amplifier.
In
1/2 OPA2111 Out –15V ±2mV OffsetTrim 100kΩ 20Ω +15V
150kΩ
FIGURE 1. Offset Voltage Trim.
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OPA2111
8
GUARDING AND SHIELDING As in any situation where high impedances are involved, careful shielding is required to reduce “hum” pickup in input leads. If large feedback resistors are used, they should also be shielded along with the external input circuitry. Leakage currents across printed circuit boards can easily exceed the bias current of the OPA2111. To avoid leakage problems, it is recommended that the signal input lead of the OPA2111 be wired to a Teflon standoff. If the OPA2111 is to be soldered directly into a printed circuit board, utmost care must be used in planning the board layout. A “guard” pattern should completely surround the high impedance input leads and should be connected to a low impedance point which is at the signal input potential (see Figure 2). NOISE: FET vs BIPOLAR Low noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in many cases, so consider the effect of source resistance on overall operational amplifier noise performance. At low source impedances, the low voltage noise of a bipolar operational amplifier is superior, but at higher impedances the high current noise of a bipolar amplifier becomes a serious liability. Above about 15kΩ the OPA2111 will have lower total noise than an OP-27 (see Figure 3). BIAS CURRENT CHANGE vs COMMON-MODE VOLTAGE The input bias currents of most popular BIFET® operational amplifiers are affected by common-mode voltage (Figure 4). Higher input FET gate-to-drain voltage causes leakage and ionization (bias) currents to increase. Due to its cascode input stage, the extremely low bias current of the OPA2111 is not compromised by common-mode voltage.
APPLICATIONS CIRCUITS Figures 5 through 13 are circuit diagrams of various applications for the OPA2111.
1k
Voltage Noise Spectral Density (EO) Typical at 1kHz (nV/ Hz)
EO
OP-27 + Resistor OPA2111 + Resistor Resistor Noise Only
100
RS
10
EO = eN2 + (iNRS)2 + 4kTRS OPA2111 + Resistor Resistor Noise Only OP-27 + Resistor
1 100 1k
BM 1M 10M
10k
100k
Source Resistance, RS (Ω)
FIGURE 3. Voltage Noise Spectral Density vs Source Resistance.
80 TA = 25°C; curves taken from manufacturers' published typical data LF156/157
Input Bias Current (pA)
60
40
20 AD547
LF155 OPA2111
0 –20
OP-15/16/17 “Perfect Bias Current Cancellation” –15 –10 –5 0 5 10 15
Common-Mode Voltage (VDC) Non-Inverting Buffer
FIGURE 4. Input Bias Currrent vs Common-Mode Voltage.
Out
In Operate 10kΩ Zero
2 A In 3 1 Out
2 A In 3 1
1MΩ 2
1/2 OPA2111BM
1
Out 100kΩ Gain = –100
Inverting In
TO-99 Bottom View 4
3
2 A 3 1 Out
3 2
7 8
5 6
100Ω 100kΩ
Polypropylene 1µF
1
VOS ≤ 5µV Drift ≤ 0.028µV/°C Zero Droop ≤ 2µV/s Referred to Input 6
7
Board layout for input guarding: guard top and bottom of board. Alternate: use Teflon® standoff for sensitive input pins. Teflon® E. I. Du Pont de Nemours & Co.
1/2 OPA2111BM
5
FIGURE 2. Connection of Input Guard.
FIGURE 5. Auto-Zero Amplifier.
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9
OPA2111