OPA211-EP
SBOS638 – JUNE 2012
1.1nV/√Hz NOISE, LOW POWER, PRECISION
OPERATIONAL AMPLIFIER
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1
1 FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
LOW VOLTAGE NOISE: 1.1nV/√Hz at 1kHz
INPUT VOLTAGE NOISE:
80nVPP (0.1Hz to 10Hz)
THD+N: –136dB (G = 1, f = 1kHz)
OFFSET VOLTAGE: 180μV (max)
OFFSET VOLTAGE DRIFT: 0.35μV/°C (typ)
LOW SUPPLY CURRENT: 3.6mA/Ch (typ)
UNITY-GAIN STABLE
GAIN BANDWIDTH PRODUCT:
80MHz (G = 100)
45MHz (G = 1)
SLEW RATE: 27V/μs
16-BIT SETTLING: 700ns
WIDE SUPPLY RANGE:
±2.25V to ±18V, +4.5V to +36V
RAIL-TO-RAIL OUTPUT
OUTPUT CURRENT: 30mA
2 APPLICATIONS
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•
•
•
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•
PLL LOOP FILTER
LOW-NOISE, LOW-POWER SIGNAL
PROCESSING
16-BIT ADC DRIVERS
DAC OUTPUT AMPLIFIERS
ACTIVE FILTERS
LOW-NOISE INSTRUMENTATION AMPS
ULTRASOUND AMPLIFIERS
PROFESSIONAL AUDIO PREAMPLIFIERS
LOW-NOISE FREQUENCY SYNTHESIZERS
INFRARED DETECTOR AMPLIFIERS
HYDROPHONE AMPLIFIERS
GEOPHONE AMPLIFIERS
MEDICAL
3 SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
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•
•
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(1)
CONTROLLED BASELINE
ONE ASSEMBLY/TEST SITE
ONE FABRICATION SITE
AVAILABLE IN MILITARY (–55°C/125°C)
TEMPERATURE RANGE (1)
EXTENDED PRODUCT LIFE CYCLE
EXTENDED PRODUCT-CHANGE
NOTIFICATION
PRODUCT TRACEABILITY
Additional temperature ranges available - contact factory
4 DESCRIPTION
The OPA211 series of precision operational amplifiers achieves very low 1.1nV/√Hz noise density with a supply
current of only 3.6mA. This series also offers rail-to-rail output swing, which maximizes dynamic range.
The extremely low voltage and low current noise, high speed, and wide output swing of the OPA211 series make
these devices an excellent choice as a loop filter amplifier in PLL applications.
In precision data acquisition applications, the OPA211 series of op amps provides 700ns settling time to 16-bit
accuracy throughout 10V output swings. This ac performance, combined with only 125μV of offset and
0.35μV/°C of drift over temperature, makes the OPA211 ideal for driving high-precision 16-bit analog-to-digital
converters (ADCs) or buffering the output of high-resolution digital-to-analog converters (DACs).
The OPA211 is specified over a wide dual-power supply range of ±2.25V to ±18V, or for single-supply operation
from +4.5V to +36V.
The OPA211 is available in a small MSOP-8 package. This op amp is specified from TA = –55°C to +125°C.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
OPA211-EP
SBOS638 – JUNE 2012
www.ti.com
INPUT VOLTAGE NOISE DENSITY vs FREQUENCY
Voltage Noise Density (nV/ÖHz)
100
10
1
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
PACKAGE/ORDERING INFORMATION (1)
(1)
2
TA
PACKAGE
ORDERABLE PART
NUMBER
PACKAGE MARKING
VID NUMBER
-55°C to 125°C
MSOP-8 - DGK
OPA211MDGKTEP
OBCM
V62/12619-01XE
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
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5 PIN CONFIGURATIONS
OPA211
MSOP-8
NC
(1)
NC denotes no internal connection.
(2)
Shutdown function:
(1)
1
8
Shutdown
-IN
2
7
V+
+IN
3
6
OUT
V-
4
5
NC
•
Device enabled: (V–) ≤ VSHUTDOWN ≤ (V+) – 3V
•
Device disabled: VSHUTDOWN ≥ (V+) – 0.35V
(2)
(1)
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
5.1
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
Supply Voltage
VS = (V+) – (V–)
Input Voltage
Input Current (Any pin except power-supply pins)
VALUE
UNIT
40
V
(V–) – 0.5 to (V+) + 0.5
V
±10
mA
Output Short-Circuit (2)
Continuous
Operating Temperature
(TA)
–55 to +125
°C
Storage Temperature
(TA)
–65 to +150
°C
Junction Temperature
(TJ)
200
°C
Human Body Model (HBM)
3000
V
Charged Device Model (CDM)
1000
V
ESD Ratings
(1)
(2)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Short-circuit to VS/2 (ground in symmetrical dual supply setups), one amplifier per package.
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6 THERMAL INFORMATION
OPA211
THERMAL METRIC (1)
DGK
UNITS
8 PINS
θJA
Junction-to-ambient thermal resistance (2)
θJCtop
Junction-to-case (top) thermal resistance (3)
71.2
θJB
Junction-to-board thermal resistance (4)
104.9
ψJT
Junction-to-top characterization parameter (5)
11.5
ψJB
Junction-to-board characterization parameter (6)
103.4
θJCbot
Junction-to-case (bottom) thermal resistance (7)
N/A
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
184.9
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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6.1
SBOS638 – JUNE 2012
ELECTRICAL CHARACTERISTICS: VS = ±2.25V to ±18V
BOLDFACE limits apply over the specified temperature range, TA = –55°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
±20
±100
μV
OFFSET VOLTAGE
Input Offset Voltage
VOS
VS = ±15V
Over Temperature
Drift
vs Power Supply
±180
dVOS/dT
PSRR
VS = ±2.25V to ±18V
0.1
Over Temperature
µV
μV/°C
0.35
0.5
μV/V
3
μV/V
INPUT BIAS CURRENT
Input Bias Current
Offset Current
IB
VCM = 0V
±50
±200
nA
IOS
VCM = 0V
±20
±150
nA
en
f = 0.1Hz to 10Hz
80
nVPP
f = 10Hz
2
nV/√Hz
f = 100Hz
1.4
nV/√Hz
f = 1kHz
1.1
nV/√Hz
f = 10Hz
3.2
pA/√Hz
f = 1kHz
1.7
pA/√Hz
NOISE
Input Voltage Noise
Input Voltage Noise Density
Input Current Noise Density
In
INPUT VOLTAGE RANGE
VS ≥ ±5V
(V–) + 1.8
(V+) – 1.4
VS < ±5V
(V–) + 2
(V+) – 1.4
VS ≥ ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V
114
120
dB
VS < ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V
108
120
dB
Differential
20k || 8
Ω || pF
Common-Mode
109 || 2
Ω || pF
Common-Mode Voltage Range
Common-Mode Rejection Ratio
VCM
CMRR
V
V
INPUT IMPEDANCE
OPEN-LOOP GAIN
Open-Loop Voltage Gain
Over Temperature
AOL
(V–) + 0.2V ≤ VO ≤ (V+) – 0.2V,
RL = 10kΩ
114
130
dB
AOL
(V–) + 0.6V ≤ VO ≤ (V+) – 0.6V,
RL = 600Ω
110
114
dB
AOL
(V–) + 0.6V ≤ VO ≤ (V+) – 0.6V,
IO ≤ 15mA
110
dB
AOL
(V–) + 0.6V ≤ VO ≤ (V+)–0.6V,
15mA < IO ≤ 30mA
103
dB
FREQUENCY RESPONSE
Gain-Bandwidth Product
G = 100
80
MHz
G=1
45
MHz
27
V/μs
VS = ±15V, G = –1, 10V Step, CL = 100pF
400
ns
0.0015% (16-bit)
VS = ±15V, G = –1, 10V Step, CL = 100pF
700
ns
Overload Recovery Time
G = –10
500
ns
G = +1, f = 1kHz,
VO = 3VRMS, RL = 600Ω
0.000015
%
–136
dB
Slew Rate
Settling Time, 0.01%
Total Harmonic Distortion + Noise
GBW
SR
tS
THD+N
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ELECTRICAL CHARACTERISTICS: VS = ±2.25V to ±18V (continued)
BOLDFACE limits apply over the specified temperature range, TA = –55°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
RL = 10kΩ, AOL ≥ 114dB
RL = 600Ω, AOL ≥ 110dB
IO < 15mA, AOL ≥ 110dB
TYP
MAX
UNIT
(V–) + 0.2
(V+) – 0.2
V
(V–) + 0.6
(V+) – 0.6
V
(V–) + 0.6
(V+) – 0.6
OUTPUT
Voltage Output
VOUT
Short-Circuit Current
ISC
Capacitive Load Drive
+30/–45
CLOAD
Open-Loop Output Impedance
See Typical Characteristics
ZO
f = 1MHz
V
mA
pF
Ω
5
SHUTDOWN
Shutdown Pin Input Voltage (1)
Device disabled (shutdown)
(V+) – 0.35
V
Device enabled
(V+) – 3
V
Shutdown Pin Leakage Current
1
μA
Turn-On Time (2)
2
μs
Turn-Off Time (2)
3
Shutdown Current
Shutdown (disabled)
1
μs
20
μA
±18
V
4.5
mA
6
mA
+125
°C
POWER SUPPLY
Specified Voltage
VS
Quiescent Current
(per channel)
IQ
±2.25
IOUT = 0A
3.6
Over Temperature
TEMPERATURE RANGE
Operating Range
TA
–55
Thermal Resistance
θ JA
(1)
(2)
200
°C/W
When disabled, the output assumes a high-impedance state.
See Typical Characteristic curves, Figure 42 through Figure 44.
1000000
Estimated Life (Hours)
100000
10000
1000
125
130
135
140
145
150
Continuous TJ (°C)
A.
See datasheet for absolute maximum and minimum recommended operating conditions.
B.
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
Figure 1. OPA211-EP Wirebond Life Derating Chart
6
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7 TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
INPUT VOLTAGE NOISE DENSITY
vs FREQUENCY
INPUT CURRENT NOISE DENSITY
vs FREQUENCY
100
Current Noise Density (pA/ÖHz)
Voltage Noise Density (nV/ÖHz)
100
10
10
1
1
0.1
1
10
100
1k
10k
0.1
100k
1
10
Frequency (Hz)
-120
G = 11
RL = 600W
G= 1
RL = 5kW
G=1
RL = 600W
-140
0.00001
100
1k
10k 20k
Total Harmonic Distortion + Noise (%)
Measurement BW = 80kHz
10
-60
0.01
-80
G = 11
0.001
-100
0.0001
-120
0.00001
Measurement BW = 80kHz
0.000001
0.01
0.1
1
10
-160
100
-120
G= 1
RL = 5kW
RL = 600W
0.00001
1k
Frequency (Hz)
10k
-140
100k
-80
Channel Separation (dB)
Total Harmonic Distortion + Noise (%)
G = 11
RL = 600W
Total Harmonic Distortion + Noise (dB)
-100
100
G = -1
Figure 5.
CHANNEL SEPARATION vs FREQUENCY
Measurement BW > 500kHz
10
-140
Output Voltage Amplitude (VRMS)
VS = ±15V
VIN = 3.5VRMS
G=1
G=1
VS = ±15V
RL = 600W
1kHz Signal
Figure 4.
THD+N RATIO vs FREQUENCY
0.0001
100k
0.1
Frequency (Hz)
0.001
10k
Total Harmonic Distortion + Noise (dB)
-100
VS = 15V
VOUT = 3VRMS
0.0001
1k
Figure 3.
THD+N RATIO vs OUTPUT VOLTAGE AMPLITUDE
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
Figure 2.
THD+N RATIO vs FREQUENCY
0.001
100
Frequency (Hz)
VS = ±15V
-90 V = 3.5V
IN
RMS
-100 G = 1
RL = 600W
-110
-120
-130
-140
RL = 2kW
-150
-160
RL = 5kW
-170
-180
10
100
1k
10k
100k
Frequency (Hz)
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
POWER-SUPPLY REJECTION RATIO
vs FREQUENCY (Referred to Input)
0.1Hz TO 10Hz NOISE
160
140
20nV/div
PSRR (dB)
120
100
-PSRR
80
+PSRR
60
40
20
0
Time (1s/div)
1
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 8.
COMMON-MODE REJECTION RATIO
vs FREQUENCY
Figure 9.
OPEN-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
140
10k
120
1k
80
ZO (W)
CMRR (dB)
100
60
100
10
40
1
20
0
0.1
10k
100k
10M
1M
100M
10
100
1k
Frequency (Hz)
Figure 10.
GAIN AND PHASE vs FREQUENCY
5
4
80
90
60
40
Gain
45
0
Phase (°)
Gain (dB)
135
Phase
Open-Loop Gain (mV/V)
120
20
1M
10M
100M
RL = 10kW
3
2
300mV Swing From Rails
1
0
-1
200mV Swing From Rails
-2
-3
-4
-20
100
1k
10k
100k
1M
10M
0
100M
-5
-75 -50 -25
0
25
50
75 100 125 150 175 200
Temperature (°C)
Frequency (Hz)
Figure 12.
8
100k
Figure 11.
NORMALIZED OPEN-LOOP GAIN vs TEMPERATURE
180
140
100
10k
Frequency (Hz)
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
112.5
125.0
87.5
100.0
62.5
75.0
37.5
50.0
25.0
0
12.5
-12.5
-37.5
-25.0
-62.5
-50.0
-87.5
-75.0
-112.5
-100.0
-125.0
Population
Population
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
Offset Voltage Drift (mV/°C)
Offset Voltage (mV)
Figure 15.
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
200
2000
150
1500
100
1000
+IB
50
IOS
500
VOS (mV)
IB and IOS Bias Current (nA)
Figure 14.
IB AND IOS CURRENT
vs
TEMPERATURE
0
-50
0
-500
-IB
-100
-1000
-150
-1500
-200
-2000
-50
-25
0
25
50
75
100
125
150
(V-)+1.0 (V-)+1.5 (V-)+2.0
(V+)-1.5 (V+)-1.0 (V+)-0.5
Ambient Temperature (°C)
VCM (V)
Figure 16.
VOS WARMUP
12
10
Figure 17.
INPUT OFFSET CURRENT vs SUPPLY VOLTAGE
100
20 Typical Units Shown
80
60
6
4
40
2
IOS (nA)
VOS Shift (mV)
8
5 Typical Units Shown
0
-2
20
0
-20
-4
-6
-40
-8
-60
-80
-10
-12
0
10
20
30
40
50
60
-100
2.25
4
6
8
10
Time (s)
VS (±V)
Figure 18.
Figure 19.
12
14
16
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
INPUT OFFSET CURRENT vs COMMON-MODE VOLTAGE
INPUT BIAS CURRENT vs SUPPLY VOLTAGE
100
150
VS = 36V
3 Typical Units Shown
75
3 Typical Units Shown
100
Unit 1
Unit 2
50
25
IB (nA)
IOS (nA)
50
0
0
Unit 3
-25
Common-Mode Range
-50
-50
-100
-IB
-75
+IB
-150
2.25
-100
1
5
10
15
20
25
30
35
4
6
8
VCM (V)
Figure 20.
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
12
14
16
18
Figure 21.
QUIESCENT CURRENT vs TEMPERATURE
6
150
VS = 36V
3 Typical Units Shown
50
-IB
+IB
5
4
Unit 2
Unit 1
IQ (mA)
100
IB (nA)
10
VS (±V)
0
3
2
-50
Unit 3
1
-100
Common-Mode Range
0
-150
1
5
10
15
20
25
30
-75 -50 -25
35
0
25
50
75 100 125 150 175 200
Temperature (°C)
VCM (V)
Figure 22.
QUIESCENT CURRENT vs
SUPPLY VOLTAGE
Figure 23.
NORMALIZED QUIESCENT CURRENT
vs TIME
4.0
0.05
3.5
0
3.0
IQ Shift (mA)
-0.05
IQ (mA)
2.5
2.0
1.5
-0.10
-0.15
1.0
-0.20
0.5
-0.25
0
-0.30
Average of 10 Typical Units
0
4
8
12
16
20
24
28
32
36
0
Figure 24.
10
60
120 180 240 300 360 420 480 540
600
Time (s)
VS (V)
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
SMALL-SIGNAL STEP RESPONSE
(100mV)
G = -1
CL = 10pF
Sourcing
CF
5.6pF
20mV/div
ISC (mA)
SHORT-CIRCUIT CURRENT
vs TEMPERATURE
RI
604W
RF
604W
+18V
OPA211
CL
Sinking
-18V
-60
-75 -50 -25
0
25
50
75
Time (0.1µs/div)
100 125 150 175 200
Temperature (°C)
Figure 26.
SMALL-SIGNAL STEP RESPONSE
(100mV)
Figure 27.
SMALL-SIGNAL STEP RESPONSE
(100mV)
G = +1
RL = 600W
CL = 10pF
G = -1
CL = 100pF
20mV/div
20mV/div
CF
5.6pF
RF
604W
RI
604W
+18V
OPA211
+18V
OPA211
-18V
RL
CL
CL
-18V
Time (0.1ms/div)
Time (0.1µs/div)
Figure 28.
SMALL-SIGNAL STEP RESPONSE
(100mV)
Figure 29.
SMALL-SIGNAL OVERSHOOT
vs CAPACITIVE LOAD (100mV Output Step)
60
+18V
OPA211
-18V
G = +1
50
Overshoot (%)
20mV/div
G = +1
RL = 600W
CL = 100pF
RL
40
G = -1
30
G = 10
20
CL
10
0
Time (0.1ms/div)
0
200
400
600
800
1000
1200
1400
Capacitive Load (pF)
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE
G = -1
CL = 100pF
RL = 600W
G = +1
CL = 100pF
RL = 600W
RF = 100W
2V/div
2V/div
RF = 0W
Note: See the
Applications Information
section, Input Protection.
Time (0.5ms/div)
1.0
0.008
0.8
0.008
0.6
0.006
0.6
0.006
0.4
0.004
0.002
0
0
-0.2
(±1/2 LSB = ±0.00075%)
-0.4
-0.002
-0.004
0
-0.2
(±1/2 LSB = ±0.00075%)
-0.4
-0.004
-0.008
-1.0
0
100
200 300
400 500 600
Time (ns)
-0.010
700 800 900 1000
Figure 35.
LARGE-SIGNAL NEGATIVE SETTLING TIME
(10VPP, CL = 10pF)
0.8
0.008
0.6
0.006
0.6
0.006
0.4
0.004
0.002
0
0
-0.2
(±1/2 LSB = ±0.00075%)
-0.4
-0.002
-0.004
-0.6
-0.006
-0.8
-1.0
100
200 300
400 500 600
Time (ns)
0.010
0.4
16-Bit Settling
0.2
0
0.004
0.002
0
-0.2
(±1/2 LSB = ±0.00075%)
-0.4
-0.002
-0.004
-0.6
-0.006
-0.008
-0.8
-0.008
-0.010
700 800 900 1000
-1.0
0
100
Figure 36.
200 300
400 500 600
Time (ns)
D From Final Value (%)
16-Bit Settling
0.2
D From Final Value (mV)
1.0
0.008
D From Final Value (%)
0.010
0.8
0
12
-0.002
-0.010
700 800 900 1000
Figure 34.
LARGE-SIGNAL NEGATIVE SETTLING TIME
(10VPP, CL = 100pF)
1.0
0.002
-0.006
-1.0
400 500 600
Time (ns)
0
0.004
-0.8
-0.8
200 300
16-Bit Settling
0.2
-0.008
-0.006
100
0.4
-0.6
-0.6
0
0.010
D From Final Value (%)
16-Bit Settling
0.2
D From Final Value (mV)
0.010
D From Final Value (%)
D From Final Value (mV)
Figure 33.
LARGE-SIGNAL POSITIVE SETTLING TIME
(10VPP, CL = 10pF)
0.8
1.0
D From Final Value (mV)
Time (0.5ms/div)
Figure 32.
LARGE-SIGNAL POSITIVE SETTLING TIME
(10VPP, CL = 100pF)
-0.010
700 800 900 1000
Figure 37.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
NEGATIVE OVERLOAD RECOVERY
POSITIVE OVERLOAD RECOVERY
G = -10
VIN
G = -10
10kW
VOUT
1kW
0V
VOUT
OPA211
VIN
5V/div
5V/div
10kW
1kW
OPA211
VOUT
VIN
0V
VOUT
VIN
Time (0.5ms/div)
Time (0.5ms/div)
Figure 38.
OUTPUT VOLTAGE vs OUTPUT CURRENT
Figure 39.
NO PHASE REVERSAL
20
0°C
15
5
5V/div
VOUT (V)
Output
+85°C
+125°C
10
+125°C
0
-55°C
0°C
+150°C
-5
+18V
-10
-15
37VPP
(±18.5V)
-20
0
10
20
30
40
IOUT (mA)
50
60
-18V
0.5ms/div
70
Figure 40.
TURN-OFF TRANSIENT
Figure 41.
TURN-ON TRANSIENT
20
20
15
15
10
10
Output Signal
Shutdown Signal
5
5V/div
5
5V/div
OPA211
Output
+85°C
0
-5
0
Output Signal
-5
-10
-10
Shutdown Signal
-15
VS = ±15V
-20
-15
VS = ±15V
-20
Time (2ms/div)
Time (2ms/div)
Figure 42.
Figure 43.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
TURN-ON/TURN-OFF TRANSIENT
20
1.6
15
1.2
10
0.8
5
0.4
0
-5
0
Output
-0.4
-10
-0.8
-15
Output Voltage (V)
Shutdown Pin Voltage (V)
Shutdown Signal
-1.2
VS = ±15V
-20
-1.6
Time (100ms/div)
Figure 44.
14
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8 APPLICATION INFORMATION
The OPA211 is a unity-gain stable, precision op amp
with very low noise. Applications with noisy or highimpedance power supplies require decoupling
capacitors close to the device pins. In most cases,
0.1μF capacitors are adequate. Figure 45 shows a
simplified schematic of the OPA211. This die uses a
SiGe bipolar process and contains 180 transistors.
8.1 OPERATING VOLTAGE
OPA211 series op amps operate from ±2.25V to
±18V
supplies
while
maintaining
excellent
performance. The OPA211 series can operate with as
little as +4.5V between the supplies and with up to
+36V between the supplies. However, some
applications do not require equal positive and
OPERATING VOLTAGE (continued)
negative output voltage swing. With the OPA211
series, power-supply voltages do not need to be
equal. For example, the positive supply could be set
to +25V with the negative supply at –5V or viceversa.
The common-mode voltage must be maintained
within the specified range. In addition, key
parameters are assured over the specified
temperature range, TA = –55°C to +125°C.
Parameters that vary significantly with operating
voltage or temperature are shown in the Typical
Characteristics.
V+
Pre-Output Driver
IN-
OUT
IN+
V-
Figure 45. OPA211 Simplified Schematic
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NOISE PERFORMANCE (continued)
The input terminals of the OPA211 are protected from
excessive differential voltage with back-to-back
diodes, as shown in Figure 46. In most circuit
applications, the input protection circuitry has no
consequence. However, in low-gain or G = 1 circuits,
fast ramping input signals can forward bias these
diodes because the output of the amplifier cannot
respond rapidly enough to the input ramp. This effect
is illustrated in Figure 33 of the Typical
Characteristics. If the input signal is fast enough to
create this forward bias condition, the input signal
current must be limited to 10mA or less. If the input
signal current is not inherently limited, an input series
resistor can be used to limit the signal input current.
This input series resistor degrades the low-noise
performance of the OPA211, and is discussed in the
Noise Performance section of this data sheet.
Figure 46 shows an example implementing a currentlimiting feedback resistor.
VOLTAGE NOISE SPECTRAL DENSITY
vs SOURCE RESISTANCE
10k
Votlage Noise Spectral Density, EO
8.2 INPUT PROTECTION
EO
1k
RS
OPA227
OPA211
100
Resistor Noise
10
2
2
2
EO = en + (in RS) + 4kTRS
1
100
1k
10k
100k
1M
Source Resistance, RS (W)
Figure 47. Noise Performance of the OPA211 and
OPA227 in Unity-Gain Buffer Configuration
RF
8.4 BASIC NOISE CALCULATIONS
-
OPA211
RI
Input
Output
+
Figure 46. Pulsed Operation
8.3 NOISE PERFORMANCE
Figure 47 shows total circuit noise for varying source
impedances with the op amp in a unity-gain
configuration (no feedback resistor network, and
therefore no additional noise contributions). Two
different op amps are shown with total circuit noise
calculated. The OPA211 has very low voltage noise,
making it ideal for low source impedances (less than
2kΩ). A similar precision op amp, the OPA227, has
somewhat higher voltage noise but lower current
noise. It provides excellent noise performance at
moderate source impedance (10kΩ to 100kΩ). Above
100kΩ, a FET-input op amp such as the OPA132
(very low current noise) may provide improved
performance. The equation in Figure 47 is shown for
the calculation of the total circuit noise. Note that en =
voltage noise, In = current noise, RS = source
impedance, k = Boltzmann’s constant = 1.38 × 10–23
J/K, and T is temperature in K.
16
Design of low-noise op amp circuits requires careful
consideration of a variety of possible noise
contributors: noise from the signal source, noise
generated in the op amp, and noise from the
feedback network resistors. The total noise of the
circuit is the root-sum-square combination of all noise
components.
The resistive portion of the source impedance
produces thermal noise proportional to the square
root of the resistance. This function is plotted in
Figure 47. The source impedance is usually fixed;
consequently, select the op amp and the feedback
resistors to minimize the respective contributions to
the total noise.
Figure 47 depicts total noise for varying source
impedances with the op amp in a unity-gain
configuration (no feedback resistor network, and
therefore no additional noise contributions). The
operational amplifier itself contributes both a voltage
noise component and a current noise component.
The voltage noise is commonly modeled as a timevarying component of the offset voltage. The current
noise is modeled as the time-varying component of
the input bias current and reacts with the source
resistance to create a voltage component of noise.
Therefore, the lowest noise op amp for a given
application depends on the source impedance. For
low source impedance, current noise is negligible and
voltage noise generally dominates. For high source
impedance, current noise may dominate.
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BASIC NOISE CALCULATIONS (continued)
Figure 48 illustrates both inverting and noninverting
op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network
resistors also contribute noise. The current noise of
the op amp reacts with the feedback resistors to
create additional noise components. The feedback
resistor values can generally be chosen to make
these noise sources negligible. The equations for
total noise are shown for both configurations.
8.5 TOTAL HARMONIC DISTORTION
MEASUREMENTS
OPA211 series op amps have excellent distortion
characteristics. THD + Noise is below 0.0002% (G =
+1, VOUT = 3VRMS) throughout the audio frequency
range, 20Hz to 20kHz, with a 600Ω load.
The distortion produced by OPA211 series op amps
is below the measurement limit of many commercially
available distortion analyzers. However, a special test
circuit illustrated in Figure 49 can be used to extend
the measurement capabilities.
Op amp distortion can be considered an internal error
source that can be referred to the input. Figure 49
shows a circuit that causes the op amp distortion to
be 101 times greater than that normally produced by
the op amp. The addition of R3 to the otherwise
standard noninverting amplifier configuration alters
the feedback factor or noise gain of the circuit. The
closed-loop gain is unchanged, but the feedback
available for error correction is reduced by a factor of
TOTAL HARMONIC DISTORTION
MEASUREMENTS (continued)
101, thus extending the resolution by 101. Note that
the input signal and load applied to the op amp are
the same as with conventional feedback without R3.
The value of R3 should be kept small to minimize its
effect on the distortion measurements.
Validity of this technique can be verified by
duplicating measurements at high gain and/or high
frequency where the distortion is within the
measurement capability of the test equipment.
Measurements for this data sheet were made with an
Audio Precision System Two distortion/noise
analyzer, which greatly simplifies such repetitive
measurements. The measurement technique can,
however, be performed with manual distortion
measurement instruments.
8.6 SHUTDOWN
The shutdown (enable) function of the OPA211 is
referenced to the positive supply voltage of the
operational amplifier. A valid high disables the op
amp. A valid high is defined as (V+) – 0.35V of the
positive supply applied to the shutdown pin. A valid
low is defined as (V+) – 3V below the positive supply
pin. For example, with VCC at ±15V, the device is
enabled at or below 12V. The device is disabled at or
above 14.65V. If dual or split power supplies are
used, care should be taken to ensure the valid high
or valid low input signals are properly referred to the
positive supply voltage. This pin must be connected
to a valid high or low voltage or driven, and not left
open-circuit. The enable and disable times are
provided in the Typical Characteristics section (see
Figure 42 through Figure 44). When disabled, the
output assumes a high-impedance state.
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Noise in Noninverting Gain Configuration
Noise at the output:
R2
2
2
EO
R1
= 1+
R2
R1
2
2
2
2
2
2
en + e1 + e2 + (inR2) + eS + (inRS)
EO
R2
Where eS = Ö4kTRS ´ 1 +
R1
2
1+
R2
R1
= thermal noise of RS
RS
e1 = Ö4kTR1 ´
VS
R2
R1
= thermal noise of R1
e2 = Ö4kTR2 = thermal noise of R2
Noise in Inverting Gain Configuration
Noise at the output:
R2
2
2
EO = 1 +
R1
R2
R1 + RS
2
EO
RS
Where eS = Ö4kTRS ´
2
2
2
2
en + e1 + e2 + (inR2) + eS
R2
R1 + RS
= thermal noise of RS
VS
e1 = Ö4kTR1 ´
R2
R1 + RS
= thermal noise of R1
e2 = Ö4kTR2 = thermal noise of R2
For the OPA211 series op amps at 1kHz, en = 1.1nV/ÖHz and in = 1.7pA/ÖHz.
Figure 48. Noise Calculation in Gain Configurations
R1
R2
SIG. DIST.
GAIN GAIN
R3
Signal Gain = 1+
OPA211
VOUT
R2
R1
Distortion Gain = 1+
R2
R1 II R3
Generator
Output
R1
R2
R3
1
101
¥
1kW
10W
11
101
100W
1kW
11W
Analyzer
Input
Audio Precision
System Two(1)
with PC Controller
(1)
Load
For measurement bandwidth, see Figure 4, Figure 5, and Figure 6.
Figure 49. Distortion Test Circuit
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8.7 ELECTRICAL OVERSTRESS
ELECTRICAL OVERSTRESS (continued)
Designers often ask questions about the capability of
an operational amplifier to withstand electrical
overstress. These questions tend to focus on the
device inputs, but may involve the supply voltage pins
or even the output pin. Each of these different pin
functions have electrical stress limits determined by
the voltage breakdown characteristics of the
particular semiconductor fabrication process and
specific circuits connected to the pin. Additionally,
internal electrostatic discharge (ESD) protection is
built into these circuits to protect them from
accidental ESD events both before and during
product assembly.
An ESD event produces a short duration, highvoltage pulse that is transformed into a short
duration, high-current pulse as it discharges through
a semiconductor device. The ESD protection circuits
are designed to provide a current path around the
operational amplifier core to prevent it from being
damaged. The energy absorbed by the protection
circuitry is then dissipated as heat.
When an ESD voltage develops across two or more
of the amplifier device pins, current flows through one
or more of the steering diodes. Depending on the
path that the current takes, the absorption device
may activate. The absorption device has a trigger, or
threshold voltage, that is above the normal operating
voltage of the OPA211 but below the device
breakdown voltage level. Once this threshold is
exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a
safe level.
It is helpful to have a good understanding of this
basic ESD circuitry and its relevance to an electrical
overstress event. Figure 50 illustrates the ESD
circuits contained in the OPA211 (indicated by the
dashed line area). The ESD protection circuitry
involves several current-steering diodes connected
from the input and output pins and routed back to the
internal power-supply lines, where they meet at an
absorption device internal to the operational amplifier.
This protection circuitry is intended to remain inactive
during normal circuit operation.
When the operational amplifier connects into a circuit
such as that illustrated in Figure 50, the ESD
protection components are intended to remain
inactive and not become involved in the application
circuit operation. However, circumstances may arise
where an applied voltage exceeds the operating
voltage range of a given pin. Should this condition
occur, there is a risk that some of the internal ESD
protection circuits may be biased on, and conduct
current. Any such current flow occurs through
steering diode paths and rarely involves the
absorption device.
RF
+V
+VS
OPA211
RI
ESD CurrentSteering Diodes
-In
+In
Op-Amp
Core
Edge-Triggered ESD
Absorption Circuit
ID
VIN
Out
RL
(1)
-V
-VS
(1) VIN = +VS + 500mV.
Figure 50. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application
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Figure 50 depicts a specific example where the input
voltage, VIN, exceeds the positive supply voltage
(+VS) by 500mV or more. Much of what happens in
the circuit depends on the supply characteristics. If
+VS can sink the current, one of the upper input
steering diodes conducts and directs current to +VS.
Excessively high current levels can flow with
increasingly higher VIN. As a result, the datasheet
specifications recommend that applications limit the
input current to 10mA.
If the supply is not capable of sinking the current, VIN
may begin sourcing current to the operational
amplifier, and then take over as the source of positive
supply voltage. The danger in this case is that the
voltage can rise to levels that exceed the operational
amplifier absolute maximum ratings. In extreme but
rare cases, the absorption device triggers on while
+VS and –VS are applied. If this event happens, a
direct current path is established between the +VS
and –VS supplies. The power dissipation of the
absorption device is quickly exceeded, and the
extreme internal heating destroys the operational
amplifier.
Another common question involves what happens to
the amplifier if an input signal is applied to the input
while the power supplies +VS and/or –VS are at 0V.
Again, it depends on the supply characteristic while at
0V, or at a level below the input signal amplitude. If
20
the supplies appear as high impedance, then the
operational amplifier supply current may be supplied
by the input source via the current steering diodes.
This state is not a normal bias condition; the amplifier
most likely will not operate normally. If the supplies
are low impedance, then the current through the
steering diodes can become quite high. The current
level depends on the ability of the input source to
deliver current, and any resistance in the input path.
8.8 THERMAL CONSIDERATIONS
The primary issue with all semiconductor devices is
junction temperature (TJ). The most obvious
consideration is assuring that TJ never exceeds the
absolute maximum rating specified for the device.
However, addressing device thermal dissipation has
benefits beyond protecting the device from damage.
Even modest increases in junction temperature can
decrease op amp performance, and temperaturerelated errors can accumulate. Understanding the
power generated by the device within the specific
application and assessing the thermal effects on the
error tolerance lead to a better understanding of
system performance and thermal dissipation needs.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA211MDGKTEP
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
OBCM
V62/12619-01XE
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
OBCM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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