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OPA2156
SBOS900B – SEPTEMBER 2018 – REVISED JUNE 2019
OPA2156 36-V, Ultra-Low Noise, Wide-Bandwidth, CMOS, Precision, Rail-to-Rail,
Operational Amplifier
1 Features
3 Description
•
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•
•
•
•
•
•
•
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The OPA2156 is the first in a planned new generation
of 36-V, rail-to-rail operational amplifiers (op amps).
Ultra-low noise: 3 nV/√Hz at 10 kHz
Low offset voltage: ±25 µV
Low offset voltage drift: ±0.5 µV/°C
Low bias current: ±5 pA
Common-Mode Rejection: 120dB
Low Noise: 3 nV/√Hz at 10 kHz
Wide bandwidth: 25-MHz GBW
Open-loop voltage gain: 154 dB
High output current: 100 mA
Rail-to-rail input and output
High slew rate: 40 V/µs
Fast settling time: 600 ns (10-V step, 0.01%)
Wide supply: ±2.25 V to ±18 V, 4.5 V to 36 V
Industry standard packages:
– Dual in SOIC-8 and VSSOP-8
1
This devices offers very low offset voltage (±25 μV),
drift (±0.5 μV/°C), and low bias current (±5 pA)
combined with very low broadband voltage noise (3
nV/√Hz) .
Unique features, such as rail-to-rail input and output
voltage ranges, wide bandwidth (25 MHz) high output
current (100 mA), and high slew rate (40 V/µs) make
the OPA2156 a robust, high-performance operational
amplifier for high-voltage precision industrial
applications.
The OPA2156 op amp is available in 8-pin SOIC and
VSSOP packages and is specified over the industrial
temperature range of –40°C to +125°C.
Device Information(1)
PART NUMBER
2 Applications
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OPA2156
Data acquisition (DAQ)
Photodiode Transimpedance Amplifiers
Vibration monitor module
Analog input module
High-Resolution ADC Driver Amplifiers
Medical Equipment
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Low Input Voltage Noise Spectral Density
OPA2156 Transimpedance Configuration
Voltage Noise Density (nV/—Hz)
1000
100
V±
10
OPA2156
Vout
+
1
100m
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
D008
V+
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2156
SBOS900B – SEPTEMBER 2018 – REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information: OPA2156 ................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 15
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
15
19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 21
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2018) to Revision B
Page
•
Added new DGK (VSSOP) package and associated content to data sheet ......................................................................... 1
•
Changed Figure 8, Input Voltage Noise Spectral Density, to include frequencies up to 10 MHz .......................................... 8
•
Changed title of input bias and offset current curves (Figures 12 to 14) to specify SOIC package performance ................ 9
Changes from Original (September 2018) to Revision A
•
2
Page
First release of production-data data sheet............................................................................................................................ 1
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SBOS900B – SEPTEMBER 2018 – REVISED JUNE 2019
5 Pin Configuration and Functions
D and DGK Packages
8-Pin SOIC and 8-Pin VSSOP
Top View
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
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OPA2156
SBOS900B – SEPTEMBER 2018 – REVISED JUNE 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
±20
(+40, single supply)
Supply voltage, VS = (V+) – (V–)
Voltage
Signal input pins
Common-mode
(V–) – 0.5
(V+) + 0.5
Differential
0.5
Current
±10
Output short circuit (2)
(2)
V
V
mA
Continuous
Temperature
(1)
UNIT
Operating junction
–40
150
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extendedperiods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
VALUE
UNIT
±3000
V
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply voltage, VS = (V+) – (V–)
4.5 (±2.25)
36 (±18)
V
(1)
–40
125
°C
Specified temperature (SOIC)
(1)
Please see Thermal Considerations section for information on ambient vs device junction temperature
6.4 Thermal Information: OPA2156
OPA2156
THERMAL METRIC (1)
8 PINS
UNIT
D (SOIC)
DGK (VSSOP)
RθJA
Junction-to-ambient thermal resistance
119.2
163.8
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
51.1
52.5
°C/W
RθJB
Junction-to-board thermal resistance
64.7
86.5
°C/W
ψJT
Junction-to-top characterization parameter
9.7
5.1
°C/W
ψJB
Junction-to-board characterization parameter
63.5
84.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOS900B – SEPTEMBER 2018 – REVISED JUNE 2019
6.5 Electrical Characteristics
at TA = 25°C, VS = ±2.25V to ±18V, VCM =VOUT = VS / 2, and RL = 2 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±25
±200
µV
±300
µV
±3
mV
±5
mV
OFFSET VOLTAGE
VOS
Input offset voltage,
PMOS
TA = –40°C to +85°C
TA = –40°C to +125°C
See Typical Characteristics
VCM = (V+) – 1.25 V
VOS
Input offset voltage,
NMOS
±0.25
VCM = (V+) – 1.25 V, TA = –40°C to +125°C (SOIC)
VCM = (V+) – 1.25 V, TA = –40°C to +105°C (MSOP)
dVOS/dT
Input offset voltage drift
PMOS, SOIC
TA = –40°C to +125°C
PMOS, MSOP
TA = –40°C to +105°C
NMOS, VCM = (V+) – 1.25 V
TA = –40°C to +125°C
±0.5
±3
±0.3
PSRR
Power-supply rejection
ratio
µV/°C
±1
±4.5
TA = –40°C to +125°C (SOIC)
±5
TA = –40°C to +105°C (MSOP)
µV/V
INPUT BIAS CURRENT
IB
Input bias current
SOIC
±5
±40
pA
MSOP
±5
±80
pA
TA = –40°C to +85°C (SOIC)
±1.5
nA
TA = –40°C to +85°C (MSOP)
±15
nA
TA = –40°C to +125°C
See Typical Characteristics
±2
IOS
Input offset current
nA
±40
pA
TA = –40°C to +85°C (SOIC)
±1.5
nA
TA = –40°C to +85°C (MSOP)
±2.5
nA
TA = –40°C to +125°C
See Typical Characteristics
nA
NOISE
En
Input voltage noise
en
Input voltage noise
density
(V–) < VCM < (V+) – 2.25 V
f = 0.1 Hz to 10 Hz
1.9
(V+) – 1.25 V < VCM < (V+)
f = 0.1 Hz to 10 Hz
3.4
f = 100 Hz
en
in
Input voltage noise
density
Input current noise
density
(V–) < VCM < (V+) – 2.25 V
(V+) – 1.25 V < VCM < (V+)
µVPP
12.0
f = 1 kHz
4
f = 10 kHz
3.0
f = 100 Hz
13.0
f = 1 kHz
9.7
f = 10 kHz
4.0
f = 1 kHz
nV/√Hz
19
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
range
CMRR
Common-mode
rejection ratio, PMOS
(V–) < VCM < (V+) – 2.25 V, VS = ±18 V
CMRR
Common-mode
rejection ratio, PMOS
TA = –40°C to +125°C (SOIC)
CMRR
Common-mode
rejection ratio, PMOS
TA = –40°C to +105°C (MSOP)
CMRR
Common-mode
rejection ratio, NMOS
(V+) – 1.25 V < VCM < (V+), VS = ±18 V
CMRR
Common-mode
rejection ratio, NMOS
TA = –40°C to +125°C (SOIC)
CMRR
Common-mode
rejection ratio, NMOS
TA = –40°C to +105°C (MSOP)
(V–) – 0.1
106
(V+) + 0.1
V
120
100
dB
82
120
74
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SBOS900B – SEPTEMBER 2018 – REVISED JUNE 2019
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Electrical Characteristics (continued)
at TA = 25°C, VS = ±2.25V to ±18V, VCM =VOUT = VS / 2, and RL = 2 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT IMPEDANCE
ZID
Differential
ZIC
Common-mode
100 || 9.1
MΩ || pF
6 || 1.9
1012Ω ||
pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 0.6 V < VO < (V+) – 0.6 V, VS = ±18 V (SOIC)
130
154
(V–) + 0.6 V < VO < (V+) – 0.6 V, VS = ±18 V (MSOP)
128
154
dB
TA = –40°C to +85°C
126
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
20
MHz
Gain bandwidth product
G = 100
25
MHz
SR
Slew rate
VS = ±18 V, G = –1, 10-V step
40
V/µs
ts
Settling time
To 0.01%, CL = 20 pF
600
ns
tOR
Overload recovery time
G = –10
VS = ±18 V, G = –1, 10-V step
G = 1, f = 1 kHz, VO = 3.5 VRMS
dB
–126
G = 1, f = 20 kHz, VO = 3.5 VRMS
Crosstalk
ns
–132
0.000025
%
Total harmonic
distortion + noise
THD+N
100
dB
0.00005%
dc
150
dB
f = 100 kHz
120
dB
OUTPUT
VO
Voltage output swing
from power supply
ISC
Short-circuit current
CL
Capacitive load drive
ZO
Open-loop output
impedance
200
VS = ±18 V
250
100
mA
See Typical Characteristics
f = 1 MHz, IO = 0 A
mV
pF
25
Ω
POWER SUPPLY
4.4
IQ
Quiescent current per
amplifier
IO = 0 A
TA = –40°C to +125°C (SOIC)
5.2
5.2
TA = –40°C to +105°C (MSOP)
mA
mA
mA
TEMPERATURE
6
Thermal protection
170
°C
Thermal hysteresis
15
°C
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SBOS900B – SEPTEMBER 2018 – REVISED JUNE 2019
6.6 Typical Characteristics
Table 1. Table of Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage vs Temperature (PMOS)
Figure 2
Offset Voltage vs Temperature (NMOS)
Figure 3
Offset Voltage vs Power Supply
Figure 4
Offset Voltage vs Common-Mode Voltage
Figure 5
Offset Voltage vs Common-Mode Voltage in Transition Region
Figure 6
Offset Voltage Drift
Figure 7
Input Voltage Noise Spectral Density
Figure 8
0.1-Hz to 10-Hz Noise
Figure 9
THD+N vs Frequency
Figure 10
THD+N vs Output Amplitude
Figure 11
Input Bias and Offset Current vs Common-Mode Voltage
Figure 12
Input Bias and Offset Current vs Temperature
Figure 13
Input Bias and Offset Current vs Temperature
Figure 14
Open-Loop Output Impedance vs Frequency
Figure 15
Maximum Output Voltage vs Frequency
Figure 16
Open-Loop Gain and Phase Vs Frequency
Figure 17
Open-Loop Gain vs Temperature
Figure 18
Closed-Loop Gain vs Frequency
Figure 19
CMRR vs Frequency
Figure 20
PSRR vs Frequency
Figure 21
CMRR vs Temperature
Figure 22
PSRR vs Temperature
Figure 23
Positive Output Voltage vs Output Current
Figure 24
Negative Output Voltage vs Output Current
Figure 26
Short-Circuit Current vs Temperature
Figure 25
No Phase Reversal
Figure 27
Phase Margin vs Capacitive Load
Figure 28
Small-Signal Overshoot vs Capacitive Load (G = –1)
Figure 29
Small-Signal Overshoot vs Capacitive Load (G= +1)
Figure 30
Settling Time
Figure 31
Negative Overload Recovery
Figure 32
Positive Overload Recovery
Figure 33
Small-Signal Step Response (Noninverting)
Figure 34
Small-Signal Step Response (Inverting)
Figure 35
Large-Signal Step Response (Noninverting)
Figure 36
Large-Signal Step Response (Inverting)
Figure 37
Quiescent Current vs Supply Voltage
Figure 38
Quiescent Current vs Temperature
Figure 39
Channel Separation vs Frequency
Figure 40
EMIRR vs Frequency
Figure 41
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
18%
200
5 Typical Units Shown
150
100
Offset Voltage (uV)
Total Amplifiers (%)
15%
12%
9%
6%
50
0
-50
-100
3%
-150
0
-200 -160 -120
-80
-40
0
40
80
Offset Voltage (PV)
120
160
-200
-50
200
-25
0
TA = 25°C
75
100
125
PMOS region
Figure 1. Offset Voltage Production Distribution
Figure 2. Offset Voltage vs Temperature (PMOS)
150
1.5
5 Typical Units Shown
5 Typical Units Shown
1
100
Offset Voltage (V)
Offset Voltage (mV)
25
50
Temperature (qC)
0.5
0
-0.5
-1
50
0
-50
-100
-1.5
-50
-150
-25
0
25
50
Temperature (qC)
75
100
125
4
8
12
16
20
24
Supply Voltage (V)
28
32
36
NMOS region
Figure 3. Offset Voltage vs Temperature (NMOS)
Figure 4. Offset Voltage vs Power Supply
2.2
40
85 qC
30
1.8
25 qC
Offset Voltage (mV)
Offset Voltage (uV)
20
10
0
-10
-20
5 Typical Units Shown
1.4
-40 qC
1
0.6
0.2
-0.2
-0.6
-1
Vcm = 15.75V
-1.4
-30
-1.8
-40
-18
-14
-10
-6
-2
2
6
Input Common-mode Voltage (V)
10
14
Vcm = 16.75V
-2.2
14
14.5
15
15.5
16
16.5
17
Input Common-mode Voltage (V)
17.5
18
Transition between PMOS and NMOS regions
Figure 5. Offset Voltage vs Common-Mode Voltage
8
Figure 6. Offset Voltage vs Common-Mode Voltage in
Transition Region
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
30%
Voltage Noise Density (nV/—Hz)
1000
Amplifiers (%)
25%
20%
15%
10%
5%
0
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5
Offset Voltage Drift (uV/qC)
2
2.5
100
10
1
100m
3
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
D008
TA = –40°C to +125°C
Figure 7. Offset Voltage Drift
Figure 8. Input Voltage Noise Spectral Density
1, RLoad = 10K:
1, RLoad = 2K:
1, RLoad = 10K:
1, RLoad = 2K:
-120
0.0001
Total Harmonic Distortion
Total Harmonic Distortion
Noise ( )
Input Referred Voltage Noise (500 nV/div)
G
G
G
G
Noise (dB)
-100
0.001
-140
1E-5
100
Time (1 s/div)
1k
Frequency (Hz)
10k
3.5 VRMS, 80-kHz measurement bandwidth
Figure 9. 0.1-Hz to 10-Hz Noise
Figure 10. THD+N vs Frequency
1, RLoad = 10K:
1, RLoad = 2K:
1, RLoad = 10K:
1, RLoad = 2K: -80
-100
0.001
-120
0.0001
1E-5
10m
-140
100m
1
Output Amplitude (VRMS)
10
80
Ib+
60
Input Bias Current (pA)
G
G
G
G
Total Harmonic Distortion + Noise (dB)
Noise (%)
Total Harmonic Distortion
0.01
100
-60
0.1
Ib-
40
20
0
-20
-40
Ios
-60
-80
-100
-20
-16
-12
-8
-4
0
4
8
12
Input Common-mode Voltage (V)
16
20
1 kHz, 80-kHz measurement bandwidth
Figure 11. THD+N vs Output Amplitude
Figure 12. Input Bias and Offset Current vs Common-Mode
Voltage (SOIC)
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
1.4
45
1.2
Ib+ and Ib- (nA)
Ib+, Ib-, and Ios (nA)
35
Ib+
1
0.8
0.6
Ib-
0.4
25
15
0.2
5
0
Ios
-0.2
-60
-40
-20
0
20
40
Temperature (qC)
60
80
-5
50
100
60
70
TA = –55°C to +85°C
80
90
100
Temperature (qC)
110
120
130
TA = –55°C to +125°C
Figure 13. Input Bias and Offset Current vs Temperature
(SOIC)
Figure 14. Input Bias and Offset Current vs Temperature
(SOIC)
50
100
Vs=r18 V
Vs=r5 V
Vs=r2.25 V
Output Voltage (V PP)
40
Zo (:
10
1
30
20
10
0
0.1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
1
100M
140
Gain
Phase 210
120
180
100
150
80
120
60
90
40
60
20
30
0
0
-20
100m
-30
1
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
Figure 17. Open-Loop Gain and Phase vs Frequency
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
Figure 16. Maximum Output Voltage vs Frequency
170
160
Open-Loop Gain (dB)
240
Phase (q)
Gain (dB)
Figure 15. Open-Loop Output Impedance vs Frequency
160
10
0.01
Vs = 36V
150
140
0.1
Vs = 4.5V
130
120
-40
Open-Loop Gain (uV/V)
1
-20
0
20
40
60
80
Temperature (qC)
100
120
1
140
Figure 18. Open-Loop Gain vs Temperature
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
50
140
G= 1
G= 1
G= 10
G= +100
40
Rejection Ratio (dB)
Gain (dB)
30
CMRR
120
20
10
0
-10
100
80
60
40
20
-20
100
0
1k
10k
100k
Frequency (Hz)
1M
10M
1
10
Figure 19. Closed-Loop Gain vs Frequency
PSRR
PSRR
140
Common-mode Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
100k
1M
10M
100
120
Figure 20. CMRR vs Frequency
120
100
80
60
40
20
1
10
100
1k
10k
Frequency (Hz)
100k
1M
120
118
116
114
-40
0
10M
-20
Figure 21. PSRR vs Frequency
125
25
50
Temperature (qC)
75
80
100
Figure 23. PSRR vs Temperature
1
125
17.5
17
25 qC
16.5
Output Voltage (V)
0.32
130
0
20
40
60
Temperature (qC)
18
Power Supply Rejection Ratio (uV/V)
135
-25
0
Figure 22. CMRR vs Temperature
0.1
140
Power Supply Rejection Ratio (dB)
1k
10k
Frequency (Hz)
122
160
120
-50
100
16
-40 qC
15.5
125 qC
15
14.5
85 qC
14
13.5
13
12.5
12
0
10
20
30
40 50 60 70 80
Output Current (mA)
90 100 110 120
Figure 24. Positive Output Voltage vs Output Current
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
-12
140
-12.5
Output Voltage (V)
Short Circuit Current (mA)
-13
-13.5
120
100
85 qC
-14
-14.5
125 qC
-15
-15.5
-16
-16.5
80
-40 qC
-17
25 qC
-17.5
60
-40
-18
-20
0
20
40
60
Temperature (qC)
80
100
0
120
Figure 25. Short-Circuit Current vs Temperature
20
40
60
80
100
Output Current (mA)
120
140
Figure 26. Negative Output Voltage vs Output Current
80
Vin (V)
Vout (V)
70
Voltage (5V/div)
Phase Margin (q)
60
50
40
30
20
10
0
10
Time (100 Ps/div)
Figure 27. No Phase Reversal
Figure 28. Phase Margin vs Capacitive Load
RISO = 0
RISO = 25
RISO = 50
90
80
50
RISO = 0
RISO = 25
RISO = 50
70
Overshoot ( )
Overshoot ( )
1000
100
70
60
100
Cload (pF)
40
30
60
50
40
30
20
20
10
0
10
10
100
Capactiance (pF)
1000
0
10
10-mV output step, gain = –1
1000
10-mV output step, gain = +1
Figure 29. Small Signal Overshoot vs Capacitive Load
12
100
Capactiance (pF)
Figure 30. Small Signal Overshoot vs Capacitive Load
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
Voltage (5 V/div)
Output (1 mV/div)
Falling
Rising
VIN
VOUT
Time (200 ns/div)
Time (200 ns/div)
Vin = 5-Vpp
Gain = –10
Figure 31. Normalized Settling Time
Figure 32. Negative Overload Recovery
VIN
VOUT
Voltage (5 V/div)
Voltage (5 mV/div)
VIN
VOUT
Time (200 ns/div)
Time (1 Ps/div)
Gain = –10
Vin = 10 mVpp, gain = 1
Figure 33. Positive Overload Recovery
Figure 34. Small-Signal Step Response (Noninverting)
Vin
Vout
Voltage (5 V/div)
Voltage (5 mV/div)
VIN
VOUT
Time (1 Ps/div)
Time (1 Ps/div)
Vin = 10 mVpp, gain = –1
Vin = 5 Vpp, gain = 1
Figure 35. Small-Signal Step Response (Inverting)
Figure 36. Large-Signal Step Response (Noninverting)
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 30 pF (unless otherwise noted)
5
Vin
Vout
Voltage (5 V/div)
Quiescent Current (mA)
4.5
4
3.5
Vs = 4.5V
3
2.5
2
Time (1 Ps/div)
0
4
8
12
16
20
24
Supply Voltage (V)
28
32
36
Vin = 5 Vpp, gain = –1
Figure 37. Large Signal Step Response (Inverting)
Figure 38. Quiescent Current vs Supply Voltage
4.44
-60
4.41
-80
Channel Seperation (dB)
Quiescent Current (mA)
4.38
4.35
Vs = 36V
4.32
4.29
4.26
4.23
Vs = 4.5V
4.2
4.17
-100
-120
-140
-160
4.14
4.11
-60
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
140
-180
1k
Figure 39. Quiescent Current vs Temperature
10k
100k
Frequency (Hz)
1M
10M
Figure 40. Channel Separation vs Frequency
120
EMIRR IN+ (dB)
100
80
60
40
20
10M
100M
1G
Frequency (Hz)
10G
Prf =-10 dBm
Figure 41. EMIRR vs Frequency
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7 Detailed Description
7.1 Overview
The OPA2156 is laser trimmed to improve offset and uses a three-gain-stage architecture to achieve very low
noise and distortion. The Functional Block Diagram shows a simplified schematic of the OPA2156 (one channel
shown). The device consists of a low noise input stage and feed-forward pathway coupled to a high-current
output stage. This topology exhibits superior distortion performance under a wide range of loading conditions
compared to other operational amplifiers.
7.2 Functional Block Diagram
Feedforward
Path
Ca
Cb
+IN
High-Current
Output
Stage
2nd Gain
Stage
Low-Noise
Input Stage
OUT
-IN
7.3 Feature Description
7.3.1 Phase Reversal Protection
The OPA2156 has internal phase-reversal protection. Many op amps exhibit phase reversal when the input is
driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits
when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into
the opposite rail. The input of the OPA2156 prevents phase reversal with excessive common-mode voltage.
Instead, the appropriate rail limits the output voltage. This performance is shown in Figure 42.
20
15
Voltage (V)
10
5
0
-5
-10
-15
-20
VIN
VOUT
Time (125 s/div)
C004
Figure 42. Output Waveform Devoid of Phase Reversal During an Input Overdrive Condition
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Feature Description (continued)
7.3.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful.
Figure 43 illustrates the ESD circuits contained in the OPA2156 (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
TVS
+
±
RF
+VS
R1
IN±
250 Ÿ
RS
IN+
250 Ÿ
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
+
±
±VS
TVS
Figure 43. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA2156 but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a safe level.
16
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Feature Description (continued)
When the operational amplifier connects into a circuit (see Figure 43), the ESD protection components are
intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any
such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 43 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current
through the steering diodes can become quite high. The current level depends on the ability of the input source
to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see Figure 43. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
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Feature Description (continued)
7.3.3 Thermal Considerations
Through normal operation the OPA2156 will experience self-heating, a natural increase in the die junction
temperature which occurs in every amplifier. This is a result of several factors including the quiescent power
consumption, the package’s thermal dissipation, PCB layout and the device operating conditions.
To fully ensure the amplifier will operate without entering thermal shutdown it is important to calculate the
approximate junction (die) temperature which can be done using Equation 1.
TJ
PD 4JA TA
(1)
Equation 2 shows the approximate junction temperature for the OPA2156 while unloaded with an ambient
temperature of 25°C.
TJ
(36V 4.4mA) 120qC / W
TJ
44qC
25qC
(2)
For high voltage, high precision amplifiers such as the OPA2156 the junction temperature can easily be 10s of
degrees higher than the ambient temperature in a quiescent (unloaded) condition. If the device then begins to
drive a heavy load the junction temperature may rise and trip the thermal shutdown circuit. The Figure 44 shows
the maximum output voltage of the OPA2156 without entering thermal shutdown vs ambient temperature in both
a loaded and unloaded condition.
Max Output Voltage (V)
20
15
10
5
Vs Max (No Load)
Vs Max (600: Load)
0
0
25
50
75
100
125
Ambient Temperature (qC)
150
175
Figure 44. OPA2156 Thermal Safe Operating Area
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Feature Description (continued)
7.3.4 Thermal Shutdown
The internal power dissipation of any amplifier causes the internal (junction) temperature to rise. This
phenomenon is called self heating. The OPA2156 has a thermal protection feature that prevents damage from
self heating.
This thermal protection works by monitoring the temperature of the output stage and turning off the op amp
output drive for temperatures above approximately 170°C. Thermal protection forces the output to a highimpedance state. The OPA2156 is also designed with approximately 15°C of thermal hysteresis. Thermal
hysteresis prevents the output stage from cycling in and out of the high-impedance state. The OPA2156 returns
to normal operation when the output stage temperature falls below approximately 155°C.
The absolute maximum junction temperature of the OPA2156 is 150°C. Exceeding the limits shown in the
Absolute Maximum Ratings table may cause damage to the device. Thermal protection triggers at 170°C
because of unit-to-unit variance, but does not interfere with device operation up to the absolute maximum ratings.
This thermal protection is not designed to prevent this device from exceeding absolute maximum ratings, but
rather from excessive thermal overload.
7.3.5 Common-Mode Voltage Range
The OPA2156 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs. The N-channel pair is active for input voltages close to the positive rail,
typically (V+) – 2.25 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV
below the negative supply to approximately (V+) – 1.25 V. There is a small transition region, typically (V+) –
2.25V to (V+) – 1.25 V in which both input pairs are active. This transition region varies modestly with process
variation. Within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance are degraded
compared to operation outside this region.
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when
possible. The OPA2156 uses a precision trim for both the N-channel and P-channel regions. This technique
enables significantly lower levels of offset than previous-generation devices, causing variance in the transition
region of the input stages to appear exaggerated relative to offset over the full common-mode range.
7.3.6 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
7.4 Device Functional Modes
The OPA2156 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPA2156 is 36 V (±18 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA2156 offers excellent dc precision and ac performance. The device operates with up to 36-V supply rails
offering true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as
25-MHz bandwidth and low input bias. These features make the OPA2156 a robust, high-performance
operational amplifier for high-voltage industrial applications.
8.1.1 Slew Rate Limit for Input Protection
In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.
By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down
at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one
additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high
output current and slew rate of the OPA2156 make the device an optimal amplifier to achieve slew rate control
for both dual- and single-supply systems.Figure 45 shows the OPA2156 in a slew-rate limit design.
Op Amp Gain Stage
Slew Rate Limiter
C1
R1
VCC
VCC
+
VIN
R2
OPA2156
-
+
OPA2156
+
VOUT
VEE
RL
VEE
Figure 45. Slew Rate Limiter Uses One Op Amp
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp.
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8.2 Typical Application
The combination of low input bias, high slew rate and a rail-to-rail input and output enable the OPA2156 to serve
as an accurate differential photodiode transimpedance amplifier. This application example shows the design of
such a system.
CF 2.7pF
RF 54.9kŸ
+12V
OPA2156
+
-12V
+
VOUT
-
+
-
OPA2156
+12V
RF 54.9kŸ
CF 2.7pF
Figure 46. OPA2156 Configured as a Differential Photodiode Transimpedance Amplifier
8.2.1 Design Requirements
The design requirements for this design are:
• Photodiode current: 0 µA to 90 µA
• Output voltage: –5 V to 5 V
• Supply voltage: ±12 V
• Filter cutoff frequency: 1 MHz
8.2.2 Detailed Design Procedure
In this example the OPA2156 serves as a transimpedance amplifier for a differential photodiode. The differential
configuration allows for a wider output range (0 to 10-V differential) compared to a single-ended configuration (0
V to 5 V). This output can be connected to a differential successive approximation register (SAR) analog-todigital converter (ADC). The basic equation for a differential transimpedance amplifier output voltage is shown in
Equation 3.
VOUT
IPD u 2 u RF
(3)
Equation 3 can be rearranged to calculate the value of the feedback resistors as shown in Equation 4.
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Typical Application (continued)
VOUT ( MAX ) VOUT ( MIN )
d RF
2 u IIN ( MAX )
5V ( 5V )
d 55.6k :
2 u 90 P A
(4)
Adding a capacitor to the feedback loop creates a filter which will remove undesired noise beyond its cutoff
frequency. For this application a 1-MHz cutoff frequency was selected. The equation for an RC filter is provided
in Equation 5.
1
2 u S u RF u CF
fC
(5)
Rearranging this equation to solve for the capacitor value is show in Equation 6.
CF d
1
d 2.7 pF
2 u S u 54k : u 1MHz
(6)
For more information on photodiode transimpedance amplifier system design and for a single-ended example,
see TIDU535: 1 MHz, Single-Supply, Photodiode Amplifier Reference Design.
8.2.3 Application Curves
120
10
9
100
7
6
Gain (dB)
Output Voltage (V)
8
5
4
80
-3dB = 1.6MHz
60
3
40
2
1
0
20
0
15
30
45
60
Input Current (PA)
75
90
100
Figure 47. Differential Photodiode DC Transfer
10k
Frequency (Hz)
1M
100M
Figure 48. Differential Photodiode AC Transfer
150
100
80
90
60
60
40
30
20
0
0
Gain (dB)
120
-30
-20
Gain
Phase
-60
100
Phase (degrees)
Phase Margin = 60 deg
10k
Frequency (Hz)
1M
-40
100M
Figure 49. Differential Photodiode Stability
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9 Power Supply Recommendations
The OPA2156 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-supply
applications.
– Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
• Make sure to physically separate digital and analog grounds paying attention to the flow of the ground
current. Separate grounding for analog and digital portions of circuitry is one of the simplest and mosteffective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup.
• In order to reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 50, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Clean the PCB following board assembly for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. After any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced
into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30
minutes is sufficient for most circumstances.
10.1.1 Power Dissipation
The OPA2156 op amp is capable of driving a variety of loads with a power-supply voltage up to ±18 V and full
operating temperature range. Internal power dissipation increases when operating at high supply voltages and/or
high output currents. Copper leadframe construction used in the OPA2156 improves heat dissipation compared
to conventional materials. Circuit board layout can also help minimize junction temperature rise. Wide copper
traces help dissipate the heat by acting as an additional heat sink. Temperature rise can be further minimized by
soldering the devices to the circuit board rather than using a socket.
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Layout Guidelines (continued)
The OPA2156 has an internal thermal protection feature which prevents it from being damaged due to self
heating, or the internal heating generated during normal operation. The protection circuitry works by monitoring
the temperature of the output stage and turns of the output drive if the junction temperature of the device rises to
approximately 170°C. The device has a thermal hysteresis of approximately 15°C, which allows the device to
safely cool down before returning to normal operation at approximately 155°C. TI recommends that the system
design takes into account the thermal dissipation of the OPA2156 to ensure that the recommended operating
junction temperature of 125°C is not exceeded to avoid decreasing the lifespan of the device or permanently
damaging the amplifier.
10.2 Layout Example
+
VIN A
+
VIN B
VOUT A
RG
VOUT B
RG
RF
RF
(Schematic Representation)
Place components
close to device and to
each other to reduce
parasitic errors.
Output A
VS+
OUTPUT A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
V+
RF
Output B
GND
-IN A
OUTPUT B
+IN A
-IN B
RF
RG
VIN A
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
VS±
+IN B
Ground (GND) plane on another layer
VIN B
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible.
Figure 50. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder at
http://www.ti.com/tool/tina-ti.
11.1.1.2 TI Precision Designs
TI Precision Designs, available online at http://www.ti.com/ww/en/analog/precision-designs/, are analog solutions
created by TI’s precision analog applications experts and offer the theory of operation, component selection,
simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful
circuits.
11.2 Documentation Support
11.2.1 Related Documentation
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
• Texas Instruments, 0-1A, Single-Supply, Low-Side, Current Sensing Solution reference design
• Texas Instruments, Op Amps for Everyone design reference
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: OPA2156
25
OPA2156
SBOS900B – SEPTEMBER 2018 – REVISED JUNE 2019
www.ti.com
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
Submit Documentation Feedback
Copyright © 2018–2019, Texas Instruments Incorporated
Product Folder Links: OPA2156
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2156ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2156
OPA2156IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1THV
OPA2156IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1THV
OPA2156IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2156
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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