OPA2171AIDR

Order Now Product Folder Support & Community Tools & Software Technical Documents Reference Design OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 OPAx171 36-V, Single-Supply, SOT-553, General-Purpose Operational Amplifiers 1 Features 3 Description • • • • • • • • • • • • The OPA171, OPA2171, and OPA4171 (OPAx171) are a family of 36-V, single-supply, low-noise operational amplifiers with the ability to operate on supplies ranging from 2.7 V (±1.35 V) to 36 V (±18 V). These devices are available in micro-packages and offer low offset, drift, and bandwidth with low quiescent current. The single, dual, and quad versions all have identical specifications for maximum design flexibility. 1 • Supply Range: 2.7 to 36 V, ±1.35 V to ±18 V Low Noise: 14 nV/√Hz Low Offset Drift: ±0.3 µV/°C (Typical) RFI Filtered Inputs Input Range Includes The Negative Supply Input Range Operates To Positive Supply Rail-to-Rail Output Gain Bandwidth: 3 MHz Low Quiescent Current: 475 µA per Amplifier High Common-Mode Rejection: 120 dB (Typical) Low-Input Bias Current: 8 pA Industry-Standard Packages: – 8-Pin SOIC – 8-Pin MSOP – 14-Pin TSSOP microPackages: – Single in SOT-553 – Dual in VSSOP-8 2 Applications • • • • • • • • • Unlike most operational amplifiers, which are specified at only one supply voltage, the OPAx171 family is specified from 2.7 to 36 V. Input signals beyond the supply rails do not cause phase reversal. The OPAx171 family is stable with capacitive loads up to 300 pF. The input can operate 100 mV below the negative rail and within 2 V of the top rail during normal operation. These devices can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of the top rail. The OPAx171 series of operational amplifiers are specified from –40°C to +125°C. Device Information(1) PART NUMBER Tracking Amplifier in Power Modules Merchant Power Supplies Transducer Amplifiers Bridge Amplifiers Temperature Measurements Strain Gauge Amplifiers Precision Integrators Battery-Powered Instruments Test Equipment SPACE 1.60 mm × 2.90 mm OPA2171 SOIC (8) 3.90 mm × 4.90 mm TSSOP (14) 4.40 mm × 5.00 mm SOIC (14) 3.90 mm × 8.65 mm OPA4171 (1) For all available packages, see the orderable addendum at the end of the data sheet. Offset Voltage vs Power Supply 350 10 Typical Units Shown 800 BODY SIZE (NOM) SOT-23 (5) Offset Voltage vs Common-Mode Voltage 1000 PACKAGE OPA171 VSUPPLY = ±2.25 V to ±18 V 10 Typical Units Shown 250 600 150 200 VOS (mV) VOS (mV) 400 0 -200 -400 50 -50 -150 -600 -250 -800 VCM = -18.1 V -350 -1000 -20 -15 -10 -5 0 VCM (V) 5 10 15 20 0 2 4 6 8 10 12 14 16 18 20 VSUPPLY (V) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7 1 1 1 2 4 7 Absolute Maximum Ratings ...................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 7 Thermal Information: OPA171 .................................. 8 Thermal Information: OPA2171 ................................ 8 Thermal Information: OPA4171 ................................ 8 Electrical Characteristics........................................... 9 Typical Characteristics: Table of Graphs ................ 11 Typical Characteristics ........................................... 12 Detailed Description ............................................ 18 7.1 Overview ................................................................. 18 7.2 Functional Block Diagram ....................................... 18 7.3 Feature Description................................................. 18 7.4 Device Functional Modes........................................ 20 8 Application and Implementation ........................ 21 8.1 Application Information............................................ 21 8.2 Typical Application ................................................. 23 9 Power Supply Recommendations...................... 27 10 Layout................................................................... 27 10.1 Layout Guidelines ................................................ 27 10.2 Layout Example .................................................... 27 11 Device and Documentation Support ................. 28 11.1 11.2 11.3 11.4 11.5 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 28 28 28 28 28 12 Mechanical, Packaging, and Orderable Information ........................................................... 28 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (April 2015) to Revision F Page • Changed minimum supply voltage value from ±20 V to 0 V in Absolute Maximum Ratings table ....................................... 7 • Added maximum supply voltage value of 40 V to Absolute Maximum Ratings table ........................................................... 7 • Rewrote Electrical Overstress subsection content in Application Information section ........................................................ 21 Changes from Revision D (September 2012) to Revision E Page • Changed device title (removed "Value Line Series").............................................................................................................. 1 • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 Changes from Revision C (June 2011) to Revision D • Page Added "Value Line Series" to title........................................................................................................................................... 1 Changes from Revision B (November 2010) to Revision C Page • Added MSOP-8 package to device graphic ........................................................................................................................... 1 • Added MSOP-8 package to Features bullets ......................................................................................................................... 1 • Added MSOP-8 package to Product Family table.................................................................................................................. 1 • Updated pinout configurations for OPA2171 and OPA4171 .................................................................................................. 4 • Added MSOP-8 package to OPA2171 Thermal Information table ......................................................................................... 8 • Added new row for Voltage Output Swing from Rail parameter to Output subsection of Electrical Characteristics............ 10 • Changed Voltage Output Swing from Rail parameter to over temperature in Output subsection of Electrical Characteristics ...................................................................................................................................................................... 10 • Changed Figure 9................................................................................................................................................................. 12 2 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 OPA171, OPA2171, OPA4171 www.ti.com SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 Changes from Revision A (November, 2010) to Revision B Page • Changed input offset voltage specification ............................................................................................................................. 9 • Changed input offset voltage, over temperature specification ............................................................................................... 9 • Changed quiescent current per amplifier, over temperature specification ........................................................................... 10 Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 Submit Documentation Feedback 3 OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 www.ti.com 5 Pin Configuration and Functions OPA171 DRL Package 5-Pin SOT-553 Top View IN+ 1 V- 2 IN- 3 5 V+ 4 OUT OPA171 DBV Package 5-Pin SOT-23 Top View OUT 1 V- 2 +IN 3 5 V+ 4 -IN OPA171 D Package 8-Pin SOIC Top View (1) NC(1) 1 8 NC(1) -IN 2 7 V+ +IN 3 6 OUT V- 4 5 NC(1) NC- no internal connection Pin Functions: OPA171 PIN NAME I/O DESCRIPTION DRL DBV D +IN 1 3 3 I Noninverting input –IN 3 4 2 I Inverting input OUT 4 1 6 O Output V+ 5 5 7 — Positive (highest) supply V– 2 2 4 — Negative (lowest) supply NC — — 1, 5, 8 — No internal connection (can be left floating) 4 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 OPA171, OPA2171, OPA4171 www.ti.com SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 OPA2171 D, DCU, and DCK Packages 8-Pin SO, VSSOP and MSOP Top View OUT A 1 8 V+ -IN A 2 7 OUT B +IN A 3 6 -IN B V- 4 5 +IN B Pin Functions: OPA2171 PIN I/O DESCRIPTION NAME NO. +IN A 3 I Noninverting input +IN B 5 I Noninverting input –IN A 2 I Inverting input –IN B 6 O Inverting input OUT A 1 O Output OUT B 7 — Output V+ 8 — Positive (highest) supply V– 4 — Negative (lowest) supply Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 Submit Documentation Feedback 5 OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 www.ti.com OPA4171 D and PW Packages 14-Pin SO and TSSOP Top View OUT A 1 14 OUT D -IN A 2 13 -IN D +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C Pin Functions: OPA4171 PIN I/O DESCRIPTION NAME NO. +IN A 3 I Noninverting input +IN B 5 I Noninverting input +IN C 10 I Noninverting input +IN D 12 I Noninverting input –IN A 2 I Inverting input –IN B 6 I Inverting input –IN C 9 I Inverting input –IN D 13 I Inverting input OUT A 1 O Output OUT B 7 O Output OUT C 8 O Output OUT D 14 O Output V+ 4 — Positive (highest) supply V– 11 — Negative (lowest) supply 6 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 OPA171, OPA2171, OPA4171 www.ti.com SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range, (unless otherwise noted) (1) MIN MAX UNIT 0 40 V Voltage (V–) – 0.5 (V+) + 0.5 V Current –10 10 mA Supply voltage Signal input terminals Output short circuit (2) Continuous Operating temperature –55 Junction temperature Storage temperature (1) (2) –65 150 °C 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Short-circuit to ground, one amplifier per package. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) V ±750 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Supply voltage (V+ – V–) Specified temperature NOM MAX UNIT 4.5 (±2.25) 36 (±18) V –40 125 °C Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 Submit Documentation Feedback 7 OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 www.ti.com 6.4 Thermal Information: OPA171 OPA171 THERMAL METRIC (1) D (SO) DBV (SOT-23) DRL (SOT-553) 8 PINS 5 PINS 5 PINS UNIT 208.1 °C/W RθJA Junction-to-ambient thermal resistance 149.5 245.8 RθJC(top) Junction-to-case(top) thermal resistance 97.9 133.9 0.1 °C/W RθJB Junction-to-board thermal resistance 87.7 83.6 42.4 °C/W ψJT Junction-to-top characterization parameter 35.5 18.2 0.5 °C/W ψJB Junction-to-board characterization parameter 89.5 83.1 42.2 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Thermal Information: OPA2171 OPA2171 THERMAL METRIC (1) D (SO) DGK (MSOP) DCU (VSSOP) 8 PINS 8 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 134.3 175.2 195.3 °C/W RθJC(top) Junction-to-case(top) thermal resistance 72.1 74.9 59.4 °C/W RθJB Junction-to-board thermal resistance 60.6 22.2 115.1 °C/W ψJT Junction-to-top characterization parameter 18.2 1.6 4.7 °C/W ψJB Junction-to-board characterization parameter 53.8 22.8 114.4 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report . 6.6 Thermal Information: OPA4171 OPA4171 THERMAL METRIC (1) D (SOIC) PW (TSSOP) 14 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal resistance 93.2 106.9 °C/W RθJC(top) Junction-to-case(top) thermal resistance 51.8 24.4 °C/W RθJB Junction-to-board thermal resistance 49.4 59.3 °C/W ψJT Junction-to-top characterization parameter 13.5 0.6 °C/W ψJB Junction-to-board characterization parameter 42.2 54.3 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W (1) 8 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 OPA171, OPA2171, OPA4171 www.ti.com SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 6.7 Electrical Characteristics at TA = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT mV OFFSET VOLTAGE VOS Input offset voltage dVOS/dT 0.25 ±1.8 Over temperature TA = –40°C to +125°C 0.3 ±2 mV Drift TA = –40°C to +125°C 0.3 ±2 µV/°C vs power supply VS = 4 to 36 V TA = –40°C to +125°C 1 ±3 µV/V Channel separation, DC DC 5 µV/V INPUT BIAS CURRENT Input bias current IB ±8 Over temperature TA = –40°C to +125°C Input offset current IOS ±15 pA ±3.5 nA ±4 Over temperature TA = –40°C to +125°C Input voltage noise f = 0.1 Hz to 10 Hz pA ±3.5 nA NOISE en Input voltage noise density 3 µVPP f = 100 Hz 25 nV/√Hz f = 1 kHz 14 nV/√Hz INPUT VOLTAGE (V–) – 0.1 V Common-mode voltage range (1) VCM CMRR Common-mode rejection ratio (V+) – 2 V V VS = ±2 V (V–) – 0.1 V < VCM < (V+) – 2 V TA = –40°C to +125°C 90 104 dB VS = ±18 V (V–) – 0.1 V < VCM < (V+) – 2 V TA = –40°C to +125°C 104 120 dB INPUT IMPEDANCE Differential Common-mode 100 || 3 MΩ || pF 6 || 3 1012Ω || pF 130 dB OPEN-LOOP GAIN AOL VS = 4 V to 36 V (V–) + 0.35 V < VO < (V+) – 0.35 V TA = –40°C to +125°C Open-loop voltage gain 110 FREQUENCY RESPONSE GBP Gain bandwidth product SR Slew rate tS G=1 Settling time THD+N 3 MHz 1.5 V/µs To 0.1% VS = ±18 V, G = 1 10-V step 6 µs To 0.01% (12 bit) VS = ±18 V, G = 1 10-V step 10 µs 2 µs Overload recovery time VIN × gain > VS Total harmonic distortion + noise G = 1, f = 1 kHz VO = 3 VRMS 0.0002% OUTPUT (1) The input range can be extended beyond (V+) – 2 V up to V+. See Typical Characteristics and Application and Implementation for additional information. Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 Submit Documentation Feedback 9 OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 www.ti.com Electrical Characteristics (continued) at TA = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, (unless otherwise noted) PARAMETER TEST CONDITIONS Voltage output swing from rail VS = 5 V RL = 10 kΩ Over temperature RL = 10 kΩ AOL ≥ 110 dB TA = –40°C to +125°C VO ISC Short-circuit current CLOAD Capacitive load drive RO Open-loop output resistance MIN TYP MAX 30 (V–) + 0.35 mV (V+) – 0.35 +25/–35 V mA See Typical Characteristics f = 1 MHz IO = 0 A UNIT pF 150 Ω POWER SUPPLY VS IQ Specified voltage range 2.7 Quiescent current per amplifier IO = 0 A Over temperature IO = 0 A TA = –40°C to +125°C 475 36 V 595 µA 650 µA TEMPERATURE 10 Specified range –40 125 °C Operating range –55 150 °C Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 OPA171, OPA2171, OPA4171 www.ti.com SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 6.8 Typical Characteristics: Table of Graphs Table 1. Characteristic Performance Measurements DESCRIPTION FIGURE Offset Voltage Production Distribution Figure 1 Offset Voltage Drift Distribution Figure 2 Offset Voltage vs Temperature Figure 3 Offset Voltage vs Common-Mode Voltage Figure 4 Offset Voltage vs Common-Mode Voltage (Upper Stage) Figure 5 Offset Voltage vs Power Supply Figure 6 IB and IOS vs Common-Mode Voltage Figure 7 Input Bias Current vs Temperature Figure 8 Output Voltage Swing vs Output Current (Maximum Supply) Figure 9 CMRR and PSRR vs Frequency (Referred-to Input) Figure 10 CMRR vs Temperature Figure 11 PSRR vs Temperature Figure 12 0.1-Hz to 10-Hz Noise Figure 13 Input Voltage Noise Spectral Density vs Frequency Figure 14 THD+N Ratio vs Frequency Figure 15 THD+N vs Output Amplitude Figure 16 Quiescent Current vs Temperature Figure 17 Quiescent Current vs Supply Voltage Figure 18 Open-Loop Gain and Phase vs Frequency Figure 19 Closed-Loop Gain vs Frequency Figure 20 Open-Loop Gain vs Temperature Figure 21 Open-Loop Output Impedance vs Frequency Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 22 Figure 23, Figure 24 No Phase Reversal Figure 25 Positive Overload Recovery Figure 26 Negative Overload Recovery Figure 27 Small-Signal Step Response (100 mV) Figure 28, Figure 29 Large-Signal Step Response Figure 30, Figure 31 Large-Signal Settling Time (10-V Positive Step) Figure 32 Large-Signal Settling Time (10-V Negative Step) Figure 33 Short-Circuit Current vs Temperature Figure 34 Maximum Output Voltage vs Frequency Figure 35 Channel Separation vs Frequency Figure 36 Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 Submit Documentation Feedback 11 OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 www.ti.com 6.9 Typical Characteristics VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 25 Distribution Taken From 3500 Amplifiers Distribution Taken From 110 Amplifiers 14 Percentage of Amplifiers (%) Percentage of Amplifiers (%) 16 12 10 8 6 4 2 0 20 15 10 5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 -1200 -1100 -1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 Offset Voltage Drift (mV/°C) Offset Voltage (mV) Figure 2. Offset Voltage Drift Distribution Figure 1. Offset Voltage Production Distribution 1000 600 5 Typical Units Shown 10 Typical Units Shown 800 400 400 VOS (mV) Offset Voltage (mV) 600 200 0 -200 200 0 -200 -400 -400 -600 -600 -800 -800 VCM = -18.1 V -1000 -75 -50 -25 0 25 50 75 100 125 -20 150 -15 -10 -5 0 Temperature (°C) 10 15 20 Figure 4. Offset Voltage vs Common-Mode Voltage Figure 3. Offset Voltage vs Temperature 10000 5 VCM (V) 350 10 Typical Units Shown 8000 VSUPPLY = ±2.25 V to ±18 V 10 Typical Units Shown 250 6000 150 2000 VOS (mV) VOS (mV) 4000 0 -2000 -4000 Normal Operation -250 -8000 -10000 15.5 -50 -150 VCM = 18.1 V -6000 50 -350 16 16.5 17 17.5 18 18.5 0 2 4 Figure 5. Offset Voltage vs Common-Mode Voltage (Upper Stage) 12 Submit Documentation Feedback 6 8 10 12 14 16 18 20 VSUPPLY (V) VCM (V) Figure 6. Offset Voltage vs Power Supply Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 OPA171, OPA2171, OPA4171 www.ti.com SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 Typical Characteristics (continued) 10000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IB+ -IB IB- +IB -IOS VCM = -18.1V 1000 Input Bias Current (pA) IB and IOS (pA) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) IB IOS 100 10 IOS 1 VCM = 16V 0 -20 -18 -12 0 -6 6 12 18 -40 20 -25 0 25 100 125 140 Common-Mode Rejection Ratio (dB), Power-Supply Rejection Ratio (dB) 18 17 Output Voltage (V) 75 Figure 8. Input Bias Current vs Temperature Figure 7. IB and IOS vs Common-Mode Voltage 16 15 14.5 -14.5 -15 -40°C +25°C +85°C +125°C -16 -17 120 100 80 60 40 +PSRR -PSRR CMRR 20 0 -18 0 2 4 6 8 10 12 14 1 16 10 100 1k 10k 100k 1M 10M Frequency (Hz) Output Current (mA) Figure 9. Output Voltage Swing vs Output Current (Maximum Supply) Figure 10. CMRR and PSRR vs Frequency (Referred-to Input) 30 3 Power-Supply Rejection Ratio (mV/V) Common-Mode Rejection Ratio (mV/V) 50 Temperature (°C) VCM (V) 20 10 0 -10 VS = 2.7V -20 VS = 4V VS = 36V -30 2 1 0 -1 -2 VS = 2.7V to 36V VS = 4V to 36V -3 -75 -50 -25 0 25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Figure 11. CMRR vs Temperature Figure 12. PSRR vs Temperature Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 125 150 Submit Documentation Feedback 13 OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 www.ti.com Typical Characteristics (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 1mV/div Voltage Noise Density (nV/ÖHz) 1000 100 10 1 Time (1s/div) 1 10 100 1k 10k 100k 1M Frequency (Hz) Figure 13. 0.1-Hz to 10-Hz Noise -120 0.0001 G = +1, RL = 10kW G = -1, RL = 2kW 0.00001 10 100 1k 10k -140 20k Total Harmonic Distortion + Noise (%) Total Harmonic Distortion + Noise (%) -100 0.001 0.1 BW = 80kHz -80 0.01 -100 0.001 -120 0.0001 G = +1, RL = 10kW G = -1, RL = 2kW 0.00001 0.01 Total Harmonic Distortion + Noise (dB) -80 VOUT = 3VRMS BW = 80kHz Total Harmonic Distortion + Noise (dB) 0.01 Figure 14. Input Voltage Noise Spectral Density vs Frequency -140 0.1 1 10 20 Output Amplitude (VRMS) Frequency (Hz) Figure 15. THD+N Ratio vs Frequency Figure 16. THD+N vs Output Amplitude 0.6 0.65 0.55 0.6 0.5 IQ (mA) IQ (mA) 0.55 0.5 0.45 0.45 0.4 0.35 0.4 0.3 0.35 0.25 Specified Supply-Voltage Range -75 -50 -25 0 25 50 75 100 125 150 0 4 8 Figure 17. Quiescent Current vs Temperature 14 Submit Documentation Feedback 12 16 20 24 28 32 36 Supply Voltage (V) Temperature (°C) Figure 18. Quiescent Current vs Supply Voltage Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 OPA171, OPA2171, OPA4171 www.ti.com SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 Typical Characteristics (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 180 180 25 Gain 20 135 135 15 Phase 45 45 Gain (dB) 90 Phase (°) Gain (dB) 10 90 5 0 -5 -10 0 0 G = 10 G=1 G = -1 -15 -45 10M -45 1 10 100 1k 10k 100k 1M -20 10k 100k 1M Figure 19. Open-Loop Gain and Phase vs Frequency 3 100M Figure 20. Closed-Loop Gain vs Frequency 1M 5 Typical Units Shown VS = 2.7 V VS = 4 V VS = 36 V 2.5 100k 10k 2 ZO (W) AOL (mV/V) 10M Frequency (Hz) Frequency (Hz) 1.5 1k 100 1 10 0.5 1 0 1m -40 -25 0 25 50 75 100 125 1 10 100 Temperature (°C) 45 45 ROUT = 0 W 40 40 ROUT = 25 W 35 35 ROUT = 50 W 30 25 20 ROUT = 0 Ω 10 ROUT = 25 Ω 5 ROUT = 50 Ω 10k 100k 1M 10M Figure 22. Open-Loop Output Impedance vs Frequency 50 G=1 18 V Overshoot (%) Overshoot (%) Figure 21. Open-Loop Gain vs Temperature 50 15 1k Frequency (Hz) 30 25 20 RI = 10 kW 15 ROUT -18 V RF = 10 kW G = -1 18 V TLV171-Q1 RL CL 10 ROUT TLV171-Q1 CL 5 -18 V 0 0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Capacitive Load (pF) Figure 23. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 24. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 Submit Documentation Feedback 15 OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 www.ti.com Typical Characteristics (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 18 V Output VOUT TLV171-Q1 VIN 5V/div 5V/div -18 V 37 VPP Sine Wave (±18.5 V) 20kW +18V 2kW OPA171 Output VOUT VIN -18V G = -10 Time (5ms/div) Time (100ms/div) Figure 25. No Phase Reversal Figure 26. Positive Overload Recovery RL = 10kW CL = 100pF +18V RL CL 20mV/div -18V VIN 5V/div G = +1 OPA171 20kW +18V 2kW OPA171 VOUT VIN VOUT -18V G = -10 Time (1ms/div) Time (5ms/div) Figure 27. Negative Overload Recovery Figure 28. Small-Signal Step Response (100 mV) RI = 2kW RF 2V/div 20mV/div CL = 100pF = 2kW +18V OPA171 CL -18V G = -1 Time (5ms/div) Time (20ms/div) Figure 29. Small-Signal Step Response (100 mV) 16 Submit Documentation Feedback Figure 30. Large-Signal Step Response Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 OPA171, OPA2171, OPA4171 www.ti.com SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 Typical Characteristics (continued) VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted) 10 2V/div D From Final Value (mV) 8 6 4 12-Bit Settling 2 0 -2 (±1/2LSB = ±0.024%) -4 -6 -8 -10 Time (4ms/div) 0 4 8 12 16 20 24 28 32 36 Time (ms) Figure 32. Large-Signal Settling Time (10-V Positive Step) 10 50 8 45 6 40 4 35 12-Bit Settling 2 ISC (mA) D From Final Value (mV) Figure 31. Large-Signal Step Response 0 -2 (±1/2LSB = ±0.024%) 25 20 -4 15 -6 10 -8 5 -10 ISC, Sink 30 ISC, Source 0 0 4 8 12 16 20 24 28 32 36 -40 -25 0 Time (ms) 25 50 75 100 125 Temperature (°C) Figure 33. Large-Signal Settling Time (10-V Negative Step) Figure 34. Short-Circuit Current vs Temperature 15 -60 VS = ±15 V 10 Channel Separation (dB) Output Voltage (VPP) 12.5 Maximum output voltage without slew-rate induced distortion. 7.5 VS = ±5 V 5 2.5 -70 -80 -90 -100 -110 0 -120 10k 100k 1M 10M 10 100 Frequency (Hz) Figure 35. Maximum Output Voltage vs Frequency 1k 10k 100k Frequency (Hz) Figure 36. Channel Separation vs Frequency Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 Submit Documentation Feedback 17 OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 www.ti.com 7 Detailed Description 7.1 Overview The OPAx171 operational amplifiers provide high overall performance, and are designed for many generalpurpose applications. The excellent offset drift of only 2 µV/°C provides excellent stability over the entire temperature range. In addition, the series offers good overall performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate. 7.2 Functional Block Diagram OPA171 PCH FF Stage Ca Cb +IN PCH Input Stage Output Stage 2nd Stage OUT -IN NCH Input Stage 7.3 Feature Description 7.3.1 Operating Characteristics The OPAx171 family of amplifiers is specified for operation from 2.7 to 36 V (±1.35 to ±18 V). Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in Typical Characteristics . 7.3.2 Common-Mode Voltage Range The input common-mode voltage range of the OPAx171 series extends 100 mV below the negative rail and within 2 V of the top rail for normal operation. This family can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of the top rail. The typical performance in this range is summarized in Table 2. 18 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 OPA171, OPA2171, OPA4171 www.ti.com SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 Feature Description (continued) 7.3.3 Phase-Reversal Protection The OPAx171 family has an internal phase-reversal protection. Many operational amplifiers exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input of the OPAx171 prevents phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 37. 18 V Output TLV171-Q1 5V/div -18 V 37 VPP Sine Wave (±18.5 V) Output Time (100ms/div) Figure 37. No Phase Reversal Table 2. Typical Performance Range PARAMETER MIN Input common-mode voltage TYP (V+) – 2 MAX (V+) + 0.1 UNIT V Offset voltage 7 mV vs temperature 12 µV/°C Common-mode rejection 65 dB Open-loop gain 60 dB GBW 0.7 MHz Slew rate 0.7 V/µs Noise at f = 1 kHz 30 nV/√Hz 7.3.4 Capacitive Load and Stability The dynamic characteristics of the OPAx171-Q1 family of devices have been optimized for commonly encountered operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. Figure 38 and Figure 39 show small-signal overshoot versus capacitive load for several values of ROUT. For details of analysis techniques and application circuits, see Applications Bulletin AB-028, available for download from TI.com. Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 Submit Documentation Feedback 19 OPA171, OPA2171, OPA4171 www.ti.com 50 50 45 45 ROUT = 0 W 40 40 ROUT = 25 W 35 35 ROUT = 50 W 30 25 20 10 ROUT = 25 Ω 5 ROUT = 50 Ω G=1 18 V ROUT = 0 Ω 15 Overshoot (%) Overshoot (%) SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 30 25 20 RI = 10 kW 15 ROUT -18 V RF = 10 kW G = -1 18 V TLV171-Q1 RL CL 10 ROUT TLV171-Q1 CL 5 -18 V 0 0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Capacitive Load (pF) Figure 38. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 39. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) 7.4 Device Functional Modes 7.4.1 Common-Mode Voltage Range The input common-mode voltage range of the OPAx171 family extends 100 mV below the negative rail and within 2 V of the top rail for normal operation. These devices can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of the top rail. The typical performance in this range is summarized in Table 2. 20 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 OPA171, OPA2171, OPA4171 www.ti.com SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The OPAx171 operational amplifiers provide high overall performance, and are designed for many generalpurpose applications. The excellent offset drift of only 2 µV/°C provides excellent stability over the entire temperature range. In addition, the series offers good overall performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate. 8.1.1 Electrical Overstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits for protection from accidental ESD events both before and during product assembly. A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful. Figure 40 shows the ESD circuits contained in the OPAx171 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power supply lines, where the diodes meet at an absorption device internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 Submit Documentation Feedback 21 OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 www.ti.com Application Information (continued) TVS + ± RF +VS R1 IN± RS IN+ 2.5 NŸ 2.5 NŸ + Power-Supply ESD Cell ID VIN RL + ± + ± ±VS TVS Figure 40. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the protection circuitry is then dissipated as heat. When an ESD voltage develops across two or more amplifier device pins, current flows through one or more steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption device contains a trigger (or threshold voltage) that is above the normal operating voltage of the OPAx171 but below the device breakdown level. When this threshold is exceeded, the absorption device quickly activates and clamps the voltage across the supply rails to a safe level. When the operational amplifier connects into a circuit (as shown in Figure 40), the ESD protection components are intended to remain inactive and do not become involved in the application circuit operation. However, circumstances may arise when an applied voltage exceeds the operating voltage of a given pin. If this condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs through steering-diode paths and rarely involves the absorption device. Figure 40 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the current, one of the upper steering diodes conducts and directs current to V+. Excessively high current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the input current to 10 mA. If the supply is not capable of sinking the current, VIN begins sourcing current to the operational amplifier and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the operational amplifier absolute maximum ratings. 22 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 OPA171, OPA2171, OPA4171 www.ti.com SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 Application Information (continued) Another common question involves what happens to the amplifier if an input signal is applied to the input when the power supplies (V+ or V–) are at 0 V. This question depends on the supply characteristic when at 0 V, or at a level below the input signal amplitude. If the supplies appear to be high-impedance, then the input source supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias condition. Most likely, the amplifier does not operate normally. If the supplies are low-impedance, then the current through the steering diodes can be quite high. The current level depends on the ability of the input source to deliver current and any resistance in the input path. If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the supply pins; see Figure 40. Select the Zener voltage so that the diode does not turn on during normal operation. However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise above the safe operating, supply-voltage level. The OPAx171 input pins are protected from excessive differential voltage with back-to-back diodes; see Figure 40. In most circuit applications, the input protection circuitry does not affect the application. However, in low gain or G = 1 circuits, fast-ramping input signals can forward bias these diodes because the output of the amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can be used to limit the input signal current. This input series resistor degrades the low noise performance of the OPAx171. Figure 40 shows an example configuration that implements a current-limiting feedback resistor. 8.2 Typical Application +VS VOUT RISO + VIN + ± CLOAD VS Figure 41. Unity-Gain Buffer With RISO Stability Compensation 8.2.1 Design Requirements The design requirements are: • Supply voltage: 30 V (±15 V) • Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF • Phase margin: 45° and 60° 8.2.2 Detailed Design Procedure Figure 42 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the circuit in Figure 42. Not shown in Figure 42 is the open-loop output resistance of the operational amplifier, Ro. 1 + CLOAD × RISO × s T(s) = 1 + Ro + RISO × CLOAD × s (1) The transfer function in Equation 1 contains a pole and a zero. The frequency of the pole (fp) is determined by (Ro + RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). Select RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20 dB/decade to obtain a stable system. Figure 42 shows the concept. The 1/β curve for a unity-gain buffer is 0 dB. Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 Submit Documentation Feedback 23 OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 www.ti.com Typical Application (continued) 120 AOL 100 1 fp 2 u Œ u RISO Gain (dB) 80 60 Ro u CLOAD 40 dB fz 40 1 2 u Œ u RISO u CLOAD 1 dec 1/ 20 ROC 20 dB dec 0 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) Figure 42. Unity-Gain Amplifier With RISO Compensation ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a measurement of overshoot percentage and AC gain peaking of the circuit using a function generator, oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 3 shows the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For more details on this design and other alternative devices that can be used in place of the OPAx171, see Capacitive Load Drive Solution using an Isolation Resistor. Table 3. Phase Margin versus Overshoot and AC Gain Peaking PHASE MARGIN OVERSHOOT AC GAIN PEAKING 45° 23.3% 2.35 dB 60° 8.8% 0.28 dB 8.2.2.1 Capacitive Load and Stability The dynamic characteristics of the OPAx171 are optimized for commonly encountered operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. Figure 38 and Figure 39 illustrate graphs of small-signal overshoot versus capacitive load for several values of ROUT. See Applications Bulletin AB-028, available for download from the TI website for details of analysis techniques and application circuits. 24 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 50 50 45 45 ROUT = 0 W 40 40 ROUT = 25 W 35 35 ROUT = 50 W 30 25 20 10 ROUT = 25 Ω 5 ROUT = 50 Ω G=1 18 V ROUT = 0 Ω 15 Overshoot (%) Overshoot (%) www.ti.com 30 25 20 RI = 10 kW 15 ROUT -18 V RF = 10 kW G = -1 18 V TLV171-Q1 RL CL 10 ROUT TLV171-Q1 CL 5 -18 V 0 0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Capacitive Load (pF) Figure 43. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 44. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 Submit Documentation Feedback 25 OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 www.ti.com 8.2.3 Application Curve The OPAx171 meets the supply voltage requirements of 30 V. The OPAx171 is tested for various capacitive loads and RISO is adjusted to get an overshoot corresponding to Table 3. The results of the these tests are summarized in Figure 45. 10000 Isolation Resistor, RISO (:) 45q Phase Margin 60q Phase Margin 1000 100 10 1 0.01 0.1 1 10 Capacitive Load (nF) 100 1000 D001 Figure 45. RISO vs CLOAD 26 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 OPA171, OPA2171, OPA4171 www.ti.com SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 9 Power Supply Recommendations The OPAx171 family is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Specifications section. CAUTION Supply voltages larger than 40 V can permanently damage the device; see the Absolute Maximum Ratings table. Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For detailed information on bypass capacitor placement, see the Layout Guidelines section. 10 Layout 10.1 Layout Guidelines For best operational performance of the devices, good printed circuit board (PCB) layout practices are recommended. Low-loss, 0.1-µF bypass capacitors must be connected between each supply pin and ground, placed as close to the devices as possible. A single bypass capacitor from V+ to ground is applicable to singlesupply applications. 10.2 Layout Example Run the input traces as far away from the supply lines as possible Place components close to device and to each other to reduce parasitic errors VS+ RF NC NC GND ±IN V+ VIN +IN OUTPUT V± NC Use a low-ESR, ceramic bypass capacitor RG GND VS± GND VOUT Ground (GND) plane on another layer Use low-ESR, ceramic bypass capacitor Figure 46. Operational Amplifier Board Layout for Noninverting Configuration Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 Submit Documentation Feedback 27 OPA171, OPA2171, OPA4171 SBOS516F – SEPTEMBER 2010 – REVISED APRIL 2018 www.ti.com 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 4. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY OPA171 Click here Click here Click here Click here Click here OPA2171 Click here Click here Click here Click here Click here OPA4171 Click here Click here Click here Click here Click here 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 28 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Product Folder Links: OPA171 OPA2171 OPA4171 PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) OPA171AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 O171A OPA171AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OSUI OPA171AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OSUI OPA171AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 O171A OPA171AIDRLR ACTIVE SOT-5X3 DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 DAP OPA171AIDRLT ACTIVE SOT-5X3 DRL 5 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 DAP OPA2171AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2171A OPA2171AIDCUR ACTIVE VSSOP DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OPOC OPA2171AIDCUT ACTIVE VSSOP DCU 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 OPOC OPA2171AIDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OPMI OPA2171AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 OPMI OPA2171AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2171A OPA4171AID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA4171 OPA4171AIDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA4171 OPA4171AIPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4171 OPA4171AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA4171 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2018 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of