OPA171-Q1, OPA2171-Q1, OPA4171-Q1
OPA171-Q1,
OPA2171-Q1,
OPA4171-Q1
SBOS556D – JUNE
2011 – REVISED
AUGUST 2020
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SBOS556D – JUNE 2011 – REVISED AUGUST 2020
OPAx171-Q1 36-V, Single-Supply, General-Purpose
Operational Amplifier
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 test guidance with the following results:
– Temperature grade 1:
–40°C to +125°C ambient operating
temperature
– Device HBM ESD classification level:
• Level 3A for OPA171-Q1
• Level 2 for OPA4171-Q1
– Device CDM ESD classification level
• Level C4A for OPA171-Q1 TLV171-Q1
• Level C6 for OPA2171-Q1
• Level C6 for OPA4171-Q1
Supply range:
– Single-supply: 2.7 V to 36 V
– Dual-supply ±1.35 V to ±18 V
Low noise: 14 nV/√Hz at 1 kHz
Low offset drift: ±0.3 µV/°C (typical)
Input range includes negative supply
Input range operates to positive supply with
reduced performance
Rail-to-rail output
Gain bandwidth: 3 MHz
Low quiescent current: 475 µA per amplifier
High Common-mode rejection: 120 dB (typical)
Low input bias current: 10 pA
Industry-Standard Package:
– 5-Pin Small-Outline Transistor SOT-23 (DBV)
Package
1000
10 Typical Units Shown
800
Tracking amplifier in power modules
Merchant power supplies
Transducer amplifiers
Bridge amplifiers
Temperature measurements
Strain gauge amplifiers
Precision integrators
Battery-powered instruments
Test equipment
3 Description
The OPA171-Q1 family of devices is a 36-V, singlesupply, low-noise operational amplifier (op amp) with
the ability to operate on supplies ranging from 2.7 V
(±1.35 V) to 36 V (±18 V). This series is available in
multiple packages and offers low offset, drift, and low
quiescent current. The single, dual, and quad versions
all have identical specifications for maximum design
flexibility.
Unlike most op amps, which are specified at only one
supply voltage, the OPAx171-Q1 family of devices is
specified from 2.7 V to 36 V. Input signals beyond the
supply rails do not cause phase reversal.
The OPAx171-Q1 family of devices is stable with
capacitive loads up to 300 pF. The input can operate
100 mV below the negative rail and within 2 V of the
top rail during normal operation. The device can
operate with full rail-to-rail input 100 mV beyond the
top rail, but with reduced performance within 2 V of
the top rail.
The OPAx171-Q1 op amp family is specified from –
40°C to +125°C.
600
VOS (µV)
400
Device Information
200
PART NUMBER
0
-200
OPA171-Q1
-400
-600
OPA2171-Q1
-800
VCM = -18.1 V
-1000
-20
-15
-10
-5
0
5
10
15
20
VCM (V)
Offset Voltage vs Common-Mode Voltage:
VSUPPLY = ±18 V
OPA4171-Q1
(1)
PACKAGE(1)
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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© 2020 Texas
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Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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SBOS556D – JUNE 2011 – REVISED AUGUST 2020
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions : OPA171-Q1 and OPA2171-Q1.................3
Pin Functions : OPA4171-Q1............................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information — OPA171-Q1 and
OPA2171-Q1................................................................. 6
6.5 Thermal Information — OPA4171-Q1.........................6
6.6 Electrical Characteristics.............................................7
6.7 Typical Characteristics................................................ 9
7 Detailed Description......................................................16
7.1 Overview................................................................... 16
7.2 Functional Block Diagram......................................... 16
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................18
8 Application and Implementation.................................. 19
8.1 Application Information............................................. 19
8.2 Typical Application.................................................... 21
9 Power Supply Recommendations................................23
10 Layout...........................................................................24
10.1 Layout Guidelines................................................... 24
10.2 Layout Example...................................................... 24
11 Device and Documentation Support..........................25
11.1 Documentation Support.......................................... 25
11.2 Related Links.......................................................... 25
11.3 Receiving Notification of Documentation Updates.. 25
11.4 Support Resources................................................. 25
11.5 Trademarks............................................................. 25
11.6 Electrostatic Discharge Caution.............................. 25
11.7 Glossary.................................................................. 25
12 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December 2015) to Revision D (August 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed OPA2171-Q1 V+ pinout table value to correctly reflect pinout image................................................. 3
• Rewrote Electrical Overstress section to match with TLV171 commercial data sheet..................................... 19
Changes from Revision B (December 2014) to Revision C (December 2015)
Page
• Changed the ESD classification levels for HBM and CDM in the Features list ................................................. 1
• Added the 8-pin VSSOP (DGK) package option for the OPA2171-Q1 device .................................................. 1
• Clarified the ESD values for each device in the ESD Ratings table .................................................................. 5
Changes from Revision A (September 2012) to Revision B (December 2014)
Page
• Added the Handling Ratings table, Feature Description section, Device Functional Modes section, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
• Added the OPA2171-Q1 and OPA4171-Q1 devices to the data sheet ..............................................................1
Changes from Revision * (June, 2011) to Revision A (September, 2012)
Page
• Added second bullet to Features: AEC-Q100 Test Guidance With the Following Results: –Device
Temperature Grade1: -40°C to 125°C Ambient Operating Temperature Range –Device HBM ESD
Classification Level H2 –Device CDM ESD Classification Level C3A................................................................ 1
• Added classification levels to ESD ratings in Absolute Maximum Ratings table................................................ 5
• Added row to Absolute Maximum Ratings table: Latch-up per JESD78D with Class 1 value............................ 5
2
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SBOS556D – JUNE 2011 – REVISED AUGUST 2020
5 Pin Configuration and Functions
OUT
1
V-
2
+IN
3
5
4
V+
OUT A
1
8
V+
–IN A
2
7
OUT B
+IN A
3
6
–IN B
V–
4
5
+IN B
-IN
Figure 5-1. OPA171-Q1 DBV Package
5-Pin SOT-23
Top View
Figure 5-2. OPA2171-Q1 D or DGK Package
8-Pin SOIC and VSSOP
Top View
Pin Functions : OPA171-Q1 and OPA2171-Q1
PIN
OPA171-Q1
SOT-23
OPA2171-Q1
SOIC AND
VSSOP
I/O
+IN
3
—
I
Noninverting input
+IN A
—
3
I
Noninverting input, channel A
+IN B
—
5
I
Noninverting input, channel B
–IN
4
—
I
Inverting input
–IN A
—
2
I
Inverting input, channel A
–IN B
—
6
I
Inverting input, channel B
OUT
1
—
O
Output
OUT A
—
1
O
Output, channel A
OUT B
—
7
O
Output, channel B
V+
5
8
—
Positive (highest) power supply
V–
2
4
—
Negative (lowest) power supply
NAME
DESCRIPTION
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OUT A
1
14
OUT D
-IN A
2
13
-IN D
+IN A
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
Figure 5-3. OPA4171-Q1 D and PW Packages
14-Pin SOIC and TSSOP
Top View
Pin Functions : OPA4171-Q1
PIN
4
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
+IN C
10
I
Noninverting input, channel C
+IN D
12
I
Noninverting input, channel D
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
–IN C
9
I
Inverting input, channel C
–IN D
13
I
Inverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V+
4
—
Positive (highest) power supply
V–
11
—
Negative (lowest) power supply
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SBOS556D – JUNE 2011 – REVISED AUGUST 2020
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
40
V
Supply voltage, VS
Signal input terminals
Voltage
(V–) – 0.5
(V+) + 0.5
V
±10
mA
150
°C
150
°C
Current
Output short circuit(2)
Continuous
Junction temperature, TJ
Latch-up per JESD78D
Class 1
Storage temperature, Tstg
(1)
(2)
–65
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
OPA171-Q1
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002(1)
±4000
Charged device model (CDM), per AEC Q100-011
±500
Human body model (HBM), per AEC Q100-002(1)
±4000
Charged device model (CDM), per AEC Q100-011
±1000
Human body model (HBM), per AEC Q100-002(1)
±2000
Charged device model (CDM), per AEC Q100-011
±1000
V
OPA2171-Q1
V(ESD)
Electrostatic discharge
V
OPA4171-Q1
V(ESD)
(1)
Electrostatic discharge
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage (V+ – V–)
Specified operating temperature
NOM
MAX
UNIT
4.5 (±2.25)
36 (±18)
V
–40
125
°C
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6.4 Thermal Information — OPA171-Q1 and OPA2171-Q1
OPA171-Q1
THERMAL METRIC(1)
OPA2171-Q1
DBV (SOT-23)
D (SOIC)
DGK (VSSOP)
5 PINS
8 PINS
8 PINS
186.5
°C/W
UNIT
RθJA
Junction-to-ambient thermal resistance
277.3
116.1
RθJC(top)
Junction-to-case(top) thermal resistance
193.3
69.8
78
°C/W
RθJB
Junction-to-board thermal resistance
121.2
56.6
107.8
°C/W
ψJT
Junction-to-top characterization parameter
51.8
22.5
15.6
°C/W
ψJB
Junction-to-board characterization parameter
109.5
56.1
106.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information — OPA4171-Q1
OPA4171-Q1
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
93.2
106.9
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
51.8
24.4
°C/W
RθJB
Junction-to-board thermal resistance
49.4
59.3
°C/W
ψJT
Junction-to-top characterization parameter
13.5
0.6
°C/W
ψJB
Junction-to-board characterization parameter
42.2
54.3
°C/W
(1)
6
D (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOS556D – JUNE 2011 – REVISED AUGUST 2020
6.6 Electrical Characteristics
at TA = 25°C, VS = 2.7 V to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
0.25
±1.8
mV
Input offset voltage over temperature
TA = –40°C to 125°C
0.3
±2
mV
dVOS/dT
Input offset voltage drift
(over temperature)
TA = –40°C to 125°C
0.3
±2 (2)
µV/°C
PSRR
Input offset voltage over temperature
vs power supply
VS = 4.5 V to 36 V
120
±3
µV/V
Channel separation, DC
5
µV/V
INPUT BIAS CURRENT
IB
Input bias current
±8
Input bias current over temperature
IOS
±15
±3.5
Input offset current
±4
Input offset current over temperature
pA
nA
pA
±3.5
nA
NOISE
Input voltage noise
en
f = 0.1 Hz to 10 Hz
Input voltage noise density
3
µVPP
f = 100 Hz
25
nV/√ Hz
f = 1 kHz
14
nV/√ Hz
INPUT VOLTAGE
VCM
CMRR
Common-mode voltage range(1)
(V–) – 0.1
Common-mode rejection ratio (over
temperature)
(V+) – 2
V
VS = ±2.25 V
(V–) – 0.1 V < VCM < (V+) – 2 V
90
104
dB
VS = ±18 V
(V–) – 0.1 V < VCM < (V+) – 2 V
104
120
dB
INPUT IMPEDANCE
Differential
100 || 3
Common-mode
MΩ || pF
6 || 3
1012Ω || pF
130
dB
OPEN-LOOP GAIN
AOL
Open-loop voltage gain (over
temperature)
VS = 4.5 V to 36 V
(V–) + 0.35 V < VO < (V+) – 0.35 V
110
FREQUENCY RESPONSE
GBP
Gain bandwidth product
SR
Slew rate
tS
Settling time
G=1
To 0.1%, VS = ±18 V
G = 1, 10-V step
To 0.01% (12 bit), VS = ±18 V
G = 1, 10-V step
Overload recovery time
V±IN × Gain > VS
Total harmonic distortion + noise
G = 1, f = 1 kHz
VO = 3 VRMS
VO
Voltage output swing from rail (over
temperature)
RL = 10 kΩ
AOL ≥ 110 dB
ISC
Short-circuit current
CLOAD
Capacitive load drive
RO
Open-loop output resistance
THD+N
3
MHz
1.5
V/µs
6
µs
10
µs
2
µs
0.0002%
OUTPUT
(V–) + 0.35
Sourcing
(V+) – 0.35
25
Sinking
mA
–37
See Section 6.7
f = 1 MHz, IO = 0 A
V
pF
150
Ω
POWER SUPPLY
VS
Specified voltage range
TA = –40°C to 125°C
4.5
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V
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SBOS556D – JUNE 2011 – REVISED AUGUST 2020
at TA = 25°C, VS = 2.7 V to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise
noted)
PARAMETER
IQ
(1)
(2)
8
Quiescent current per amplifier
TEST CONDITIONS
MIN
IO = 0 A, TA = –40°C to 125°C
TYP
MAX
UNIT
475
595
µA
The input range can be extended beyond (V+) – 2 V up to V+ at reduced performance. See Section 6.7 and Section 7 for additional
information.
Not production tested.
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SBOS556D – JUNE 2011 – REVISED AUGUST 2020
6.7 Typical Characteristics
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Table 6-1. Characteristic Performance Measurements
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 6-1
Offset Voltage Drift Distribution
Figure 6-2
Offset Voltage vs Temperature
Figure 6-3
Offset Voltage vs Common-Mode Voltage
Figure 6-4
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Figure 6-5
Offset Voltage vs Power Supply
Figure 6-6
IB and IOS vs Common-Mode Voltage
Figure 6-7
Input Bias Current vs Temperature
Figure 6-8
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 6-9
CMRR and PSRR vs Frequency (Referred-to Input)
Figure 6-10
CMRR vs Temperature
Figure 6-11
PSRR vs Temperature
Figure 6-12
0.1Hz to 10Hz Noise
Figure 6-13
Input Voltage Noise Spectral Density vs Frequency
Figure 6-14
THD+N Ratio vs Frequency
Figure 6-15
THD+N vs Output Amplitude
Figure 6-16
Quiescent Current vs Temperature
Figure 6-17
Quiescent Current vs Supply Voltage
Figure 6-18
Open-Loop Gain and Phase vs Frequency
Figure 6-19
Closed-Loop Gain vs Frequency
Figure 6-20
Open-Loop Gain vs Temperature
Figure 6-21
Open-Loop Output Impedance vs Frequency
Figure 6-22
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 6-23, Figure 6-24
No Phase Reversal
Figure 6-25
Positive Overload Recovery
Figure 6-26
Negative Overload Recovery
Figure 6-27
Small-Signal Step Response (100 mV)
Figure 6-28, Figure 6-29
Large-Signal Step Response
Figure 6-30, Figure 6-31
Large-Signal Settling Time (10-V Positive Step)
Figure 6-32
Large-Signal Settling Time (10-V Negative Step)
Figure 6-33
Short-Circuit Current vs Temperature
Figure 6-34
Maximum Output Voltage vs Frequency
Figure 6-35
Channel Separation vs Frequency
Figure 6-36
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6.7.1 Typical Characteristics
25
Distribution Taken From 3500 Amplifiers
14
Percentage of Amplifiers (%)
Percentage of Amplifiers (%)
16
12
10
8
6
4
2
0
Distribution Taken From 110 Amplifiers
20
15
10
5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
-1200
-1100
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
0
Offset Voltage Drift (mV/°C)
Offset Voltage (mV)
Figure 6-2. Offset Voltage Drift Distribution
Figure 6-1. Offset Voltage Production Distribution
1000
600
5 Typical Units Shown
10 Typical Units Shown
800
400
Offset Voltage (mV)
600
200
VOS (µV)
400
0
-200
200
0
-200
-400
-400
-600
-600
-800
-800
VCM = -18.1 V
-1000
-75
-50
-25
0
25
50
75
100
125
-20
150
-15
-10
-5
0
10
15
20
Figure 6-4. Offset Voltage vs Common-Mode
Voltage: VSUPPLY (V) = ±18 V
Figure 6-3. Offset Voltage vs Temperature
10000
5
VCM (V)
Temperature (°C)
350
10 Typical Units Shown
8000
VSUPPLY = ±2.25 V to ±18 V
10 Typical Units Shown
250
6000
150
2000
VOS (µV)
VOS (µV)
4000
0
-2000
-4000
Normal
Operation
-250
-8000
-10000
15.5
-50
-150
VCM = 18.1 V
-6000
50
16
16.5
17
17.5
18
18.5
-350
0
2
4
6
VCM (V)
Figure 6-5. Offset Voltage vs Common-Mode
Voltage: VSUPPLY (V) = ±18 V
(Upper Stage)
10
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10
12
14
16
18
20
VSUPPLY (V)
Figure 6-6. Offset Voltage vs Power Supply
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SBOS556D – JUNE 2011 – REVISED AUGUST 2020
10000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IB-
+IB
-IOS
VCM = -18.1V
1000
IB
IOS
100
10
IOS
1
VCM = 16V
0
-20
-18
-12
0
-6
6
12
18
-40
20
-25
0
25
Figure 6-7. IB and IOSvs Common-Mode Voltage
75
100
125
Figure 6-8. Input Bias Current vs Temperature
140
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
18
17
16
15
14.5
-14.5
-15
-40°C
+25°C
+85°C
+125°C
-16
-17
120
100
80
60
40
+PSRR
-PSRR
CMRR
20
0
-18
0
2
4
6
8
10
12
14
1
16
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Output Current (mA)
Figure 6-9. Output Voltage Swing vs Output
Current (Maximum Supply)
Figure 6-10. CMRR and PSRR vs Frequency
(Referred-to Input)
30
3
Power-Supply Rejection Ratio (mV/V)
Common-Mode Rejection Ratio (mV/V)
50
Temperature (°C)
VCM (V)
Output Voltage (V)
IB+
-IB
Input Bias Current (pA)
IB and IOS (pA)
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20
10
0
-10
VS = 2.7V
-20
VS = 4V
VS = 36V
-30
2
1
0
-1
-2
VS = 2.7V to 36V
VS = 4V to 36V
-3
-75
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 6-11. CMRR vs Temperature
150
-75
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Figure 6-12. PSRR vs Temperature
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1mV/div
Voltage Noise Density (nV/ÖHz)
1000
100
10
1
1
10
100
Time (1s/div)
-120
0.0001
G = +1, RL = 10kW
G = -1, RL = 2kW
0.00001
1k
10k
-140
20k
-80
BW = 80kHz
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
1M
0.01
-100
0.001
-120
0.0001
G = +1, RL = 10kW
G = -1, RL = 2kW
0.00001
0.01
Total Harmonic Distortion + Noise (dB)
-100
0.001
100
100k
0.1
Total Harmonic Distortion + Noise (dB)
-80
VOUT = 3VRMS
BW = 80kHz
10
10k
Figure 6-14. Input Voltage Noise Spectral Density
vs Frequency
Figure 6-13. 0.1- to 10-Hz Noise
0.01
1k
Frequency (Hz)
-140
0.1
1
10
20
Output Amplitude (VRMS)
Frequency (Hz)
Figure 6-15. THD+N Ratio vs Frequency
Figure 6-16. THD+N vs Output Amplitude
0.6
0.65
0.55
0.6
0.5
IQ (mA)
IQ (mA)
0.55
0.5
0.45
0.45
0.4
0.35
0.4
0.3
0.35
0.25
Specified Supply-Voltage Range
-75
-50
-25
0
25
50
75
100
125
150
0
4
8
12
Temperature (°C)
Figure 6-17. Quiescent Current vs Temperature
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20
24
28
32
36
Supply Voltage (V)
Figure 6-18. Quiescent Current vs Supply Voltage
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180
180
25
Gain
20
135
15
Phase
90
45
45
0
0
10
Gain (dB)
90
Phase (°)
Gain (dB)
135
5
0
-5
-10
-45
1
10
100
1k
10k
100k
1M
-20
Frequency (Hz)
10k
Figure 6-19. Open-Loop Gain and Phase vs
Frequency
3
100k
1M
10M
100M
Frequency (Hz)
Figure 6-20. Closed-Loop Gain vs Frequency
1M
5 Typical Units Shown
VS = 2.7 V
VS = 4 V
VS = 36 V
2.5
100k
10k
2
ZO (W)
AOL (mV/V)
G = 10
G=1
G = -1
-15
-45
10M
1.5
1k
100
1
10
0.5
1
0
1m
-40
-25
0
25
50
75
100
125
1
10
100
Temperature (°C)
50
50
45
45
ROUT = 0 W
40
40
ROUT = 25 W
35
35
ROUT = 50 W
30
25
20
ROUT = 0 Ω
10
ROUT = 25 Ω
5
ROUT = 50 Ω
10k
100k
1M
10M
Figure 6-22. Open-Loop Output Impedance vs
Frequency
G=1
18 V
Overshoot (%)
Overshoot (%)
Figure 6-21. Open-Loop Gain vs Temperature
15
1k
Frequency (Hz)
30
25
20
RI = 10 kW
15
ROUT
-18 V
RF = 10 kW
G = -1
18 V
TLV171-Q1
RL
CL
10
ROUT
TLV171-Q1
CL
5
0
-18 V
0
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 6-23. Small-Signal Overshoot vs Capacitive
Load
(100-mV Output Step)
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 6-24. Small-Signal Overshoot vs Capacitive
Load
(100-mV Output Step)
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18 V
Output
VOUT
TLV171-Q1
VIN
5V/div
5V/div
-18 V
37 VPP
Sine Wave
(±18.5 V)
20kW
+18V
2kW
Output
OPA171
VOUT
VIN
-18V
G = -10
Time (100ms/div)
Time (5ms/div)
Figure 6-25. No Phase Reversal
Figure 6-26. Positive Overload Recovery
RL = 10kW
CL = 100pF
+18V
OPA171
RL
CL
20mV/div
-18V
VIN
5V/div
G = +1
20kW
+18V
2kW
OPA171
VOUT
VIN
VOUT
-18V
G = -10
Time (1ms/div)
Time (5ms/div)
Figure 6-27. Negative Overload Recovery
Figure 6-28. Small-Signal Step Response (100 mV)
RI
= 2kW
RF
2V/div
20mV/div
CL = 100pF
= 2kW
+18V
OPA171
CL
-18V
G = -1
Time (5ms/div)
Time (20ms/div)
Figure 6-29. Small-Signal Step Response (100 mV)
G=1
RL = 10 kΩ
CL = 100 pF
Figure 6-30. Large-Signal Step Response
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10
2V/div
D From Final Value (mV)
8
6
4
12-Bit Settling
2
0
-2
(±1/2LSB = ±0.024%)
-4
-6
-8
-10
Time (4ms/div)
G = –1
0
RL = 10 kΩ
4
8
12
16
20
24
28
32
36
Time (ms)
CL = 100 pF
G = –1
Figure 6-32. Large-Signal Settling Time (10-V
Positive Step)
10
50
8
45
6
40
4
35
12-Bit Settling
2
ISC (mA)
D From Final Value (mV)
Figure 6-31. Large-Signal Step Response
0
-2
(±1/2LSB = ±0.024%)
30
25
20
-4
15
-6
10
-8
5
-10
ISC, Sink
ISC, Source
0
0
4
8
12
16
20
24
28
32
36
-40
-25
0
Time (ms)
25
50
75
100
125
Temperature (°C)
Figure 6-34. Short-Circuit Current vs Temperature
G = –1
Figure 6-33. Large-Signal Settling Time (10-V
Negative Step)
15
-60
VS = ±15 V
10
Channel Separation (dB)
Output Voltage (VPP)
12.5
Maximum output voltage without
slew-rate induced distortion.
7.5
VS = ±5 V
5
-70
-80
-90
-100
-110
2.5
-120
0
10k
100k
1M
10M
10
100
Figure 6-35. Maximum Output Voltage vs
Frequency
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 6-36. Channel Separation vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx171-Q1 family of operational amplifiers provides high overall performance, making them ideal for many
general-purpose applications. The excellent offset drift of only 1.5 μV/°C (maximum) provides excellent stability
over the entire temperature range. In addition, the device offers very good overall performance with high CMRR,
PSRR, AOL, and superior THD.
7.2 Functional Block Diagram
OPA171-Q1
+
PCH
FF Stage
±
Ca
Cb
+IN
+
+
PCH
Input Stage
±IN
±
+
Output
Stage
2nd Stage
±
OUT
±
+
NCH
Input Stage
±
7.3 Feature Description
7.3.1 Operating Characteristics
The OPAx171-Q1 family of devices is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are shown in Section 6.7.
7.3.2 Phase-Reversal Protection
The OPAx171-Q1 family of devices has an internal phase-reversal protection. Many op amps exhibit a phase
reversal when the input is driven beyond the linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input of the OPAx171-Q1 family of devices prevents
phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. Figure
7-1 shows this performance.
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18 V
Output
TLV171-Q1
5V/div
-18 V
37 VPP
Sine Wave
(±18.5 V)
Output
Time (100ms/div)
Figure 7-1. No Phase Reversal
7.3.3 Capacitive Load and Stability
50
50
45
45
ROUT = 0 W
40
40
ROUT = 25 W
35
35
ROUT = 50 W
30
25
20
15
10
ROUT = 25 Ω
5
ROUT = 50 Ω
G=1
18 V
ROUT = 0 Ω
Overshoot (%)
Overshoot (%)
The dynamic characteristics of the OPAx171-Q1 family of devices are optimized for commonly encountered
operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase
margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be
isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT
equal to 50 Ω) in series with the output. Figure 7-2 and Figure 7-3 shows small-signal overshoot versus
capacitive load for several values of ROUT. For details of analysis techniques and application circuits, see
Applications Bulletin AB-028, available for download from TI.com.
30
25
20
RI = 10 kW
15
ROUT
-18 V
RF = 10 kW
G = -1
18 V
TLV171-Q1
RL
CL
10
ROUT
TLV171-Q1
CL
5
0
-18 V
0
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 7-2. Small-Signal Overshoot versus
Capacitive Load (100-mV Output Step)
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 7-3. Small-Signal Overshoot versus
Capacitive Load (100-mV Output Step)
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7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx171-Q1 family of devices extends 100 mV below the
negative rail and within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance
within 2 V of the top rail. The typical performance in this range is listed in Table 7-1.
Table 7-1. Typical Performance Range
PARAMETER
Input common-mode voltage
MIN
TYP
(V+) – 2
MAX
UNIT
(V+) + 0.1
V
Offset voltage
7
mV
Offset voltage vs temperature
12
µV/°C
Common-mode rejection
65
dB
Open-loop gain
60
dB
GBW
0.7
MHz
Slew rate
0.7
V/µs
Noise at f = 1kHz
30
nV/√ Hz
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The OPAx171-Q1 operational amplifier family provides high overall performance, making the device ideal for
many general-purpose applications. The excellent offset drift of only 2 µV/°C provides excellent stability over the
entire temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR,
and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling
capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
8.1.1 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits for protection from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful.
illustrates the ESD circuits contained in the (indicated by the dashed line area). The ESD protection circuitry
involves several current-steering diodes connected from the input and output pins and routed back to the internal
power-supply lines, where the diodes meet at an absorption device internal to the operational amplifier. This
protection circuitry is intended to remain inactive during normal circuit operation.
TVS
+
±
RF
+VS
R1
IN±
RS
IN+
2.5 NŸ
2.5 NŸ
+
Power-Supply
ESD Cell
ID
VIN
+
±
RL
+
±
±VS
TVS
Figure 8-1. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
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provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The
absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPAx171Q1 but below the device breakdown voltage level. When this threshold is exceeded, the absorption device
quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (as shown in ), the ESD protection components are
intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any
such current flow occurs through steering-diode paths and rarely involves the absorption device.
shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500 mV or
more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the current, one
of the upper input steering diodes conducts and directs current to V+. Excessively high current levels can flow
with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the input
current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the
current through the steering diodes can become quite high. The current level depends on the ability of the input
source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see . Select the Zener voltage so that the diode does not turn on during normal operation. However,
the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise above
the safe-operating, supply-voltage level.
The OPAx171-Q1 input pins are protected from excessive differential voltage with back-to-back diodes; see . In
most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1 circuits, fastramping input signals can forward-bias these diodes because the output of the amplifier cannot respond rapidly
enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, limit the input
signal current to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can be
used to limit the input signal current. This input series resistor degrades the low-noise performance of the
OPAx171-Q1. illustrates an example configuration that implements a current-limiting feedback resistor.
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8.2 Typical Application
8.2.1 Capacitive Load Drive Solution Using an Isolation Resistor
The OPAx171-Q1 device can be used capacitive loads such as cable shields, reference buffers, MOSFET gates,
and diodes. The circuit uses an isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the
open loop gain of the system to ensure the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
CLOAD
+
±
VIN
-VS
Figure 8-2. Unity-Gain Buffer with RISO Stability Compensation
8.2.1.1 Design Requirements
The design requirements are:
• Supply voltage: 30 V (±15 V)
•
•
Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
Phase margin: 45° and 60°
8.2.1.2 Detailed Design Procedure
Figure 8-3 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 8-3. Not shown in Figure 8-3 is the open-loop output resistance of the op amp, Ro.
T(s) =
1 + CLOAD × RISO × s
1 + Ro + RISO × CLOAD × s
(1)
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro +
RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is
obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20
dB/decade. Figure 8-3 shows the concept. The 1/β curve for a unity-gain buffer is 0 dB.
120
AOL
100
1
fp
2 u Πu RISO
Gain (dB)
80
60
Ro
u CLOAD
40 dB
fz
40
1
2 u Πu RISO u CLOAD
1 dec
1/
20
ROC
20 dB
dec
0
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 8-3. Unity-Gain Amplifier with RISO Compensation
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ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and AC gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table
8-1 lists the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For
more details on this design and other alternative devices that can be used in place of the OPA171-Q1 , see
Capacitive Load Drive Solution using an Isolation Resistor.
Table 8-1. Phase Margin versus Overshoot and AC Gain Peaking
PHASE MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
23.3%
2.35 dB
60°
8.8%
0.28 dB
8.2.1.3 Application Curve
The OPAx171-Q1 series meets the supply voltage requirements of 30 V. The OPAx171-Q1 device was tested for
various capacitive loads and RISO was adjusted to achieve an overshoot corresponding to Table 8-1. Figure 8-4
shows the test results.
10000
Isolation Resistor, RISO (:)
45q Phase Margin
60q Phase Margin
1000
100
10
1
0.01
0.1
1
10
Capacitive Load (nF)
100
1000
D001
Figure 8-4. RISO vs CLOAD
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9 Power Supply Recommendations
The OPAx171-Q1 family of devices is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in Section 6.7.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the Section 6.1 table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For detailed information on bypass capacitor placement, see Section 10.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
•
•
•
•
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace
perpendicular as opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. As shown in Figure 10-1, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
GND
VS±
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 10-1. Operational Amplifier Board Layout for Noninverting Configuration
24
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Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
OPA171-Q1, OPA2171-Q1, OPA4171-Q1
www.ti.com
SBOS556D – JUNE 2011 – REVISED AUGUST 2020
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Applications Bulletin AB-028
• Capacitive Load Drive Solution Using an Isolation Resistor
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 11-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA171-Q1
Click here
Click here
Click here
Click here
Click here
OPA2171-Q1
Click here
Click here
Click here
Click here
Click here
OPA4171-Q1
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: OPA171-Q1 OPA2171-Q1 OPA4171-Q1
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25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA171AQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OULQ
OPA2171AQDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2171
OPA2171AQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
2171AQ
OPA4171AQDRQ1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA4171Q1
OPA4171AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
O4171Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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