OPA186, OPA2186, OPA4186
SBOS968C – JUNE 2022 – REVISED JULY 2023
OPAx186 Precision, Rail-to-Rail Input/Output, 24-V, Zero-Drift Operational Amplifiers
1 Features
3 Description
•
The OPA186, OPA2186, and OPA4186 (OPAx186)
are low-power, 24-V, rail-to-rail input and output, zerodrift operational amplifiers (op amps). These op amps
feature only 10 µV of offset voltage (maximum) and
0.04 µV/°C of offset voltage drift over temperature
(maximum). These devices are a great choice for
precision instrumentation, signal measurement, and
active-filtering applications.
•
•
•
•
The low quiescent current consumption of 90 μA
makes the OPAx186 an excellent option for powersensitive applications, such as battery-powered
instrumentation and portable systems.
2 Applications
•
•
•
•
•
•
Moreover, the high common-mode architecture along
with low offset voltage allows for high-side current
shunt monitoring at the positive rail. These devices
also provide robust ESD protection during shipment,
handling, and assembly.
PC PSU and game console unit
Merchant DC/DC
Flow transmitter
Pressure transmitter
Merchant battery charger
Electricity meter
Device Information
PART NUMBER
Single
OPA2186
Dual
OPA4186
Quad
(1)
PACKAGE(1)
D (SOIC, 8)
DBV (SOT-23, 5)
D (SOIC, 8)
DDF (SOT-23, 8)
D (SOIC, 14)
For all available packages, see the package option
addendum at the end of the data sheet.
4
RS
6 V to 24 V
Microcontroller
Battery /
Power
Supply
CHANNELS
OPA186
ADC
OPAx186
+
0 V to 5 V
High-Side Current Shunt Monitor Application
Input-referred Offset Voltage (µV)
•
•
High precision:
– Offset drift: 0.01 μV/°C
– Low offset voltage: 1 μV
Low quiescent current: 90 µA
Excellent dynamic performance:
– Gain bandwidth: 750 kHz
– Slew rate: 0.35 V/µs
Robust design:
– RFI/EMI filtered inputs
Rail-to-rail input/output
Supply range: 4.5 V to 24 V
Temperature: –40°C to +125°C
3
2
1
0
-1
-2
-3
-4
-5
-6
-12.5 -10
-7.5 -5 -2.5
0
2.5
5
7.5
Input Common-mode Voltage (V)
10
12.5
VOS vs Input Common Mode Voltage
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA186, OPA2186, OPA4186
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SBOS968C – JUNE 2022 – REVISED JULY 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information: OPA186.................................... 6
6.5 Thermal Information: OPA2186.................................. 6
6.6 Thermal Information: OPA4186.................................. 6
6.7 Electrical Characteristics.............................................7
6.8 Typical Characteristics................................................ 9
7 Detailed Description......................................................17
7.1 Overview................................................................... 17
7.2 Functional Block Diagram......................................... 17
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................22
8 Application and Implementation.................................. 23
8.1 Application Information............................................. 23
8.2 Typical Applications.................................................. 25
8.3 Power Supply Recommendations.............................29
8.4 Layout....................................................................... 30
9 Device and Documentation Support............................31
9.1 Device Support......................................................... 31
9.2 Documentation Support............................................ 31
9.3 Receiving Notification of Documentation Updates....31
9.4 Support Resources................................................... 31
9.5 Trademarks............................................................... 32
9.6 Electrostatic Discharge Caution................................32
9.7 Glossary....................................................................32
10 Mechanical, Packaging, and Orderable
Information.................................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2022) to Revision C (July 2023)
Page
• Added OPA186 D (SOIC, 8) package and associated content as production data (active)............................... 1
Changes from Revision A (June 2022) to Revision B (November 2022)
Page
• Added OPA186 and OPA4186 devices and associated content........................................................................ 1
• Changed ESD Ratings table HBM value............................................................................................................ 5
• Changed ESD Ratings table CDM value............................................................................................................ 5
Changes from Revision * (June 2022) to Revision A (September 2022)
Page
• Changed OPA2186 from advanced information (preview) to production data (active).......................................1
2
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SBOS968C – JUNE 2022 – REVISED JULY 2023
5 Pin Configuration and Functions
±IN
2
+IN
3
V±
4
8
NC
±
7
V+
+
6
OUT
5
NC
OUT
1
V±
2
+IN
3
5
V+
4
±IN
±
1
+
NC
Not to scale
Not to scale
Figure 5-1. OPA186: D Package, 8-Pin SOIC
(Top View)
Figure 5-2. OPA186: DBV Package, 5-Pin SOT-23
(Top View)
Table 5-1. Pin Functions: OPA186
PIN
NAME
NO.
TYPE
D (SOIC)
DBV (SOT-23)
–IN
4
2
+IN
3
OUT
1
V–
V+
NC
DESCRIPTION
Input
Inverting input
3
Input
Noninverting input
6
Output
Output
2
4
Power
Negative (lowest) power supply
5
7
Power
Positive (highest) power supply
—
1, 8, 5
—
No connection (can be left floating)
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
Not to scale
Figure 5-3. OPA2186: D Package, 8-Pin SOIC and DDF Package, 8-Pin SOT-23 (Top View)
Table 5-2. Pin Functions: OPA2186
PIN
TYPE
DESCRIPTION
NAME
NO.
–IN A
2
Input
Inverting input channel A
+IN A
3
Input
Noninverting input channel A
–IN B
6
Input
Inverting input channel B
+IN B
5
Input
Noninverting input channel B
OUT A
1
Output
Output channel A
OUT B
7
Output
Output channel B
V–
4
Power
Negative supply
V+
8
Power
Positive supply
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OUT A
1
14
OUT D
±IN A
2
13
±IN D
+IN A
3
12
+IN D
V+
4
11
V±
+IN B
5
10
+IN C
±IN B
6
9
±IN C
OUT B
7
8
OUT C
Not to scale
Figure 5-4. OPA4186: D Package, 14-Pin SOIC (Top View)
Table 5-3. Pin Functions: OPA4186
PIN
4
TYPE
DESCRIPTION
NAME
NO.
–IN A
2
Input
Inverting input channel A
+IN A
3
Input
Noninverting input channel A
–IN B
6
Input
Inverting input channel B
+IN B
5
Input
Noninverting input channel B
–IN C
9
Input
Inverting input channel C
+IN C
10
Input
Noninverting input channel C
–IN D
13
Input
Inverting input channel D
+IN D
12
Input
Noninverting input channel D
OUT A
1
Output
Output channel A
OUT B
7
Output
Output channel B
OUT C
8
Output
Output channel C
OUT D
14
Output
Output channel D
V–
11
Power
Negative supply
V+
4
Power
Positive supply
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SBOS968C – JUNE 2022 – REVISED JULY 2023
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VS
MAX
Supply voltage, VS = (V+) – (V–)
Input voltage
26
Common-mode
(V–) –0.5
Differential
(V+) + 0.5
(V+) – (V–) + 0.2
Output short-circuit(2)
UNIT
V
V
Continuous
TJ
Operating junction temperature
-40
150
°C
Tstg
Storage temperature
-65
150
°C
(1)
(2)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
Charged-device model (CDM), per JANSI/ESDA/JEDEC JS-002(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Single supply
VS
Supply
voltage
TA
Specified temperature
Dual supply
NOM
MAX
4.5
24
±2.25
±12
–40
125
UNIT
V
°C
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6.4 Thermal Information: OPA186
OPA186
THERMAL METRIC(1)
D (SOIC)
DBV (SOT-23)
8 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
135.3
166.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
75.6
62.2
°C/W
RθJB
Junction-to-board thermal resistance
78.7
38.6
°C/W
ΨJT
Junction-to-top characterization parameter
25.4
12.1
°C/W
ΨJB
Junction-to-board characterization parameter
78.0
38.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2186
OPA2186
THERMAL METRIC(1)
DDF (SOT-23)
D (SOIC)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
150.4
128.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
85.6
69.2
°C/W
RθJB
Junction-to-board thermal resistance
70.0
72.3
°C/W
ΨJT
Junction-to-top characterization parameter
8.1
20.7
°C/W
ΨJB
Junction-to-board characterization parameter
69.6
71.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4186
OPA4186
THERMAL METRIC(1)
D (SOIC)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
84.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
37.4
°C/W
RθJB
Junction-to-board thermal resistance
41.4
°C/W
ΨJT
Junction-to-top characterization parameter
6.7
°C/W
ΨJB
Junction-to-board characterization parameter
40.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS968C – JUNE 2022 – REVISED JULY 2023
6.7 Electrical Characteristics
at TA = 25°C, VS = ±2.25 V to ±12 V, RL = 10 kΩ connected to VS / 2, VCM = VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
OPA186, OPA2186(1)
±1
±10
OPA4186(1)
±6
±40
±0.01
±0.04
±0.025
±0.1
OPA186, OPA2186
±0.02
±0.2
OPA4186
±0.08
±0.4
±5
±55
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
TA = –40℃ to +125℃(1)
PSRR
Power-supply rejection
ratio
TA = –40℃ to +125℃(1)
OPA186, OPA2186
OPA4186
μV
μV/°C
μV/V
INPUT BIAS CURRENT
TA = –40℃ to
IB
Input bias current
VS = ±12 V
+85℃(1)
TA = –40℃ to +125℃(1),
OPA186, OPA2186
TA = –40℃ to
OPA4186
±4.8
nA
+125℃(1),
±6.2
±10
IOS
Input offset current
TA = –40℃ to +85℃(1)
TA = –40℃ to +125℃(1)
pA
±550
±100
pA
±1
OPA186, OPA2186
±1.25
OPA4186
nA
±3.8
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
eN
Input voltage noise density f = 1 kHz
iN
Input current noise
f = 1 kHz
125
nVRMS
40
nV/√Hz
120
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
(V–) – 0.2
VS = ±2.25 V,
(V–) – 0.1 < VCM < (V+) + 0.1 V
CMRR
Common-mode rejection
ratio
(V+) + 0.2
OPA2186
120
140
OPA186
118
140
OPA4186
105
120
VS = ±12 V,
(V–) – 0.1 < VCM < (V+) + 0.1 V
OPA186, OPA2186
120
146
OPA4186
118
134
VS = ±2.25 V,
(V–) – 0.1 < VCM < (V+) + 0.1 V,
TA = –40℃ to +125℃(1)
OPA186, OPA2186
106
120
OPA4186
100
114
VS = ±12 V,
(V–) – 0.1 < VCM < (V+) + 0.1 V,
TA = –40℃ to +125℃(1)
OPA186, OPA2186
115
124
OPA4186
115
124
V
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
1-V step, G = 1
750
kHz
0.35
V/μs
tS
Settling time
To 0.1%, 1-V step, G = 1
7.5
μs
Overload recovery time
VIN × gain > VS
10
μs
INPUT CAPACITANCE
ZID
Differential
100 || 5
MΩ || pF
ZICM
Common-mode
50 || 2.5
GΩ || pF
OPEN-LOOP VOLTAGE GAIN
AOL
Open-loop voltage gain
VS = ±12 V, RL = 10 kΩ,
(V–) + 0.3 V < VO < (V+) – 0.3 V
VS = ±12 V, RL = 2 kΩ,
(V–) + 0.65 V < VO < (V+) – 0.65 V
TA = –40℃ to +125℃(1)
TA = –40℃ to +125℃(1)
123
148
123
146
123
148
123
146
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6.7 Electrical Characteristics (continued)
at TA = 25°C, VS = ±2.25 V to ±12 V, RL = 10 kΩ connected to VS / 2, VCM = VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5
10
UNIT
OUTPUT
No load
Positive rail
65
RL = 2 kΩ
345
425
95
120
5
10
RL = 10 kΩ,
TA = –40℃ to +125℃(1)
Voltage output swing from
the rail
VO
RL = 10 kΩ
No load
Negative rail
RL = 10 kΩ
30
RL = 2 kΩ
90
120
RL = 10 kΩ,
TA = –40℃ to +125℃(1)
35
50
ISC
Short-circuit current
CLOAD
Capacitive load drive
See typical curves
±20
RO
Open-loop output
impedance
See typical curves
mV
mA
POWER SUPPLY
IQ
(1)
8
Quiescent current per
amplifier
VS = ±2.25 V to ±12 V
90
TA = –40℃ to +125℃(1)
130
150
µA
Specification established from device population bench system measurements across multiple lots.
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6.8 Typical Characteristics
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted)
Table 6-1. Typical Characteristic Graphs
DESCRIPTION
FIGURE
Offset Voltage Distribution
Figure 6-1
Offset Voltage Drift (-40°C to +125C°C)
Figure 6-2
Input Bias Current Distribution
Figure 6-3
Input Offset Current Distribution
Figure 6-4
Offset Voltage vs Common-Mode Voltage
Figure 6-5
Offset Voltage vs Supply Voltage
Figure 6-6
Input Bias Current vs Common-Mode Voltage
Figure 6-7
Open-Loop Gain and Phase vs Frequency
Figure 6-8
Closed-Loop Gain vs Frequency
Figure 6-9
Input Bias Current and Offset Current vs Temperature
Figure 6-10
Output Voltage Swing vs Output Current (Sourcing)
Figure 6-11
Output Voltage Swing vs Output Current (Sinking)
Figure 6-12
CMRR and PSRR vs Frequency
Figure 6-13
CMRR vs Temperature
Figure 6-14
PSRR vs Temperature
Figure 6-15
0.1-Hz to 10-Hz Voltage Noise
Figure 6-16
Input Voltage Noise Spectral Density vs Frequency
Figure 6-17
THD+N vs Frequency
Figure 6-18
THD+N vs Output Amplitude
Figure 6-19
Quiescent Current vs Supply Voltage
Figure 6-20
Quiescent Current vs Temperature
Figure 6-21
Open-Loop Gain vs Temperature (10 kΩ)
Figure 6-22
Open-Loop Gain vs Temperature (2 kΩ)
Figure 6-23
Open-Loop Output Impedance vs Frequency
Figure 6-24
Small-Signal Overshoot vs Capacitive Load (Gain = –1, 10-mV step)
Figure 6-25
Small-Signal Overshoot vs Capacitive Load (Gain = 1, 10-mV step)
Figure 6-26
No Phase Reversal
Figure 6-27
Positive Overload Recovery
Figure 6-28
Negative Overload Recovery
Figure 6-29
Small-Signal Step Response (Gain = 1, 10-mV step)
Figure 6-30
Small-Signal Step Response (Gain = –1, 10-mV step)
Figure 6-31
Large-Signal Step Response (Gain = 1, 10-V step)
Figure 6-32
Large-Signal Step Response (Gain = –1, 10-V step)
Figure 6-33
Phase Margin vs Capacitive Load
Figure 6-34
Settling Time (1-V Step, 0.1% Settling)
Figure 6-35
Short Circuit Current vs Temperature
Figure 6-36
Maximum Output Voltage vs Frequency
Figure 6-37
EMIRR vs Frequency
Figure 6-38
Channel Separation
Figure 6-39
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6.8 Typical Characteristics (continued)
40
40
36
36
32
32
28
28
Amplifiers (%)
Amplifiers (%)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted)
24
20
16
24
20
16
12
12
8
8
4
4
0
-50
-40
-30
-20 -10
0
10
20
Input Offset Voltage (µV)
30
40
0
-0.1
50
Figure 6-1. Offset Voltage Distribution
72
54
64
48
56
Amplifiers (%)
Amplifiers (%)
42
36
30
24
18
40
32
24
16
6
8
-0.6
-0.4 -0.2
0
0.2 0.4
Input Bias Current (nA)
0.6
0.8
0
-600
1
Input Offset Voltage (µV)
Input Offset Voltage (µV)
-200
0
200
Input Offset Current (pA)
400
600
4
20
10
0
-10
2
0
-2
-4
-7.5
-5 -2.5
0
2.5
5
Common-mode Voltage (V)
7.5
10
Figure 6-5. Offset Voltage vs Common-Mode Voltage
10
-400
Figure 6-4. Input Offset Current Distribution
Figure 6-3. Input Bias Current Distribution
-20
-12.5 -10
0.1
48
12
-0.8
0.075
Figure 6-2. Offset Voltage Drift (-40°C to 125C°C)
60
0
-1
-0.075 -0.05 -0.025
0
0.025 0.05
Offset Voltage Drift (µV/°C)
12.5
4
6
8
10
12
14
16
18
Total Supply Voltage (V)
20
22
24
Figure 6-6. Offset Voltage vs Supply Voltage
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted)
180
50
40
150
180
Gain
Phase 150
120
120
90
90
60
60
30
30
0
0
Gain (dB)
20
10
0
-10
-20
-30
IBIB+
-40
-50
-12.5 -10
-7.5
-5 -2.5
0
2.5
5
Common-mode Voltage (V)
7.5
10
-30
10m 100m
10
100
1k
10k
Frequency (Hz)
100k
1M
-30
10M
Figure 6-8. Open-Loop Gain and Phase vs Frequency
30
2.5
G= 1
G= 1
G= 10
10
0
IBIB+
IOS
2
Input Bias Current (nA)
20
1.5
1
0.5
-10
0
-20
100
1k
10k
100k
Frequency (Hz)
1M
10M
-0.5
-50
12
12.5
10
10
8
7.5
Output Voltage (V)
6
4
2
0
-2
-4
-40qC
25qC
85qC
125qC
-6
-8
-25
0
25
50
Temperature (°C)
75
100
125
Figure 6-10. Input Bias Current and Offset Current vs
Temperature
Figure 6-9. Closed-Loop Gain vs Frequency
Output Voltage (V)
1
12.5
Figure 6-7. Input Bias Current vs Common-Mode Voltage
Gain (dB)
Phase (q)
Bias Current (pA)
30
-40qC
25qC
85qC
125qC
5
2.5
0
-2.5
-5
-7.5
-10
-10
-12.5
0
2.5
5
7.5
10 12.5 15 17.5
Output Current (mA)
20
Figure 6-11. Output Voltage Swing vs
Output Current (Sourcing)
22.5
25
0
3
6
9
12
15
18
Output Current (mA)
21
24
27
Figure 6-12. Output Voltage Swing vs
Output Current (Sinking)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted)
160
Common-mode Rejection Ration (dB)
120
100
80
60
40
20
1
10
100
1k
10k
Frequency (Hz)
100k
1M
160
0.01
155
150
145
140
0.1
135
130
-50
10M
Figure 6-13. CMRR and PSRR vs Frequency
-25
0
25
50
Temperature (°C)
75
100
0.01
125
-40
1
Noise ( )
Total Harmonic Distortion
Voltage Noise Density (nV/—Hz)
110 125
Figure 6-16. 0.1-Hz to 10-Hz Voltage Noise
1000
100
0.1
G=
G=
G=
G=
1, RL = 10 k:
1, RL = 2 k:
1, RL = 10 k:
1, RL = 2 k:
-60
0.01
-80
0.001
-100
-120
0.0001
1
10
100
1k
Frequency (Hz)
10k
100k
Figure 6-17. Input Voltage Noise Spectral Density vs Frequency
12
90
Time (1 s/div)
Figure 6-15. PSRR vs Temperature
10
100m
10
30
50
70
Temperature (°C)
Input Referred Voltage Noise (200 nV/div)
170
Power Supply Rejection Ration (µV/V)
Power Supply Rejection Ration (dB)
0.001
160
-50
-10
Figure 6-14. CMRR vs Temperature
190
180
-30
Noise (dB)
0
100m
165
Total Harmonic Distortion
Rejection Ratio (dB)
140
Common-mode Rejection Ration (µV/V)
170
PSRR
PSRR
CMRR
100
1k
Frequency (Hz)
10k
Figure 6-18. THD+N vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted)
-60
0.1
-80
0.01
0.001
10m
90
80
Quiescent Current (µA)
1, RL = 10 k:
1, RL = 2 k:
1, RL = 10 k:
1, RL = 2 k:
Total Harmonic Distortion + Noise (dB)
G=
G=
G=
G=
Noise (%)
Total Harmonic Distortion
100
-40
1
60
VS Min = 4.5 V
50
40
30
20
10
-100
10
100m
1
Output Amplitude (VRMS)
70
0
0
2
4
6
8
10 12 14 16
Supply Voltage (V)
18
20
22
24
Figure 6-20. Quiescent Current vs Supply Voltage
Figure 6-19. THD+N vs Output Amplitude
180
110
VS = 4.5 V
VS = 24 V
Open-loop Gain (dB)
Quiescent Current (µA)
100
90
80
160
140
70
60
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
120
-40
110 125
Figure 6-21. Quiescent Current vs Temperature
5
20 35 50 65
Temperature (qC)
80
95
110 125
1000
Open-Loop Output Impedance, ZO (:)
Open-loop Gain (dB)
-10
Figure 6-22. Open-Loop Gain vs Temperature
180
160
140
120
-40
-25
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
100
10
1
0.1
0.01
10
100
1k
10k
Frequency (Hz)
100k
1M
RL = 2 kΩ
Figure 6-23. Open-Loop Gain vs Temperature
Figure 6-24. Open-Loop Output Impedance vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted)
40
100
RISO = 0 :
RISO = 25 :
RISO = 50 :
35
RISO = 0 :
RISO = 25 :
RISO = 50 :
80
Overshoot ( )
Overshoot ( )
30
25
20
60
40
15
20
10
5
10
100
Capactiance (pF)
0
10
1000
100
Capactiance (pF)
Gain = –1, 10-mV step
1000
Gain = 1, 10-mV step
Figure 6-25. Small-Signal Overshoot vs
Capacitive Load
Figure 6-26. Small-Signal Overshoot vs
Capacitive Load
VIN
VOUT
Voltage (5 V/div)
Voltage (5 V/div)
VIN (V)
VOUT (V)
Time (10 Ps/div)
Time (100 Ps/div)
Figure 6-27. No Phase Reversal
Figure 6-28. Positive Overload Recovery
Voltage (5 V/div)
Voltage (5 mV/div)
VIN
VOUT
VIN
VOUT
Time (10 Ps/div)
Time (10 Ps/div)
Gain = 1, 10-mV step
Figure 6-29. Negative Overload Recovery
14
Figure 6-30. Small-Signal Step Response
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted)
VIN (V)
VOUT (V)
Voltage (2 V/div)
Voltage (5 mV/div)
VIN
VOUT
Time (10 Ps/div)
Time (10 Ps/div)
Gain = –1, 10-mV step
Gain = 1, 10-V step
Figure 6-31. Small-Signal Step Response
Figure 6-32. Large-Signal Step Response
65
VIN (V)
VOUT (V)
60
Voltage (2 V/div)
Phase Margin (q)
55
50
45
40
35
30
25
20
15
10
100
CLOAD (pF)
Time (10 Ps/div)
1000
Gain = –1, 10-V step
Figure 6-34. Phase Margin vs Capacitive Load
Figure 6-33. Large-Signal Step Response
32
Falling
Rising
Sinking
Sourcing
31
Output (1 mV/div)
Short Circuit Current (mA)
30
29
28
27
26
25
24
23
22
21
20
-40
Time (5 Ps/div)
-20
0
20
40
60
Temperature (qC)
80
100
120
1-V step, 0.1% settling
Figure 6-35. Settling Time
Figure 6-36. Short Circuit Current vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±12 V, VCM = VS / 2, RL = 10 kΩ (unless otherwise noted)
30
175
VS = r12 V
VS = r2.25 V
150
20
EMIRR IN+ (dB)
Output Voltage (VPP)
25
15
10
125
100
5
75
50
0
1
10
100
1k
10k
Frequency (Hz)
100k
25
10M
1M
Figure 6-37. Maximum Output Voltage vs Frequency
100M
1G
Frequency (Hz)
10G
Figure 6-38. EMIRR vs Frequency
-60
Channel Seperation (dB)
-80
-100
-120
-140
-160
-180
1k
10k
100k
1M
Frequency (Hz)
Figure 6-39. Channel Separation
16
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7 Detailed Description
7.1 Overview
The OPAx186 operational amplifier combines precision offset and drift with excellent overall performance,
making the device a great choice for a wide variety of precision applications. The precision offset drift of only
0.01 µV/°C provides stability over the entire operating temperature range of –40°C to +125°C. In addition, this
device offers excellent linear performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications
with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most
cases, 0.1-µF capacitors are adequate. For details and a layout example, see Section 8.4.
The OPAx186 is part of a family of zero-drift, MUX-friendly, rail-to-rail output operational amplifiers. This device
operates from 4.5 V to 24 V, is unity-gain stable, and is designed for a wide range of general-purpose
and precision applications. The zero-drift architecture provides ultra-low input offset voltage and near-zero
input offset voltage drift over temperature and time. This choice of architecture also offers outstanding ac
performance, such as ultra-low broadband noise, zero flicker noise, and outstanding distortion performance
when operating at less than the chopper frequency.
The following section shows a representation of the proprietary OPAx186 architecture.
7.2 Functional Block Diagram
C2
CHOP1
+IN
±IN
GM1
CHOP2
Notch
Filter
GM2
GM3
OUT
24-V
Differential
Front End
GM_FF
C1
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7.3 Feature Description
The OPAx186 operational amplifier has several integrated features to help maintain a high level of precision
through a variety of applications. These include a rail-to-rail inputs, phase-reversal protection, input bias current
clock feedthrough, EMI rejection, electrical overstress protection and MUX-friendly Inputs.
7.3.1 Rail-to-Rail Inputs
Unlike many chopper amplifiers, the OPAx186 has rail-to-rail inputs that allow the input common-mode voltage
to not only reach, but exceed the supply voltages by 200 mV. This configuration simplifies power-supply
requirements by not requiring headroom over the input signal range.
The OPAx186 is specified for operation from 4.5 V to 24 V (±2.25 V to ±12 V) with rail-to-rail inputs. Many
specifications apply from –40°C to +125°C.
7.3.2 Phase-Reversal Protection
The OPAx186 has internal phase-reversal protection. Some op amps exhibit a phase reversal when the input is
driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits
when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into
the opposite rail. The OPAx186 input prevents phase reversal with excessive common-mode voltage. Instead,
the output limits into the appropriate rail. Figure 7-1 shows this performance.
Voltage (5 V/div)
VIN (V)
VOUT (V)
Time (100 Ps/div)
Figure 7-1. No Phase Reversal
7.3.3 Input Bias Current Clock Feedthrough
Zero-drift amplifiers such as the OPAx186 use a switching architecture on the inputs to correct for the intrinsic
offset and drift of the amplifier. Charge injection from the integrated switches on the inputs can introduce short
transients in the input bias current of the amplifier. The extremely short duration of these pulses prevents the
pulses from amplifying; however, the pulses can be coupled to the output of the amplifier through the feedback
network. The most effective method to prevent transients in the input bias current from producing additional
noise at the amplifier output is to use a low-pass filter, such as an RC network.
18
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7.3.4 EMI Rejection
The OPAx186 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely-populated boards with a mix of analog
signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx186
benefits from these design improvements. Texas Instruments has developed the ability to accurately measure
and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to
6 GHz. Figure 7-2 shows the results of this testing on the OPAx186. Table 7-1 lists the EMIRR +IN values for the
OPAx186 at particular frequencies commonly encountered in real-world applications. Table 7-1 lists applications
that can be centered on or operated near the particular frequency shown. See also the EMI Rejection Ratio of
Operational Amplifiers application report, available for download from www.ti.com.
175
EMIRR IN+ (dB)
150
125
100
75
50
25
10M
100M
1G
Frequency (Hz)
10G
Figure 7-2. EMIRR Testing
Table 7-1. OPAx186 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION AND ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
48.4 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
52.8 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
69.1 dB
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
88.9 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
82.5 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
95.5 dB
5 GHz
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The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of
RF signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has
a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but
this section provides the EMIRR +IN, which specifically describes the EMIRR performance when the RF signal is
applied to the noninverting input pin of the op amp. In general, only the noninverting input is tested for EMIRR for
the following three reasons:
• Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the
supply or output pins.
• The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit nearly matching
EMIRR performance
• EMIRR is more simple to measure on noninverting pins than on other pins because the noninverting
input terminal can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the
noninverting input terminal with no complex interactions from other components or connecting PCB traces.
High-frequency signals conducted or radiated to any pin of the operational amplifier can result in adverse effects,
as there is insufficient amplifier loop gain to correct for signals with spectral content outside the bandwidth.
Conducted or radiated EMI on inputs, power supply, or output can result in unexpected dc offsets, transient
voltages, or other unknown behavior. Take care to properly shield and isolate sensitive analog nodes from noisy
radio signals and digital clocks and interfaces.
Figure 7-2 shows the EMIRR +IN of the OPAx186 plotted versus frequency. The OPAx186 unity-gain bandwidth
is 750 kHz. EMIRR performance less than this frequency denotes interfering signals that fall within the op-amp
bandwidth.
7.3.4.1 EMIRR +IN Test Configuration
Figure 7-3 shows the circuit configuration for testing the EMIRR +IN. An RF source is connected to the op-amp
noninverting input pin using a transmission line. The op amp is configured in a unity-gain buffer topology with
the output connected to a low-pass filter (LPF) and a digital multimeter (DMM). A large impedance mismatch
at the op amp input causes a voltage reflection; however, this effect is characterized and accounted for when
determining the EMIRR IN+. The multimeter samples and measures the resulting dc offset voltage. The LPF
isolates the multimeter from residual RF signals that can interfere with multimeter accuracy.
Ambient temperature: 25Û&
V+
±
Low-Pass
Filter
50
+
RF Source
DC Bias: 0 V
Modulation: None (CW)
Frequency Sweep: 201 pt. Log
Sample /
Averaging
V±
Digital
Multimeter
Not shown: 0.1 µF and 10 µF supply decoupling
Figure 7-3. EMIRR +IN Test Configuration
20
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7.3.5 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect from accidental
ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is
helpful. Figure 7-4 shows an illustration of the ESD circuits contained in the OPAx186 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device
internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit
operation.
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse while discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or
more steering diodes. Depending on the path that the current takes, the absorption device can activate. The
absorption device has a trigger or threshold voltage that is greater than the normal operating voltage of the
OPAx186, but less than the device breakdown voltage level. When this threshold is exceeded, the absorption
device quickly activates and clamps the voltage across the supply rails to a safe level.
Figure 7-4 shows that when the operational amplifier connects into a circuit, the ESD protection components
are intended to remain inactive, and do not become involved in the application circuit operation. However,
circumstances can arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits are biased on and conduct current.
Any such current flow occurs through steering-diode paths and rarely involves the absorption device.
(2)
TVS
RF
V+
RI
ESD CurrentSteering Diodes
IN
(3)
RS
+IN
Op Amp
Core
Edge-Triggered ESD
Absorption Circuit
ID
VIN
OUT
RL
(1)
V±
(2)
TVS
(1) VIN = (V+) + 500 mV
(2) TVS: 26 V > VTVSBR (min) > V+, where VTVSBR (min) is the minimum specified value for the transient voltage suppressor breakdown
voltage.
(3) Suggested value is approximately 5 kΩ in example overvoltage condition.
Figure 7-4. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
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Figure 7-4 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+)
by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can
sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high
current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies V+ or V– are at 0 V. Again, this question depends on the supply characteristic while at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current can be supplied by the input source through the current-steering diodes. This state is
not a normal biasing condition for the amplifier and can result in specification degradation or abnormal operation.
If the supplies are low impedance, then the current through the steering diodes can become quite high. The
current level depends on the ability of the input source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to
the supply pins; see also Figure 7-4. The Zener voltage must be selected such that the diode does not turn on
during normal operation. However, the Zener voltage must be low enough so that the Zener diode conducts if the
supply pin begins to rise above the safe operating supply voltage level.
7.3.6 MUX-Friendly Inputs
The OPAx186 features a proprietary input stage design that allows an input differential voltage to be applied
while maintaining high input impedance. Typically, high-voltage CMOS or bipolar-junction input amplifiers feature
antiparallel diodes that protect input transistors from large VGS voltages that can exceed the semiconductor
process maximum and permanently damage the device. Large VGS voltages can be forced when applying a
large input step, switching between channels, or attempting to use the amplifier as a comparator.
The OPAx186 solves these problems with a switched-input technique that prevents large input bias currents
when large differential voltages are applied. This input architecture addresses many issues seen in switched or
multiplexed applications, where large disruptions to RC filtering networks are caused by fast switching between
large potentials. The OPAx186 offers outstanding settling performance as a result of these design innovations
and built-in slew-rate boost and wide bandwidth. The OPAx186 can also be used as a comparator. Differential
and common-mode input ranges still apply.
7.4 Device Functional Modes
The OPAx186 has a single functional mode, and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx186 is 24 V (±12 V).
22
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The OPAx186 operational amplifier combines precision offset and drift with excellent overall performance,
making the device an excellent choice for many precision applications. The precision offset drift of only
0.01 µV/°C provides stability over the entire temperature range. In addition, the device pairs excellent CMRR,
PSRR, and AOL dc performance with outstanding low-noise operation. As with all amplifiers, applications with
noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases,
0.1‑µF capacitors are adequate.
8.1.1 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. In many cases, external noise sources
can dominate; consider the effect of source resistance on overall op-amp noise performance. Total noise of the
circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. The source impedance is usually fixed; consequently, select op amp and the feedback resistors that
minimize the respective contributions to the total noise.
Figure 8-1 shows both noninverting (A) and inverting (B) op-amp circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the
op amp reacts with the feedback resistors to create additional noise components. However, the extremely low
current noise of the OPAx186 means that the current noise contribution can be ignored.
The feedback resistor values can generally be chosen to make these noise sources negligible. Low impedance
feedback resistors load the output of the amplifier. The equations for total noise are shown for both
configurations.
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(A) Noise in Noninverting Gain Configuration
R1
Noise at the output is given as EO, where
R2
GND
±
EO
+
RS
+
±
VS
Source
GND
'1 = l1 +
:2;
A5 = ¥4 „ G$ „ 6(-) „ 45
d
:3;
A41 æ42 = ¨4 „ G$ „ 6(-) „ d
8
41 „ 42
h d
h
41 + 42
¾*V
Thermal noise of R1 || R2
:4;
G$ = 1.38065 „ 10F23
Boltzmann Constant
:5;
,
h
-
6(-) = 237.15 + 6(°%)
(B) Noise in Inverting Gain Configuration
R1
RS
R2
h
>-?
Thermal noise of RS
Temperature in kelvins
:45 + 41 ; „ 42
42
2
p „ ¨:A0 ;2 + kA41 +45 æ42 o + FE0 „ H
IG
45 + 41
45 + 41 + 42
:6;
'1 = l1 +
+
:7;
:45 + 41 ; „ 42
8
I d
A41 +45 æ42 = ¨4 „ G$ „ 6(-) „ H
h
45 + 41 + 42
¾*V Thermal noise of (R1 + RS) || R2
GND
:8;
G$ = 1.38065 „ 10F23
:9;
6(-) = 237.15 + 6(°%)
±
+
±
d
8
¾*V
> 84/5 ?
Noise at the output is given as EO, where
EO
VS
42
41 „ 42 2
2
p „ ¨:A5 ;2 + :A0 ;2 + kA41 æ42 o + :E0 „ 45 ;2 + lE0 „ d
hp
41
41 + 42
:1;
Source
GND
d
,
h
-
2
> 84/5 ?
Boltzmann Constant
>-?
Temperature in kelvins
Copyright © 2017, Texas Instruments Incorporated
Where en is the voltage noise spectral density of the amplifier. For the OPAx186 operational amplifier, en = 38 nV/√Hz at 1 kHz.
NOTE: For additional resources on noise calculations, visit TI Precision Labs.
Figure 8-1. Noise Calculation in Gain Configurations
24
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8.2 Typical Applications
8.2.1 High-Side Current Sensing
RL
+
24 V
–
IL
Load Current
R1
R2
+ 24 V –
+
R1 = R3, R2 = R4
VO
–
R3
OPA2186
R4
Figure 8-2. High-Side Current Monitor
8.2.1.1 Design Requirements
A common systems requirement is to monitor the current being delivered to a load. Monitoring makes sure that
normal current levels are being maintained, and also provides an alert if an overcurrent condition occurs.
Fortunately, a relatively simple current monitor design can be achieved using a precision rail-to-rail input/output
op amp such as the OPAx186. This device has an input common-mode voltage (VCM) range that extends
200 mV beyond each power supply rail allowing for operation at the supply rail.
The OPAx186 is configured as a difference amplifier with a predetermined gain. The difference amplifier
inputs are connected across a sense resistor through which the load current flows. The sense resistor can be
connected to the high side or low side of the circuit through which the load current flows. Commonly, high-side
current sensing is applied. Figure 8-2 shows an applicable OPAx186 configuration. Low-side current sensing can
be applied as well if the sense resistor can be placed between the load and ground.
Use the following parameters for this design example:
• Single supply: 24 V
• Linear output voltage range: 0.3 V to 3.3 V
• Load current, IL: 1 A to 11 A
The following design details and equations can be used to reconfigure this design for different output voltage
ranges and current loads.
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8.2.1.2 Detailed Design Procedure
Designing a high-side current monitor circuit is straightforward, provided that the amplifier electrical
characteristics are carefully considered so that linear operation is maintained. Other additional characteristics,
such as the input voltage range of the analog to digital converter (ADC) that follows the current monitor stage,
must also be considered when configuring the system.
For example, consider the design of a OPAx186 high-side current monitor with an output voltage range set to be
compatible with the input of an ADC with an input range of 3.3 V, such as one integrated in a microcontroller.
The full-scale input range of this converter is 0 V to 3.3 V. Although the OPAx186 is specified as a rail-to-rail
input/output (RRIO) amplifier, the linear output operating range (like all amplifiers) does not quite extend all the
way to the supply rails. This linear operating range must be considered.
In this design example, the OPAx186 is powered by 24 V; therefore, the device is easily capable of providing the
3.3-V positive level; or even more, if the ADC has a wider input range. However, because the OPAx186 output
does not swing completely to 0 V, the specified lower swing limit must be observed in the design.
The best measure of an op-amp linear output voltage range comes from the open-loop voltage gain (AOL)
specification listed in the Electrical Characteristics table. The AOL test conditions specify a linear swing range
300 mV from each supply rail (RL = 10 kΩ). Therefore, the linear swing limit on the low end (VoMIN) is 300 mV,
and 3.3 V is the VoMAX limit, thus yielding an 11:1 VoMAX to VoMIN ratio. This ratio proves important in determining
the difference amplifier operating parameters.
A nominal load current (IL) of 10 A is used in this example. In most applications, however, the ability to monitor
current levels far less than 10 A is useful. This situation is where the 11:1 VoMAX to VoMIN ratio is crucial. If 11 A
is set as the maximum current, this current must correspond to a 3.3-V output. Using the 11:1 ratio, the minimum
current of 1 A corresponds to 300 mV.
Selection of current sense resistor RS comes down to how much voltage drop can be tolerated at maximum
current and the permissible power loss or dissipation. A good compromise for a 10-A sense application is an RS
of 10 mΩ. That value results in a power dissipation of 1 W, and a 0.1-V drop at 10 A.
Next, determine the gain of the OPAx186 difference amplifier circuit. The maximum current of 11 A flowing
through a 10-mΩ sense resistor results in 110 mV across the resistor. That voltage appears as a differential
voltage, VR, that is applied across the OPAx186 difference amplifier circuit inputs:
VS
IL * RS
VS
11 A * 10 m :
110 mV
(1)
The OPAx186 required voltage gain is determined from:
GA
VOMAX
VS
GA
3.3 V
0.11 V
30
V
V
(2)
Now, checking the VoMIN using IL = 1 A:
26
VOMIN
GA * ISMIN * RS
VOMIN
30
V
* 1 A * 10 m:
V
300 mV
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Figure 8-3 shows the complete OPAx186 high-side current monitor. The circuit is capable of monitoring a current
range of < 1 A to 11 A, with a VCM very close to the 24-V supply voltage.
RL = 10 m
+
24 V
–
IL
Load Current
1 A to 11 A
R2 = 30 k
R1 = 1 k
+ 3.3 V –
+ 24 V –
R3 = 1 k
–
+
R4 = 30 k
OPA2186
µController
ADC
VO = 300 mV to 3.3 V
Figure 8-3. OPAx186 Configured as a High-Side Current Monitor
In this example, the OPAx186 output voltage is intentionally limited to 3.3 V. However, because of the 24-V
supply, the output voltage can be much higher to allow for a higher-voltage data converter with a higher dynamic
range.
The circuit in Figure 8-3 was checked using the TINA Spice circuit simulation tool to verify the correct operation
of the OPAx186 high-side current monitor. The simulation results are seen in Figure 8-4. The performance is
exactly as expected. Upon careful inspection of the plots, one possible surprise is that VO continues towards
zero as the sense current drops below 1 A, where VO is 300 mV and less.
RL = 10 m
+
24 V
–
IL
Load Current
1 A to 11 A
R2 = 30 k
R1 = 1 k
+ 3.3 V –
+ 24 V –
R3 = 1 k
–
+
R4 = 30 k
OPA2186
µController
ADC
VO = 300 mV to 3.3 V
Figure 8-4. OPAx186 High-Side Current-Monitor Simulation Schematic
The OPAx186 output, as well as other CMOS output amplifiers, often swing closer to 0 V than the linear
output parameters suggest. The voltage output swing, VO (see the Electrical Characteristics table), is not an
indication of the linear output range, but rather how close the output can move towards the supply rail. In that
region, the amplifier output approaches saturation, and the amplifier ceases to operate linearly. Thus, in the
current-monitor application, the current-measurement capability can continue to much less than the 300-mV
output level. However, keep in mind that the linearity errors are becoming large.
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Lastly, some notes about maximizing the high-side current monitor performance:
• All resistor values are critical for accurate gain results. Match resistor pairs of [R1 and R3] and [R2 and R4]
as closely as possible to minimize common-mode mismatch error. Use a 0.1% tolerance, or better. Often,
selecting two adjacent resistors on a reel provides close matching compared to random selection.
• Keep the closed-loop gain, GA, of the OPAx186 difference amplifier set to a reasonable value to reduce gain
error and maximize bandwidth. A GA of 30 V/V is used in the example.
• Although current monitoring is often used for monitoring dc supply currents, ac current can also be monitored.
The –3-dB bandwidth, or upper cutoff frequency, of the circuit is:
fH
GBW
Noise Gain
(4)
where
•
•
GBW = the amplifier unity gain bandwidth; 750 kHz for the OPAx186.
Noise Gain = the gain as seen going into the op-amp noninverting input, and is defined by:
GNG
1
R2
R1
(5)
For the OPAx186 circuit in Figure 8-3, the results are:
GNG
fH
30 k:
V
31
1 k:
V
750 kHz
24.2 kHz
31
1
(6)
Make sure that the amplifier slew rate is sufficient to support the expected output voltage swing range and
waveform. Also, if a single power supply (such as 24 V) is used, the ac power source applied to the sense input
must have a positive dc component to keep the VCM greater than 0 V. To maintain normal operation, the input
voltage cannot drop to less than 0 V.
The OPAx186 output can attain a 0‑V output level if a small negative voltage is used to power the V– pin
instead of ground. The LM7705 is a switched capacitor voltage inverter with a regulated, low-noise, –0.23-V
fixed voltage output. Powering the OPAx186 V– pin at this level approximately matches the 300‑mV linear output
voltage swing lower limit, thus extending the output swing to 0 V, or very near 0 V. This configuration greatly
improves the resolution at low sense current levels.
The LM7705 requires only about 78 μA of quiescent current, but be aware that the specified supply range is 3 V
to 5.25 V. The 3.3-V or 5-V supply used by the ADC can be used as a power source.
For more information about amplifier-based, high-side current monitors, see the TI Analog Engineer’s Circuit
Cookbook: Amplifiers.
28
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8.2.1.3 Application Curve
4
24.2
VOUT
VLOAD
24.16
3.2
24.12
2.8
24.08
2.4
24.04
2
24
1.6
23.96
1.2
23.92
0.8
23.88
0.4
23.84
0
0
1
2
3
4
5
6
7
Input Current (A)
8
9
10
Load Voltage (V)
Output Voltage (V)
3.6
23.8
11
Figure 8-5. High-Side Results
8.2.2 Bridge Amplifier
Figure 8-6 shows the basic configuration for a bridge amplifier. Click the following link to download the TINA-TI
file: Bridge Amplifier Circuit.
VEX
R1
R
R
R
R
+5V
VOUT
VREF
Copyright © 2017, Texas Instruments Incorporated
Figure 8-6. Bridge Amplifier
8.3 Power Supply Recommendations
The OPAx186 is specified for operation from 4.5 V to 24 V (±2.25 V to ±12 V); many specifications apply from
–40°C to +125°C.
CAUTION
Supply voltages larger than 40 V can permanently damage the device (see the Absolute Maximum
Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high‑impedance power supplies. For more detailed information on bypass capacitor placement, see Section 8.4.
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8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices:
• For the lowest offset voltage, avoid temperature gradients that create thermoelectric (Seebeck) effects in the
thermocouple junctions formed from connecting dissimilar conductors. Also:
– Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
– Thermally isolate components from power supplies or other heat sources.
– Shield operational amplifier and input circuitry from air currents, such as cooling fans.
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information, see the
The PCB is a component of op amp design analog application journal.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close as possible to the device. As Figure 8-7 shows, keep the feedback
resistor (R3) and gain resistor (R4) close to the inverting input to minimize parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• For best performance, clean the PCB following board assembly.
• Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake
at 85°C for 30 minutes is sufficient for most circumstances.
8.4.2 Layout Example
GND
+V
C3
R3
Use ground pours for
shielding the input
signal pairs
Place bypass
capacitors as close to
device as possible
(avoid use of vias)
C3
C4
R3
IN–
1
NC
NC
8
IN–
2
–IN
–
V+
7
IN+
3
+IN
+
OUT
6
4
V–
NC
5
C4
1
NC
NC
8
2
–IN
V+
7
3
+IN
OUT
6
4
V–
NC
5
+V
R1
R1
R2
R4
OUT
IN+
GND
R4
C2
OUT
R2
–V
C1
Place components
close to device and to
each other to reduce
parasitic errors
C1
–V
Use a low-ESR,
ceramic bypass
capacitor
C2
Figure 8-7. Operational Amplifier Board Layout for Difference Amplifier Configuration
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
9.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Design tools and simulation web page, TINA-TI simulation software offers
extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments
offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Zero-drift Amplifiers: Features and Benefits application brief
• Texas Instruments, The PCB is a component of op amp design application note
• Texas Instruments, Operational amplifier gain stability, Part 3: AC gain-error analysis
• Texas Instruments, Operational amplifier gain stability, Part 2: DC gain-error analysis
• Texas Instruments, Using infinite-gain, MFB filter topology in fully differential active filters application note
• Texas Instruments, Op Amp Performance Analysis
• Texas Instruments, Single-Supply Operation of Operational Amplifiers application note
• Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes application note
• Texas Instruments, Feedback Plots Define Op Amp AC Performance application note
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application note
• Texas Instruments, Analog Linearization of Resistance Temperature Detectors application note
• Texas Instruments, TI Precision Design TIPD102 High-Side Voltage-to-Current (V-I) Converter
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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9.5 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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25-Oct-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
OPA186DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
31CQ
Samples
OPA186DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
31CQ
Samples
OPA186DR
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O186
Samples
OPA2186DDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2MZ3
Samples
OPA2186DR
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2186
Samples
OPA4186DR
ACTIVE
SOIC
D
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4186
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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