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OPA2188
SBOS525C – AUGUST 2011 – REVISED JUNE 2016
OPA2188 0.03-μV/°C Drift, Low-Noise, Rail-to-Rail Output,
36-V, Zero-Drift Operational Amplifiers
1 Features
3 Description
•
•
•
The OPA2188 operational amplifier uses TI
proprietary auto-zeroing techniques to provide low
offset voltage (25 μV, maximum), and near zero-drift
over time and temperature. This miniature, highprecision, low quiescent current amplifier offers high
input impedance and rail-to-rail output swing within 15
mV of the rails. The input common-mode range
includes the negative rail. Either single or dual
supplies can be used in the range of 4 V to 36 V (±2
V to ±18 V).
1
•
•
•
•
•
•
•
Low Offset Voltage: 25 μV (Maximum)
Zerø-Drift: 0.03 μV/°C
Low Noise: 8.8 nV/√Hz
0.1-Hz to 10-Hz Noise: 0.25 µVPP
Excellent DC Precision:
PSRR: 142 dB
CMRR: 146 dB
Open-Loop Gain: 136 dB
Gain Bandwidth: 2 MHz
Quiescent Current: 475 μA (Maximum)
Wide Supply Range: ±2 V to ±18 V
Rail-to-Rail Output:
Input Includes Negative Rail
RFI Filtered Inputs
MicroSIZE Packages
The OPA2188 device is available in MSOP-8 and
SO-8 packages. The device is specified for operation
from –40°C to +105°C.
Device Information(1)
PART NUMBER
OPA2188
2 Applications
•
•
•
•
•
•
•
•
•
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Bridge Amplifiers
Strain Gauges
Test Equipment
Transducer Applications
Temperature Measurement
Electronic Scales
Medical Instrumentation
Resistance Temperature Detectors
Precision Active Filters
Offset Voltage vs Temperature
145
OPA2188 Zero-Drift Architecture
Precision Laser Trim Architecture
Offset Voltage (mV)
125
105
85
65
45
25
5
-55
-35
-15
5
25
45
65
85
105
125
Temperature (°C)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2188
SBOS525C – AUGUST 2011 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Zero-Drift Amplifier Portfolio ................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: High-Voltage Operation, VS
= ±4 V to ±18 V (VS = 8 V to 36 V)............................ 5
7.6 Electrical Characteristics: Low-Voltage Operation, VS
= ±2 V to < ±4 V (VS = +4 V to < +8 V) ..................... 7
7.7 Typical Characteristics: Table of Graphs .................. 9
7.8 Typical Characteristics ............................................ 10
8
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 20
9
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Applications ................................................ 21
9.3 System Examples ................................................... 22
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
27
27
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2012) to Revision C
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Changed Input Bias Current, IB and IOS parameters overtemperature maximum specification in Electrical
Characteristics: High-Voltage Operation table ....................................................................................................................... 5
•
Changed Noise, Input voltage noise density parameter units in Electrical Characteristics: High-Voltage Operation table... 5
•
Changed Power Supply, IQ parameter maximum specifications in Electrical Characteristics: High-Voltage Operation
table ....................................................................................................................................................................................... 6
•
Changed Input Bias Current, IB and IOS parameters overtemperature maximum specification in Electrical
Characteristics: Low-Voltage Operation table ....................................................................................................................... 7
•
Changed Noise, Input voltage noise density parameter units in Electrical Characteristics: Low-Voltage Operation
table ....................................................................................................................................................................................... 7
•
Changed Power Supply, IQ parameter maximum specifications in Electrical Characteristics: Low-Voltage Operation
table ....................................................................................................................................................................................... 8
Changes from Revision A (June 2012) to Revision B
•
Page
Changed second to last Applications bullet............................................................................................................................ 1
Changes from Original (August 2011) to Revision A
Page
•
Deleted all references to OPA188 and OPA4188 throughout document ............................................................................... 1
•
Updated document to current standards ................................................................................................................................ 1
•
Changed document status to Production Data....................................................................................................................... 1
2
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SBOS525C – AUGUST 2011 – REVISED JUNE 2016
5 Zero-Drift Amplifier Portfolio
VERSION
Single
Dual
Quad
PRODUCT
OFFSET VOLTAGE (µV)
OFFSET VOLTAGE DRIFT
(µV/°C)
BANDWIDTH (MHz)
OPA188 (4 V to 36 V)
25
0.085
2
OPA333 (5 V)
10
0.05
0.35
OPA378 (5 V)
50
0.25
0.9
OPA735 (12 V)
5
0.05
1.6
OPA2188 (4 V to 36 V)
25
0.085
2
OPA2333 (5 V)
10
0.05
0.35
OPA2378 (5 V)
50
0.25
0.9
OPA2735 (12 V)
5
0.05
1.6
OPA4188 (4 V to 36 V)
25
0.085
2
OPA4330 (5 V)
50
0.25
0.35
6 Pin Configuration and Functions
D and DGK Packages
8-Pin SOIC and MSOP
Top View
OUT A
-IN A
1
A
2
+IN A
3
V-
4
B
8
V+
7
OUT B
6
-IN B
5
+IN B
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Negative (inverting) input signal, channel A
–IN B
6
I
Negative (inverting) input signal, channel B
+IN A
3
I
Positive (noninverting) input signal, channel A
+IN B
5
I
Positive (noninverting) input signal, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) power supply
V+
8
—
Positive (highest) power supply
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OPA2188
SBOS525C – AUGUST 2011 – REVISED JUNE 2016
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage
Voltage
Signal input terminals, voltage
(2)
Signal input terminals, current (2)
Current
(3)
(V+) + 0.5
V
–10
10
mA
125
°C
150
°C
150
°C
–55
Junction, TJ
Storage, Tstg
(2)
V
Continuous
Operating, TA
(1)
UNIT
(V–) – 0.5
Output short-circuit (3)
Temperature
MAX
±20, 40
(single supply)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current-limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Supply voltage
TA
Specified temperature range
NOM
MAX
UNIT
4 (±2)
36 (±18)
V
-40
+105
°C
7.4 Thermal Information
THERMAL METRIC (1)
OPA2188ID
OPA2188IDGK
D (SOIC)
DGK (VSSOP)
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
111
159.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
54.9
37.4
°C/W
RθJB
Junction-to-board thermal resistance
51.7
48.5
°C/W
ψJT
Junction-to-top characterization parameter
9.3
1.2
°C/W
ψJB
Junction-to-board characterization parameter
51.1
77.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
°C/W
(1)
4
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
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SBOS525C – AUGUST 2011 – REVISED JUNE 2016
7.5 Electrical Characteristics: High-Voltage Operation, VS = ±4 V to ±18 V (VS = 8 V to 36 V)
at TA = 25°C, RL = 10 kΩ connected to VS/2, and VCOM = VOUT = VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
PSRR
Power-supply rejection ratio
6
25
0.03
0.085
μV/°C
0.075
0.3
μV/V
0.3
μV/V
TA = –40°C to +105°C
VS = 4 V to 36 V, VCM = VS / 2
VS = 4 V to 36 V, VCM = VS / 2,
TA = –40°C to +105°C
μV
4 (1)
Long-term stability
Channel separation, DC
μV
1
μV/V
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
VCM = VS / 2
±160
TA = –40°C to +105°C
±320
TA = –40°C to +105°C
±850
pA
±18
nA
±1700
pA
±6
nA
NOISE
en
Input voltage noise
f = 0.1 Hz to 10 Hz
0.25
μVPP
en
Input voltage noise density
f = 1 kHz
8.8
nV/√Hz
in
Input current noise density
f = 1 kHz
7
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
CMRR
Common-mode rejection ratio
V–
(V+) – 1.5
V
(V–) < VCM < (V+) – 1.5 V
120
134
dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V,
VS = ±18 V
130
146
dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V,
VS = ±18 V, TA = –40°C to +105°C
120
126
dB
INPUT IMPEDANCE
Differential
100 || 6
MΩ || pF
Common-mode
6 || 9.5
1012 Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 500 mV < VO < (V+) – 500 mV,
RL = 10 kΩ
130
136
dB
(V–) + 500 mV < VO < (V+) – 500 mV,
RL = 10 kΩ, TA = –40°C to +105°C
120
126
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
2
MHz
SR
Slew rate
G = +1
0.8
V/μs
Settling time, 0.1%
VS = ±18 V, G = 1, 10-V step
20
μs
Settling time, 0.01%
VS = ±18 V, G = 1, 10-V step
27
μs
Overload recovery time
VIN × G = VS
1
μs
Total harmonic distortion + noise
1 kHz, G = 1, VOUT = 1 VRMS
0.0001
%
THD+N
(1)
1000-hour life test at +125°C demonstrated randomly distributed variation in the range of measurement limits—approximately 4 μV.
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SBOS525C – AUGUST 2011 – REVISED JUNE 2016
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Electrical Characteristics: High-Voltage Operation, VS = ±4 V to ±18 V (VS = 8 V to 36
V) (continued)
at TA = 25°C, RL = 10 kΩ connected to VS/2, and VCOM = VOUT = VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
No load
Voltage output swing from rail
ISC
Short-circuit current
RO
Open-loop output resistance
CLOAD
Capacitive load drive
6
15
mV
RL = 10 kΩ
220
250
mV
RL = 10 kΩ, TA = –40°C to +105°C
310
350
mV
±18
f = 1 MHz, IO = 0
mA
120
Ω
1
nF
POWER SUPPLY
VS
IQ
6
Operating voltage
Quiescent current (per amplifier)
4 to 36 (±2 to ±18)
VS = ±4 V to VS = ±18 V
IO = 0 mA, TA = –40°C to +105°C
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415
V
510
μA
600
μA
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SBOS525C – AUGUST 2011 – REVISED JUNE 2016
7.6 Electrical Characteristics: Low-Voltage Operation, VS = ±2 V to < ±4 V (VS = +4 V to < +8 V)
at TA = 25°C, RL = 10 kΩ connected to VS/2, and VCOM = VOUT = VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
PSRR
Power-supply rejection ratio
TA = –40°C to +105°C
VS = 4 V to 36 V, VCM = VS / 2
6
25
0.03
0.085
μV/°C
0.075
0.3
μV/V
0.3
μV/V
VS = 4 V to 36 V, VCM = VS / 2,
TA = –40°C to +105°C
μV
4 (1)
Long-term stability
Channel separation, dc
μV
1
μV/V
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
VCM = VS / 2
±160
TA = –40°C to +105°C
±320
TA = –40°C to +105°C
±850
pA
±18
nA
±1700
pA
±6
nA
NOISE
en
in
Input voltage noise
f = 0.1 Hz to 10 Hz
0.25
μVPP
Input voltage noise density
f = 1 kHz
8.8
nV/√Hz
Input current noise density
f = 1 kHz
7
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
TA = –40°C to +105°C
V–
(V+) – 1.5
V
(V–) < VCM < (V+) – 1.5 V
106
114
dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V,
VS = ±2 V
114
120
dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V,
VS = ±2 V, TA = –40°C to +105°C
110
120
dB
INPUT IMPEDANCE
Differential
Common-mode
100 || 6
MΩ || pF
6 || 95
1012 Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 500 mV < VO < (V+) – 500 mV,
RL = 5 kΩ, VS = 5 V
110
120
dB
(V–) + 500 mV < VO < (V+) – 500 mV,
RL = 10 kΩ
120
130
dB
(V–) + 500 mV < VO < (V+) – 500 mV,
RL = 10 kΩ, TA = –40°C to +105°C
114
120
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
G = +1
Overload recovery time
VIN × G = VS
Total harmonic distortion + noise
1 kHz, G = 1, VOUT = 1 VRMS
THD+N
(1)
2
MHz
0.8
V/μs
1
μs
0.0001
%
1000-hour life test at +125°C demonstrated randomly distributed variation in the range of measurement limits—approximately 4 μV.
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Electrical Characteristics: Low-Voltage Operation, VS = ±2 V to < ±4 V (VS = +4 V to < +8
V) (continued)
at TA = 25°C, RL = 10 kΩ connected to VS/2, and VCOM = VOUT = VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
No load
Voltage output swing from rail
ISC
Short-circuit current
RO
Open-loop output resistance
CLOAD
Capacitive load drive
6
15
mV
RL = 10 kΩ
220
250
mV
RL = 10 kΩ, TA = –40°C to +105°C
310
350
mV
±18
f = 1 MHz, IO = 0
mA
120
Ω
1
nF
POWER SUPPLY
VS
IQ
Operating voltage range
Quiescent current (per amplifier)
4 to 36 (±2 to ±18)
VS = ±2 V to VS = ±4 V
385
IO = 0 mA, TA = –40°C to +105°C
V
485
μA
590
μA
TEMPERATURE RANGE
Specified temperature range
–40
105
°C
TA
Operating temperature range
–40
125
°C
Tstg
Storage temperature
–65
150
°C
8
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7.7 Typical Characteristics: Table of Graphs
Table 1. Characteristic Performance Measurements
DESCRIPTION
FIGURE NO.
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature
Figure 3
Offset Voltage vs Common-Mode Voltage
Figure 4, Figure 5
Offset Voltage vs Power Supply
Figure 6
IB and IOS vs Common-Mode Voltage
Figure 7
Input Bias Current vs Temperature
Figure 8
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 9
CMRR and PSRR vs Frequency (Referred-to-Input)
Figure 10
CMRR vs Temperature
Figure 11, Figure 12
PSRR vs Temperature
Figure 13
0.1-Hz to 10-Hz Noise
Figure 14
Input Voltage Noise Spectral Density vs Frequency
Figure 15
THD+N Ratio vs Frequency
Figure 16
THD+N vs Output Amplitude
Figure 17
Quiescent Current vs Supply Voltage
Figure 18
Quiescent Current vs Temperature
Figure 19
Open-Loop Gain and Phase vs Frequency
Figure 20
Closed-Loop Gain vs Frequency
Figure 21
Open-Loop Gain vs Temperature
Figure 22
Open-Loop Output Impedance vs Frequency
Figure 23
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 24, Figure 25
No Phase Reversal
Figure 26
Positive Overload Recovery
Figure 27
Negative Overload Recovery
Figure 28
Small-Signal Step Response (100 mV)
Figure 29, Figure 30
Large-Signal Step Response
Figure 31, Figure 32
Large-Signal Settling Time (10-V Positive Step)
Figure 33
Large-Signal Settling Time (10-V Negative Step)
Figure 34
Short-Circuit Current vs Temperature
Figure 35
Maximum Output Voltage vs Frequency
Figure 36
Channel Separation vs Frequency
Figure 37
EMIRR IN+ vs Frequency
Figure 38
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7.8 Typical Characteristics
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
20
40
Distribution Taken From 1400 Amplifiers
Percentage of Amplifiers (%)
16
14
12
10
8
6
4
Distribution Taken From 78 Amplifiers
35
30
25
20
15
10
5
2
15
5 Typical Units Shown
VS = ±18 V
VOS (mV)
-5
-10
-10
-55
-35
-15
5
25
45
65
85
105
-15
-2.5
125
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
VCM (V)
Temperature (°C)
Figure 3. Offset Voltage vs Temperature
Figure 4. Offset Voltage vs Common-Mode Voltage
15
5 Typical Units Shown
VS = ±18 V
5 Typical Units Shown
VSUPPLY = ±2 V to ±18 V
10
5
VOS (mV)
5
VOS (mV)
0.09
0
-5
-15
0
0
-5
-5
-10
-10
-15
-15
-20
-15
-10
-5
0
5
10
15
20
0
VCM (V)
2
4
6
8
10
12
14
16
18
20
VSUPPLY (V)
Figure 5. Offset Voltage vs Common-Mode Voltage
10
0.08
5
0
10
0.07
5 Typical Units Shown
VS = ±2 V
10
5
VOS (mV)
0.05
Figure 2. Offset Voltage Drift Distribution
15
15
0.06
0.03
Offset Voltage Drift (mV/°C)
Figure 1. Offset Voltage Production Distribution
10
0.04
0.01
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
18
20
Offset Voltage (mV)
0.1
0
0
0.02
Percentage of Amplifiers (%)
18
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Figure 6. Offset Voltage vs Power Supply
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Typical Characteristics (continued)
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
4000
500
IB+
+IB
400
IB and IOS (pA)
IOS
Input Bias Current (pA)
IOS
300
IB-
3000
-IB
200
100
0
-100
2000
1000
0
-1000
-200
-300
-2000
-20
-15
-10
0
-5
5
10
15
20
-55
-35
5
-15
VCM (V)
20
19
18
17
16
15
14
-14
-15
-16
-17
-18
-19
-20
65
85
105
125
160
-40°C
+85°C
+125°C
140
120
100
80
60
40
+PSRR
-PSRR
CMRR
20
0
0
2
4
6
8
10
12
14
16
18
20
22
1
24
10
100
Figure 9. Output Voltage Swing vs Output Current
(Maximum Supply)
10k
100k
1M
Figure 10. CMRR and PSRR vs Frequency (Referred-toInput)
Common-Mode Rejection Ratio (mV/V)
40
(V-) < VCM < (V+) - 1.5 V
35
1k
Frequency (Hz)
Output Current (mA)
Common-Mode Rejection Ratio (mV/V)
45
Figure 8. Input Bias Current vs Temperature
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
Output Voltage (V)
Figure 7. IB and IOS vs Common-Mode Voltage
30
25
Temperature (°C)
(V-) + 0.5 V < VCM < (V+) - 1.5 V
VSUPPLY = ±2 V
25
20
15
10
5
0
8
(V-) < VCM < (V+) - 1.5 V
7
6
(V-) + 0.5 V < VCM < (V+) - 1.5 V
VSUPPLY = ±18 V
5
4
3
2
1
0
-55
-35
-15
5
25
45
65
85
105
125
-55
-35
-15
5
25
45
65
85
Temperature (°C)
Temperature (°C)
Figure 11. CMRR vs Temperature
Figure 12. CMRR vs Temperature
105
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Typical Characteristics (continued)
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
5 Typical Units Shown
VSUPPLY = ±2 V to ±18 V
0.6
0.4
50 nV/div
Power-Supply Rejection Ratio (mV/V)
1
0.8
0.2
0
-0.2
-0.4
-0.6
-0.8
Peak-to-Peak Noise = 250 nV
-1
-55
-35
5
-15
25
45
65
85
105
Time (1 s/div)
125
Temperature (°C)
Figure 14. 0.1-Hz to 10-Hz Noise
Figure 13. PSRR vs Temperature
Total Harmonic Distortion + Noise (%)
0.01
10
1
0.1
1
10
100
1k
10k
0.001
-100
0.0001
-120
G = +1, RL = 10 kW
G = -1, RL = 10 kW
10
100
0.01
-80
0.001
-100
0.0001
-120
G = +1, RL = 10 kW
G = -1, RL = 10 kW
-140
10
20
0.5
0.48
0.46
0.44
IQ (mA)
Total Harmonic Distortion + Noise (%)
-60
BW = 80 kHz
0.42
0.4
0.38
0.36
0.34
0.32
Specified Supply-Voltage Range
0.3
0
Output Amplitude (VRMS)
4
8
12
16
20
24
28
32
36
Supply Voltage (V)
Figure 17. THD+N vs Output Amplitude
12
10k
Figure 16. THD+N Ratio vs Frequency
Total Harmonic Distortion + Noise (dB)
0.1
1
1k
Frequency (Hz)
Figure 15. Input Voltage Noise Spectral Density vs
Frequency
0.1
-140
20k
0.00001
100k
Frequency (Hz)
0.00001
0.01
-80
VOUT = 1 VRMS
BW = 80 kHz
Total Harmonic Distortion + Noise (dB)
Voltage Noise Density (nV/ÖHz)
100
Figure 18. Quiescent Current vs Supply Voltage
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Typical Characteristics (continued)
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
0.5
180
140
VS = ±18 V
0.48
VS = ±2 V
0.46
Gain
Phase
120
135
100
0.42
0.4
80
40
0.36
20
0.34
0
0.32
90
60
0.38
45
−20
1
0.3
-55
-35
5
-15
25
45
65
85
105
Phase (°)
Gain (dB)
IQ (mA)
0.44
10
100
125
1k
10k 100k
Frequency (Hz)
1M
10M
0
100M
G001
Temperature (°C)
Figure 20. Open-Loop Gain and Phase vs Frequency
Figure 19. Quiescent Current vs Temperature
3
25
20
VSUPPLY = 4 V, RL = 10 kW
VSUPPLY = 36 V, RL = 10 kW
2.5
15
2
AOL (mV/V)
Gain (dB)
10
5
0
1.5
1
-5
-10
G = 10
G = +1
G = -1
-15
0.5
0
-20
10k
100k
1M
10M
-55
-35
5
-15
Frequency (Hz)
25
45
65
85
105
125
Temperature (°C)
Figure 21. Closed-Loop Gain vs Frequency
Figure 22. Open-Loop Gain vs Temperature
10k
40
RL = 10 kW
35
ROUT = 0 W
30
Overshoot (%)
ZO (W)
1k
100
10
ROUT = 25 W
25
ROUT = 50 W
20
15
G = +1
+18 V
ROUT
10
Device
1
-18 V
5
RL
CL
0
1m
1
10
100
1k
10k
100k
1M
10M
0
Frequency (Hz)
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 23. Open-Loop Output Impedance vs Frequency
Figure 24. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
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Typical Characteristics (continued)
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
40
ROUT = 0 W
35
Device
ROUT = 50 W
30
25
-18 V
37 VPP
Sine Wave
(±18.5 V)
5 V/div
Overshoot (%)
+18 V
ROUT = 25 W
20
15
RI = 10 kW
10
RF = 10 kW
G = -1
+18 V
VIN
VOUT
ROUT
Device
5
CL
RL = 10 kW
-18 V
0
0
Time (100 ms/div)
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 26. No Phase Reversal
Figure 25. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
VIN
VOUT
20 kW
20 kW
+18 V
Device
5 V/div
5 V/div
2 kW
VOUT
VIN
-18 V
2 kW
+18 V
VOUT
Device
VIN
-18 V
G = -10
G = -10
VOUT
VIN
Time (5 ms/div)
Time (5 ms/div)
Figure 27. Positive Overload Recovery
Figure 28. Negative Overload Recovery
+18 V
RL = 10 kW
CL = 10 pF
20 mV/div
20 mV/div
RL = 10 kW
CL = 10 pF
G = +1
RI
= 2 kW
RF
= 2 kW
+18 V
Device
Device
-18 V
RL
CL
CL
-18 V
G = -1
Time (20 ms/div)
Time (1 ms/div)
Figure 29. Small-Signal Step Response (100 mV)
14
Figure 30. Small-Signal Step Response (100 mV)
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Typical Characteristics (continued)
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
G = +1
RL = 10 kW
CL = 10 pF
5 V/div
5 V/div
G = -1
RL = 10 kW
CL = 10 pF
Time (50 ms/div)
Time (50 ms/div)
Figure 31. Large-Signal Step Response
10
10
G = -1
6
4
12-Bit Settling
2
0
-2
(±1/2 LSB = ±0.024%)
-4
-6
6
4
0
-2
-6
-8
-10
20
30
40
50
(±1/2 LSB = ±0.024%)
-4
-10
10
12-Bit Settling
2
-8
0
G = -1
8
D From Final Value (mV)
8
D From Final Value (mV)
Figure 32. Large-Signal Step Response
60
0
10
20
Time (ms)
Figure 33. Large-Signal Settling Time (10-V Positive Step)
40
50
60
Figure 34. Large-Signal Settling Time (10-V Negative Step)
30
15
20
12.5
Output Voltage (VPP)
VS = ±15 V
10
ISC (mA)
30
Time (ms)
ISC, Source
0
ISC, Sink
-10
-20
10
Maximum output voltage without
slew-rate induced distortion.
7.5
VS = ±5 V
5
2.5
-30
VS = ±2.25 V
0
-55
-35
-15
5
25
45
65
85
105
125
1k
10k
100k
1M
10M
Frequency (Hz)
Temperature (°C)
Figure 35. Short-Circuit Current vs Temperature
Figure 36. Maximum Output Voltage vs Frequency
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Typical Characteristics (continued)
VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted.
160
-60
Channel A to B
Channel B to A
140
-80
120
EMIRR IN+ (dB)
Channel Separation (dB)
-70
-90
-100
-110
-120
100
80
60
40
-130
20
-140
-150
1
10
100
1k
10k
100k
1M
10M
100M
0
10M
Frequency (Hz)
1G
10G
Frequency (Hz)
Figure 37. Channel Separation vs Frequency
16
100M
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8 Detailed Description
8.1 Overview
The OPA2188 operational amplifier combines precision offset and drift with excellent overall performance,
making the device ideal for many precision applications. The precision offset drift of only 0.085 µV/°C provides
stability over the entire temperature range. In addition, the device offers excellent overall performance with high
CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require
decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
8.2 Functional Block Diagram
C2
CHOP1
GM1
CHOP2
Notch
Filter
GM2
GM3
+IN
OUT
-IN
C1
GM_FF
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8.3 Feature Description
8.3.1 Operating Characteristics
The OPA2188 is specified for operation from 4 V to 36 V (±2 V to ±18 V). Many of the specifications apply from
–40°C to +105°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
8.3.2 EMI Rejection
The OPA2188 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely populated boards with a mix of analog
signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx188
benefits from these design improvements. Texas Instruments has developed the ability to accurately measure
and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to
6 GHz. Figure 39 shows the results of this testing on the OPA2188. Detailed information can also be found in the
application report EMI Rejection Ratio of Operational Amplifiers (SBOA128), available for download from the TI
website.
160
140
EMIRR IN+ (dB)
120
100
80
60
40
20
0
10M
100M
1G
10G
Frequency (Hz)
Figure 39. EMIRR Testing
8.3.3 Phase-Reversal Protection
The OPA2188 device has an internal phase-reversal protection. Many op amps exhibit a phase reversal when
the input is driven beyond its linear common-mode range. This condition is most often encountered in
noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the
output to reverse into the opposite rail. The OPA2188 input prevents phase reversal with excessive commonmode voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 40.
+18 V
Device
5 V/div
-18 V
37 VPP
Sine Wave
(±18.5 V)
VIN
VOUT
Time (100 ms/div)
Figure 40. No Phase Reversal
18
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Feature Description (continued)
8.3.4 Capacitive Load and Stability
The dynamic characteristics of the OPA2188 have been optimized for a range of common operating conditions.
The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier
and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the
output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in
series with the output. Figure 41 and Figure 42 illustrate graphs of small-signal overshoot versus capacitive load
for several values of ROUT. Also, refer to the applications report, Feedback Plots Define Op Amp AC Performance
(SBOA015), available for download from the TI website, for details of analysis techniques and application
circuits.
40
40
RL = 10 kW
ROUT = 0 W
35
35
ROUT = 0 W
ROUT = 25 W
25
ROUT = 25 W
ROUT = 50 W
30
Overshoot (%)
Overshoot (%)
30
ROUT = 50 W
20
15
G = +1
+18 V
ROUT
10
-18 V
20
15
RI = 10 kW
10
Device
5
25
RL
RF = 10 kW
G = -1
+18 V
ROUT
CL
Device
5
CL
RL = 10 kW
-18 V
0
0
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Capacitive Load (pF)
Figure 41. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 42. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
8.3.5 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA as stated in the Absolute Maximum Ratings. Figure 43 shows how a series input resistor may be added to
the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and
its value should be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10 mA max
VIN
5 kW
VOUT
Device
Figure 43. Input Current Protection
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Feature Description (continued)
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When the operational amplifier connects into a circuit, the ESD protection components are intended to remain
inactive and not become involved in the application circuit operation. However, circumstances may arise where
an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk
that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow
occurs through ESD cells and rarely involves the absorption device.
If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be
added to the supply pins. The zener voltage must be selected such that the diode does not turn on during normal
operation.
However, its zener voltage must be low enough so that the zener diode conducts if the supply pin begins to rise
above the safe operating supply voltage level.
8.4 Device Functional Modes
The OPA2188 device has a single functional mode. The device is powered on as long as the power supply
voltage is between 4 V (±2 V) and 36 V (±18 V).
20
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Applications
9.2.1 High-Side Voltage-to-Current (V-I) Converter
The circuit shown in Figure 44 is a high-side voltage-to-current (V-I) converter. It translates in input voltage of 0 V
to 2 V to and output current of 0 mA to 100 mA. Figure 45 shows the measured transfer function for this circuit.
The low offset voltage and offset drift of the OPA2188 facilitate excellent dc accuracy for the circuit.
V+
RS2
RS3
IRS2
470
VRS2
IRS3
4.7
10 k
R4
VRS3
C7
2200 pF
R5
A2
+
V+
200
+
330
Q2
Q1
A1
R3
VIN
+
±
1000 pF
C6
10 k
VRS1
R2
RS1
2k
IRS1
VLOAD
RLOAD
ILOAD
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Figure 44. High-Side Voltage-to-Current (V-I) Converter
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Typical Applications (continued)
9.2.1.1 Design Requirements
The design requirements are as follows:
• Supply Voltage: 5 V DC
• Input: 0 V to 2 V DC
• Output: 0 mA to 100 mA DC
9.2.1.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three
current sensing resistors, RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that
flows through the first stage of the design. The current gain from the first stage to the second stage is based on
the relationship between RS2 and RS3.
For a successful design, pay close attention to the dc characteristics of the operational amplifier chosen for the
application. To meet the performance goals, this application benefits from an operational amplifier with low offset
voltage, low temperature drift, and rail-to-rail output. The OPA2188 CMOS operational amplifier is a highprecision, ultra-low offset, ultra-low drift amplifier optimized for low-voltage, single-supply operation with an output
swing to within 15 mV of the positive rail. The OPA2188 family uses chopping techniques to provide low initial
offset voltage and near-zero drift over time and temperature. Low offset voltage and low drift reduce the offset
error in the system, making these devices appropriate for precise dc control. The rail-to-rail output stage of the
OPA2188 ensures that the output swing of the operational amplifier is able to fully control the gate of the
MOSFET devices within the supply rails.
A detailed error analysis, design procedure, and additional measured results are given in TIPD102.
9.2.1.3 Application Curve
0.1
Load
Output Current (A)
0.075
0.05
0.025
0
0
0.5
1
Input Voltage (V)
1.5
2
D001
Figure 45. Measured Transfer Function for High-Side V-I Converter
9.3 System Examples
9.3.1 Discrete INA + Attenuation for ADC With 3.3-V Supply
The application examples of Figure 46 and Figure 47 highlight only a few of the circuits where the OPA2188 can
be used.
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System Examples (continued)
15 V
U2
1/2
OPA2188
VOUTP
3.3 V
VDIFF/2
-15 V
R5
1 kW
Ref 1
Ref 2
RG
500 W
+
VCM
10
R7
1 kW
U1
INA159
VOUT
Sense
-15 V
-VDIFF/2
U5
1/2
OPA2188
VOUTN
15 V
Figure 46. Discrete INA + Attenuation for ADC with 3.3-V Supply
9.3.2 RTD Amplifier with Linearization
+15 V
(5 V)
Out
REF5050
In
1 mF
1 mF
R2
49.1 kW
R3
60.4 kW
R1
4.99 kW
1/2
OPA2188
VOUT
0°C = 0 V
200°C = 5 V
R5
(1)
105.8 kW
RTD
Pt100
R4
1 kW
(1) R5 provides positive-varying excitation to linearize output.
Figure 47. RTD Amplifier with Linearization
10 Power Supply Recommendations
The OPA2188 is specified for operation from 4 V to 36 V (±2 V to ±18 V); many specifications apply from –40°C
to 105°C. The Typical Characteristics presents parameters that can exhibit significant variance with regard to
operating voltage or temperature.
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CAUTION
Supply voltages larger than 40 V can permanently damage the device (see the
Absolute Maximum Ratings).
TI recommends placing 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in
from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement,
refer to the Layout Guidelines section.
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11 Layout
11.1 Layout Guidelines
Pay attention to good layout practices. Keep traces short and when possible, use a printed-circuit-board (PCB)
ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-μF
capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve
performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility.
Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified
as a variation in offset voltage or DC signal levels with changes in the interfering RF signal. The OPA2188 is
specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to
previous generation devices. Strong RF fields may still cause varying offset levels.
11.2 Layout Example
Input
±
A
+
±
B
Output
+
Connect to low impedance
ground plane
GND
Place power supply bypass
capacitors close to the device
V+
OUT A
Keep high impedance
input traces short
V+
Output
Input
GND
-IN A
OUT B
+IN A
-IN B
Keep high impedance
input traces short
Connect to low impedance
ground plane
V-
+IN B
GND
V-
GND
Place power supply bypass
capacitors close to the device
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Figure 48. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
12.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount ICs. The evaluation
tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (MSOP-8), DBV (SOT23-6, SOT23-5 and
SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used with
terminal strips or may be wired directly to existing circuits.
12.1.1.3 Universal Op Amp EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of IC package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, MSOP, TSSOP and SOT23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own ICs. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
12.1.1.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
12.1.1.5 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
26
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: OPA2188
OPA2188
www.ti.com
SBOS525C – AUGUST 2011 – REVISED JUNE 2016
12.2 Documentation Support
12.2.1 Related Documentation
The following documents are relevant to using the OPA2188, and recommended for reference. All are available
for download at www.ti.com unless otherwise noted.
• EMI Rejection Ratio of Operational Amplifiers.
• Feedback Plots Define Op Amp AC Performance
• Op Amp Performance Analysis.
• Single-Supply Operation of Operational Amplifiers
• Tuning in Amplifiers.
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2011–2016, Texas Instruments Incorporated
Product Folder Links: OPA2188
27
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2188AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
(2188 ~ OPA2188)
OPA2188AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
2188
OPA2188AIDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
2188
OPA2188AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
(2188 ~ OPA2188)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2188AIDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2188AIDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2188AIDGKT
VSSOP
DGK
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2188AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2188AIDGKR
VSSOP
DGK
8
2500
346.0
346.0
41.0
OPA2188AIDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA2188AIDGKT
VSSOP
DGK
8
250
366.0
364.0
50.0
OPA2188AIDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
(.041)
[1.04]
TYPICAL
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
SYMM
5
4
(R.002 ) TYP
[0.05]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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