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OPA211, OPA2211
SBOS377L – OCTOBER 2006 – REVISED JANUARY 2020
OPAx211 1.1-nv/√Hz Noise, Low Power, Precision Operational Amplifiers
1 Features
3 Description
•
•
•
•
•
•
•
•
The OPAx211 series of precision operational
amplifiers achieves very low 1.1-nV/√Hz noise density
with a supply current of only 3.6 mA. This series also
offers rail-to-rail output swing, which maximizes
dynamic range.
1
•
•
•
•
•
•
Low voltage noise: 1.1 nV/√Hz at 1 kHz
Input voltage noise: 80 nVPP (0.1 to 10 Hz)
THD + N: –136 dB (G = 1, ƒ = 1 kHz)
Offset voltage: 125 μV (maximum)
Offset voltage drift: 0.35 μV/°C (typical)
Low supply current: 3.6 mA/Ch (typical)
Unity-gain stable
Gain bandwidth product:
– 80 MHz (G = 100)
– 45 MHz (G = 1)
Slew rate: 27 V/μs
16-Bit settling: 700 ns
Wide supply range:
– ±2.25 to ±18 V, 4.5 V to 36 V
Rail-to-rail output
Output current: 30 mA
SON-8 (3 mm × 3 mm), VSSOP-8, and SOIC-8
The extremely low voltage and low current noise,
high-speed, and wide output swing of the OPAx211
series make these devices an excellent choice as a
loop filter amplifier in PLL applications.
In precision data acquisition applications, the
OPAx211 series of operational amplifiers provides
700-ns settling time to 16-bit accuracy throughout 10V output swings. This ac performance, combined with
only 125 μV of offset and 0.35 μV/°C of drift over
temperature, makes the OPAx211 series a great
choice for driving high-precision 16-bit analog-todigital converters (ADCs) or buffering the output of
high-resolution digital-to-analog converters (DACs).
The OPAx211 series is specified over a wide dualpower supply range of ±2.25 to ±18 V, or for singlesupply operation from 4.5 to 36 V.
2 Applications
•
•
•
•
•
•
•
•
•
•
•
The OPA211 is available in the small SON-8 (3 mm ×
3 mm), VSSOP-8, and SOIC-8 packages. The dual
version OPA2211 is available in a SON-8 (3 mm × 3
mm) or an SO-8 PowerPAD™ package. This series
of operational amplifiers is specified from TA = –40°C
to +125°C.
Ultrasound scanner
Semiconductor test
X-ray systems
Lab and field instrumentation
Data acquisition (DAQ)
Radar
Wireless communications test
Seismic data acquisition
DC power supply, ac source, electronic load
Power analyzer
Source measurement unit (SMU)
Device Information(1)
PART NUMBER
OPA211
OPA2211
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.90 mm
SON (8)
3.00 mm × 3.00 mm
VSSOP (8)
3.00 mm × 3.00 mm
SON (8)
3.00 mm × 3.00 mm
SO PowerPAD (8)
4.90 mm × 3.90 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Input Voltage Noise Density vs Frequency
Voltage Noise Density (nV/ √ Hz)
100
10
1
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA211, OPA2211
SBOS377L – OCTOBER 2006 – REVISED JANUARY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
6
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information: OPA211 and OPA211A .......... 7
Thermal Information: OPA2211 and OPA2211A ...... 7
Electrical Characteristics: Standard Grade
OPAx211A ................................................................. 8
6.7 Electrical Characteristics: High-Grade OPAx211.... 10
6.8 Typical Characteristics ............................................ 12
7
Detailed Description ............................................ 19
7.1 Overview ................................................................. 19
7.2 Functional Block Diagram ....................................... 19
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 21
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application ................................................. 27
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
31
31
31
31
31
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (September 2018) to Revision L
Page
•
Deleted NOM value from supply voltage in the Recommended Operating Conditions table ................................................ 6
•
Changed operating temperature to specified temperature in Recommended Operating Conditons table, and
changed MIN and MAX from –55°C and +150°C to –40°C and +125°C, respectively .......................................................... 6
•
Changed electrical characteristics table titles to clarify difference between standard and high-grade devices..................... 8
Changes from Revision J (February 2018) to Revision K
Page
•
Changed format of GPN from "OPA2x11" to "OPAx211" ...................................................................................................... 1
•
Corrected system-generated errors: "Time" units from "ms/div" back to "µs/div" and unit for resistors from "W" back
to "Ω" in Typical Characteristics .......................................................................................................................................... 12
•
Corrected system-generated error in unit for resistors from "W" back to "Ω" in Figure 43 ................................................. 21
•
Reverted Figure 51 back to that of rev. I ............................................................................................................................. 29
Changes from Revision I (June 2016) to Revision J
Page
•
Changed product status from mixed product status to production data ................................................................................ 1
•
Deleted Device Comparison table ......................................................................................................................................... 4
•
Changed formatting of document reference in EMI Rejection section ................................................................................. 24
•
Changed formatting of document references in SON Layout Guidelines section ................................................................ 29
•
Changed formatting of document references in Related Documentation section ................................................................ 30
Changes from Revision H (November 2015) to Revision I
Page
•
Changed the SON pin number for V+ from 4 to 7 in the Pin Functions: OPA211 table ....................................................... 4
•
Changed the SON pin number for V- From: 7 To: 4 in the Pin Functions: OPA211 table .................................................... 4
2
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SBOS377L – OCTOBER 2006 – REVISED JANUARY 2020
Changes from Revision G (May 2009) to Revision H
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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OPA211, OPA2211
SBOS377L – OCTOBER 2006 – REVISED JANUARY 2020
www.ti.com
5 Pin Configuration and Functions
OPA211 D Package
8-Pin SOIC
Top View
OPA211 DGK Package
8-Pin VSSOP
Top View
NC
1
8
NC
NC
1
8
Shutdown
–IN
2
7
V+
–IN
2
7
V+
+IN
3
6
OUT
+IN
3
6
OUT
V–
4
5
NC
V–
4
5
NC
OPA211 DRG Package
8-Pin SON With Exposed Thermal Pad
Top View
NC 1
8 Shutdown
–IN 2
7 V+
+IN 3
6 OUT
V– 4
5 NC
Pin Functions: OPA211
PIN
NAME
NO.
I/O
DESCRIPTION
+IN
3
I
Noninverting input
–IN
2
I
Inverting input
NC
1, 5
—
No internal connection. This pin can be left floating or connected to any voltage between
(V–) and (V+).
6
O
Output
OUT
Shutdown, active high
The shutdown function is as follows:
Shutdown
8
I
V+
7
I
Positive power supply
V–
4
I
Negative power supply
Thermal pad
—
—
Device enabled: (V–) ≤ VSHUTDOWN ≤ (V+) – 3 V
Device disabled: VSHUTDOWN ≥ (V+) – 0.35 V
4
Exposed thermal die pad on underside; connect thermal die pad to V–. Soldering the
thermal pad to the printed circuit board is required and improves heat dissipation and
provides specified performance.
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SBOS377L – OCTOBER 2006 – REVISED JANUARY 2020
OPA2211 DRG Package
8-Pin SON With Exposed Thermal Pad
Top View
8 V+
OUT A 1
–IN A 2
OPA2211 DDA Package
8-Pin SO PowerPAD With Exposed Thermal Pad
Top View
A
+IN A 3
OUT A
1
7 OUT B
–IN A
2
6 –IN B
+IN A
3
5 +IN B
V–
4
A
B
8
V+
7
OUT B
6
–IN B
5
+IN B
B
V– 4
Pin Functions: OPA2211
PIN
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Noninverting input channel A
–IN A
2
I
Inverting input channel A
+IN B
5
I
Noninverting input channel B
–IN B
6
I
Inverting input channel B
OUT A
1
O
Output channel A
OUT B
7
O
Output channel B
V+
8
I
Positive power supply
V–
4
I
Negative power supply
Thermal pad
—
—
Exposed thermal die pad on underside; connect thermal die pad to V–. Soldering the thermal
pad improves heat dissipation and provides specified performance.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
MIN
VS
MAX
Supply voltage, VS = (V+) – (V–)
Input voltage
(V–) – 0.5
Output short-circuit (2)
Operating temperature
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
V
(V+) + 0.5
Input current (any pin except power-supply pins)
TA
UNIT
40
V
±10
mA
150
°C
200
°C
150
°C
Continuous
–55
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to VS / 2 (ground in symmetrical dual-supply setups), one amplifier per package.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
VALUE
UNIT
3000
V
1000
V
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Supply voltage, VS = (V+) – (V–)
TA
Specified temperature
6
NOM
4.5 (±2.25)
–40
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25
MAX
UNIT
36 (±18)
V
125
°C
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SBOS377L – OCTOBER 2006 – REVISED JANUARY 2020
6.4 Thermal Information: OPA211 and OPA211A
OPA211, OPA211A
THERMAL METRIC
(1)
D (SOIC)
DRG (SON)
DGK
(VSSOP)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance, high-K board
122.2
125
184.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
62.5
N/A
71.2
°C/W
RθJB
Junction-to-board thermal resistance
64.3
28.8
104.9
°C/W
ψJT
Junction-to-top characterization parameter
14.2
3
11.5
°C/W
ψJB
Junction-to-board characterization parameter
63.6
25
103.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
19.1
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2211 and OPA2211A
OPA2211, OPA2211A
THERMAL METRIC
(1)
DDA
(SO-PowerPAD)
DRG (SON)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance, high-K board
50.4
125
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
N/A
N/A
°C/W
RθJB
Junction-to-board thermal resistance
13
28.8
°C/W
ψJT
Junction-to-top characterization parameter
5.2
3
°C/W
ψJB
Junction-to-board characterization parameter
11.7
25
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.1
19.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Electrical Characteristics: Standard Grade OPAx211A
at TA = 25°C, VS = ±2.25 to ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
OPA211A
±30
±125
OPA2211A
±50
±150
±0.35
±1.5
0.1
1
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VS = ±15 V
dVOS/dT
Input offset drift
VS = ±15 V,
TA = –40°C to +125°C
PSRR
Input offset voltage vs power
supply
TA = 25°C
TA = –40°C to +125°C
3
μV
μV/°C
μV/V
INPUT BIAS CURRENT
VCM = 0 V
IB
Input bias current
VCM = 0 V,
TA = –40°C to +125°C
±60
±200
OPA2211A
±250
VCM = 0 V
IOS
Input offset current
VCM = 0 V,
TA = –40°C to +125°C
Input voltage noise
ƒ = 0.1 to 10 Hz
±175
OPA211A
±25
nA
±100
±150
nA
NOISE
en
80
ƒ = 10 Hz
Input voltage noise density
In
Input current noise density
nVPP
2
ƒ = 100 Hz
1.4
ƒ = 1 kHz
1.1
ƒ = 10 Hz
3.2
ƒ = 1 kHz
1.7
nV/√Hz
pA/√Hz
INPUT VOLTAGE
VCM
CMRR
Common-mode voltage range
Common-mode rejection ratio
VS ≥ ±5 V
(V–) + 1.8
(V+) – 1.4
VS < ±5 V
(V–) + 2
(V+) – 1.4
VS ≥ ±5 V,
(V–) + 2 V ≤ VCM ≤ (V+) – 2 V,
TA = –40°C to +125°C
114
VS < ±5 V,
(V–) + 2 V ≤ VCM ≤ (V+) – 2 V,
TA = –40°C to +125°C
110
V
120
dB
120
INPUT IMPEDANCE
Differential
20 || 8
kΩ || pF
Common-mode
10 || 2
GΩ || pF
OPEN-LOOP GAIN
AOL
8
Open-loop voltage gain
(V–) + 0.2 V ≤ VO ≤ (V+) – 0.2 V,
RL = 10 kΩ,
TA = –40°C to +125°C
114
130
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V,
RL = 600 Ω
110
114
OPA211A:
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V,
IO ≤ 15 mA,
TA = –40°C to +125°C
110
OPA211A:
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V,
15 mA < IO ≤ 30 mA,
TA = –40°C to +125°C
103
OPA2211A:
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V,
IO ≤ 15 mA,
TA = –40°C to +125°C
100
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Electrical Characteristics: Standard Grade OPAx211A (continued)
at TA = 25°C, VS = ±2.25 to ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
THD+N
G = 100
80
G=1
45
MHz
27
Settling time
VS = ±15 V,
G = –1,
10-V step,
CL = 100 pF
Overload recovery time
G = –10
Total harmonic distortion + noise
G = 1,
ƒ = 1 kHz,
VO = 3 VRMS,
RL = 600 Ω
0.01%
400
0.0015%
(16-bit)
700
V/μs
ns
500
ns
0.000015%
–136
dB
OUTPUT
VOUT
Voltage output
ISC
Short-circuit current
CLOAD
Capacitive load drive
ZO
Open-loop output impedance
RL = 10 kΩ,
AOL ≥ 114 dB,
TA = –40°C to +125°C
(V–) + 0.2
(V+) – 0.2
RL = 600 Ω,
AOL ≥ 110 dB
(V–) + 0.6
(V+) – 0.6
IO < 15 mA,
AOL ≥ 110 dB,
TA = –40°C to +125°C
(V–) + 0.6
(V+) – 0.6
+30/–45
mA
See Typical Characteristics
ƒ = 1 MHz
V
pF
5
Ω
SHUTDOWN
VShutdown
Shutdown pin input voltage (1)
Device disabled (shutdown)
(V+) – 0.35
Device enabled
Shutdown pin leakage current
(V+) – 3
1
V
μA
(2)
2
μs
Turn-off time (2)
3
µs
Turn-on time
Shutdown current
Shutdown (disabled)
1
20
3.6
4.5
µA
POWER SUPPLY
IOUT = 0 A
IQ
(1)
(2)
Quiescent current (per channel)
IOUT = 0 A,
TA = –40°C to +125°C
6
mA
When disabled, the output assumes a high-impedance state.
See Typical Characteristics curves (Figure 39 through Figure 41).
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6.7 Electrical Characteristics: High-Grade OPAx211
at TA = 25°C, VS = ±2.25 to ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±20
±50
μV
±0.15
±0.85
0.1
0.5
OFFSET VOLTAGE
VOS
Input offset voltage
VS = ±15 V
dVOS/dT
Input offset drift
VS = ±15 V,
TA = –40°C to +125°C
PSRR
Input offset voltage vs power
supply
TA = 25°C
TA = –40°C to +125°C
3
μV/°C
μV/V
INPUT BIAS CURRENT
VCM = 0 V
IB
Input bias current
IOS
Input offset current
±50
VCM = 0 V,
TA = –40°C to +125°C
±125
±200
VCM = 0 V
±20
TA = –40°C to +125°C
±75
±150
nA
nA
NOISE
en
Input voltage noise
ƒ = 0.1 to 10 Hz
80
ƒ = 10 Hz
Input voltage noise density
In
Input current noise density
nVPP
2
ƒ = 100 Hz
1.4
ƒ = 1 kHz
1.1
ƒ = 10 Hz
3.2
ƒ = 1 kHz
1.7
nV/√Hz
pA/√Hz
INPUT VOLTAGE
VCM
CMRR
Common-mode voltage range
Common-mode rejection ratio
VS ≥ ±5 V
(V–) + 1.8
(V+) – 1.4
VS < ±5 V
(V–) + 2
(V+) – 1.4
VS ≥ ±5 V,
(V–) + 2 V ≤ VCM ≤ (V+) – 2 V,
TA = –40°C to +125°C
114
VS < ±5 V,
(V–) + 2 V ≤ VCM ≤ (V+) – 2 V,
TA = –40°C to +125°C
110
V
120
dB
120
INPUT IMPEDANCE
Differential
20 || 8
kΩ || pF
Common-mode
10 || 2
GΩ || pF
OPEN-LOOP GAIN
AOL
10
Open-loop voltage gain
(V–) + 0.2 V ≤ VO ≤ (V+) – 0.2 V,
RL = 10 kΩ,
TA = –40°C to +125°C,
114
130
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V,
RL = 600 Ω
110
114
OPA211:
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V,
IO ≤ 15 mA,
TA = –40°C to +125°C
110
OPA211:
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V,
15 mA < IO ≤ 30 mA,
TA = –40°C to +125°C
103
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Electrical Characteristics: High-Grade OPAx211 (continued)
at TA = 25°C, VS = ±2.25 to ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
THD+N
G = 100
80
G=1
45
Settling time
VS = ±15 V,
G = –1,
10-V step,
CL = 100 pF
Overload recovery time
G = –10
Total harmonic distortion + noise
G = 1,
ƒ = 1 kHz,
VO = 3 VRMS,
RL = 600 Ω
MHz
27
V/μs
0.01%
400
ns
0.0015%
(16-bit)
700
ns
500
ns
0.000015%
–136
dB
OUTPUT
VOUT
Voltage output
ISC
Short-circuit current
CLOAD
Capacitive load drive
ZO
Open-loop output impedance
RL = 10 kΩ,
AOL ≥ 114 dB,
TA = –40°C to +125°C
(V–) + 0.2
(V+) – 0.2
RL = 600 Ω,
AOL ≥ 110 dB
(V–) + 0.6
(V+) – 0.6
IO < 15 mA,
AOL ≥ 110 dB,
TA = –40°C to +125°C
(V–) + 0.6
(V+) – 0.6
+30 /–45
mA
See Typical Characteristics
ƒ = 1 MHz
V
pF
5
Ω
SHUTDOWN
VShutdown
Shutdown pin input voltage (1)
Device disabled (shutdown)
(V+) – 0.35
Device enabled
Shutdown pin leakage current
(V+) – 3
V
1
μA
(2)
2
μs
Turn-off time (2)
3
Turn-on time
Shutdown current
Shutdown (disabled)
μs
1
20
3.6
4.5
μA
POWER SUPPLY
IQ
(1)
(2)
Quiescent current
(per channel)
IOUT = 0 A
IOUT = 0 A,
TA = –40°C to +125°C
6
mA
When disabled, the output assumes a high-impedance state.
See Typical Characteristics curves (Figure 39 through Figure 41).
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6.8 Typical Characteristics
at TA = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
100
Current Noise Density (pA/ÖHz)
Voltage Noise Density (nV/ÖHz)
100
10
10
1
1
0.1
1
10
100
1k
10k
0.1
100k
1
10
G = 11
VOUT = 3 VRMS
-120
0.0001
G=1
VOUT = 3 VRMS
-140
0.00001
100
1k
10k 20k
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
RL = 600 Ω
10
10k
100k
0.1
-60
0.01
-80
G = 11
0.001
-100
0.0001
-120
G=1
0.00001
VS = ±15 V
-140
RL = 600 Ω
1 kHz Signal
0.000001
0.01
G = -1
0.1
1
Total Harmonic Distortion + Noise (dB)
VS = ±15 V
Total Harmonic Distortion + Noise (dB)
-100
G = -1
VOUT = 3 VRMS
1k
Figure 2. Input Current Noise Density vs Frequency
Figure 1. Input Voltage Noise Density vs Frequency
0.001
100
Frequency (Hz)
Frequency (Hz)
-160
100
10
Output Voltage Amplitude (VRMS)
Frequency (Hz)
Figure 3. THD + N Ratio vs Frequency
Figure 4. THD + N Ratio vs Output Voltage Amplitude
160
140
20nV/div
PSRR (dB)
120
100
-PSRR
80
+PSRR
60
40
20
0
1
10
Time (1s/div)
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 5. 0.1- to 10-Hz Noise
12
100
Figure 6. Power-Supply Rejection Ratio vs Frequency
(Referred to Input)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
140
10k
120
1k
80
ZO (W)
CMRR (dB)
100
60
100
10
40
1
20
0
0.1
10k
100k
10M
1M
100M
10
100
1k
Frequency (Hz)
Figure 7. Common-Mode Rejection Ratio vs Frequency
140
5
1M
10M
100M
RL = 10 kΩ
4
135
Phase
90
60
40
Phase (°)
80
Gain
45
20
0
Open-Loop Gain (mV/V)
120
Gain (dB)
100k
Figure 8. Open-Loop Output Impedance vs Frequency
180
100
10k
Frequency (Hz)
3
2
300 mV Swing From Rails
1
0
-1
200 mV Swing From Rails
-2
-3
-4
-20
100
1k
10k
100k
1M
-5
0
100M
10M
-75 -50 -25
0
25
50
75 100 125 150 175 200
Temperature (°C)
Frequency (Hz)
Figure 10. Open-Loop Gain vs Temperature
112.5
125.0
87.5
100.0
62.5
75.0
37.5
50.0
25.0
0
12.5
-12.5
-37.5
-25.0
-62.5
-50.0
-87.5
-75.0
-112.5
-100.0
-125.0
Population
Population
Figure 9. Gain and Phase vs Frequency
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
Offset Voltage Drift (mV/°C)
Offset Voltage (mV)
Figure 11. Offset Voltage Production Distribution
Figure 12. Offset Voltage Drift Production Distribution
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Typical Characteristics (continued)
200
2000
150
1500
100
1000
+IB
50
IOS
500
VOS (mV)
IB and IOS Bias Current (nA)
at TA = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
0
-50
0
-500
-IB
-100
-1000
-150
-1500
-200
-2000
-50
-25
0
25
50
75
100
125
150
(V-)+1.0 (V-)+1.5 (V-)+2.0
(V+)-1.5 (V+)-1.0 (V+)-0.5
VCM (V)
Ambient Temperature (°C)
Figure 13. IB and IOS Current vs Temperature
12
10
Figure 14. Offset Voltage vs Common-Mode Voltage
100
20 Typical Units Shown
60
6
4
40
2
IOS (nA)
VOS Shift (mV)
5 Typical Units Shown
80
8
0
-2
-4
-6
20
0
-20
-40
-60
-8
-80
-10
-100
2.25
-12
0
10
20
30
40
50
60
4
6
8
10
Time (s)
14
16
18
Figure 16. Input Offset Current vs Supply Voltage
Figure 15. VOS Warm-Up
150
100
VS = 36 V
3 Typical Units Shown
75
3 Typical Units Shown
100
Unit 1
50
Unit 2
50
25
IB (nA)
IOS (nA)
12
VS (±V)
0
0
Unit 3
-25
-50
Common-Mode Range
-50
-100
-75
-IB
+IB
-100
1
5
10
15
20
25
30
35
-150
2.25
4
VCM (V)
8
10
12
14
16
18
VS (±V)
Figure 17. Input Offset Current vs Common-Mode Voltage
14
6
Figure 18. Input Bias Current vs Supply Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
6
150
50
+IB
5
4
Unit 2
Unit 1
IQ (mA)
100
IB (nA)
-IB
VS = 36 V
3 Typical Units Shown
0
3
2
-50
Unit 3
-100
1
Common-Mode Range
0
-150
1
5
10
15
20
25
30
-75 -50 -25
35
25
0
50
75 100 125 150 175 200
Temperature (°C)
VCM (V)
Figure 20. Quiescent Current vs Temperature
Figure 19. Input Bias Current vs Common-Mode Voltage
4.0
0.05
3.5
0
3.0
IQ Shift (mA)
-0.05
IQ (mA)
2.5
2.0
1.5
-0.10
-0.15
1.0
-0.20
0.5
-0.25
0
-0.30
Average of 10 Typical Units
0
4
8
12
16
20
24
28
32
0
36
60
120 180 240 300 360 420 480 540
Figure 22. Normalized Quiescent Current vs Time
G = -1
RL = 600 Ω
CL = 10 pF
Sourcing
CF
5.6 pF
20 mV/div
ISC (mA)
Figure 21. Quiescent Current vs Supply Voltage
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
600
Time (s)
VS (V)
RI
604 Ω
RF
604 Ω
+18 V
OPA211
Sinking
CL
RL
-18 V
-60
-75 -50 -25
0
25
50
75
100 125 150 175 200
Temperature (°C)
Time (0.1 µs/div)
Figure 23. Short-Circuit Current vs Temperature
Figure 24. Small-Signal Step Response (100 mV)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
G = -1
G = +1
RL = 600 Ω
RL = 600 Ω
CL = 100 pF
CL = 10 pF
20 mV/div
20 mV/div
CF
5.6 pF
RF
604 Ω
RI
604 Ω
+18 V
+18 V
OPA211
OPA211
-18 V
RL
CL
RL
CL
-18 V
Time (0.1 µs/div)
Time (0.1 µs/div)
(100 mV)
(100 mV)
Figure 25. Small-Signal Step Response
Figure 26. Small-Signal Step Response
60
G = +1
G = +1
RL = 600 Ω
50
Overshoot (%)
20 mV/div
CL = 100 pF
+18 V
OPA211
-18 V
RL
40
G = -1
30
G = 10
20
CL
10
0
Time (0.1 µs/div)
0
200
(100 mV)
400
600
800
1000
1200
1400
Capacitive Load (pF)
(100-mV output step)
Figure 27. Small-Signal Step Response
Figure 28. Small-Signal Overshoot vs Capacitive Load
G = +1
G = -1
CL = 100 pF
CL = 100 pF
RF = 0 Ω
RL = 600 Ω
RF = 100 Ω
2 V/div
2 V/div
RL = 600 Ω
Note: See the
Applications Information
section, Input Protection.
Time (0.5 µs/div)
Time (0.5 µs/div)
Figure 29. Large-Signal Step Response
16
Figure 30. Large-Signal Step Response
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Typical Characteristics (continued)
1.0
0.010
1.0
0.010
0.8
0.008
0.8
0.008
0.6
0.006
0.6
0.006
0.4
0.004
16-Bit Settling
0.2
0.002
0
0
-0.002
-0.2
(±1/2 LSB = ±0.00075%)
-0.4
-0.004
D From Final Value (mV)
D From Final Value (mV)
at TA = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
0.4
0
-0.006
-0.008
-0.8
-1.0
-0.010
700 800 900 1000
-1.0
10 VPP
0
CL = 100 pF
100
200 300
400 500 600
Time (ns)
10 VPP
Figure 31. Large-Signal Positive Settling Time
-0.010
700 800 900 1000
CL = 10 pF
Figure 32. Large-Signal Positive Settling Time
1.0
0.010
1.0
0.010
0.8
0.008
0.8
0.008
0.6
0.006
0.6
0.006
0.4
0.004
16-Bit Settling
0.2
0.002
0
0
-0.2
(±1/2 LSB = ±0.00075%)
-0.4
-0.002
-0.004
-0.6
-0.006
-0.8
-1.0
0
100
200 300
10 VPP
400 500 600
Time (ns)
D From Final Value (mV)
D From Final Value (mV)
-0.002
-0.004
-0.008
400 500 600
Time (ns)
(±1/2 LSB = ±0.00075%)
-0.6
-0.8
200 300
0.002
-0.4
-0.006
100
0.004
0
-0.2
-0.6
0
16-Bit Settling
0.2
0.4
16-Bit Settling
0.2
0
0.004
0.002
0
-0.2
(±1/2 LSB = ±0.00075%)
-0.4
-0.002
-0.004
-0.6
-0.006
-0.008
-0.8
-0.008
-0.010
700 800 900 1000
-1.0
0
CL = 100 pF
100
200 300
400 500 600
Time (ns)
10 VPP
Figure 33. Large-Signal Negative Settling Time
-0.010
700 800 900 1000
CL = 10 pF
Figure 34. Large-Signal Negative Settling Time
G = -10
VIN
G = -10
10 kΩ
VOUT
1 kΩ
0V
OPA211
OPA211
VIN
5 V/div
5 V/div
10 kΩ
1 kΩ
VOUT
VIN
VOUT
0V
VOUT
VIN
Time (0.5 µs/div)
Time (0.5 µs/div)
Figure 35. Negative Overload Recovery
Figure 36. Positive Overload Recovery
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
20
0 °C
15
5
5 V/div
VOUT (V)
Output
+85 °C
+125 °C
10
+125 °C
0
-55 °C
+150 °C
0 °C
-5
+18 V
-10
OPA211
Output
+85 °C
-15
37 VPP
(±18.5V)
-18 V
-20
0
10
20
30
40
IOUT (mA)
50
60
0.5 ms/div
70
Figure 38. No Phase Reversal
Figure 37. Output Voltage vs Output Current
20
20
15
15
10
10
Shutdown Signal
Output Signal
5
5 V/div
5 V/div
5
0
-5
0
Output Signal
-5
-10
-10
Shutdown Signal
-15
-15
VS = ±15 V
-20
VS = ±15 V
-20
Time (2 µs/div)
Time (2 µs/div)
Figure 39. Turnoff Transient
Figure 40. Turnon Transient
20
1.6
15
1.2
10
0.8
5
0.4
0
-5
0
Output
-0.4
-10
-0.8
-15
Output Voltage (V)
Shutdown Pin Voltage (V)
Shutdown Signal
-1.2
VS = ±15 V
-20
-1.6
Time (100 µs/div)
Figure 41. Turnon and Turnoff Transient
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7 Detailed Description
7.1 Overview
The OPAx211 family of operational amplifiers are available in single-channel versions (OPA211) and dualchannel versions (OPA2211). Single-channel versions are available with and without shutdown. The OPAx211
family of operational amplifiers features ultra-low noise of 1.1-nV/√Hz, low total harmonic distortion + noise of
0.000015% and wide, rail-to-rail output swing. These unique features makes the OPAx211 family a great choice
for wide dynamic range applications and driving high-speed analog-to-digital converters. The OPAx211 family is
protected against excessive differentially applied input voltages and is fully characterized for electromagnetic
interference rejection ratio (EMIRR). The OPAx211 operates with as little as 4.5-V (±2.25-V) power supply
voltage and with power supply voltages up to 36 V (±18 V). The OPAx211 family is specified to operate from
–40°C to +125°C with little change in parametric behavior over the full temperature range.
7.2 Functional Block Diagram
V+
Pre-Output Driver
IN-
OUT
IN+
V-
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7.3 Feature Description
7.3.1 Total Harmonic Distortion Measurements
OPA211 series operational amplifiers have excellent distortion characteristics. THD + noise is below 0.0001% (G
= 1, VO = 3 VRMS) throughout the audio frequency range, 20 Hz to 20 kHz, with a 600-Ω load.
The distortion produced by OPAx211 series operational amplifiers is below the measurement limit of many
commercially available distortion analyzers. However, a special test circuit shown in Figure 43 can extend the
measurement capabilities.
Operational amplifier distortion can be considered an internal error source that can be referred to the input.
Figure 43 shows a circuit that causes the operational amplifier distortion to be 101 times greater than that
normally produced by the operational amplifier. The addition of R3 to the otherwise standard noninverting
amplifier configuration alters the feedback factor or noise gain of the circuit. The closed-loop gain is unchanged,
but the feedback available for error correction is reduced by a factor of 101, thus extending the resolution by 101.
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Feature Description (continued)
NOTE
The input signal and load applied to the operational amplifier are the same as with
conventional feedback without R3. The value of R3 should be kept small to minimize its
effect on the distortion measurements.
Validity of this technique can be verified by duplicating measurements at high gain and/or high frequency where
the distortion is within the measurement capability of the test equipment. Measurements for this data sheet were
made with an Audio Precision System Two distortion/noise analyzer, which greatly simplifies such repetitive
measurements. The measurement technique can, however, be performed with manual distortion measurement
instruments.
Noise in Noninverting Gain Configuration
Noise at the output:
R2
2
2
EO
R1
= 1+
R2
R1
2
2
2
2
2
2
en + e1 + e2 + (inR2) + eS + (inRS)
EO
R2
Where eS = Ö4kTRS ´ 1 +
R1
2
1+
R2
R1
= thermal noise of RS
RS
R2
e1 = Ö4kTR1 ´
R1
VS
= thermal noise of R1
e2 = Ö4kTR2 = thermal noise of R2
Noise in Inverting Gain Configuration
Noise at the output:
R2
2
2
EO = 1 +
R1
R2
R1 + RS
EO
RS
2
2
2
2
2
en + e1 + e2 + (inR2) + eS
Where eS = Ö4kTRS ´
R2
R1 + RS
= thermal noise of RS
VS
e1 = Ö4kTR1 ´
R2
R1 + RS
= thermal noise of R1
e2 = Ö4kTR2 = thermal noise of R2
For the OPA211 series op amps at 1kHz, en = 1.1nV/ÖHz and in = 1.7pA/ÖHz.
Figure 42. Noise Calculation in Gain Configurations
20
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Figure 43. Distortion Test Circuit
7.4 Device Functional Modes
The OPAx211 is operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum
power supply voltage for the OPAx211 series is 36 V (±18 V).
7.4.1 Shutdown
The shutdown (enable) function of the OPA211 is referenced to the positive supply voltage of the operational
amplifier. A valid high disables the operational amplifier. A valid high is defined as (V+) – 0.35 V of the positive
supply applied to the shutdown pin. A valid low is defined as (V+) – 3 V below the positive supply pin. For
example, with VCC at ±15 V, the device is enabled at or below 12 V. The device is disabled at or above 14.65 V.
If dual or split power supplies are used, make sure the valid high or valid low input signals are properly referred
to the positive supply voltage. This pin must be connected to a valid high or low voltage or driven, and not left
open-circuit. The enable and disable times are provided in the Typical Characteristics section (see Figure 39
through Figure 41). When disabled, the output assumes a high-impedance state.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA211 and OPA2211 are unity-gain stable, precision operational amplifiers with very-low noise.
Applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins.
In most cases, 0.1-μF capacitors are adequate.
8.1.1 Operating Voltage
OPA211 series operational amplifiers operate from ±2.25- to ±18-V supplies while maintaining excellent
performance. The OPA211 series can operate with as little as 4.5 V between the supplies and with up to 36 V
between the supplies. However, some applications do not require equal positive and negative output voltage
swing. With the OPA211 series, power-supply voltages do not need to be equal. For example, the positive supply
could be set to 25 V with the negative supply at –5 V or vice-versa.
The common-mode voltage must be maintained within the specified range. In addition, key parameters are
assured over the specified temperature range, TA = –40°C to +125°C. Parameters that vary significantly with
operating voltage or temperature are shown in the Typical Characteristics.
8.1.2 Input Protection
The input terminals of the OPA211 are protected from excessive differential voltage with back-to-back diodes, as
shown in Figure 44. In most circuit applications, the input protection circuitry has no consequence. However, in
low-gain or G = 1 circuits, fast ramping input signals can forward bias these diodes because the output of the
amplifier cannot respond rapidly enough to the input ramp. This effect is shown in Figure 30 of the Typical
Characteristics. If the input signal is fast enough to create this forward bias condition, the input signal current
must be limited to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can
be used to limit the signal input current. This input series resistor degrades the low-noise performance of the
OPA211, and is discussed in the Noise Performance section of this data sheet. Figure 44 shows an example
implementing a current-limiting feedback resistor.
RF
-
OPA211
RI
Input
Output
+
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Figure 44. Pulsed Operation
22
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Application Information (continued)
8.1.3 Noise Performance
Figure 45 shows total circuit noise for varying source impedances with the operational amplifier in a unity-gain
configuration (no feedback resistor network, and therefore no additional noise contributions). Two different
operational amplifiers are shown with total circuit noise calculated. The OPAx211 has very low voltage noise,
making the family a viable option for low source impedances (less than 2 kΩ). A similar precision operational
amplifier, the OPA227, has somewhat higher voltage noise but lower current noise. It provides excellent noise
performance at moderate source impedance (10 to 100 kΩ). Above 100 kΩ, a FET-input operational amplifier
such as the OPA132 (very low current noise) may provide improved performance. The equation in Figure 45 is
shown for the calculation of the total circuit noise.
NOTE
en = voltage noise, In = current noise, RS = source impedance, k = Boltzmann’s constant =
1.38 × 10–23 J/K, and T is temperature in K.
Votlage Noise Spectral Density, EO
10k
EO
1k
RS
OPA227
OPA211
100
Resistor Noise
10
2
2
2
EO = en + (in RS) + 4kTRS
1
100
1k
10k
100k
1M
Source Resistance, RS (Ω)
Figure 45. Noise Performance of the OPA211 and OPA227 in Unity-Gain Buffer Configuration
8.1.4 Basic Noise Calculations
Design of low-noise operational amplifier circuits requires careful consideration of a variety of possible noise
contributors: noise from the signal source, noise generated in the operational amplifier, and noise from the
feedback network resistors. The total noise of the circuit is the root-sum-square combination of all noise
components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. This function is plotted in Figure 45. The source impedance is usually fixed; consequently, select the
operational amplifier and the feedback resistors to minimize the respective contributions to the total noise.
Figure 45 depicts total noise for varying source impedances with the operational amplifier in a unity-gain
configuration (no feedback resistor network, and therefore no additional noise contributions). The operational
amplifier itself contributes both a voltage noise component and a current noise component. The voltage noise is
commonly modeled as a time-varying component of the offset voltage. The current noise is modeled as the timevarying component of the input bias current and reacts with the source resistance to create a voltage component
of noise. Therefore, the lowest noise operational amplifier for a given application depends on the source
impedance. For low source impedance, current noise is negligible and voltage noise generally dominates. For
high source impedance, current noise may dominate.
Figure 42 shows both inverting and noninverting operational amplifier circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors also contribute noise. The current noise of the
operational amplifier reacts with the feedback resistors to create additional noise components. The feedback
resistor values can generally be chosen to make these noise sources negligible. The equations for total noise are
shown for both configurations.
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Application Information (continued)
8.1.5 EMI Rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many operational amplifiers is a change in the offset voltage as a
result of RF signal rectification. An operational amplifier that is more efficient at rejecting this change in offset as
a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in
many ways, but this section provides the EMIRR IN+, which specifically describes the EMIRR performance when
the RF signal is applied to the noninverting input pin of the operational amplifier. In general, only the noninverting
input is tested for EMIRR for the following three reasons:
1. Operational amplifier input pins are known to be the most sensitive to EMI, and typically rectify RF signals
better than the supply or output pins.
2. The noninverting and inverting operational amplifier inputs have symmetrical physical layouts and exhibit
nearly matching EMIRR performance.
3. EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input terminal
can be isolated on a printed-circuit-board (PCB). This isolation allows the RF signal to be applied directly to
the noninverting input terminal with no complex interactions from other components or connecting PCB
traces.Figure 46
The EMIRR IN+ of the OPA211 is plotted versus frequency as shown in Figure 46. If available, any dual and
quad operational amplifier device versions have nearly similar EMIRR IN+ performance. The OPA211 unity-gain
bandwidth is 45 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the
operational amplifier bandwidth.
Detailed information can also be found in the EMI Rejection Ratio of Operational Amplifiers application report,
available for download from www.ti.com.
140
PRF = -10 dbm
120 VS = r12 V
VCM = 0 V
EMIRR IN+ (db)
100
80
60
40
20
0
10M
100M
1G
Frequency (Hz)
10G
Figure 46. OPA211 EMIRR
Table 1 shows the EMIRR IN+ values for the OPA211 at particular frequencies commonly encountered in realworld applications. Applications listed in Table 1 may be centered on or operated near the particular frequency
shown. This information may be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
24
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Application Information (continued)
Table 1. OPA211 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
48.4 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
34.6 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
56.9 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
61.5 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
76.7 dB
5 GHz
46 dB
8.1.6 EMIRR +IN Test Configuration
Figure 47shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the operational
amplifier noninverting input terminal using a transmission line. The operational amplifier is configured in a unitygain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter (DMM).
NOTE
A large impedance mismatch at the operational amplifier input causes a voltage reflection;
however, this effect is characterized and accounted for when determining the EMIRR IN+.
The resulting DC offset voltage is sampled and measured by the multimeter.
The LPF isolates the multimeter from residual RF signals that may interfere with multimeter accuracy.
Ambient temperature: 25Û&
+VS
±
50
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
Frequency Sweep: 201 pt. Log
-VS
Not shown: 0.1 µF and 10 µF
supply decoupling
Sample /
Averaging
Digital Multimeter
Figure 47. EMIRR +IN Test Configuration
8.1.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstress
event. Figure 48 shows the ESD circuits contained in the OPA211 (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where they meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
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An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from damage. The energy absorbed by
the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or
more of the steering diodes. Depending on the path that the current takes, the absorption device may activate.
The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the
OPA211 but below the device breakdown voltage level. Once this threshold is exceeded, the absorption device
quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit such as that shown in Figure 48, the ESD protection
components are intended to remain inactive and not become involved in the application circuit operation.
However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin.
Should this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on,
and conduct current. Any such current flow occurs through steering diode paths and rarely involves the
absorption device.
RF
+VS
+V
OPA211
RI
ESD CurrentSteering Diodes
-IN
+IN
Op-Amp
Core
Edge-Triggered ESD
Absorption Circuit
ID
VIN
OUT
RL
(1)
-V
-VS
Copyright © 2017, Texas Instruments Incorporated
(1) VIN = +VS + 500 mV.
Figure 48. Equivalent Internal ESD Circuitry and the Relation to a Typical Circuit Application
Figure 48 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the datasheet specifications recommend that applications
limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings. In extreme but rare cases, the absorption
device triggers on while +VS and –VS are applied. If this event happens, a direct current path is established
between the +VS and –VS supplies. The power dissipation of the absorption device is quickly exceeded, and the
extreme internal heating destroys the operational amplifier.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS and/or –VS are at 0 V. Again, it depends on the supply characteristic while at 0 V, or at a
level below the input signal amplitude. If the supplies appear as high impedance, then the operational amplifier
supply current may be supplied by the input source through the current steering diodes. This state is not a
normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance, then
the current through the steering diodes can become quite high. The current level depends on the ability of the
input source to deliver current, and any resistance in the input path.
26
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8.2 Typical Application
R4
2.94 k
C5
1 nF
R1
590
R3
499
Input
C2
39 nF
±
Output
+
OPAx211
Copyright © 2017, Texas Instruments Incorporated
Figure 49. OPAx211 Simplified Schematic
8.2.1 Design Requirements
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPAx211 devices are designed to construct high-speed, high-precision active filters. Figure 49 shows a
second-order low-pass filter commonly encountered in signal processing applications.
Use the following parameters for this design example:
• Gain = 5 V/V (inverting gain)
• Low-pass cutoff frequency = 25 kHz
• Second-order Chebyshev filter response with 3-dB gain peaking in the passband
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 50 . Use Equation 1
to calculate the voltage transfer function.
1 R1R3C2C5
Output
s
2
Input
s
s C2 1 R1 1 R3 1 R4 1 R3R4C2C5
(1)
This circuit produces a signal inversion. For this circuit, the gain at DC and the low-pass cutoff frequency are
calculated by Equation 2:
R4
Gain
R1
fC
1
2S
1 R3R 4 C2C5
(2)
Software tools are readily available to simplify filter design.WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH Filter Designer allows the user to create optimized
filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web based tool from the WEBENCH Design Center, WEBENCH® Filter Designer allows the user
to design, optimize, and simulate complete multistage active filter solutions within minutes.
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Typical Application (continued)
8.2.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 50. OPAx211 2nd-Order 25-kHz, Chebyshev, Low-Pass Filter
9 Power Supply Recommendations
The OPAx211 are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational
amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pick-up. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information, see
Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 51, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
28
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Layout Guidelines (continued)
10.1.1 SON Layout Guidelines
The OPA211 is offered in an SON-8 package (also known as SON). The SON package is a QFN package with
lead contacts on only two sides of the bottom of the package. This leadless package maximizes board space and
enhances thermal and electrical characteristics through an exposed pad.
SON packages are physically small, and have a smaller routing area, improved thermal performance, and
improved electrical parasitics. Additionally, the absence of external leads eliminates bent-lead issues.
The SON package can be easily mounted using standard printed circuit board (PCB) assembly techniques. See
the QFN/SON PCB Attachment application note and the Quad Flatpack No-Lead Logic Packages application
report, both available for download at www.ti.com.
NOTE
The exposed leadframe die pad on the bottom of the package must be connected to V–.
Soldering the thermal pad improves heat dissipation and enables specified device
performance.
The exposed leadframe die pad on the SON package should be soldered to a thermal pad on the PCB. A
mechanical drawing showing an example layout is attached at the end of this data sheet. Refinements to this
layout may be necessary based on assembly process requirements. Mechanical drawings located at the end of
this data sheet list the physical dimensions for the package and pad. The five holes in the landing pattern are
optional, and are intended for use with thermal vias that connect the leadframe die pad to the heat sink area on
the PCB.
Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push,
package shear, and similar board-level tests. Even with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.
10.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Copyright © 2017, Texas Instruments Incorporated
Figure 51. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the WEBENCH® Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
The OPAx211 is featured in several TI Precision Designs, available online at
http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s
precision analog applications experts and offer the theory of operation, component selection, simulation,
complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.
11.1.1.3 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer the user to create optimized filter designs using a selection of TI operational amplifiers and
passive components from TI's vendor partners.
Available as a web based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows the
user to design, optimize, and simulate complete multistage active filter solutions within minutes.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see:
• Texas Instruments, Circuit Board Layout Techniques
• Texas Instruments, Op Amps for Everyone
• Texas Instruments, OPA211, OPA211A, OP2211, OPA2211A EMI Immunity Performance (Rev. A)
• Texas Instruments, Operational amplifier gain stability, Part 3: AC gain-error analysis
• Texas Instruments, Operational amplifier gain stability, Part 2: DC gain-error analysis
• Texas Instruments, Using infinite-gain, MFB filter topology in fully differential active filters
• Texas Instruments, Op Amp Performance Analysis
• Texas Instruments, Single-Supply Operation of Operational Amplifiers
• Texas Instruments, Tuning in Amplifiers
• Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes
30
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11.3 Related Links
Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA211
Click here
Click here
Click here
Click here
Click here
OPA2211
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates — go to the product folder for your device on ti.com. In the
upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information
that has changed (if any). For change details, check the revision history of any revised document.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
PowerPAD, TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA211AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
211
A
OPA211AIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
211
A
OPA211AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OBCQ
OPA211AIDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OBCQ
OPA211AIDGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
Call TI
Level-2-260C-1 YEAR
-40 to 125
OBCQ
OPA211AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
211
A
OPA211AIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
211
A
OPA211AIDRGR
ACTIVE
SON
DRG
8
3000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OBDQ
OPA211AIDRGT
ACTIVE
SON
DRG
8
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OBDQ
OPA211AIDRGTG4
ACTIVE
SON
DRG
8
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OBDQ
OPA211ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
211
OPA211IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OBCQ
OPA211IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OBCQ
OPA211IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
211
OPA211IDRGR
ACTIVE
SON
DRG
8
3000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OBDQ
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
6-Feb-2020
Status
(1)
OPA211IDRGT
ACTIVE
OPA2211AIDDA
Package Type Package Pins Package
Drawing
Qty
SON
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRG
8
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OBDQ
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OPA
2211
A
OPA2211AIDDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OPA
2211
A
OPA2211AIDRGR
ACTIVE
SON
DRG
8
3000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OBHQ
OPA2211AIDRGT
ACTIVE
SON
DRG
8
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OBHQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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