Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
OPA2313-Q1
SBOS823 – DECEMBER 2018
OPA2313-Q1 Low-Power, Rail-to-Rail In/Out, 500-µV Typical Offset,
1-MHz Operational Amplifier for Cost-Sensitive Systems
1 Features
3 Description
•
The OPA2313-Q1 dual-channel operational amplifier
combines low power consumption with good
performance. This enables it to be used in a wide
range of applications, such as infotainment, engine
control units, automotive lighting and more. The
OPA2313-Q1 features rail-to-rail input and output
(RRIO) swings, low quiescent current (50 µA, typical),
wide bandwidth (1 MHz) and very low noise (25
nV/√Hz at 1 kHz), making it attractive for a variety of
applications that require a good balance between
cost and performance. Furthermore, low input bias
current enables this device to be used in applications
with megaohm source impedances.
1
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified for Automotive Applications
– Device Temperature Grade 1:
–40°C to +125°C TA
Precision Amplifier for Cost-Sensitive Systems
Low IQ: 50 µA/ch
Wide Supply Range: 1.8 V to 5.5 V
Low Noise: 25 nV/√Hz at 1 kHz
Gain Bandwidth: 1 MHz
Rail-to-Rail Input/Output
Low Input Bias Current: 0.2 pA
Low Offset Voltage: 0.5 mV
Unity-Gain Stable
Internal RFI/EMI Filter
2 Applications
•
•
•
•
•
•
•
•
Infotainment
Engine Control Unit
Automotive Lighting
Low-Side Sensing
Battery Management Systems
Passive Safety
Capacitive Sensing
Fuel Pumps
The robust design of the OPA2313-Q1 provides
ease-of-use to the circuit designer: unity-gain stability
with capacitive loads of up to 150 pF, integrated
RFI/EMI rejection filter, no phase reversal in overdrive
conditions, and high electrostatic discharge (ESD)
protection (4-kV HBM).
The device is optimized for operation at voltages as
low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V), and
is specified over the extended temperature range of
–40°C to +125°C.
Device Information(1)
PART NUMBER
OPA2313-Q1
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
EMIRR IN+ vs Frequency
120
EMIRR IN+ (dB)
100
80
60
40
20
0
10
100
1000
Frequency (MHz)
10000
C033
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2313-Q1
SBOS823 – DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
7.4 Device Functional Modes........................................ 18
1
1
1
2
3
4
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 19
8.3 System Examples ................................................... 20
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 22
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: 5.5 V ................................ 5
Electrical Characteristics: 1.8 V ................................ 7
Typical Characteristics: Tables of Graphs ................ 9
Typical Characteristics ............................................ 10
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 17
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
2
DATE
REVISION
NOTES
December 2018
*
Initial release.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
OPA2313-Q1
www.ti.com
SBOS823 – DECEMBER 2018
5 Pin Configuration and Functions
OPA2313-Q1 D, DGK Packages
8-Pin SOIC, VSSOP
Top View
OUT1
1
8
V+
IN1±
2
7
OUT2
IN1+
3
6
IN2±
V±
4
5
IN2+
Not to scale
Pin Functions: OPA2313-Q1
PIN
NAME
NO.
I/O
DESCRIPTION
IN1–
2
I
Inverting input, channel 1
IN1+
3
I
Noninverting input, channel 1
IN2–
6
I
Inverting input, channel 2
IN2+
5
I
Noninverting input, channel 2
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
V–
4
—
Negative (lowest) supply or ground (for single-supply operation)
V+
8
—
Positive (highest) supply
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
3
OPA2313-Q1
SBOS823 – DECEMBER 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
0
7
Signal input terminals (2)
(V–) – (0.5)
(V+) + 0.5
Signal input terminals (2)
–10
10
Supply voltage (V+) – (V–)
Voltage
Current
Output short circuit (3)
–40
(2)
(3)
mA
150
Junction, TJ
150
Storage, Tstg
(1)
V
Continuous
Operating, TA
Temperature
UNIT
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
HBM ESD Classification Level 3A
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
CDM ESD Classification Level C6
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VS
Supply voltage (V+) – (V–)
1.8
5.5
UNIT
V
TA
Specified temperature
–40
125
°C
6.4 Thermal Information
OPA2313-Q1
THERMAL METRIC
(1)
D (SOIC)
DGK (VSSOP)
8 Pins
8 Pins
UNIT
191.2
°C/W
RθJA
Junction-to-ambient thermal resistance
138.4
RθJC(top)
Junction-to-case (top) thermal resistance
89.5
61.9
°C/W
RθJB
Junction-to-board thermal resistance
78.6
111.9
°C/W
ψJT
Junction-to-top characterization parameter
29.9
5.1
°C/W
ψJB
Junction-to-board characterization parameter
78.1
110.2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
OPA2313-Q1
www.ti.com
SBOS823 – DECEMBER 2018
6.5 Electrical Characteristics: 5.5 V (1)
For VS= (V+) – (V–) = 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, (unless otherwise
noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
2.5
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage vs temperature
PSRR
Power-supply rejection ratio
Channel separation, dc
TA = –40°C to 125°C
2
TA = –40°C to 125°C
74
At dc
mV
µV/°C
90
dB
10
µV/V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
No phase reversal, rail-to-rail input
(V–) – 0.2
(V+) + 0.2
(V–) – 0.2 V < VCM < (V+) – 1.3 V TA = –40°C to 125°C
70
85
VCM = –0.2 V to 5.7 V
64
80
TA = –40°C to 125°C
V
dB
INPUT BIAS CURRENT
±0.2
IB
Input bias current
±50
TA = –40°C to 125°C (2)
±600
±0.2
IOS
TA = –40°C to 85°C (2)
Input offset current
±10
TA = –40°C to 85°C (2)
TA = –40°C to 125°C
±10
±50
(2)
pA
pA
±600
NOISE
Input voltage noise (peak-to-peak)
en
Input voltage noise density
in
Input current noise density
f = 0.1 Hz to 10 Hz
6
f = 10 kHz
22
f = 1 kHz
25
f = 1 kHz
5
µVPP
nV/√Hz
fA/√Hz
INPUT CAPACITANCE
CIN
Differential
1
Common-mode
5
pF
OPEN-LOOP GAIN
0.05 V < VO < (V+) – 0.05 V, RL = 100 kΩ
AOL
Open-loop voltage gain
Phase margin
90
104
0.3 V < VO < (V+) – 0.3 V, RL = 2 kΩ
100
110
0.1 V < VO < (V+) – 0.1 V
104
116
TA = –40°C to 125°C
VS = 5 V, G = +1
dB
65
°
1
MHz
0.5
V/µs
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
VS = 5 V, CL = 10 pF
SR
Slew rate
VS = 5 V, G = +1
tS
Settling time
THD+N
To 0.1%, VS = 5 V, 2-V step, G = +1
5
To 0.01%, VS = 5 V, 2-V step, G = +1
6
Overload recovery time
VS = 5 V, VIN × Gain > VS
3
Total harmonic distortion + noise (3)
VS = 5 V, VO = 1 VRMS, G = +1, f = 1 kHz
µs
0.0045%
OUTPUT
RL = 100 kΩ (2)
VO
Voltage output swing from supply rails
RL = 100 kΩ (2)
RL = 2 kΩ (2)
RL = 2 kΩ (2)
ISC
Short-circuit current
RO
Open-loop output impedance
(1)
(2)
(3)
5
20
75
100
TA = –40°C to 125°C
30
TA = –40°C to 125°C
125
±15
TA = –40°C to 125°C
mV
±12
2300
mA
Ω
Parameters with minimum or maximum specification limits are 100% production tested at 25°C, unless otherwise noted. Overtemperature limits are based on characterization and statistical analysis.
Specified by design and characterization; not production tested.
Third-order filter; bandwidth = 80 kHz at –3 dB.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
5
OPA2313-Q1
SBOS823 – DECEMBER 2018
www.ti.com
Electrical Characteristics: 5.5 V(1) (continued)
For VS= (V+) – (V–) = 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, (unless otherwise
noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per amplifier
Power-on time
6
1.8 (±0.9)
VS = 5 V, IO = 0 mA
VS = 5 V, IO = 0 mA
5.5 (±2.75)
50
TA = –40°C to 125°C
VS = 0 V to 5 V, to 90% IQ level
Submit Documentation Feedback
60
85
10
V
µA
µs
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
OPA2313-Q1
www.ti.com
SBOS823 – DECEMBER 2018
6.6 Electrical Characteristics: 1.8 V (1)
For VS= (V+) – (V–) = 1.8 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS+ – 1.3 V, and VOUT = VS / 2, (unless
otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
2.5
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage vs temperature
PSRR
Power-supply rejection ratio
Channel separation, dc
TA = –40°C to 125°C
TA = –40°C to 125°C
2
74
At dc
mV
µV/°C
90
dB
10
µV/V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
No phase reversal, rail-to-rail input
(V–) – 0.2
(V+) + 0.2
(V–) – 0.2 V < VCM < (V+) – 1.3 V TA = –40°C to 125°C
70
85
VS= 1.8 V, VCM = –0.2 V to 1.8 V
58
73
58
70
VCM = –0.2 V to 1.6 V
TA = –40°C to 125°C
V
dB
INPUT BIAS CURRENT
±0.2
IB
Input bias current
±50
TA = –40°C to 125°C (2)
±600
±0.2
IOS
Input offset current
±10
TA = –40°C to 85°C (2)
TA = –40°C to 85°C
(2)
±10
±50
TA = –40°C to 125°C (2)
pA
pA
±600
NOISE
Input voltage noise (peak-to-peak)
en
Input voltage noise density
in
Input current noise density
f = 0.1 Hz to 10 Hz
6
f = 10 kHz
22
f = 1 kHz
25
f = 1 kHz
5
µVPP
nV/√Hz
fA/√Hz
INPUT CAPACITANCE
CIN
Differential
1
Common-mode
5
pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
0.05 V < VO < (V+) – 0.05 V, RL = 100 kΩ
0.1 V < VO < (V+) – 0.1 V
TA = –40°C to 125°C
100
110
90
110
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
CL = 10 pF
SR
Slew rate
G = +1
tS
Settling time
THD+N
0.9
MHz
0.45
V/µs
To 0.1%, VS = 5 V, 2-V step, G = +1
5
To 0.01%, VS = 5 V, 2-V step, G = +1
6
Overload recovery time
VS = 5 V, VIN × Gain > VS
3
Total harmonic distortion + noise (3)
VS = 5 V, VO = 1 VRMS, G = +1, f = 1kHz
µs
0.0045%
OUTPUT
RL = 100 kΩ (2)
VO
Voltage output swing from supply rails
RL = 100 kΩ (2)
RL = 2 kΩ (2)
RL = 2 kΩ (2)
ISC
Short-circuit current
RO
Open-loop output impedance
(1)
(2)
(3)
5
TA = –40°C to 125°C
15
30
25
TA = –40°C to 125°C
50
mV
125
±6
2300
mA
Ω
Parameters with minimum or maximum specification limits are 100% production tested at 25°C, unless otherwise noted. Overtemperature limits are based on characterization and statistical analysis.
Specified by design and characterization; not production tested.
Third-order filter; bandwidth = 80 kHz at –3 dB.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
7
OPA2313-Q1
SBOS823 – DECEMBER 2018
www.ti.com
Electrical Characteristics: 1.8 V(1) (continued)
For VS= (V+) – (V–) = 1.8 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS+ – 1.3 V, and VOUT = VS / 2, (unless
otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS
Specified voltage range
IQ
Quiescent current per amplifier
VS = 5 V, IO = 0 mA
50
Power-on time
VS = 0 V to 5 V, to 90% IQ level
10
8
1.8 (±0.9)
Submit Documentation Feedback
5.5 (±2.75)
V
60
µA
µs
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
OPA2313-Q1
www.ti.com
SBOS823 – DECEMBER 2018
6.7 Typical Characteristics: Tables of Graphs
Table 1. Characteristic Performance Measurements
TITLE
FIGURE
Open-Loop Gain and Phase vs Frequency
Figure 1
Open-Loop Gain vs Temperature
Figure 2
Quiescent Current vs Supply Voltage
Figure 3
Quiescent Current vs Temperature
Figure 4
Offset Voltage Production Distribution
Figure 5
Offset Voltage Drift Distribution
Figure 6
Offset Voltage vs Common-Mode Voltage (Maximum Supply)
Figure 7
Offset Voltage vs Temperature
Figure 8
CMRR and PSRR vs Frequency (RTI)
Figure 9
CMRR and PSRR vs Temperature
Figure 10
0.1-Hz to 10-Hz Input Voltage Noise (5.5 V)
Figure 11
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V)
Figure 12
Input Voltage Noise vs Common-Mode Voltage (5.5 V)
Figure 13
Input Bias and Offset Current vs Temperature
Figure 14
Open-Loop Output Impedance vs Frequency
Figure 15
Maximum Output Voltage vs Frequency and Supply Voltage
Figure 16
Output Voltage Swing vs Output Current (over Temperature)
Figure 17
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (1.8 V)
Figure 18
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (5.5 V)
Figure 19
Small-Signal Overshoot vs Load Capacitance
Figure 20
Phase Margin vs Capacitive Load
Figure 21
Small-Signal Step Response, Noninverting (1.8 V)
Figure 22
Small-Signal Step Response, Noninverting ( 5.5 V)
Figure 23
Large-Signal Step Response, Noninverting (1.8 V)
Figure 24
Large-Signal Step Response, Noninverting ( 5.5 V)
Figure 25
Positive Overload Recovery
Figure 26
Negative Overload Recovery
Figure 27
No Phase Reversal
Figure 28
Channel Separation vs Frequency (Dual)
Figure 29
THD+N vs Amplitude (G = +1, 2 kΩ, 10 kΩ)
Figure 30
THD+N vs Amplitude (G = –1, 2 kΩ, 10 kΩ)
Figure 31
THD+N vs Frequency (0.5 VRMS, G = +1, 2 kΩ, 10 kΩ)
Figure 32
EMIRR IN+ vs Frequency
Figure 33
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
9
OPA2313-Q1
SBOS823 – DECEMBER 2018
www.ti.com
6.8 Typical Characteristics
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
180
140
Gain
Phase
100 k , 5.5 V
135
100
135
CL=10pF
C
L = 10 pF
80
60
Phase (o)
Gain (dB)
140
90
40
20
45
C
L = 100 pF
CL=100pF
0
Open-Loop Gain (dB)
120
130
10 k , 5.5 V
125
120
2 k , 5.5 V
115
110
105
-20
1
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
0
100M
10 k , 1.8 V
100
-50
C001
Figure 1. Open-Loop Gain and Phase vs Frequency
-25
0
25
50
Temperature (oC)
75
100
125
C002
Figure 2. Open-Loop Gain vs Temperature
65
60
Quiescent Current (µA/ch)
Quiescent Current (µA/ch)
58
56
54
52
50
48
46
44
60
VS = 5.5 V
55
50
45
VS = 1.8 V
40
42
40
35
1.5
2
2.5
3
3.5
4
4.5
Supply Voltage (V)
5
5.5
-50
6
-25
0
C003
Figure 3. Quiescent Current vs Supply
25
50
Temperature (oC)
75
100
125
C004
Figure 4. Quiescent Current vs Temperature
25
9
Percent of Amplifiers (%)
Percent of Amplifiers (%)
8
7
6
5
4
3
2
20
15
10
5
3
2.75
2.5
2
2.25
1.75
1.5
1.25
1
0.75
0.5
Offset Voltage Drift (µV/oC)
C005
Figure 5. Offset Voltage Production Distribution
10
0
0.25
Offset Voltage (mV)
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0
-2.5
1
C006
Figure 6. Offset Voltage Drift Distribution
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
OPA2313-Q1
www.ti.com
SBOS823 – DECEMBER 2018
Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
1200
900
900
Offset Voltage (µV)
1500
1200
Offset Voltage (µV)
1500
600
300
0
-300
-600
600
300
0
-300
-600
-900
-900
-1200
-1200
-1500
-1500
0
0.5
1
1.5 2 2.5 3 3.5 4
Common-Mode Voltage (V)
4.5
5
5.5
-50
Figure 7. Offset Voltage vs Common-Mode Voltage
0
25
50
Temperature (oC)
75
100
125
C008
Figure 8. Offset Voltage vs Temperature
110
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
120
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
-25
C007
100
80
+PSRR
60
CMRR
40
20
-PSRR
105
PSRR
100
95
90
CMRR
85
80
75
70
65
60
0
10
100
1k
10k
Frequency (Hz)
100k
-50
1M
-25
0
C009
25
50
75
Temperature (oC)
100
125
C001
Figure 10. CMRR and PSRR vs Temperature
Figure 9. CMRR and PSRR vs Frequency
(Referred-to-Input)
1000
9ROWDJH 1RLVH Q9 ¥+]
Voltage Noise (1 µV/div)
VS = 1.8 V
100
10
VS = 5.5 V
1
Time (1 s/div)
1
C011
Figure 11. 0.1-Hz to 10-Hz Input Voltage Noise
10
100
1k
Frequency (Hz)
10k
100k
C012
Figure 12. Input Voltage Noise Spectral Density vs
Frequency
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
11
OPA2313-Q1
SBOS823 – DECEMBER 2018
www.ti.com
Typical Characteristics (continued)
40
200
35
150
Input Bias Current (pA)
9ROWDJH1RLVH'HQVLW\Q9¥+]
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
30
25
20
IBN
100
IBP
50
0
15
IOS
-50
10
-100
0
0.5
1
1.5 2 2.5 3 3.5 4 4.5
Common-Mode Input Voltage (V)
5
5.5
-50
-25
0
25
50
Temperature (oC)
C013
Figure 13. Voltage Noise vs Common-Mode Voltage
75
100
125
C014
Figure 14. Input Bias and Offset Current vs Temperature
6
100k
VS = 5.5 V
Output Voltage (V)
Output Impedance ( )
5
VS = 1.8 V
10k
4
VS = 1.8 V
3
2
1
VS = 5.5 V
0
1000
1000
1
10
100
1k
Frequency (Hz)
10k
100k
1M
C016
Figure 16. Maximum Output Voltage vs Frequency and
Supply Voltage
3
40
G = +10 V/V
2
20
oC
+125
+125oC
0
+25oC
+25 oC
Gain (dB)
1
-40 oC
-40oC
G = +1 V/V
0
-1
-2
G = -1 V/V
-20
-3
0
5
10
Output Current (mA)
15
20
10
C017
Figure 17. Output Voltage Swing vs Output Current (Over
Temperature)
12
100k
Frequency (Hz)
Figure 15. Open-Loop Output Impedance vs Frequency
Output Voltage Swing (V)
10k
C015
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
C018
Figure 18. Closed-Loop Gain vs Frequency (Minimum
Supply)
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
OPA2313-Q1
www.ti.com
SBOS823 – DECEMBER 2018
Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
50
40
45
VS = 1.8V, VCM = 0.5V
40
G = +10 V/V
Overshoot (%)
Gain (dB)
20
G = +1 V/V
0
35
30
25
VS = 5.5V
20
15
10
G = -1 V/V
5
0
±20
10
100
1k
10k
100k
1M
Frequency (Hz)
10M
0
100M
100
C000
Figure 19. Closed-Loop Gain vs Frequency
(Maximum Supply)
200
Capacitive Load (pF)
300
400
C002
Figure 20. Small-Signal Overshoot vs
Load Capacitance
90
CL = 100 pF
80
VIN
Voltage (25 mV/div)
Phase Margin (o)
70
60
50
VS = 5.5V
40
30
CL = 10 pF
20
VS = 1.8V, VCM = 0.5V
10
0
0
100
200
Capacitive Load (pF)
300
400
Time (1 µs/div)
C004
C003
Figure 22. Small-Signal Pulse Response
(Minimum Supply)
Figure 21. Phase Margin vs Capacitive Load
VIN
Voltage (250 mV/div)
Voltage (25 mV/div)
CL = 100 pF
CL = 10 pF
VOUT
VIN
Time (2.5 µs/div)
Time (1 µs/div)
C024
C023
Figure 23. Small-Signal Pulse Response
(Maximum Supply)
Figure 24. Large-Signal Pulse Response
(Minimum Supply)
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
13
OPA2313-Q1
SBOS823 – DECEMBER 2018
www.ti.com
Typical Characteristics (continued)
Voltage (500 mV/div)
Voltage (250 mV/div)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
VOUT
VIN
VOUT
VIN
Time (2.5 µs/div)
Time (2 µs/div)
C025
C026
Figure 26. Positive Overload Recovery
Voltage (1 V/div)
Voltage (500 mV/div)
Figure 25. Large-Signal Pulse Response
(Maximum Supply)
VIN
VOUT
VOUT
VIN
Time (125 µs/div)
Time (2 µs/div)
C028
C027
Figure 27. Negative Overload Recovery
Figure 28. No Phase Reversal
-60
0.1
-100
THD + N (%)
Crosstalk (dB)
-80
chB to chA
-120
chA to chB
0.01
RL = 2 k
0.001
-140
RL = 10 k
-160
100
1k
10k
100k
Frequency (Hz)
1M
0.0001
0.01
0.1
1
Output Amplitude (VRMS)
C029
Figure 29. Channel Separation vs Frequency
14
10M
10
C030
Figure 30. THD+N vs Output Amplitude
(Minimum Supply)
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
OPA2313-Q1
www.ti.com
SBOS823 – DECEMBER 2018
Typical Characteristics (continued)
At TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted.
0.1
0.1
0.01
0.01
THD + N (%)
THD + N (%)
RL = 2 k
RL = 2 k
0.001
0.001
RL = 10 k
R L = 10 k
0.0001
0.01
0.0001
0.1
1
Output Amplitude (VRMS)
10
10
100
1k
Frequency (Hz)
C031
10k
100k
C032
Figure 32. THD+N vs Frequency
Figure 31. THD+N vs Output Amplitude
(Maximum Supply)
120
EMIRR IN+ (dB)
100
80
60
40
20
0
10
100
1000
Frequency (MHz)
10000
C033
Figure 33. EMIRR IN+ vs Frequency
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
15
OPA2313-Q1
SBOS823 – DECEMBER 2018
www.ti.com
7 Detailed Description
7.1 Overview
The OPA2313-Q1 is a low-power, rail-to-rail input and output operational amplifier designed for cost-constrained
applications. This device operates from 1.8 V to 5.5 V, is unity-gain stable, and suitable for a wide range of
general-purpose applications. The class AB output stage is capable of driving loads greater than 10-kΩ
connected to any point between V+ and ground. The input common-mode voltage range includes both rails, and
allows the OPA2313-Q1 to be used in virtually any single-supply application. Rail-to-rail input and output swing
significantly increases dynamic range, especially in low-supply applications, and makes this device ideal for
driving sampling analog-to-digital converters (ADCs).
The OPA2313-Q1 features 1-MHz bandwidth and 0.5-V/µs slew rate with only 50-µA supply current per channel,
providing good ac performance at very low power consumption. Low frequency (dc) applications are also well
served with a low input noise voltage of 25 nV/√Hz at 1 kHz, low input bias current (0.2 pA), and an input offset
voltage of 0.5 mV (typical). The typical offset voltage drift is 2 µV/°C; over the full temperature range the input
offset voltage changes only 200 µV (0.5 mV to 0.7 mV).
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
16
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
OPA2313-Q1
www.ti.com
SBOS823 – DECEMBER 2018
7.3 Feature Description
7.3.1 Operating Voltage
The OPA2313-Q1 device is fully specified and tested from 1.8 V to 5.5 V (±0.9 V to ±2.75 V). Parameters that
vary with supply voltage are illustrated in the Typical Characteristics section.
7.3.2 Rail-to-Rail Input
The input common-mode voltage range of the OPA2313-Q1 device extends 200 mV beyond the supply rails.
This performance is achieved with a complementary input stage: an N-channel input differential pair in parallel
with a P-channel differential pair, as shown in the Functional Block Diagram section. The N-channel pair is active
for input voltages close to the positive rail, typically (V+) – 1.3 V to 200 mV above the positive supply, while the
P-channel pair is on for inputs from 200 mV below the negative supply to approximately (V+) – 1.3 V. There is a
small transition region, typically (V+) – 1.4 V to (V+) – 1.2 V, in which both pairs are on. This 200-mV transition
region may vary up to 300 mV with process variation. Thus, the transition region (both stages on) may range
from (V+) – 1.7 V to (V+) – 1.5 V on the low end, up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this
transition region, PSRR, CMRR, offset voltage, offset drift, and THD may be degraded compared to device
operation outside this region.
7.3.3 Rail-to-Rail Output
Designed as a micro-power, low-noise operational amplifier, the OPA2313-Q1 delivers a robust output drive
capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing
capability. For resistive loads up to 10 kΩ, the output swings typically to within 5 mV of either supply rail
regardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier to
swing close to the rails, as shown in Figure 17.
7.3.4 Common-Mode Rejection Ratio (CMRR)
CMRR for the OPA2313-Q1 device is specified in several ways so the best match for a given application may be
used; see the Electrical Characteristics. First, the CMRR of the device in the common-mode range below the
transition region (VCM < (V+) – 1.3 V) is given. This specification is the best indicator of the capability of the
device when the application requires use of one of the differential input pairs. Second, the CMRR over the entire
common-mode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the variations seen through
the transition region, as shown in Figure 7.
7.3.5 Capacitive Load and Stability
The OPA2313-Q1 device is designed to be used in applications where driving a capacitive load is required. As
with all op amps, there may be specific instances where the OPA2313-Q1 device may become unstable. The
particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether or not an amplifier is stable in operation. An op amp in the unity-gain (+1-V/V) buffer
configuration that drives a capacitive load exhibits a greater tendency to be unstable than an amplifier operated
at a higher noise gain. The capacitive load, in conjunction with the op amp output resistance, creates a pole
within the feedback loop that degrades the phase margin. The degradation of the phase margin increases as the
capacitive loading increases. When operating in the unity-gain configuration, the OPA2313-Q1 device remains
stable with a pure capacitive load up to approximately 1 nF. The equivalent series resistance (ESR) of some
capacitors (CL greater than 1 µF) is sufficient to alter the phase characteristics in the feedback loop such that the
amplifier remains stable. Increasing the amplifier closed-loop gain allows the amplifier to drive increasingly larger
capacitance. This increased capability is evident when observing the overshoot response of the amplifier at
higher voltage gains. See the typical characteristic graph, Figure 20.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
17
OPA2313-Q1
SBOS823 – DECEMBER 2018
www.ti.com
Feature Description (continued)
One technique for increasing the capacitive load drive capability of the amplifier when it operates in a unity-gain
configuration is to insert a small resistor, typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 34.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique is that a voltage divider is created with the added series resistor and any resistor
connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output that
reduces the output swing.
V+
RS
VOUT
Device
10 W to
20 W
VIN
RL
CL
Figure 34. Improving Capacitive Load Drive
7.3.6 EMI Susceptibility and Input Filtering
Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the op amp, the DC offset observed at the amplifier output may shift from the nominal
value while EMI is present. This shift is a result of signal rectification associated with the internal semiconductor
junctions. While all op amp pin functions may be affected by EMI, the signal input pins are likely to be the most
susceptible. The OPA2313-Q1 device incorporates an internal input low-pass filter that reduces the amplifiers
response to EMI. Both common-mode and differential mode filtering are provided by this filter. The filter is
designed for a common-mode cutoff frequency of approximately 35 MHz (–3 dB), with a rolloff of 20 dB per
decade.
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR)
metric allows op amps to be directly compared by the EMI immunity. Figure 33 illustrates the results of this
testing on the OPA2313-Q1 device. Detailed information may be found in EMI Rejection Ratio of Operational
Amplifiers, available for download from www.ti.com.
7.3.7 Input and ESD Protection
The OPA2313-Q1 device incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the
case of input and output pins, this protection primarily consists of current-steering diodes connected between the
input and power-supply pins. The ESD protection diodes also provide in-circuit, input overdrive protection, as
long as the current is limited to 10 mA as stated in the Absolute Maximum Ratings. Figure 35 shows how a
series input resistor may be added to the driven input to limit the input current. The added resistor contributes
thermal noise at the amplifier input and the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
Device
VOUT
VIN
5 kW
Figure 35. Input Current Protection
7.4 Device Functional Modes
The OPA2313-Q1 device has a single functional mode. The device is powered on as long as the power-supply
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
18
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
OPA2313-Q1
www.ti.com
SBOS823 – DECEMBER 2018
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA2313-Q1 device is a low-power, rail-to-rail input and output operational amplifier. The device operates
from 1.8 V to 5.5 V, is unity-gain stable, and is designed for a wide range of general-purpose applications. The
class AB output stage is capable of driving loads greater than 10 kΩ connected to any point between V+ and
ground. The input common-mode voltage range includes both rails, and allows the OPA2313-Q1 to be used in
virtually any single-supply application.
8.2 Typical Application
A typical application for an operational amplifier is an inverting amplifier, as shown in Figure 36. An inverting
amplifier takes a positive voltage on the input and outputs a signal inverted to the input, making a negative
voltage of the same magnitude. In the same manner, the amplifier also makes negative input voltages positive on
the output. In addition, amplification may be added by selecting the input resistor (RI) and the feedback resistor
(RF.)
RF
VSUP+
RI
VOUT
+
VIN
VSUP±
Figure 36. Inverting Amplifier Application
8.2.1 Design Requirements
The supply voltage must be chosen to be larger than the input voltage range and the desired output range. The
limits of the input common-mode range (VCM) and the output voltage swing to the rails (VO) must also be
considered. For instance, this application scales a signal of ±0.5 V (1 V) to ±1.8 V (3.6 V). Setting the supply at
±2.5 V is sufficient to accommodate this application.
8.2.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier using Equation 1 and Equation 2:
VOUT
AV
VIN
AV
1.8
0.5
3.6
(1)
(2)
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
19
OPA2313-Q1
SBOS823 – DECEMBER 2018
www.ti.com
Typical Application (continued)
When the desired gain is determined, choose a value for RI or RF. Choosing a value in the kilohm range is
desirable for general-purpose applications because the amplifier circuit uses currents in the milliamp range. This
milliamp current range ensures the device does not draw too much current. The trade-off is that very large
resistors (100s of kilohms) draw the smallest current but generate the highest noise. Small resistors (100s of
ohms) generate low noise but draw high current. This example uses 10 kΩ for RI, resulting in a 36-kΩ resistor
being used for RF. The values are determined by Equation 3:
RF
AV
RI
(3)
8.2.3 Application Curve
2
Input
Output
1.5
Voltage (V)
1
0.5
0
-0.5
-1
-1.5
-2
Time
Figure 37. Inverting Amplifier Input and Output
8.3 System Examples
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of the
amplifier, as shown in Figure 38.
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Figure 38. Single-Pole Low-Pass Filter
20
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
OPA2313-Q1
www.ti.com
SBOS823 – DECEMBER 2018
System Examples (continued)
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter may be used for this
task, as shown in Figure 39. For best results, the amplifier must have a bandwidth that is 8 to 10 times the filter
frequency bandwidth. Failure to follow this guideline may result in phase shift of the amplifier.
C1
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking factor
(Butterworth Q = 0.707)
R2
VIN
VOUT
C2
1
2pRC
f-3 dB =
RF
RF
RG =
RG
(
2-
1
Q
(
Figure 39. Two-Pole, Low-Pass, Sallen-Key Filter
9 Power Supply Recommendations
The OPA2313-Q1 device is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications
apply from –40°C to +125°C. The Typical Characteristics section presents parameters that may exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings table).
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines section.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
21
OPA2313-Q1
SBOS823 – DECEMBER 2018
www.ti.com
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise may propagate into analog circuitry through the power pins of the circuit and the operational
amplifier. Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, see Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If the traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better
than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keep RF and RG close to the inverting
input to minimize parasitic capacitance, as shown in Figure 40.
• Keep the length of input traces as short as possible. Remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
+
VIN 1
+
VIN 2
VOUT 1
RG
VOUT 2
RG
RF
RF
Figure 40. Schematic Representation for Figure 41
Place components
close to device and to
each other to reduce
parasitic errors .
OUT 1
VS+
OUT1
V+
IN1 ±
OUT2
IN1 +
IN2 ±
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
RF
OUT 2
GND
RF
RG
VIN 1
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
VS±
IN2 +
Ground (GND) plane on another layer
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible .
Figure 41. Layout Example
22
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
OPA2313-Q1
www.ti.com
SBOS823 – DECEMBER 2018
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• EMI Rejection Ratio of Operational Amplifiers
• Circuit Board Layout Techniques
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: OPA2313-Q1
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2313QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
23131
OPA2313QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2313Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
