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OPA314-Q1, OPA2314-Q1, OPA4314-Q1
SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
OPAx314-Q1 3-MHz, Low-Power, Low-Noise, RRIO, 1.8-V CMOS
Operational Amplifier
1 Features
3 Description
•
•
The OPAx314-Q1 series is a family of single–, and
dual–, and quad-channel operational amplifiers (op
amps) that represents a new generation of lowpower, general-purpose CMOS amplifiers. Rail-to-rail
input and output swings, low quiescent current (150
μA typically at 5 VS) combined with a wide bandwidth
of 3 MHz, and very low noise (14 nV/√Hz at 1 kHz)
make this device family very attractive for a variety of
battery-powered applications that require a good
balance between cost and performance. The lowinput bias current supports applications with
megaohm source impedances.
1
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade : –40°C to +125°C
Ambient Operating Temperature Range
– Device HBM Classification Level 2
– Device CDM Classification Level C6
Low IQ: 150 µA/ch
Wide Supply Range: 1.8 V to 5.5 V
Low Noise: 14 nV/√Hz at 1 kHz
Gain Bandwidth: 3 MHz
Low Input Bias Current: 0.2 pA
Low Offset Voltage: 0.5 mV
Unity-Gain Stable
Internal RF and EMI Filter
Specified Temperature Range:
–40°C to +125°C
2 Applications
•
Automotive Applications:
– ADAS
– Body Electronics and Lighting
– Current Sensing
– Battery Monitoring
The robust design of the OPAx314-Q1 series
provides ease-of-use to the circuit designer: unitygain stability with capacitive loads of up to 300 pF, an
integrated RF and EMI rejection filter, no phase
reversal in overdrive conditions, and high electrostatic
discharge (ESD) protection (4-kV HBM).
The device is optimized for low-voltage operation as
low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V), and
is specified over the full extended temperature range
of –40°C to +125°C.
The single-channel device, OPA314-Q1, is offered in
the SOT-23 package and the dual-channel device,
OPA2314-Q1, is offered in the VSSOP (8) package.
The quad-channel OPA4314-Q1 is available in the
14-pin TSSOP package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
OPA314-Q1
SOT-23 (5)
2.90 mm × 1.60 mm
OPA2314-Q1
VSSOP (8)
4.90 mm × 3.91 mm
OPA4314-Q1
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
EMIRR vs Frequency
120
110
EMIRR IN+ (dB)
100
90
80
70
60
50
40
30
20
10
0
10M
100M
1G
Frequency (Hz)
10G
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA314-Q1, OPA2314-Q1, OPA4314-Q1
SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
1
1
1
2
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions ...................... 6
Thermal Information: OPA314-Q1 ............................ 7
Thermal Information: OPA2314-Q1 .......................... 8
Thermal Information: OPA4314-Q1 .......................... 9
Electrical Characteristics......................................... 10
Typical Characteristics ............................................ 12
Detailed Description ............................................ 19
7.1 Overview ................................................................. 19
7.2 Functional Block Diagram ....................................... 19
7.3 Feature Description................................................. 19
7.4 Device Functional Modes ....................................... 20
8
Application and Implementation ........................ 21
8.1 Application Information .......................................... 21
8.2 Typical Application ................................................. 23
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................ 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
Changes from Revision A (January 2015) to Revision B
Page
•
Added part number OPA4314-Q1 to document ..................................................................................................................... 1
•
Added part number OPA4314-Q1 to the Device Information table ....................................................................................... 1
•
Changed OPA2314-Q1 package from SOIC (8) to VSSOP (8) in the Device Information table ........................................... 1
•
Added OPA314-Q1 (SOT-23 package) throughout document............................................................................................... 3
•
Added pinout drawing for the OPA4314-Q1 device in the Pin Configurations and Functions section .................................. 5
•
Added the Pin Functions: OPA4314-Q1 table to the Pin Configurations and Functions section .......................................... 5
•
Changed formatting of all Thermal Information table notes .................................................................................................. 7
•
Added footnotes to all Thermal Information tables................................................................................................................. 7
•
Added Thermal Information: OPA4314-Q1 table.................................................................................................................... 9
•
Changed formatting of application report reference in the EMI Susceptibility and Input Filtering section .......................... 20
•
Changed package drawing to reflect an example of the 5-pin SOT-23 package in the Layout Example section ............... 26
•
Changed formatting of Related Documentation section ...................................................................................................... 27
•
Added part number OPA4314-Q1 to the Related Links table ............................................................................................. 27
Changes from Original (December 2014) to Revision A
•
2
Page
Changed the device status from Product Preview to Production Data ................................................................................. 1
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SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
5 Pin Configuration and Functions
OPA314-Q1 DBV Package
5-Pin SOT-23
Top View
Pin Functions: OPA314-Q1
PIN
NAME
NO.
–IN
4
+IN
OUT
I/O
DESCRIPTION
I
Inverting input
3
I
Noninverting input
1
O
Output
V–
2
—
Negative supply or ground (for single-supply operation).
V+
5
—
Positive supply
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3
OPA314-Q1, OPA2314-Q1, OPA4314-Q1
SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
www.ti.com
OPA2314-Q1 DGK Package
8-Pin VSSOP
Top View
Pin Functions: OPA2314-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative supply or ground (for single-supply operation).
V+
8
—
Positive supply
4
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SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
OPA4314-Q1 DGK Package
14-Pin TSSOP
Top View
Pin Functions: OPA4314-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
–IN C
9
I
Inverting input, channel C
+IN C
10
I
Noninverting input, channel C
–IN D
13
I
Inverting input, channel D
+IN D
12
I
Noninverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V–
11
—
Negative supply or ground (for single-supply operation).
V+
4
—
Positive supply
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5
OPA314-Q1, OPA2314-Q1, OPA4314-Q1
SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
7
V
Supply voltage
(2)
Signal input terminals
Current (2)
Signal input terminals
Voltage
(V–) – 0.5
Output short-circuit (3)
–40
Junction temperature, TJ
Storage temperature, Tstg
(2)
(3)
V
±10
mA
Continuous
Operating temperature, TA
(1)
(V+) + 0.5
–65
mA
150
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
±2000
Charged device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Supply voltage
TA
Ambient operating temperature
6
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NOM
MAX
UNIT
1.8 (±0.9)
5.5 (±2.75)
V
–40
125
°C
Copyright © 2014–2017, Texas Instruments Incorporated
Product Folder Links: OPA314-Q1 OPA2314-Q1 OPA4314-Q1
OPA314-Q1, OPA2314-Q1, OPA4314-Q1
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SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
6.4 Thermal Information: OPA314-Q1
OPA314-Q1
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
5 PINS
Junction-to-ambient thermal resistance (2)
RθJA
(3)
221.7
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
144.7
°C/W
RθJB
Junction-to-board thermal resistance (4)
49.7
°C/W
ψJT
Junction-to-top characterization parameter (5)
26.1
°C/W
ψJB
Junction-to-board characterization parameter (6)
49
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance (7)
N/A
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2014–2017, Texas Instruments Incorporated
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SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
www.ti.com
6.5 Thermal Information: OPA2314-Q1
OPA2314-Q1
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
Junction-to-ambient thermal resistance (2)
RθJA
138.4
°C/W
(3)
RθJC(top)
Junction-to-case(top) thermal resistance
89.5
°C/W
RθJB
Junction-to-board thermal resistance (4)
78.6
°C/W
ψJT
Junction-to-top characterization parameter (5)
29.9
°C/W
ψJB
Junction-to-board characterization parameter (6)
78.1
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance (7)
N/A
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
6.6 Thermal Information: OPA4314-Q1
OPA4314-Q1
THERMAL METRIC (1)
PW (TSSOP)
UNIT
14 PINS
Junction-to-ambient thermal resistance (2)
RθJA
(3)
121
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
49.4
°C/W
RθJB
Junction-to-board thermal resistance (4)
62.8
°C/W
ψJT
Junction-to-top characterization parameter (5)
5.9
°C/W
ψJB
Junction-to-board characterization parameter (6)
62.2
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance (7)
N/A
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2014–2017, Texas Instruments Incorporated
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SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
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6.7 Electrical Characteristics
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, VS = 1.8 V to 5.5 V, unless otherwise noted.
The phrase overtemperature refers to values over the specified temperature range of TA = –40°C to 125°C. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
2.5
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage vs
temperature
PSRR
vs power supply
VCM = (VS+) – 1.3 V
VCM = (VS+) – 1.3 V
78
Input offset voltage
overtemperature
Channel separation, DC
1
μV/°C
92
dB
74
At DC
mV
dB
10
µV/V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
range
CMRR
Common-mode rejection
ratio
Common-mode rejection
ratio overtemperature
(V–) – 0.2
VS = 1.8 V to 5.5 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V
(V+) + 0.2
V
75
96
dB
66
80
dB
VS = 1.8 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V
70
86
dB
VS = 5.5 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V
73
90
dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V
VS = 5.5 V, VCM = –0.2 V to 5.7 V
(2)
(2)
60
dB
INPUT BIAS CURRENT
IB
Input bias current
±0.2
Input bias current
overtemperature
IOS
Input offset current
±10
pA
±600
pA
±10
pA
±600
pA
±0.2
Input offset current
overtemperature
NOISE
Input voltage noise (peakto-peak)
en
Input voltage noise density
in
Input current noise density
(1)
(2)
10
f = 0.1 Hz to 10 Hz
5
μVPP
f = 10 kHz
13
nV/√Hz
f = 1 kHz
14
nV/√Hz
f = 1 kHz
5
fA/√Hz
Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted.
Overtemperature limits are based on characterization and statistical analysis.
Specified by design and characterization; not production tested.
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SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
Electrical Characteristics (continued)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, VS = 1.8 V to 5.5 V, unless otherwise noted.
The phrase overtemperature refers to values over the specified temperature range of TA = –40°C to 125°C.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CAPACITANCE
CIN
Differential
VS = 5 V
1
pF
Common-mode
VS = 5 V
5
pF
OPEN-LOOP GAIN
AOL
VS = 1.8 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ
90
115
dB
VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ
100
128
dB
VS = 1.8 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ (2)
90
100
dB
VS = 5.5 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ (2)
94
110
dB
Open-loop voltage gain
overtemperature
VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ
90
110
dB
Phase margin
Open-loop voltage gain
VS = 5.5 V, 0.5 V < VO < (V+) – 0.2 V, RL = 2 kΩ
100
dB
VS = 5 V, G = 1, RL = 10 kΩ
65
degrees
VS = 1.8 V, RL = 10 kΩ, CL = 10 pF
2.7
MHz
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
3
MHz
VS = 5 V, G = 1
1.5
V/μs
To 0.1%, VS = 5 V, 2-V step , G = 1
2.3
μs
To 0.01%, VS = 5 V, 2-V step , G = 1
3.1
μs
Overload recovery time
VS = 5 V, VIN × Gain > VS
5.2
μs
Total harmonic distortion +
noise (4)
VS = 5 V, VO = 1 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ
(3)
Settling time
THD+N
VS = 5 V, RL = 10 kΩ, CL = 10 pF
0.001%
OUTPUT
VO
Voltage output swing from
supply rails
VS = 1.8 V, RL = 10 kΩ
5
15
mV
VS = 5.5 V, RL = 10 kΩ
5
20
mV
VS = 1.8 V, RL = 2 kΩ
15
30
mV
VS = 5.5 V, RL = 2 kΩ
22
40
mV
30
mV
Voltage output swing from
supply rails
overtemperature
VS = 5.5 V, RL = 10 kΩ
60
mV
ISC
Short-circuit current
VS = 5 V
±20
mA
RO
Open-loop output
impedance
VS = 5.5 V, f = 100 Hz
570
Ω
VS = 5.5 V, RL = 2 kΩ
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per
amplifier
5.5
V
VS = 1.8 V, IO = 0 mA
1.8
130
180
µA
VS = 5 V, IO = 0 mA
150
190
µA
220
µA
Quiescent current per
amplifier overtemperature
VS = 5 V, IO = 0 mA
Power-on time
VS = 0 V to 5 V, to 90% IQ level
44
µs
TEMPERATURE
(3)
(4)
Specified range
–40
125
°C
Operating range
–40
150
°C
Storage range
–65
150
°C
Signifies the slower value of the positive or negative slew rate.
Third-order filter; bandwidth = 80 kHz at –3 dB.
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6.8 Typical Characteristics
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted
Table 1. Characteristic Performance Measurements
TITLE
FIGURE
Open-Loop Gain and Phase vs Frequency
Figure 1
Open-Loop Gain vs Temperature
Figure 2
Quiescent Current vs Supply Voltage
Figure 3
Quiescent Current vs Temperature
Figure 4
Offset Voltage Production Distribution
Figure 5
Offset Voltage Drift Distribution
Figure 6
Offset Voltage vs Common-Mode Voltage (Maximum Supply)
Figure 7
Offset Voltage vs Temperature
Figure 8
CMRR and PSRR vs Frequency (RTI)
Figure 9
CMRR and PSRR vs Temperature
Figure 10
0.1-Hz to 10-Hz Input Voltage Noise (5.5 V)
Figure 11
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V)
Figure 12
Input Voltage Noise vs Common-Mode Voltage (5.5 V)
Figure 13
Input Bias and Offset Current vs Temperature
Figure 14
Open-Loop Output Impedance vs Frequency
Figure 15
Maximum Output Voltage vs Frequency and Supply Voltage
Figure 16
Output Voltage Swing vs Output Current (over Temperature)
Figure 17
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (1.8 V)
Figure 18
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (5.5 V)
Figure 19
Small-Signal Overshoot vs Load Capacitance
Figure 20
Small-Signal Step Response, Noninverting (1.8 V)
Figure 21
Small-Signal Step Response, Noninverting ( 5.5 V)
Figure 22
Large-Signal Step Response, Noninverting (1.8 V)
Figure 23
Large-Signal Step Response, Noninverting ( 5.5 V)
Figure 24
Positive Overload Recovery
Figure 25
Negative Overload Recovery
Figure 26
No Phase Reversal
Figure 27
Channel Separation vs Frequency (Dual)
Figure 28
THD+N vs Amplitude (G = 1, 2 kΩ, 10 kΩ)
Figure 29
THD+N vs Amplitude (G = –1, 2 kΩ, 10 kΩ)
Figure 30
THD+N vs Frequency (0.5 VRMS, G = 1, 2 kΩ, 10 kΩ)
Figure 31
EMIRR
Figure 32
12
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140
0
120
-20
100
-40
80
-60
60
-80
40
-100
20
-120
0
-140
-20
1
10
100
1k
10k
100k
1M
Open-Loop Gain (dB)
140
Phase (°)
Gain (dB)
www.ti.com
-160
10M
10 kΩ, 5.5 V
2 kΩ, 5.5 V
10 kΩ, 1.8 V
130
120
110
100
-50
-25
0
25
Frequency (Hz)
RL = 10 kΩ / 10 pF
125
Figure 2. Open-Loop Gain vs Temperature
180
160
170
155
Quiescent Current (µA/Ch)
Quiescent Current (µA/Ch)
100
VS = ±2.5 V
Figure 1. Open-loop Gain and Phase vs Frequency
160
150
140
130
120
110
100
VS = 5.5 V
VS = 1.8 V
150
145
140
135
130
125
90
80
120
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
-50
-25
0
25
Supply Voltage (V)
10
25
Percent of Amplifiers (%)
30
6
4
2
100
125
Figure 4. Quiescent Current vs Temperature
12
8
75
50
Temperature (°C)
Figure 3. Quiescent Current vs Supply
Percent of Amplifiers (%)
75
50
Temperature (°C)
20
15
10
5
-1.4
-1.3
-1.2
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
0
Offset Voltage (mV)
Figure 5. Offset Voltage Production Distribution
Copyright © 2014–2017, Texas Instruments Incorporated
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Offset Voltage Drift (µV/°C)
Figure 6. Offset Voltage Drift Distribution
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1000
1500
800
1000
Offset Voltage (µV)
Offset Voltage (µV)
600
400
200
0
-200
-400
-600
500
0
-500
-1000
-800
-1000
-2.75
-1500
-2
-1.25
-0.5
0
0.5
1.25
2
2.75
-40 -25 -10
5
20
Common-Mode Voltage (V)
Typical units
VS = ±2.75 V
Typical units
Figure 7. Offset Voltage vs Common-Mode Voltage
50
65
80
95
110 125
VS = ±2.75 V
Figure 8. Offset Voltage vs Temperature
120
104
–PSRR
PSRR
CMRR
100
80
60
40
20
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
35
Temperature (°C)
0
PSRR
CMRR
102
100
98
CMRR
96
94
92
PSRR
90
88
86
84
10
100
1k
10k
100k
1M
-50
-25
0
Frequency (Hz)
25
50
75
100
125
Temperature (°C)
VS = ±2.75 V
Figure 9. CMRR and PSRR vs Frequency (Referred-to-Input)
Figure 10. CMRR and PSRR vs Temperature
100
VS = ±0.9 V
Voltage (0.5 mV/div)
Voltage Noise (nv/√Hz)
VS = ±2.75 V
10
Time (1 s/div)
10
100
1k
10k
100k
Frequency (Hz)
Figure 11. 0.1-Hz to 10-Hz Input Voltage Noise
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Figure 12. Input Voltage Noise Spectral Density vs
Frequency
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20
1000
IOS
IB
18
Input Bias Current (pA)
Voltage Noise (nV/√Hz)
900
16
14
12
800
700
600
500
400
300
200
100
10
0
0
0.5
1
1.5
2.5
2
3
3.5
4
4.5
5
5.5
-50
-25
0
25
Common-Mode Input Voltage (V)
f = 1 kHz
75
100
125
150
VS = ±2.75 V
Figure 13. Voltage Noise vs Common-Mode Voltage
100k
Figure 14. Input Bias and Offset Current vs Temperature
6
VS = ±0.9 V
VS = ±2.75 V
10k
1k
VIN = 5.5 V
VIN = 3.3 V
VIN = 1.8 V
5
Voltage (VPP)
Output Impedance (Ω)
50
Temperature (°C)
4
3
2
1
1
0
1
10
100
1k
10k
100k
1M
10M
10k
100k
Frequency (Hz)
1M
RL = 10 kΩ
Figure 15. Open-Loop Output Impedance vs Frequency
CL = 10 pF
Figure 16. Maximum Output Voltage vs Frequency and
Supply Voltage
40
3
G = –1 V/V
G = 1 V/V
G = 10 V/V
2
20
1
Gain (dB)
Output Voltage Swing (V)
10M
Frequency (Hz)
–40°C
25°C
125°C
0
0
-1
-2
-20
-3
0
5
10
15
20
25
30
35
40
10k
100k
VS = ±2.75 V
1M
10M
Frequency (Hz)
Output Current (mA)
VS = 1.8 V
Figure 17. Output Voltage Swing vs Output Current
(Overtemperature)
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Figure 18. Closed-Loop Gain vs Frequency
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40
70
G = –1 V/V
G = 1 V/V
G = 10 V/V
60
50
Gain (dB)
Overshoot (%)
20
0
40
30
20
10
0
-20
10k
100k
1M
0
10M
200
400
600
VS = 5.5 V
RL = 10 kΩ
Figure 19. Closed-Loop Gain vs Frequency
VS = ±2.75 V
Voltage (25 mV/div)
Voltage (25 mV/div)
Time (1 µs/div)
G = 1 V/V
RF = 10 kΩ
Figure 21. Small-Signal Pulse Response (Noninverting)
1
0.25
0.5
-0.25
0
-0.5
-0.5
-1
-0.75
-1.5
-1
-2
Time (1 µs/div)
RL = 10 kΩ
VS = ±0.9 V
Time (1 µs/div)
G = 1 V/V
Figure 23. Large-Signal Pulse Response (Noninverting)
16
G = 1 V/V
VOUT
VIN
1.5
Voltage (V)
Voltage (V)
2
0.5
0
VS = ±2.75 V
Figure 22. Small-Signal Pulse Response (Inverting)
VOUT
VIN
0.75
G = 1 V/V
VIN
Time (1 µs/div)
1
1200
ZL = 10 pF + 10 kΩ
ZL = 100 pF + 10 kΩ
VIN
VS = ±0.9 V
1000
Figure 20. Small-Signal Overshoot vs Load Capacitance
ZL = 10 pF + 10 kΩ
ZL = 100 pF + 10 kΩ
RF = 10 kΩ
800
Capacitive Load (pF)
Frequency (Hz)
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RL = 10 kΩ
VS = ±2.75 V
G = 1 V/V
Figure 24. Large-Signal Pulse Response (Inverting)
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3
2.5
Output
Input
0.5
2
Voltage (0.5 V/div)
Voltage (0.5 V/div)
1
Output
Input
1.5
1
0.5
0
-0.5
-1
-1.5
0
-2
-0.5
-2.5
-1
-3
0
4
2
6
8
10
12
14
0
4
2
6
Time (2 µs/div)
Figure 25. Positive Overload Recovery
4
12
14
Figure 26. Negative Overload Recovery
Channel Separation (dB)
2
Voltage (1 V/div)
10
-60
VOUT
VIN
3
8
Time (2 µs/div)
1
0
-1
-2
-80
-100
-120
-3
-140
-4
0
250
500
750
100
1000
1k
10k
100k
1M
10M
Frequency (Hz)
Time (125 µs/div)
VS = ±2.75 V
Figure 28. Channel Separation vs Frequency
Figure 27. No Phase Reversal
Load = 10 kΩ
Load = 2 kΩ
0.01
0.001
0.0001
0.01
0.1
1
10
0.1
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
0.1
Load = 10 kΩ
Load = 2 kΩ
0.01
0.001
0.0001
0.01
Output Amplitude (VRMS)
f = 1 kHz
BW = 80 kHz
VS = ±2.5 V
G = 1 V/V
Figure 29. THD+N vs Output Amplitude (G = 1 V/V)
Copyright © 2014–2017, Texas Instruments Incorporated
0.1
1
10
Output Amplitude (VRMS)
f = 1 kHz
BW = 80 kHz
VS = ±2.5 V
G = –1 V/V
Figure 30. THD+N vs Output Amplitude (G = –1 V/V)
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120
Load = 10 kΩ
Load = 2 kΩ
110
100
90
EMIRR IN+ (dB)
Total Harmonic Distortion + Noise (%)
0.1
www.ti.com
0.01
0.001
80
70
60
50
40
30
20
0.0001
10
100
1k
10k
100k
10
0
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
VOUT = 0.5 VRMS
BW = 80 kHz
VS = ±2.5 V
Figure 31. THD+N vs Frequency
18
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G = 1 V/V
PRF = –10 dBm
VS = ±2.5 V
10G
VCM = 0 V
Figure 32. Electromagnetic Interference Rejection Ratio
Referred To Noninverting Input (EMIRR IN+) vs Frequency
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SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
7 Detailed Description
7.1 Overview
The OPAx314-Q1 is a family of low-power, rail-to-rail input and output operational amplifiers. These devices
operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose
applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected to any point between V+
and ground. The input common-mode voltage range includes both rails and allows the OPAx314-Q1 series to be
used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic
range, especially in low-supply applications, and makes them ideal for driving sampling analog-to-digital
converters (ADCs).
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Operating Voltage
The OPAx314-Q1 op-amp family is fully specified and ensured for operation from 1.8 V to 5.5 V. In addition,
many specifications apply from –40°C to +125°C. Parameters that vary significantly with operating voltages or
temperature are shown in the Typical Characteristics section. Power-supply pins must be bypassed with 0.01-μF
ceramic capacitors.
7.3.2 Rail-to-Rail Input
The input common-mode voltage range of the OPAx314-Q1 family extends 200 mV beyond the supply rails. This
performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a
P-channel differential pair. The N-channel pair is active for input voltages close to the positive rail, typically (V+) –
1.3 V to 200 mV above the positive supply. The P-channel pair is on for inputs from 200 mV below the negative
supply to approximately (V+) – 1.3 V. A small transition region exists, typically (V+) – 1.4 V to (V+)
– 1.2 V, in which both pairs are on. This 200-mV transition region can vary up to 300 mV with process variation.
Thus, the transition region (both stages on) can range from (V+) – 1.7 V to (V+) – 1.5 V on the low end, up to
(V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset
drift, and THD may be degraded compared to device operation outside this region.
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Feature Description (continued)
7.3.3 Input and ESD Protection
The OPAx314-Q1 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the
case of input and output pins, this protection primarily consists of current-steering diodes connected between the
input and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as
long as the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. Figure 33 shows how a
series input resistor can be added to the driven input to limit the input current. The added resistor contributes
thermal noise at the amplifier input and the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
Device
VOUT
VIN
5 kW
Figure 33. Input Current Protection
7.3.4 Common-Mode Rejection Ratio (CMRR)
CMRR for the OPAx314-Q1 family is specified in several ways so the best match for a given application may be
used; see the Electrical Characteristics table. First, the CMRR of the device in the common-mode range below
the transition region [VCM < (V+) – 1.3 V] is given. This specification is the best indicator of the capability of the
device when the application requires use of one of the differential input pairs. Second, the CMRR over the entire
common-mode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the variations seen through
the transition region, as shown in Figure 7.
7.3.5 EMI Susceptibility and Input Filtering
Op amps vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If conducted
EMI enters the op-amp, the dc offset observed at the amplifier output may shift from the nominal value while EMI
is present. This shift is a result of signal rectification associated with the internal semiconductor junctions. While
all op-amp pin functions can be affected by EMI, the signal input pins are likely to be the most susceptible. The
OPAx314-Q1 family incorporates an internal input low-pass filter that reduces the amplifiers response to EMI.
Both common-mode and differential mode filtering are provided by this filter. The filter is designed for a cutoff
frequency of approximately 80 MHz (–3 dB), with a roll-off of 20 dB per decade.
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR)
metric allows op amps to be directly compared by the EMI immunity. Figure 32 shows the results of this testing
on the OPAx314-Q1 family. Detailed information can also be found in the EMI Rejection Ratio of Operational
Amplifiers application report, available for download from www.ti.com.
7.3.6 Rail-to-Rail Output
Designed as a micro-power, low-noise operational amplifier, the OPAx314-Q1 family delivers a robust output
drive capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output
swing capability. For resistive loads up to 10 kΩ, the output swings typically to within 5 mV of either supply rail
regardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier to
swing close to the rails; see Figure 17.
7.4 Device Functional Modes
The OPAx314-Q1 family is powered on when the supply is connected. The device can operate as a single-supply
operational amplifier or a dual-supply amplifier, depending on the application.
20
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx314-Q1 family is a low-power, rail-to-rail input and output operational amplifier specifically designed for
portable applications. The device operates from 1.8 V to 5.5 V, is unity-gain stable, and suitable for a wide range
of general-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected to any
point between V+ and ground. The input common-mode voltage range includes both rails, and allows the
OPAx314-Q1 family to be used in virtually any single-supply application. Rail-to-rail input and output swing
significantly increases dynamic range, especially in low-supply applications, and makes the device ideal for
driving sampling analog-to-digital converters (ADCs).
The OPAx314-Q1 family features a 3-MHz bandwidth and 1.5-V/μs slew rate with only 150-μA supply current per
channel, providing good AC performance at very low power consumption. DC applications are also well served
with a very-low input noise voltage of 14 nV/√Hz at 1 kHz, low-input bias current (0.2 pA), and an input offset
voltage of 0.5 mV (typical).
8.1.1 General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of the
amplifier, as shown in Figure 34.
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Figure 34. Single-Pole Low-Pass Filter
If additional attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task, as shown in Figure 35. For best results, the amplifier must have a bandwidth that is eight to ten times the
filter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.
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Application Information (continued)
C1
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking factor
(Butterworth Q = 0.707)
R2
VIN
VOUT
C2
1
2pRC
f-3 dB =
RF
RF
RG =
RG
(
2-
1
Q
(
Figure 35. Two-Pole Low-Pass Sallen-Key Filter
8.1.2 Capacitive Load and Stability
The OPAx314-Q1 family is designed to be used in applications where driving a capacitive load is required. As
with all op amps, specific instances can occur where the OPAx314-Q1 can become unstable. The particular opamp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing
whether or not an amplifier is stable in operation. An op-amp in the unity-gain (1 V/V) buffer configuration that
drives a capacitive load exhibits a greater tendency to be unstable than an amplifier operated at a higher noise
gain. The capacitive load, in conjunction with the op-amp output resistance, creates a pole within the feedback
loop that degrades the phase margin. The degradation of the phase margin increases as the capacitive loading
increases. When operating in the unity-gain configuration, the OPAx314-Q1 remains stable with a pure capacitive
load up to approximately 1 nF. The equivalent series resistance (ESR) of some very large capacitors (CL greater
than 1 μF) is sufficient to alter the phase characteristics in the feedback loop such that the amplifier remains
stable. Increasing the amplifier closed-loop gain allows the amplifier to drive increasingly larger capacitance. This
increased capability is evident when observing the overshoot response of the amplifier at higher voltage gains;
see , Figure 20.
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor, typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 36.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique, however, is that a voltage divider is created with the added series resistor and any
resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output
that reduces the output swing.
V+
RS
VOUT
Device
VIN
10 W to
20 W
RL
CL
Figure 36. Improving Capacitive Load Drive
22
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8.2 Typical Application
Some applications require differential signals. Figure 37 shows a simple circuit to convert a single-ended input of
0.1 V to 2.4 V into a differential output of ±2.3 V on a single 2.7-V supply. The output range is intentionally limited
to maximize linearity. The circuit is composed of two amplifiers. One amplifier functions as a buffer and creates a
voltage (VOUT+. ) The second amplifier inverts the input and adds a reference voltage to generate VOUT–. Both
VOUT+ and VOUT– range from 0.1 V to 2.4 V. The difference (VDIFF) is the difference between VOUT+ and VOUT–.
This makes the differential output voltage range 2.3 V.
R2
2.7 V
R1
±
VOUT±
+
Device
R3
+
VREF
2.5 V
R4
V
VDIFF
+
2.7 V
±
VOUT+
+
Device
Copyright © 2017, Texas Instruments Incorporated
+
+
VIN
Figure 37. Schematic for a Single-Ended Input to Differential Output Conversion
8.2.1 Design Requirements
The design requirements are as follows:
• Supply voltage: 2.7 V
• Reference voltage: 2.5 V
• Input: 0.1 V to 2.4 V
• Output differential: ±2.3 V
• Output common-mode voltage: 1.25 V
• Small-signal bandwidth: 1 MHz
8.2.2 Detailed Design Procedure
The circuit in Figure 37 takes a single-ended input signal, VIN, and generates two output signals, VOUT+ and
VOUT– using two amplifiers and a reference voltage, VREF. VOUT+ is the output of the first amplifier and is a
buffered version of the input signal, VIN (as shown in Equation 1). VOUT– is the output of the second amplifier
which uses VREF to add an offset voltage to VIN and feedback to add inverting gain. The transfer function for
VOUT– is given in Equation 2.
VOUT
VIN
(1)
V287±
§ R 4 · § R2 ·
R2
V5() u ¨
¸ u ¨1
¸ V,1 u
R1 ¹
R1
© R3 R4 ¹ ©
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(2)
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Typical Application (continued)
The differential output signal (VDIFF) is the difference between the two single-ended output signals (VOUT+ and
VOUT–). Equation 3 shows the transfer function for VDIFF. By applying the conditions that R1 = R2 and R3 = R4, the
transfer function is simplified into Equation 6. Using this configuration, the maximum input signal is equal to the
reference voltage and the maximum output of each amplifier is equal to VREF. The differential output range is 2 ×
VREF. Furthermore, the common-mode voltage is one half of VREF (see Equation 7).
V',))
V287
VOUT
VIN
V287±
V5()
V287±
§ R 4 · § R2 ·
§ R2 ·
V,1 u ¨ 1
¸ u ¨1
¸ V5() u ¨
¸
R1 ¹
R1 ¹
©
© R3 R 4 ¹ ©
(3)
(4)
V,1
(5)
VDIFF
2 u VIN VREF
VCM
V287± ·
§ V287
¨
¸
2
©
¹
(6)
1
VREF
2
(7)
8.2.2.1 Amplifier Selection
Linearity over the input range is key for good dc accuracy. The common-mode input range and output swing
limitations determine the linearity. In general, an amplifier with rail-to-rail input and output swing is required.
Bandwidth is a key concern for this design, so the OPAx314-Q1 family is selected because the bandwidth is
greater than the target of 1 MHz. The bandwidth and power ratio makes this device power efficient and the low
offset and drift ensure good accuracy for moderate precision applications.
8.2.2.2 Passive Component Selection
Because the transfer function of VOUT– is heavily reliant on resistors (R1, R2, R3, and R4), use resistors with low
tolerances to maximize performance and minimize error. This design uses resistors with resistance values of
49.9 kΩ and tolerances of 0.1%. However, if the noise of the system is a key parameter, smaller resistance
values (6 kΩ or lower) can be selected to keep the overall system noise low. This ensures that the noise from the
resistors is lower than the amplifier noise.
2.50
2.50
2.00
2.00
1.50
1.50
Vout- (V)
Vout+ (V)
8.2.3 Application Curves
1.00
0.50
0.00
0.00
0.50
0.50
1.00
1.50
2.00
Input voltage (V)
Figure 38. VOUT+ vs Input Voltage
24
1.00
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2.50
0.00
0.00
0.50
1.00
1.50
2.00
Input voltage (V)
C027
2.50
C027
Figure 39. VOUT– vs Input Voltage
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Product Folder Links: OPA314-Q1 OPA2314-Q1 OPA4314-Q1
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SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
2.50
2.00
1.50
Vdiff (V)
1.00
0.50
0.00
-0.50
-1.00
-1.50
-2.00
-2.50
0.00
0.50
1.00
1.50
2.00
Input voltage (V)
2.50
C027
Figure 40. VDIFF vs Input Voltage
9 Power Supply Recommendations
The OPAx314-Q1 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications
apply from –40°C to +125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing lowimpedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to
physically separate digital and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the
inverting input minimizes parasitic capacitance, as shown in Figure 41.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Run the input traces
as far away from
the supply lines
VIN
as possible.
VS+
VS±
+IN
V+
Use a low-ESR,
ceramic bypass
capacitor.
V±
Use a low-ESR,
ceramic bypass
capacitor.
GND
RG
OUT
±IN
VOUT
GND
Place components
close to the device
and to each other to
reduce parasitic
errors.
RF
Copyright © 2017, Texas Instruments Incorporated
Figure 41. Operational Amplifier Board Layout for Noninverting Configuration
26
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OPA314-Q1, OPA2314-Q1, OPA4314-Q1
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SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• EMI Rejection Ratio of Operational Amplifiers
11.1.2 Related Links
Table 2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA314-Q1
Click here
Click here
Click here
Click here
Click here
OPA2314-Q1
Click here
Click here
Click here
Click here
Click here
OPA4314-Q1
Click here
Click here
Click here
Click here
Click here
11.2 Trademarks
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2014–2017, Texas Instruments Incorporated
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27
PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2314AQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
O2314Q
OPA314AQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14ZD
OPA314AQDBVTQ1
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
14ZD
OPA4314AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4314Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
