OPA328, OPA2328
SBOS957D – FEBRUARY 2022 – REVISED DECEMBER 2023
OPAx328 Precision, 40-MHz, 1.0-pA, Low-Noise, RRIO, CMOS Operational Amplifiers
With Shutdown
1 Features
3 Description
•
The single-channel OPA328 and dual-channel
OPA2328 (OPAx328) are a new generation family of
precision, low-voltage CMOS operational amplifiers
optimized for very low noise and wide bandwidth.
•
•
•
•
•
•
•
Precision with zero-crossover distortion:
– Low offset voltage: 50 µV (maximum)
– High CMRR: 120 dB
– Rail-to-rail I/O
Wide bandwidth: 40 MHz
Low input bias current: 1 pA (maximum)
Low noise: 6.1 nV/√Hz at 10 kHz
Slew rate: 30 V/µs
Fast 0.01% settling time: 180 ns
Single-supply voltage range: 2.2 V to 5.5 V
Unity-gain stable
2 Applications
•
•
•
•
•
•
•
•
•
The OPAx328 have a linear input stage with zerocrossover distortion that delivers excellent commonmode rejection ratio (CMRR) of 120 dB (typical)
over the full input range. The input common-mode
voltage range extends 100 mV beyond the negative
and positive supply rails. The output voltage typically
swings within 10 mV of the rails.
The OPAx328 also use Texas Instrument's proprietary
e‑trim™ operational amplifier technology, enabling a
unique combination of ultra-low offset and low input
offset drift without the need for any input switching or
auto-zero techniques.
Optical module
Position sensor
Multiparameter patient monitor
CT and PET scanner
Chemistry and gas analyzer
Bidirectional 400-V and 800-V to LV
Merchant network and server PSU
String inverter
Solar power optimizer
Low-noise (6.1 nV/√Hz) and high-speed operation
(40 MHz, 30 V/μs) make these devices a great choice
for driving sampling analog-to-digital converters
(ADCs).
The OPAx328 are also a great choice for highimpedance-input, single-supply applications. Low
input bias current and low input capacitance allows
for high-frequency transimpedance gains at low
photocurrent operation (< 1 nA).
V+
OPAx328
Charge
pump
Device Information
+IN
IN
PMOS
input
pair
PART NUMBER
OUT
Σ
CHANNELS /
SHUTDOWN
OPA328
Single / No
DBV (SOT-23, 5)
OPA328S(2)
Single / Yes
DBV (SOT-23, 6)
POR
D (SOIC, 8)
OPA2328
Dual / No
OPA4328(2)
Block Diagram
DGK (VSSOP, 8)
DRG (WSON, 8)
e-trim™
V
PACKAGE(1)
(1)
(2)
Quad / No
PW (TSSOP, 14)
Quad / Yes
RUM (WQFN, 16)
For more information, see Section 10.
Preview information (not Production Data).
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
OPA328, OPA2328
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SBOS957D – FEBRUARY 2022 – REVISED DECEMBER 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 5
5.1 Absolute Maximum Ratings........................................ 5
5.2 ESD Ratings .............................................................. 5
5.3 Recommended Operating Conditions.........................5
5.4 Thermal Information - OPA328................................... 6
5.5 Thermal Information - OPA2328................................. 6
5.6 Electrical Characteristics.............................................7
5.7 Typical Characteristics................................................ 9
6 Detailed Description......................................................15
6.1 Overview................................................................... 15
6.2 Functional Block Diagram......................................... 15
6.3 Feature Description...................................................16
6.4 Device Functional Modes..........................................16
2
7 Application and Implementation.................................. 17
7.1 Application Information............................................. 17
7.2 Typical Applications.................................................. 17
7.3 Power Supply Recommendations.............................21
7.4 Layout....................................................................... 21
8 Device and Documentation Support............................22
8.1 Device Support......................................................... 22
8.2 Documentation Support............................................ 23
8.3 Receiving Notification of Documentation Updates....23
8.4 Support Resources................................................... 23
8.5 Trademarks............................................................... 23
8.6 Electrostatic Discharge Caution................................23
8.7 Glossary....................................................................23
9 Revision History............................................................ 23
10 Mechanical, Packaging, and Orderable
Information.................................................................... 24
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4 Pin Configuration and Functions
OUT
1
V-
2
+IN
3
V+
5
4
VOUT
1
6
V+
V-
2
5
SHDN
+IN
3
4
-IN
-IN
Figure 4-1. OPA328 DBV Package,
5-Pin SOT-23 (Top View)
Figure 4-2. OPA328S DBV Package (Preview)
6-Pin SOT-23 (Top View)
Pin Functions: OPA328 and OPA328S
PIN
NAME
TYPE
DESCRIPTION
OPA328
OPA328S
–IN
4
4
+IN
3
OUT, VOUT
1
SHDN
—
5
Input
V–
2
2
Power
Negative (lowest) power supply
V+
5
6
Power
Positive (highest) power supply
OUT A
Input
Negative (inverting) input
3
Input
Positive (noninverting) input
1
Output
1
8
Output
Shutdown, active low
V+
OUT A
1
-IN A
2
7
OUT B
+IN A
3
6
-IN B
+IN A
3
V-
4
5
+IN B
V-
4
-IN A
Figure 4-3. OPA2328 D Package, 8-pin SOIC and
DGK Package, 8-Pin VSSOP (Top View)
2
Exposed
Thermal
Die Pad
on
Underside(2)
8
V+
7
OUT B
6
-IN B
5
+IN B
Figure 4-4. OPA2328 DRG Package,
8-Pin WSON (Top View)
Pin Functions: OPA2328
PIN
TYPE
DESCRIPTION
NAME
NO.
–IN A
2
Input
Inverting input, channel A
+IN A
3
Input
Noninverting input, channel A
–IN B
6
Input
Inverting input, channel B
+IN B
5
Input
Noninverting input, channel B
OUT A
1
Output
Output, channel A
OUT B
7
Output
Output, channel B
V–
4
Power
Negative (lowest) power supply
V+
8
Power
Positive (highest) power supply
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OUT A
1
14
OUT D
±IN A
2
13
±IN D
+IN A
3
12
+IN D
V+
4
11
V±
+IN B
5
10
+IN C
±IN B
6
9
±IN C
OUT B
7
8
OUT C
Not to scale
+IN A
1
–IN A
OUT A
OUT D
–IN D
16
15
14
13
Figure 4-5. OPA4328 PW Package (Preview), 14-Pin TSSOP (Top View)
12
+IN D
V+
2
11
V–
+IN B
3
10
+IN C
–IN B
4
9
–IN C
5
6
7
8
OUT B
EN AB
EN CD
OUT C
Thermal Pad
Not to scale
Figure 4-6. OPA4328 RUM Package (Preview), 16-Pin WQFN (Top View)
Table 4-1. Pin Functions: OPA4328
PIN
NAME
4
NO.
TYPE
DESCRIPTION
PW (TSSOP)
RUM (WQFN)
EN AB
—
6
Input
Enable pin for A and B amplifiers. High = amplifiers A and B are enabled.
EN CD
—
7
Input
Enable pin for C and D amplifiers. High = amplifiers C and D are enabled.
–IN A
2
16
Input
Inverting input, channel A
+IN A
3
1
Input
Noninverting input, channel A
–IN B
6
4
Input
Inverting input, channel B
+IN B
5
3
Input
Noninverting input, channel B
–IN C
9
9
Input
Inverting input, channel C
+IN C
10
10
Input
Noninverting input, channel C
–IN D
13
13
Input
Inverting input, channel D
+IN D
12
12
Input
Noninverting input, channel D
OUT A
1
15
Output
Output, channel A
OUT B
7
5
Output
Output, channel B
OUT C
8
8
Output
Output, channel C
OUT D
14
14
Output
Output, channel D
Thermal Pad
—
Thermal Pad
Power
Connect thermal pad to V–
V–
11
11
Power
Negative (lowest) power supply
V+
4
2
Power
Positive (highest) power supply
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SBOS957D – FEBRUARY 2022 – REVISED DECEMBER 2023
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS
Supply voltage, VS = (V+) – (V–)
Input voltage, all pins
UNIT
–0.3
6
V
(V–) – 0.3
(V+) + 0.3
V
–10
10
Input current (INA+, INA–, INB+, INB–, INSA/B, OUTSA/B/1/2/3)
Output short-circuit(2)
MAX
mA
Continuous Continuous
TA
Operating temperature
–55
150
°C
TJ
Junction temperature
–55
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
Short-circuit to ground, one amplifier per package.
5.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
2000
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Single-supply
VS
Supply
voltage
TA
Specified temperature
Dual-supply
NOM
MAX
UNIT
2.2
5.5
V
±1.1
±2.75
V
–40
125
°C
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SBOS957D – FEBRUARY 2022 – REVISED DECEMBER 2023
5.4 Thermal Information - OPA328
OPA328
THERMAL
METRIC(1)
DBV (SOT-23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
163.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
97.6
°C/W
RθJB
Junction-to-board thermal resistance
62.8
°C/W
ΨJT
Junction-to-top characterization parameter
40.7
°C/W
ΨJB
Junction-to-board characterization parameter
62.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
5.5 Thermal Information - OPA2328
OPA2328
THERMAL METRIC(1)
DGK (VSSOP)
DRG (WSON)
UNIT
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
123.9
165
50.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
63.1
53
50.2
°C/W
RθJB
Junction-to-board thermal resistance
67.4
87
23.4
°C/W
ΨJT
Junction-to-top characterization parameter
15.7
4.9
0.8
°C/W
ΨJB
Junction-to-board characterization parameter
66.6
85
23.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
7.3
°C/W
(1)
6
D (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS957D – FEBRUARY 2022 – REVISED DECEMBER 2023
5.6 Electrical Characteristics
at TA = 25°C, VS = ±1.1 V to ±2.75 V (VS = 2.2 V to 5.5 V), RL = 10 kΩ connected to VS / 2, VCM = VOUT = VS / 2, and min and
max specification established from manufacturing final test (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
OPA2328D, DGK, and DRG
±3
±50
OPA328DBV
±3
±75
OPA328DBV,
OPA2328D, DGK
±0.15
±1
OPA2328DRG
±0.15
±1.5
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift TA = –40°C to +125°C
PSRR
Power-supply rejection
ratio
VS = ±1.1 V to ±2.75 V
±1
±10
VS = ±1.1 V to ±2.75 V, TA = –40°C to +125°C
±15
±40
Channel separation
(dual, quad)
f = dc
140
f = 100 kHz
μV
μV/°C
μV/V
dB
75
INPUT BIAS CURRENT
±0.2
IB
Input bias current
TA = 0°C to 85°C
10
TA = –40°C to +125°C
Input offset current
pA
100
±0.2
IOS
±1
TA = 0°C to 85°C
±1
10
TA = –40°C to +125°C
pA
100
NOISE
Input voltage noise
eN
iN
Input voltage noise
density
Input current noise
f = 0.1 Hz to 10 Hz
3
f = 100 Hz
25
f = 1 kHz
9.8
f = 10 kHz
6.1
f = 10 kHz
0.125
μVPP
nV/√Hz
pA/√Hz
INPUT VOLTAGE
VCM
CMRR
Common-mode voltage
Common-mode
rejection ratio
(V–) – 0.1
(V–) – 0.1 V < VCM <
(V+) + 0.1 V
TA = –40°C to +125°C
(V+) + 0.1
106
120
96
110
V
dB
INPUT CAPACITANCE
ZID
Differential
1 || 4
TΩ || pF
ZICM
Common-mode
1 || 2
TΩ || pF
OPEN-LOOP GAIN
(V–) + 100 mV < VO <
(V+) – 100 mV
AOL
Open-loop voltage gain
(V–) + 200 mV < VO <
(V+) – 200 mV,
RL = 2 kΩ
TA = –40°C to +125°C
TA = –40°C to +125°C
108
132
96
130
106
123
dB
90
FREQUENCY RESPONSE
GBW
Gain-bandwidth product Gain = 100
40
MHz
SR
Slew rate
30
V/μs
tS
Settling time
4-V step, gain = +1
To 0.1%, 1-V step, gain = +1
0.1
To 0.01%, 1-V step, gain = +1
0.18
Overload recovery time VIN × gain > VS
THD+N
Total harmonic
distortion + noise
VO = 1 VRMS, gain = +1, f = 1 kHz
μs
0.5
μs
0.0001
%
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5.6 Electrical Characteristics (continued)
at TA = 25°C, VS = ±1.1 V to ±2.75 V (VS = 2.2 V to 5.5 V), RL = 10 kΩ connected to VS / 2, VCM = VOUT = VS / 2, and min and
max specification established from manufacturing final test (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
5
VS = 2.2 V
RL = 2 kΩ
15
OPA328DBV,
OPA2328D, DGK
Voltage output swing
from both rails
VS = 5.5 V
ISC
Short-circuit current
CLOAD
RO
5
OPA2328DRG
10
RL = 2 kΩ,
OPA328DBV,
OPA2328D, DGK
15
RL = 2 kΩ,
OPA2328DRG
20
Sinking, VS = 5.5 V
–65
mV
mA
Sourcing, VS = 5.5 V
55
Capacitive load drive
Gain = +1
28
pF
Open-loop output
impedance
f = 10 kHz
55
Ω
IO = 0 A
3.8
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 A, TA = –40°C to +125°C
4.5
5.0
mA
SHUTDOWN (OPA328SDBV and OPA4328RUM)
8
IQSD
Quiescent current in
shutdown
All amplifiers disabled
30
ZOFF
Output impedance in
shutdown
All amplifiers disabled
100 || 16
VIH
High-level input voltage Amplifier enabled
VIL
Low-level input voltage
Amplifier disabled
tON
Output enable time
G = 1, VOUT = 0.9 × VS/2, all amplifiers enabled
tOFF
Output disable time
G = 1, VOUT = 0.1 × VS/2, all amplifiers disabled
EN pin input leakage
current
VIH = V+
0.02
VIL = V–
1
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50
µA
GΩ || pF
(V+) – 0.5
V
(V–) + 0.5
V
10
µs
3
µs
µA
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5.7 Typical Characteristics
at TA = 25°C, VS = 5.5 V, VCM = VOUT = mid-supply, CL = 20 pF, and RL = 10 kΩ (unless otherwise noted)
20%
30%
25%
Amplifiers (%)
Amplifiers (%)
15%
10%
20%
15%
10%
5%
5%
0
-25
-20
-15
-10
-5
0
5
10
Offset Voltage (V)
15
20
0
-25
25
-20
-15
-10
-5
0
5
10
Offset Voltage (V)
15
20
25
VS = 2.2 V
Figure 5-1. Offset Voltage Production Distribution
Figure 5-2. Offset Voltage Production Distribution
50
Input Offset Voltage (µV)
Input Offset Voltage (µV)
50
25
0
-25
-50
-1.25
-1
-0.75 -0.5 -0.25 0
0.25 0.5
Common-mode Voltage (V)
0.75
1
25
0
-25
-50
-3
1.25
-2
-1
0
1
Common-mode Voltage (V)
2
3
VS = 2.2 V
Figure 5-3. Offset Voltage vs Common-Mode Voltage
120
140
100
120
80
100
60
80
40
60
20
40
0
20
-20
100m
0
1
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
Figure 5-5. Open-Loop Gain and Phase vs Frequency
160
0.01
140
0.1
120
1
100
10
80
-50
VS = 2.2 V
VS = 5.5 V
-25
0
25
50
Temperature (°C)
75
100
Open-Loop Gain (µV/V)
180
Gain
Phase 160
Open-Loop Gain (dB)
140
Phase ()
Gain (dB)
160
Figure 5-4. Offset Voltage vs Common-Mode Voltage
100
125
Figure 5-6. Open-Loop Gain vs Temperature
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5.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VOUT = mid-supply, CL = 20 pF, and RL = 10 kΩ (unless otherwise noted)
200
0.5
Input Bias Current (pA)
0.3
IB−
IB+
IOS
50
0.2
0.1
0
-0.1
-0.2
-0.3
20
10
5
2
1
0.5
0.2
-0.4
0.1
-0.5
-3 -2.5
-2 -1.5 -1 -0.5 0 0.5 1 1.5
Common-Mode Voltage (V)
2
2.5
0.05
-55
3
Figure 5-7. Input Bias Current vs Common-Mode Voltage
20
45
70
Temperature (C)
95
120
145
30%
25%
Amplifiers (%)
Quiescent Current (mA)
-5
35%
4.25
4
3.75
20%
15%
10%
3.5
3.25
-50
5%
VS = 2.2 V
VS = 5.5 V
-25
0
25
50
Temperature (°C)
75
100
0
-1
125
Figure 5-9. Quiescent Current vs Supply Voltage
60%
30%
50%
25%
40%
20%
30%
20%
-0.5 -0.25
0
0.25
0.5
Positive Input Bias Current (pA)
0.75
1
15%
10%
5%
10%
0
-1
-0.75
Figure 5-10. Positive Input Bias Current Distribution
Amplifiers (%)
Amplifiers (%)
-30
Figure 5-8. Input Bias Current vs Temperature
4.5
-0.75
-0.5 -0.25
0
0.25
0.5
Negative Input Bias Current (pA)
0.75
Figure 5-11. Negative Input Bias Current Distribution
10
IB−
IB+
IOS
100
Input Bias Current (pA)
0.4
1
0
-1
-0.75
-0.5
-0.25
0
0.25
0.5
Bias Current Offset (pA)
0.75
1
Figure 5-12. Input Bias Offset Current Distribution
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5.7 Typical Characteristics (continued)
Common-mode Rejection Ration (dB)
Power Supply Rejection Ratio (µV/V)
10
5
0
-5
-10
-50
160
0.01
140
0.1
120
1
100
-50
-25
0
25
50
Temperature (°C)
75
100
-25
0
125
Figure 5-13. PSRR vs Temperature
25
50
Temperature (°C)
75
100
10
125
Figure 5-14. CMRR vs Temperature
1000
PSRR−
PSRR+
CMRR
120
100
80
60
40
20
0
10m 100m
1
10
100 1k
10k 100k
Frequency (Hz)
1M
Voltage Noise Spectral Density (nV/Hz)
140
Rejection Ratio (dB)
VS = 2.2 V
VS = 5.5 V
Common-mode Rejection Ration (µV/V)
at TA = 25°C, VS = 5.5 V, VCM = VOUT = mid-supply, CL = 20 pF, and RL = 10 kΩ (unless otherwise noted)
500
300
200
100
50
30
20
10
5
3
2
1
100m
10M
Figure 5-15. CMRR and PSRR vs Frequency
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
Figure 5-16. Input Voltage Noise Spectral Density vs Frequency
8
VS = 5.5 V
VS = 2.2 V
Output Voltage (VPP)
Output Voltage (1 V/div)
7
6
5
4
3
2
1
0
1
10
Time (1 s/div)
Figure 5-17. 0.1-Hz to 10-Hz Input Voltage Noise
100
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 5-18. Maximum Output Voltage vs Frequency
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5.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VOUT = mid-supply, CL = 20 pF, and RL = 10 kΩ (unless otherwise noted)
1.2
0
TA = −40C
TA = 25C
TA = 85C
TA = 125C
-0.3
Output Voltage (V)
Output Voltage (V)
0.9
0.6
TA = −40C
TA = 25C
TA = 85C
TA = 125C
-0.6
-0.9
0.3
-1.2
0
0
10
20
30
40
50
Output Current (mA)
60
0
70
10
60
70
Figure 5-19. Output Voltage Swing vs Output Current
Figure 5-20. Output Voltage Swing vs Output Current
2.75
-1.25
TA = −40C
TA = 25C
TA = 85C
TA = 125C
2.5
2.25
Output Voltage (V)
Output Voltage (V)
30
40
50
Output Current (mA)
VV+ = 1.1 V, VV– = –1.1 V, current source load
VV+ = 1.1 V, VV– = –1.1 V, current source load
2
1.75
1.5
TA = −40C
TA = 25C
TA = 85C
TA = 125C
1.25
-1.75
-2.25
-2.75
1
0
10
20
30
40
50
60
70
Output Current (mA)
80
90
0
100
-20
-40
-60
-80
Output Current (mA)
-100
-120
VV+ = 2.75 V, VV– = –2.75 V, current source load
VV+ = 2.75 V, VV– = –2.75 V, current source load
Figure 5-21. Output Voltage Swing vs Output Current
Figure 5-22. Output Voltage Swing vs Output Current
5.5
10000
7000
5000
5
4
3.5
3
2.5
2
VS = 5.5 V
VS = 5.0 V
VS = 4.0 V
VS = 3.0 V
VS = 2.2 V
1.5
1
0.5
0
0
10
20
30
40
50
60
70
Output Current (mA)
80
90
100
Output Impedance ()
4.5
Output Voltage (V)
20
3000
2000
1000
700
500
300
200
100
70
50
30
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
VV+ = 5.5 V, VV– = 0 V, voltage source load
Figure 5-23. Output Voltage Swing vs Output Current
12
Figure 5-24. Open-Loop Output Impedance vs Frequency
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5.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VOUT = mid-supply, CL = 20 pF, and RL = 10 kΩ (unless otherwise noted)
140
120
Open-Loop Gain (dB)
Open-Loop Gain (dB)
120
140
RL = 10 k
RL = 2 k
100
80
60
40
20
0
0.001
100
TA = −40C
TA = 0C
TA = 25C
TA = 85C
TA = 125C
80
60
40
20
0.002
0
0.001
0.005
0.01
0.02 0.03 0.050.07 0.1
Supply Voltage − Output Voltage (V)
0.002
0.005
0.01
0.02 0.03 0.050.07 0.1
Supply Voltage − Output Voltage (V)
RL = 2 kΩ
Figure 5-25. Open-Loop Gain vs Output to Supply Voltage Delta
30
25
Figure 5-26. Open-Loop Gain vs Output to Supply Voltage Delta
70
RISO = 0
RISO = 25
RISO = 50
65
60
RISO = 0
RISO = 25
RISO = 50
Overshoot ()
Overshoot ()
55
20
15
10
50
45
40
35
30
25
5
20
15
0
10
20
30 40 50 70 100
200 300
Capacitance (pF)
10
10
500 700 1000
20
30 40 50 70 100
200 300
Capacitance (pF)
G = –1
G = +1
0.02
0.01
0.005
-80
0.002
0.001
0.0005
-100
2E-5
1E-5
Figure 5-28. Small-Signal Overshoot vs Load Capacitance
0.002
-60
G = −1, RL = 10 k
G = −1, RL = 2 k
G = −1, RL = 600
G = +1, RL = 10 k
G = +1, RL = 2 k
G = +1, RL = 600
-120
-140
100m
Output Amplitude (VRMS)
1
Total Harmonic Distortion + Noise ()
0.1
0.05
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
Figure 5-27. Small-Signal Overshoot vs Load Capacitance
0.0002
0.0001
5E-5
500 700 1000
0.001
0.0007
G = −1, RL = 10 k
G = −1, RL = 2 k
G = −1, RL = 600
G = +1, RL = 10 k
G = +1, RL = 2 k
G = +1, RL = 600
-100
0.0005
0.0004
0.0003
0.0002
0.0001
20
200
2k
-120
20k
Frequency (Hz)
f = 1 kHz
VOUT = 1 VRMS
Figure 5-29. THD+N vs Amplitude
Figure 5-30. THD+N vs Frequency
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5.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VOUT = mid-supply, CL = 20 pF, and RL = 10 kΩ (unless otherwise noted)
60
50
40
Gain (dB)
30
20
10
0
-10
G = −1
G = +1
G = +10
G = +100
-20
-30
-40
100
1k
10k
100k
1M
Frequency (Hz)
10M
100M
G = –1
Figure 5-31. Closed-Loop Gain vs Frequency
Figure 5-32. Small-Signal Step Response
VIN
VOUT
Voltage (5 mV/div)
Voltage (500 mV/div)
VIN
VOUT
Time (200 ns/div)
Time (200 ns/div)
G = +1
G = –1
Figure 5-34. Large-Signal Step Response
Figure 5-33. Small-Signal Step Response
Voltage (500 mV/div)
VIN
VOUT
Time (200 ns/div)
G = +1
Figure 5-35. Large-Signal Step Response
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6 Detailed Description
6.1 Overview
The OPAx328 family features high-speed, precision amplifiers that make this op amp family an excellent
choice for driving high-resolution analog-to-digital converters (ADCs). Low output impedance with flat frequency
characteristics and zero-crossover distortion circuitry enable high linearity over the full input common-mode
range, achieving true rail-to-rail input from a 2.2-V to 5.5-V single supply.
6.2 Functional Block Diagram
V+
OPAx328
Charge
pump
+IN
IN
PMOS
input
pair
OUT
Σ
POR
e-trim™
V
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6.3 Feature Description
6.3.1 Input and ESD Protection
The OPAx328 incorporate internal electrostatic discharge (ESD) protection circuits on all pins. In the case of
input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit input overdrive protection if the
current is limited to 10 mA. Many input signals are inherently current-limited to less than 10 mA; therefore, a
limiting resistor is not required. Figure 6-1 shows how a series input resistor (RIN) can be added to the driven
input to limit the input current. The added resistor contributes thermal noise at the amplifier input; therefore, keep
this value to a minimum in noise-sensitive applications.
V+
–
Amp
+
RIN
VIN
VOUT
IOVERLOAD
10 mA Max
Figure 6-1. Input Current Protection
6.3.2 Rail-to-Rail Input
The OPAx328 feature true rail-to-rail input operation, with supply voltages as low as ±1.1 V (2.2 V). The
design of the OPAx328 amplifiers includes an internal charge-pump that powers the amplifier input stage with
an internal supply rail at approximately 1.6 V greater than the external supply (VS+). This internal supply rail
allows the single differential input pair to operate and remain very linear over a very-wide input common-mode
range. A unique zero-crossover input topology eliminates the input offset transition region typical of many
rail-to-rail, complementary-input-stage operational amplifiers. This topology allows the OPAx328 to provide
excellent common-mode performance (CMRR > 120 dB, typical) over the entire common-mode input range,
which extends 100 mV beyond both power-supply rails. When driving analog-to-digital converters (ADCs), the
highly linear VCM range of the OPAx328 provides maximum linearity and lowest distortion.
6.3.3 Phase Reversal
The OPAx328 op amps are designed to be immune to phase reversal when the input pins exceed the supply
voltages, and thus provide further in-system stability and predictability. Figure 6-2 shows the input voltage
exceeding the supply voltage without any phase reversal.
Voltage (1 V/div)
VIN
VOUT
Time (100 µs/div)
Figure 6-2. No Phase Reversal
6.4 Device Functional Modes
The OPAx328 operational amplifier is operational when power-supply voltages between 2.2 V to 5.5 V are
applied. Devices with an S suffix have shutdown capability.
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7 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
7.1 Application Information
The OPAx328 offer outstanding dc and ac performance. These devices operate with up to a 5.5-V power supply,
and offer an ultra-low input bias current and a 40-MHz bandwidth. These features make the OPAx328 family of
robust operational amplifiers great for both communication and industrial applications.
7.1.1 Capacitive Load and Stability
The OPAx328 are designed for use in high-speed applications for transimpedance amplifiers (TIA) and ADC
input-driving amplifiers. As with all op amps, there can be specific instances where the OPAx328 become
unstable. The particular op-amp circuit configuration, layout, gain, and output loading are some of the factors
to consider when establishing whether an amplifier is stable in operation. An op amp in the unity-gain (1‑V/V)
buffer configuration driving a capacitive load exhibits a greater tendency to become unstable compared to an
amplifier operating at a higher noise gain (see Figure 5-28). The capacitive load, in conjunction with the op-amp
output impedance, creates a pole within the loop gain that degrades the phase margin. The degradation of the
phase margin increases as the capacitive loading increases. When operating in the unity-gain configuration, the
OPAx328 remain stable with a pure capacitive load up to 100 pF.
Figure 7-1 shows one technique to increase the capacitive load drive capability of an amplifier operating in a
unity-gain configuration is to insert a small resistor (RS), typically 10 Ω to 50 Ω, in series with the output. This
resistor significantly reduces the overshoot and ringing associated with large capacitive loads.
–
RS
VOUT
VIN
+
RL
CL
GND
Figure 7-1. Improving Capacitive Load Drive
7.2 Typical Applications
7.2.1 Bidirectional Current-Sensing
This single-supply, low-side, bidirectional current-sensing design example detects load currents from –1 A to
+1 A. The single-ended output spans from 110 mV to 3.19 V. This design uses the OPAx328 because of the low
offset voltage and rail-to-rail input and output. One of the amplifiers is configured as a difference amplifier and
the other amplifier provides the reference voltage.
Figure 7-2 shows the schematic.
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VCC
VREF
VCC
R5
+
U1B
ILOAD
R6
R2
VBUS
+
±
R1
+
VSHUNT
+
RSHUNT
±
VOUT
R3
U1A
RL
VCC
R4
Figure 7-2. Bidirectional Current-Sensing Schematic
7.2.1.1 Design Requirements
This design example has the following requirements:
•
•
•
Supply voltage: 3.3 V
Input: –1 A to +1 A
Output: 1.65 V ±1.54 V (110 mV to 3.19 V)
7.2.1.2 Detailed Design Procedure
The load current, ILOAD, flows through the shunt resistor, RSHUNT, to develop the shunt voltage, VSHUNT. The
shunt voltage is then amplified by the difference amplifier consisting of U1A and R1 through R4. The gain of the
difference amplifier is set by the ratio of R4 to R3. To minimize errors, set R2 = R4 and R1 = R3. The reference
voltage, VREF, is supplied by buffering a resistor divider using U1B. The transfer function is given by Equation 1.
VOUT = VSHUNT ´ GainDiff_Amp + VREF
(1)
where
•
•
•
VSHUNT = ILOAD ´ RSHUNT
R
GainDiff_Amp = 4
R3
VREF = VCC ´
R6
R5 + R6
There are two types of errors in this design: offset and gain. Gain errors are introduced by the tolerance of the
shunt resistor and the ratios of R4 to R3 and, similarly, R2 to R1. Offset errors are introduced by the voltage
divider (R5 and R6) and how closely the ratio of R4 / R3 matches R2 / R1. The latter value affects the CMRR of
the difference amplifier, ultimately translating to an offset error.
The value of VSHUNT is the ground potential for the system load because VSHUNT is a low-side measurement.
Therefore, a maximum value must be placed on VSHUNT. In this design, the maximum value for VSHUNT is set
to 100 mV. Equation 2 calculates the maximum value of the shunt resistor given a maximum shunt voltage of
100 mV and maximum load current of 1 A.
RSHUNT(Max) =
18
VSHUNT(Max) 100 mV
= 100 mW
=
ILOAD(Max)
1A
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The tolerance of RSHUNT is directly proportional to cost. For this design, a shunt resistor with a tolerance of 0.5%
is selected. If greater accuracy is required, select a 0.1% resistor or better.
The load current is bidirectional; therefore, the shunt voltage range is –100 mV to +100 mV. This voltage is
divided down by R1 and R2 before reaching the operational amplifier, U1A. Make sure that the voltage present
at the noninverting node of U1A is within the common-mode range of the device. Therefore, use an operational
amplifier, such as the OPAx328, that has a common-mode range that extends below the negative supply
voltage. Finally, to minimize offset error, the OPAx328 have a typical offset voltage of merely ±3 µV (±25 µV
maximum).
Given a symmetric load current of –1 A to +1 A, the voltage divider resistors (R5 and R6) must be equal. To
be consistent with the shunt resistor, a tolerance of 0.5% is selected. To minimize power consumption, 10‑kΩ
resistors are used.
To set the gain of the difference amplifier, the common-mode range and output swing of the OPAx328 must
be considered. Equation 3 and Equation 4 depict the typical common-mode range and maximum output swing,
respectively, of the OPAx328 given a 3.3-V supply.
–100 mV < VCM < 3.4 V
(3)
100 mV < VOUT < 3.2 V
(4)
The gain of the difference amplifier can now be calculated as shown in Equation 5:
GainDiff_Amp =
VOUT_Max - VOUT_Min
3.2 V - 100 mV
V
= 15.5
=
V
100 mW ´ [1 A - (- 1A)]
RSHUNT ´ (IMAX - IMIN)
(5)
The resistor value selected for R1 and R3 is 1 kΩ. A value of 15.4 kΩ is selected for R2 and R4 because this
number is the nearest standard value. Therefore, the calculated gain of the difference amplifier is 15.4 V/V.
The gain error of the circuit primarily depends on R1 through R4. As a result of this dependence, 0.1% resistors
are selected. This configuration reduces the likelihood that the design requires a two-point calibration. A simple
one-point calibration, if desired, removes the offset errors introduced by the 0.5% resistors.
7.2.1.3 Application Curve
Output Voltage (V)
3.30
1.65
0
-1.0
-0.5
0
Input Current (A)
0.5
1.0
Figure 7-3. Bidirectional Current-Sensing Circuit Performance: Output Voltage vs Input Current
7.2.2 Transimpedance Amplifier
Wide gain bandwidth, low input bias current, low input voltage, and low current noise make the OPAx328
excellent wideband photodiode transimpedance amplifiers. Low-voltage noise is important because photodiode
capacitance causes the effective noise gain of the circuit to increase at high frequency.
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Figure 7-4 shows that the key elements to a transimpedance design are the:
•
•
•
Expected diode capacitance (CD), including the parasitic input common-mode voltage and differential-mode
input capacitance
Desired transimpedance gain (RF)
Gain-bandwidth (GBW) = 40 MHz
With these three variables set, the feedback capacitor (CF) value can be set to control the frequency response.
CF includes the stray capacitance of RF, which is 0.2 pF for a typical surface-mount resistor.
CF
RF
10 M
V+
–
CD
Amp
VOUT
+
V–
NOTE: CF is optional to prevent gain peaking, and includes the stray capacitance of RF.
Figure 7-4. Dual-Supply Transimpedance Amplifier
For an optimized frequency response, use Equation 6 to set the feedback pole:
1
=
2pRFCF
GBW
4pRFCD
(6)
Equation 7 calculates the bandwidth:
f-3dB =
GBW
2pRFCD
(Hz)
(7)
For single-supply applications, the +IN input can be biased with a positive dc voltage to allow the output to reach
true zero when the photodiode is not exposed to any light, and respond without the added delay that results from
coming out of the negative rail. Figure 7-5 shows this configuration. This bias voltage also appears across the
photodiode, providing a reverse bias for faster operation.
CF
RF
10 M
V+
–
Amp
VBIAS
VOUT
+
NOTE: CF is optional to prevent gain peaking, and includes the stray capacitance of RF.
Figure 7-5. Single-Supply Transimpedance Amplifier
For more information, see the Compensate Transimpedance Amplifiers Intuitively application report.
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7.3 Power Supply Recommendations
The OPAx328 are specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V); many specifications apply
from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in Section 5.7.
CAUTION
Supply voltages greater than 6 V can permanently damage the device; see Section 5.1.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section 7.4.
7.4 Layout
7.4.1 Layout Guidelines
The OPA328 is a wideband amplifier. To realize the full operational performance of this device, use good,
high-frequency PCB layout practices. Connect the bypass capacitors between each supply pin and ground, as
close to the device as possible. Design the bypass capacitor traces for minimum inductance.
7.4.2 Layout Example
+
VIN A
+
VIN B
VOUT A
RG
VOUT B
RG
RF
RF
(Schematic Representation)
Place components
close to device and to
each other to reduce
parasitic errors.
VOUT A
VS+
OUT A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
V+
RF
VOUT B
GND
-IN A
OUT B
+IN A
-IN B
RF
RG
VIN A
GND
RG
V–
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
VS–
+IN B
Ground (GND) plane on another layer
VIN B
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible.
Figure 7-6. Operational Amplifier Board Layout for Noninverting Configuration
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8 Device and Documentation Support
8.1 Device Support
8.1.1 Development Support
8.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
8.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Design tools and simulation web page, TINA-TI simulation software offers
extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments
offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.
8.1.1.3 DIP-Adapter-EVM
Speed up your op amp prototyping and testing with the DIP-Adapter-EVM, which provides a fast, easy and
inexpensive way to interface with small, surface-mount devices. Connect any supported op amp using the
included Samtec terminal strips or wire them directly to existing circuits. The DIP-Adapter-EVM kit supports
the following industry-standard packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT-23-6,
SOT-23-5 and SOT-23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6).
8.1.1.4 DIYAMP-EVM
The DIYAMP-EVM is a unique evaluation module (EVM) that provides real-world amplifier circuits, enabling the
user to quickly evaluate design concepts and verify simulations. This EVM is available in three industry-standard
packages (SC70, SOT23, and SOIC) and 12 popular amplifier configurations, including amplifiers, filters, stability
compensation, and comparator configurations for both single and dual supplies.
8.1.1.5 Filter Design Tool
The filter design tool is a simple, powerful, and easy-to-use active filter design program. The filter design tool
allows the user to create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web-based tool from the Design tools and simulation web page, the filter design tool allows the
user to design, optimize, and simulate complete multistage active filter solutions within minutes.
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8.2 Documentation Support
8.2.1 Related Documentation
The following documents are recommended as a reference for this device, and available for download at
www.ti.com:
•
•
•
•
•
•
•
•
Texas Instruments, Software Pacemaker Detection Design Guide
Texas Instruments, TIDA-00378 Schematic and Block Diagram
Texas Instruments, PM2.5/PM10 Particle Sensor Analog Front-End for Air Quality Monitoring Design
Texas Instruments, QFN/SON PCB Attachment
Texas Instruments, Quad Flatpack No-Lead Logic Packages
Texas Instruments, Compensate Transimpedance Amplifiers Intuitively
Texas Instruments, Noise Analysis of FET Transimpedance Amplifiers
Texas Instruments, Noise Analysis for High-Speed Op Amps
8.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.5 Trademarks
e‑trim™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
All trademarks are the property of their respective owners.
8.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
8.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2023) to Revision D (December 2023)
Page
• Changed OPA2328 D (SOIC, 8) and DRG (WSON, 8) package status from preview to production data
(active) and added associated content ..............................................................................................................1
Changes from Revision B (November 2022) to Revision C (May 2023)
Page
• Changed OPA328 DBV (SOT-23, 5) package from advanced information (preview) to production data
(active) ...............................................................................................................................................................1
• Added OPA4328 PW (TSSOP, 14) and RUM (WQFN, 16) pin configurations and pin functions table.............. 3
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: OPA328 OPA2328
23
OPA328, OPA2328
SBOS957D – FEBRUARY 2022 – REVISED DECEMBER 2023
www.ti.com
Changes from Revision A (June 2022) to Revision B (November 2022)
Page
• Changed OPA328 device status from preview to advanced information............................................................1
• Added junction temperature to Absolute Maximum Ratings ..............................................................................5
Changes from Revision * (February 2022) to Revision A (June 2022)
Page
• Changed OPA2328 from advanced information (preview) to production data (active).......................................1
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: OPA328 OPA2328
PACKAGE OPTION ADDENDUM
www.ti.com
5-Dec-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
OPA2328DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2K6S
Samples
OPA2328DGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2K6S
Samples
OPA328DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
OP328
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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