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OPA2333-HT
SBOS483I – JULY 2009 – REVISED MAY 2015
OPA2333-HT 1.8-V Micropower CMOS Operational Amplifier Zero-Drift Series
1 Features
•
•
•
•
•
•
•
•
•
•
•
1
•
•
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•
3 Description
The OPA2333 series of CMOS operational amplifiers
uses a proprietary auto-calibration technique to
simultaneously provide very low offset voltage and
near-zero drift over time and temperature(1). These
miniature,
high-precision,
low-quiescent-current
amplifiers offer high-impedance inputs that have a
common-mode range 100 mV beyond the rails, and
rail-to-rail output that swings within 150 mV of the
rails. Single or dual supplies as low as 1.8 V (±0.9 V)
and up to 5.5 V (±2.75 V) may be used. They are
optimized for low-voltage single-supply operation.
Low Offset Voltage: 26 μV (Maximum)
0.01-Hz to 10-Hz Noise: 1.5 μVPP
Quiescent Current: 50 μA
Single-Supply Operation
Supply Voltage: 1.8 V to 5.5 V
Rail-to-Rail Input and Output
Supports Extreme Temperature Applications
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Extreme (–55°C to 210°C)
Temperature Range
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Texas Instruments' high temperature products use
highly optimized silicon (die) solutions with design
and process enhancements to maximize
performance over extended temperatures.
The OPA2333 offers excellent common-mode
rejection ratio (CMRR) without the crossover
associated with traditional complementary input
stages. This design results in superior performance
for driving analog-to-digital converters (ADCs) without
degradation of differential linearity.
Device Information(2)
PART NUMBER
PACKAGE
OPA2333-HT
NOTE: Custom temperature ranges available
4.90 mm × 3.91 mm
CFP (8)
6.90 mm × 5.65 mm
CFP (8)
7.035 mm × 5.75 mm
CDIP SB (8)
18.55 mm × 7.49 mm
(1) See Electrical Characteristics for
performance degradation over temperature.
(2) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
BODY SIZE (NOM)
SOIC (8)
Down-Hole Drilling
High Temperature Environments
Typical Application
V+
RS2
RS3
IRS2
470
VRS2
IRS3
4.7
10 k
R4
VRS3
C7
2200 pF
R5
A2
+
V+
200
+
330
Q2
Q1
A1
R3
VIN
+
±
1000 pF
C6
10 k
VRS1
R2
RS1
2k
IRS1
VLOAD
RLOAD
ILOAD
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2333-HT
SBOS483I – JULY 2009 – REVISED MAY 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagrams ..................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Applications ............................................... 15
8.3 System Examples ................................................... 20
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (November 2013) to Revision I
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Removed Ordering Information table .................................................................................................................................... 1
•
Moved temperature range from Electrical Characteristics table to the Absolute Maximum Ratings and
Recommended Operating Conditions tables ......................................................................................................................... 5
Changes from Revision G (September 2012) to Revision H
•
2
Page
Changed Operating Life Derating Chart ................................................................................................................................. 8
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SBOS483I – JULY 2009 – REVISED MAY 2015
5 Pin Configuration and Functions
D, JD, or HKJ Package
8-Pin SOIC, CDIP SB, or CFP
Top View
OUT A
-IN A
+IN A
V-
1
8
2
7
3
6
4
5
HKQ Package
8-Pin CFP
Top View
V+
OUT B
-IN B
+IN B
1
8
OUT A
V+
OUT B
-IN A
-IN B
+IN A
V-
+IN B
5
4
HKQ as formed or HKL mounted dead bug
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
OUT A
O
Analog output channel A
2
–IN A
I
Inverting analog input channel A
3
+IN A
I
Noninverting analog input channel A
5
+IN B
I
Noninverting analog input channel B
6
–IN B
I
Inverting analog input channel B
4
V–
—
Negative (lowest) power supply
7
OUT B
O
Analog output channel B
8
V+
—
Positive (highest) power supply
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|
|
|
962 mm
OUT A
V+
-IN A
-IN B
+IN A
V-
1490 mm
|
38 mm
OUT B
|
+IN B
|
38 mm
Table 1. Bare Die Information
DIE THICKNESS
BACKSIDE FINISH
BACKSIDE
POTENTIAL
BOND PAD
METALLIZATION COMPOSITION
15 mils.
Silicon with backgrind
V-
Al-Si-Cu (0.5%)
Table 2. Bond Pad Coordinates
4
DESCRIPTION
PAD NUMBER
A
B
C
D
OUT A
1
21.20
1288.50
97.20
1364.50
–IN A
2
21.20
923.65
97.20
999.65
+IN A
3
21.20
533.05
97.20
609.05
V–
4
31.30
172.20
107.30
248.20
+IN B
5
864.80
162.25
940.80
238.25
–IN B
6
864.80
552.65
940.80
628.65
OUT B
7
864.80
897.10
940.80
973.10
V+
8
854.70
1280.45
930.70
1356.45
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
7
V
(V+) + 0.3
V
Supply voltage
Signal input terminals, voltage
(2)
–0.3
Output short circuit (3)
Continuous
Operating temperature
Junction temperature
JD, HKJ, HKQ packages
–55
210
D package
–55
175
JD, HKJ, HKQ packages
210
D package
175
Storage temperature, Tstg
(1)
(2)
(3)
–65
°C
°C
210
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less.
Short circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage, VS = (V+) – (V–)
Operating temperature
MIN
NOM
MAX
1.8 (±0.9)
5 (±2.5)
5.5 (±2.75)
UNIT
V
JD, HKJ, HKQ packages
–55
210
D package
–55
175
°C
6.4 Thermal Information
OPA2333-HT
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal
resistance (2)
RθJC(top)
Junction-to-case (top) thermal
resistance
JD
(CDIP SB)
HKJ
(CFP)
HKQ
(CFP)
D
(SOIC)
8 PINS
8 PINS
8 PINS
8 PINS
High-K board (3), no airflow
—
—
—
117.5
No airflow
—
—
—
—
UNIT
°C/W
53.8
57.7
to ceramic side of case
—
—
15.2
62.0
—
to top of case lid (metal side of case)
—
—
—
—
76.0
61.0
151.6
57.7
°C/W
°C/W
RθJB
Junction-to-board thermal
resistance
ψJT
Junction-to-top characterization parameter
—
—
—
19.4
°C/W
ψJB
Junction-to-board characterization parameter
—
—
—
57.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
26.7
15.2
56.9
—
°C/W
(1)
(2)
(3)
High-K board without underfill
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The intent of RθJA specification is solely for a thermal performance comparison of one package to another in a standardized
environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
JED51-7, high effective thermal conductivity test board for leaded surface mount packages
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6.5 Electrical Characteristics
VS = 1.8 V to 5.5 V, TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2 (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2
10
UNIT
OFFSET VOLTAGE
TA = 25°C
VOS
Input offset voltage
VS = 5 V
TA = –55°C to 125°C
22
TA = –55°C to 175°C (1)
26
TA = –55°C to 210°C (2)
dVOS/dT
Input Offset Voltage
Temperature Drift
VS = 5 V
26
TA = –55°C to 125°C
0.02
TA = –55°C to 175°C (1)
0.05
TA = –55°C to 210°C (2)
0.05
TA = –55°C to 125°C
PSRR
Input Offset Voltage vs
Power Supply
VS = 1.8 V to 5.5 V
μV
μV/°C
1
6
TA = –55°C to 175°C (1)
1.2
8
(2)
1.7
11
±70
±200
TA = –55°C to 210°C
μV
μV/V
INPUT BIAS CURRENT
TA = 25°C
IB
Input bias current
IOS
Input offset current
TA = –55°C to 125°C
±150
TA = –55°C to 175°C
±1250
TA = –55°C to 210°C
±5300
TA = –55°C to 125°C
±140
TA = –55°C to 175°C
±700
TA = –55°C to 210°C
±10600
pA
±400
pA
NOISE
TA = –55°C to 125°C
f = 0.01 Hz to 1 Hz
Input Noise Voltage
f = 0.1 Hz to 10 Hz
in
Input Noise Current Density
f = 10 Hz
0.3
TA = –55°C to 175°C (1)
1
TA = –55°C to 210°C (2)
1
TA = –55°C to 125°C
1.1
TA = –55°C to 175°C (1)
1.5
TA = –55°C to 210°C (2)
1.5
TA = 25°C
100
μVPP
μVPP
fA/√Hz
INPUT VOLTAGE RANGE (3)
Common mode voltage
range
VCM
TA = –55°C to 125°C
(V–) – 0.1
(V+) + 0.1
TA = –55°C to 175°C
(V–) – 0.25
(V+) + 0.25
TA = –55°C to 210°C
(V–) – 0.25
TA = –55°C to 125°C
CMRR
Common-Mode Rejection
Ratio
(V–) – 0.1 V < VCM < (V+) +
0.1 V
102
V
(V+) + 0.25
130
TA = –55°C to 175°C
101
TA = –55°C to 210°C
91
dB
INPUT CAPACITANCE
Differential
Common mode
TA = –55°C to 125°C
2
TA = –55°C to 175°C
4.25
TA = –55°C to 210°C
4.25
TA = –55°C to 125°C
4
TA = –55°C to 175°C
12.25
TA = –55°C to 210°C
12.25
pF
pF
OPEN-LOOP GAIN
TA = –55°C to 125°C
AOL
(1)
(2)
(3)
6
Open-loop voltage gain
(V–) + 100 mV < VO < (V+) –
100 mV, RL = 10 kΩ
104
130
TA = –55°C to 175°C (1)
93
110
TA = –55°C to 210°C (2)
85
93
dB
Minimum and maximum parameters are characterized for operation at TA = 175°C, but may not be production tested at that
temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.
Minimum and maximum parameters are characterized for operation at TA = 210°C, but may not be production tested at that
temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.
The OPA2333-HT is not intended to be used as a comparator due to its limited differential input range capability.
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Electrical Characteristics (continued)
VS = 1.8 V to 5.5 V, TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2 (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
Slew rate
CL = 100 pF
G=1
TA = –55°C to 125°C
350
TA = –55°C to 175°C
350
TA = –55°C to 210°C
350
TA = –55°C to 125°C
0.16
TA = –55°C to 175°C
0.25
TA = –55°C to 210°C
0.25
kHz
V/μs
OUTPUT
TA = 25°C
Voltage output swing from
rail
30
TA = –55°C to 125°C
RL = 10 kΩ
85
TA = –55°C to 175°C (1)
110
TA = –55°C to 210°C (2)
ISC
Short-circuit current
TA = 25°C
Open-loop output
impedance (4)
f = 350 kHz, IO = 0
50
mV
150
±5
mA
2
kΩ
POWER SUPPLY
VS
Specified voltage range
TA = –55°C to 210°C (2)
1.8
TA = 25°C
IQ
Quiescent current per
amplifier
IO = 0
TA = –55°C to 125°C
TA = –55°C to 175°C (1)
TA = –55°C to 210°C (2)
Turnon time
(4)
VS = 5 V
5.5
17
TA = 25°C
V
25
30
35
40
50
80
100
μA
μs
See Typical Characteristics.
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Estimated Life (Hours)
1000000
100000
Electromigration Fail Mode
10000
1000
110
120
130
140
150
160
170
180
190
200
210
Continuous TJ (°C)
(1)
See datasheet for absolute maximum and minimum recommended operating conditions.
(2)
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3)
The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
(4)
This device is qualified for 1000 hours of continuous operation at maximum rated temperature.
Figure 1. OPA2333SKGD1 and OPA2333HD Operating Life Derating Chart
8
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6.6 Typical Characteristics
- 10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
10
0
0.0025
0.0050
0.0075
0.0100
0.0125
0.0150
0.0175
0.0200
0.0225
0.0250
0.0275
0.0300
0.0325
0.0350
0.0375
0.0400
0.0425
0.0450
0.0475
0.0500
Population
Population
At TA = 25°C, VS = 5 V, and CL = 0 pF (unless otherwise noted).
Offset Voltage (µV)
Offset Voltage Drift (µV/ C)
Figure 3. Offset Voltage Drift Production Distribution
250
140
100
200
120
80
150
100
60
100
40
50
20
0
40
- 50
20
- 100
0
0
- 20
100
10
1k
10k
100k
CMRR (dB)
120
Phase (° )
AOL (dB)
Figure 2. Offset Voltage Production Distribution
80
60
1
1M
10
100
Frequency (Hz)
1k
10k
100k
Figure 4. Open−Loop Gain vs Frequency
Figure 5. CMMR vs Frequency
3
120
VS = ±2.75V
VS = ±0.9V
+PSRR
2
100
Output Swing (V)
PSRR (dB)
- PSRR
80
60
40
- 40° C
1
+25° C
+125° C
0
+25° C
- 40° C
-1
+125° C
+25° C
-2
20
- 40° C
-3
0
1
10
100
1k
1M
Frequency (Hz)
10k
100k
1M
0
1
2
3
4
5
6
7
8
9
10
Frequency (Hz)
Output Current (mA)
Figure 6. PSRR vs Frequency
Figure 7. Output Voltage Swing vs Output Current
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Typical Characteristics (continued)
100
200
80
60
VS = 5.5V
VS = 1.8V
- IB
100
40
VS = 5V
20
- IB
50
IB (pA)
IB (pA)
150
- IB
0
- 20
0
+IB
- 50
- 40
- 100
- 60
+IB
- 80
+I B
- 150
- 200
- 100
1
0
2
3
4
5
- 25
- 50
0
Common−Mode Voltage (V)
25
50
75
100
125
Temperature (°C)
Figure 8. Input Bias Current vs Common−Mode Voltage
Figure 9. Input Bias Current vs Temperature
G=1
RL = 10kΩ
Output Voltage (1V/div)
IQ (mA)
60
40
20
0
-55
-25
0
25
50
75
100
125
150
175
200
210
Time (50µs/div)
Temperature (°C)
Figure 11. Large−Signal Step Response
Figure 10. Quiescent Current vs Temperature
POSITIVE OVER- VOLTAGE RECOVERY
Output Voltage (50mV/div)
2V/div
G = +1
RL = 10kΩ
0
Input
Output
1 0kΩ
1V/div
+2 .5V
1 kΩ
0
OPA2333
−2.5V
Time (5µs/div)
Time (50µs/div)
Figure 12. Small−Signal Step Response
10
Figure 13. Positive Overvoltage Recovery
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Typical Characteristics (continued)
NEGATIVE OVER- VOLTAGE RECOVERY
600
4V Step
500
Settling Time (µs)
1V/div
2V/div
Input
0
0
10k Ω
400
300
200
0.001%
+ 2.5V
1kΩ
100
Output
O PA2333
0.01%
0
− 2.5V
10
1
100
Time (50µs/div)
Gain (dB)
Figure 14. Negative Overvoltage Recovery
Figure 15. Settling Time vs Closed−Loop Gain
40
35
25
500nV/div
Overshoot (%)
30
20
15
10
5
0
100
1000
1s/div
Load Capacitance (pF)
Figure 17. 0.1-Hz to 10-Hz Noise
Figure 16. Small−Signal Overshoot vs Load Capacitance
Voltage Noise (nV//Hz)
1000
1000
Continues with no 1/f (flicker) noise.
Current Noise
100
100
Voltage Noise
Current Noise (fA//Hz)
10
10
10
1
10
100
1k
10k
Frequency (Hz)
Figure 18. Current and Voltage Noise Spectral Density vs Frequency
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7 Detailed Description
7.1 Overview
The OPA2333 is a Zero-Drift, low-power, rail-to-rail input and output dual operational amplifier. The device
operates from 1.8 V to 5.5 V, is unity-gain stable, and is suitable for a wide range of general-purpose
applications. The Zero-Drift architecture provides low offset voltage and near zero offset voltage drift.
7.2 Functional Block Diagrams
V+
+IN A
+
OUT A
±IN A
±
V±
V+
+IN B
+
OUT B
±IN B
±
V±
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Figure 19. Functional Block Diagram for A and B Amps
7.3 Feature Description
The OPA2333 is unity-gain stable and free from unexpected output phase reversal. It uses a proprietary autocalibration technique to provide low offset voltage and very low drift over time and temperature. For lowest offset
voltage and precision performance, circuit layout and mechanical conditions should be optimized. Avoid
temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from
connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by ensuring they
are equal on both input terminals. Other layout and design considerations include: (5)
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals)
• Thermally isolate components from power supplies or other heat sources
• Shield operational amplifier and input circuitry from air currents, such as cooling fans
Following these guidelines will reduce the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltages of 0.1 μV/°C or higher, depending on materials used.
7.3.1 Operating Voltage
The OPA2333 operational amplifier operates over a power-supply range of 1.8 V to 5.5 V (±0.9 V to
±2.75 V). Supply voltages higher than 7 V (absolute maximum) can permanently damage the device. Parameters
that vary over supply voltage or temperature are shown in Typical Characteristics.
(5)
At TA = 25°C (unless otherwise noted).
12
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Feature Description (continued)
7.3.2 Input Voltage
The OPA2333 input common-mode voltage range extends 0.1 V beyond the supply rails. The OPA2333 is
designed to cover the full range without the troublesome transition region found in some other rail-to-rail
amplifiers.
Normally, input bias current is about 70 pA; however, input voltages exceeding the power supplies can cause
excessive current to flow into or out of the input pins. Momentary voltages greater than the power supply can be
tolerated if the input current is limited to 10 mA. This limitation is easily accomplished with an input resistor (see
Figure 20).
+5V
IOVE R L OAD
10mA max
V OUT
OPA2333
VIN
5kΩ
Copyright © 2016, Texas Instruments Incorporated
Current-limiting resistor required if input voltage exceeds supply rails by ≥ 0.5 V
Figure 20. Input Current Protection
7.3.3 Internal Offset Correction
The OPA2333 operational amplifier uses an auto-calibration technique with a time-continuous 350-kHz
operational amplifier in the signal path. This amplifier is zero corrected every 8 μs using a proprietary technique.
Upon power up, the amplifier requires approximately 100 μs to achieve specified VOS accuracy. This design has
no aliasing or flicker noise.
7.3.4 Achieving Output Swing to the Operational Amplifier Negative Rail
Some applications require output voltage swings from 0 V to a positive full-scale voltage (such as 2.5 V) with
excellent accuracy. With most single-supply operational amplifiers, problems arise when the output signal
approaches 0 V, near the lower output swing limit of a single-supply operational amplifier. A good single-supply
operational amplifier may swing close to single-supply ground, but will not reach ground. The output of the
OPA2333 can be made to swing to ground, or slightly below, on a single-supply power source. To do so requires
the use of another resistor and an additional, more negative, power supply than the operational amplifier
negative supply. A pulldown resistor may be connected between the output and the additional negative supply to
pull the output down below the value that the output would otherwise achieve (see Figure 21).
V+ = +5V
VOUT
OPA2333
VIN
R P = 20kΩ
Op Amp V− = Gnd
−5V
Additional
Negative
S upply
Copyright © 2016, Texas Instruments Incorporated
Figure 21. VOUT Range to Ground
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Feature Description (continued)
The OPA2333 has an output stage that allows the output voltage to be pulled to its negative supply rail, or
slightly below, using the technique previously described. This technique only works with some types of output
stages. The OPA2333 has been characterized to perform with this technique; however, the recommended
resistor value is approximately 20 kΩ.
NOTE
This configuration will increase the current consumption by several hundreds of
microamps.
Accuracy is excellent down to 0 V and as low as –2 mV. Limiting and nonlinearity occurs below –2 mV, but
excellent accuracy returns as the output is again driven above –2 mV. Lowering the resistance of the pulldown
resistor allows the operational amplifier to swing even further below the negative rail. Resistances as low as 10
kΩ can be used to achieve excellent accuracy down to –10 mV.
7.4 Device Functional Modes
The OPA2333 device has a single functional mode. The device is powered on as long as the power supply
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
14
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA2333 family is a unity-gain stable, precision operational amplifier with very low offset voltage drift; these
devices are also free from output phase reversal. Applications with noisy or high-impedance power supplies
require decoupling capacitors close to the device power-supply pins. In most cases, 0.1-μF capacitors are
adequate.
8.2 Typical Applications
8.2.1 High-Side Voltage-to-Current (V-I) Converter
The circuit shown in Figure 22 is a high-side voltage-to-current (V-I) converter. It translates in input voltage of 0 V
to 2 V to and output current of 0 mA to 100 mA. Figure 23 shows the measured transfer function for this circuit.
The low offset voltage and offset drift of the OPA2333 facilitate excellent dc accuracy for the circuit.
V+
RS2
RS3
IRS2
470
VRS2
IRS3
4.7
10 k
R4
VRS3
C7
2200 pF
R5
A2
+
V+
200
+
330
Q2
Q1
A1
R3
VIN
+
±
1000 pF
C6
10 k
VRS1
R2
RS1
2k
IRS1
VLOAD
RLOAD
ILOAD
Copyright © 2016, Texas Instruments Incorporated
Figure 22. High-Side Voltage-to-Current (V-I) Converter
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Typical Applications (continued)
8.2.1.1 Design Requirements
The design requirements are as follows:
• Supply Voltage: 5-V DC
• Input: 0-V to 2-V DC
• Output: 0-mA to 10-mA DC
8.2.1.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, and the three
current sensing resistors, RS1, RS2, and RS3. The relationship between VIN and RS1 determines the current that
flows through the first stage of the design. The current gain from the first stage to the second stage is based on
the relationship between RS2 and RS3.
For a successful design, pay close attention to the DC characteristics of the operational amplifier chosen for the
application. To meet the performance goals, this application benefits from an operational amplifier with low offset
voltage, low temperature drift, and rail-to-rail output. The OPA2333 CMOS operational amplifier is a highprecision, 5-µV offset, 0.05-μV/°C drift amplifier optimized for low-voltage, single-supply operation with an output
swing to within 50 mV of the positive rail. The OPA2333 family uses chopping techniques to provide low initial
offset voltage and near-zero drift over time and temperature. Low offset voltage and low drift reduce the offset
error in the system, making these devices appropriate for precise DC control. The rail-to-rail output stage of the
OPA2333 ensures that the output swing of the operational amplifier is able to fully control the gate of the
MOSFET devices within the supply rails.
See TIPD102 for a detailed error analysis, design procedure, and additional measured results.
8.2.1.3 Application Curve
0.1
Load
Output Current (A)
0.075
0.05
0.025
0
0
0.5
1
Input Voltage (V)
1.5
2
D001
Figure 23. Measured Transfer Function for High-Side V-I Converter
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Typical Applications (continued)
8.2.2 Precision, Low-Level Voltage-to-Current (V-I) Converter
The circuit shown in Figure 24 is a precision, low-level voltage-to-current (V-I) converter. The converter translates
in input voltage of 0 V to 5 V and output current of 0 µA to 5 µA. Figure 25 shows the measured transfer function
for this circuit. The low offset voltage and offset drift of the OPA2333 facilitate excellent dc accuracy for the
circuit. Figure 26 shows the calibrated error for the entire range of the circuit.
R3 100 k
C1 10 nF
R4 100 k
5V
VOUT_OPA
1/2
OPA2333
5V
+R1
+
+
U2
INA326
R1
40.2 k
Rset
100 k
VOUT_INA
R1
±
VIN
RLOAD
IOUT
R2
R2
200 k
C2 1 nF
+
A
AM1
Copyright © 2016, Texas Instruments Incorporated
Figure 24. Low-Level, Precision V-I Converter
8.2.2.1 Design Requirements
The design requirements are as follows:
• Supply Voltage: 5-V DC
• Input: 0-V to 5-V DC
• Output: 0-μA to 5-μA DC
8.2.2.2 Detailed Design Procedure
The V-I transfer function of the circuit is based on the relationship between the input voltage, VIN, RSET, and the
instrumentation amplifier (INA) gain. During operation, the input voltage divided by the INA gain appears across
the set resistor in Equation 1:
VSET = VIN/GINA
(1)
The current through RSET must flow through the load, so IOUT is VSET / RSET. IOUT remains a well-regulated current
as long as the total voltage across RSET and RLOAD does not violate the output limits of the operational amplifier
or the input common-mode limits of the INA. The voltage across the set resistor (VSET) is the input voltage
divided by the INA gain (that is, VSET = 1 V / 10 = 0.1 V). The current is determined by VSET and RSET shown in
Equation 2:
IOUT = VSET / RSET = 0.1 V / 100 kΩ = 1 μA
(2)
See TIPD107 for a detailed error analysis, design procedure, and additional measured results.
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Typical Applications (continued)
8.2.2.3 Application Curves
100
Measured Output Current Error (pA)
Output Current (µA)
0.1
0.075
0.05
0.025
0
0
80
60
40
20
0
–20
–40
–60
–80
–100
1
3
2
Input Voltage (V)
5
4
0
1
3
4
2
Desired Output Current, Iout_desired (µA)
D002
Figure 25. Measured Transfer Function for Low-Level
Precision V-I
5
D002
Figure 26. Calibrated Output Error for Low-Level V-I
8.2.3 Composite Amplifier
The circuit shown in Figure 27 is a composite amplifier used to drive the reference on the ADS8881. The
OPA2333 provides excellent dc accuracy, and the THS4281 allows the output of the circuit to respond quickly to
the transient current requirements of a typical SAR data converter reference input. The ADS8881 system was
optimized for THD and achieved a measured performance of –110 dB. The linearity of the ADC is shown
Figure 28.
REFERENCE DRIVE CIRCUIT
20k
1µF
THS4281
+
-
1k
AVDD
+
0.2
1µF
AVDD
10µF
REF5045
1k
+
1/2
+
OPA2333
AVDD
Vout
Vin
Temp
1µF
Trim Gnd
1µF
1K
1K
AVDD
AVDD
VIN+
THS4521
+ + -
VCM
-
10
REFP AVDD
AINP
V+
10nF
+
AINM
10
GND
CONVST
+
VIN-
CONVST
ADS8881
1K
1K
INPUT DRIVER
18-Bit 1MSPS
SAR ADC
Figure 27. Composite Amplifier Reference Driver Circuit
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Typical Applications (continued)
8.2.3.1 Design Requirements
The design requirements for this block design are:
• System Supply Voltage: 5-V DC
• ADC Supply Voltage: 3.3-V DC
• ADC Sampling Rate: 1 MSPS
• ADC Reference Voltage (VREF): 4.5-V DC
• ADC Input Signal: A differential input signal with amplitude of Vpk = 4.315 V (–0.4 dBFS to avoid clipping) and
frequency, fIN = 10 kHz are applied to each differential input of the ADC
8.2.3.2 Detailed Design Procedure
The two primary design considerations to maximize the performance of a high-resolution SAR ADC are the input
driver and the reference driver design. The circuit comprises the critical analog circuit blocks, the input driver,
anti-aliasing filter, and the reference driver. Each analog circuit block should be carefully designed based on the
ADC performance specifications in order to maximize the distortion and noise performance of the data
acquisition system while consuming low power. The diagram includes the most important specifications for each
individual analog block. This design systematically approaches the design of each analog circuit block to achieve
a 16-bit, low-noise and low-distortion data acquisition system for a 10-kHz sinusoidal input signal. The first step
in the design requires an understanding of the requirement of extremely low distortion input driver amplifier. This
understanding helps in the decision of an appropriate input driver configuration and selection of an input amplifier
to meet the system requirements. The next important step is the design of the anti-aliasing RC-filter to attenuate
ADC kick-back noise while maintaining the amplifier stability. The final design challenge is to design a highprecision reference driver circuit, which would provide the required value VREF with low offset, drift, and noise
contributions.
In designing a very low distortion data acquisition block, it is important to understand the sources of nonlinearity.
Both the ADC and the input driver introduce nonlinearity in a data acquisition block. To achieve the lowest
distortion, the input driver for a high-performance SAR ADC must have a distortion that is negligible against the
ADC distortion. This parameter requires the input driver distortion to be 10 dB lower than the ADC THD. This
stringent requirement ensures that overall THD of the system is not degraded by more than –0.5 dB.
THDAMP < THDADC – 10 dB
(3)
It is therefore important to choose an amplifier that meets the above criteria to avoid the system THD from being
limited by the input driver. The amplifier nonlinearity in a feedback system depends on the available loop gain.
See TIPD115 for a detailed error analysis, design procedure, and additional measured results.
8.2.3.3 Application Curve
Integral Non-Linearity Error (LSB)
1.5
1
0.5
0
–0.5
–1
–1.5
–4.5
–3.5 –2.5
–1.5 –0.5 0.5
1.5
ADC Differential Input
2.5
3.5
4.5
D002
Figure 28. Linearity of the ADC8881 System
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8.3 System Examples
8.3.1 Temperature Measurement Application
Figure 29 shows a temperature measurement application.
REF3140
+5 V
0.1 mF
4.096 V
+
R9
150 kW
R1
6.04 kW
R5
31.6 kW
D1
+5 V
0.1 mF
+
-
R2
2.94 kW
-
+ +
R2
549 W
R4
6.04 kW
VO
OPA2333
R6
200 W
K-Type
Thermocouple
40.7 mV/°C
Zero
Adjust
R3
60.4 W
Figure 29. Temperature Measurementf
8.3.2 Single Operational Amplifier Bridge Amplifier Application
Figure 30 shows the basic configuration for a bridge amplifier.
VEX
R1
+5 V
R R
R R
VOUT
OPA2333
R1
VREF
Figure 30. Single Operational Amplifier Bridge Amplifier
8.3.3 Low-Side Current Monitor Application
A low-side current shunt monitor is shown in Figure 31. RN are operational resistors used to isolate the ADS1100
from the noise of the digital I2C bus. The ADS1100 is a 16-bit converter; therefore, a precise reference is
essential for maximum accuracy. If absolute accuracy is not required and the 5-V power supply is sufficiently
stable, the REF3130 can be omitted.
3V
+5 V
REF3130
Load
R1
4.99 kW
R2
49.9 kW
R6
71.5 kW
V
ILOAD
RSHUNT
1W
RN
56 W
OPA2333
R3
4.99 kW
R4
48.7 kW
Stray Ground-Loop Resistance
ADS1100
R7
1.18 kW
RN
56 W
2
IC
(PGA Gain = 4)
FS = 3.0 V
NOTE: 1% resistors provide adequate common-mode rejection at small ground-loop errors.
Figure 31. Low-Side Current Monitor
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8.3.4 Other Applications
Additional application ideas are shown in Figure 32 through Figure 35.
RG
zener
RSHUNT
(1)
V+
(2)
R1
10 kW
MOSFET rated to
stand-off supply voltage
such as BSS84 for
up to 50 V.
1/2
OPA2333
+5V
V+
Two zener
biasing methods
(3)
are shown.
Output
Load
RBIAS
RL
Copyright © 2016, Texas Instruments Incorporated
(1)
Zener rated for operational amplifier supply capability (that is, 5.1 V for OPA2333).
(2)
Current-limiting resistor.
(3)
Choose zener biasing resistor or dual N-MOSFETs (FDG6301N, NTJD4001N, or Si1034).
Figure 32. High-Side Current Monitor
100 kW
1 MW
60 kW
3V
NTC
Thermistor
1 MW
1/2
OPA2333
Figure 33. Thermistor Measurement
V1
-In
INA152
1/2
OPA2333
R2
R1
2
5
6
3
V2
+In
VO
R2
1
1/2
OPA2333
VO = (1 + 2R2 / R1) (V2 - V1)
Figure 34. Precision Instrumentation Amplifier
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+VS
R1
100 kW
fLPF = 150 Hz
C4
1.06 nF
1/2
OPA2333
RA
+VS
R2
100 kW
R6
100 kW
1/2
OPA2333
+VS
3
2
LL
7
INA321
(1)
4
5
R8
100 kW
+VS
ac
dc
R3
100 kW
1/2
OPA2333
GINA = 5
R12
5 kW
6
+VS
1
C3
1 mF
1/2
OPA2333
R13
318 kW
VOUT
GOPA = 200
+VS
1/2
OPA2333
Wilson
LA
R14
1 MW
GTOT = 1 kV/V
R7
100 kW
VCENTRAL
C1
47 pF
(RA + LA + LL) / 3
fHPF = 0.5 Hz
(provides ac signal coupling)
1/2 VS
R5
390 kW
R9
20 kW
+VS
R4
100 kW
RL
1/2
OPA2333
Inverted
VCM
+VS
VS = +2.7 V to +5.5 V
BW = 0.5 Hz to 150 Hz
1/2
OPA2333
+VS
R10
1 MW
1/2 VS
C2
0.64 mF
R11
1 MW
fO = 0.5 Hz
(1)
Other instrumentation amplifiers can be used, such as the INA326, which has lower noise, but higher quiescent
current.
Figure 35. Single-Supply, Very Low Power, ECG Circuit
9 Power Supply Recommendations
The OPA2333 is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply from
–40°C to 125°C. The Recommended Operating Conditions presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings).
TI recommends placing 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in
from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, see
Layout.
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10 Layout
10.1 Layout Guidelines
10.1.1 General Layout Guidelines
Pay attention to good layout practices. Keep traces short and when possible, use a printed-circuit board (PCB)
ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-μF
capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve
performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility.
Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified
as a variation in offset voltage or DC signal levels with changes in the interfering RF signal. The OPA2333 is
specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to
previous generation devices. Strong RF fields may still cause varying offset levels.
10.1.2 DFN Layout Guidelines
Solder the exposed leadframe die pad on the DFN package to a thermal pad on the PCB. A mechanical drawing
showing an example layout is attached at the end of this data sheet. Refinements to this layout may be
necessary based on assembly process requirements. Mechanical drawings located at the end of this data sheet
list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are
intended for use with thermal vias that connect the leadframe die pad to the heatsink area on the PCB.
Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push,
package shear, and similar board-level tests. Even with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.
10.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 36. OPA2333-HT Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For development support on this product, see the following:
• High-Side V-I Converter, 0 V to 2 V to 0 mA to 100 mA, 1% Full-Scale Error, TIPD102
• Low-Level V-to-I Converter Reference Design, 0-V to 5-V Input to 0-µA to 5-µA Output, TIPD107
• 18-Bit, 1-MSPS, Serial Interface, microPower, Truly-Differential Input, SAR ADC, ADS8881
• Very Low-Power, High-Speed, Rail-To-Rail Input/Output, Voltage Feedback Operational Amplifier, THS4281
• Data Acquisition Optimized for Lowest Distortion, Lowest Noise, 18-bit, 1-MSPS Reference Design, TIPD115
• Self-Calibrating, 16-Bit Analog-to-Digital Converter, ADS1100
• 20-ppm/Degrees C Max, 100-µA, SOT23-3 Series Voltage Reference, REF3130
• Precision, Low Drift, CMOS Instrumentation Amplifier, INA326, INA326
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
OPA2333HD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-4-260C-72 HR
-55 to 175
O2333H
Samples
OPA2333SHKJ
ACTIVE
CFP
HKJ
8
25
RoHS & Green
Call TI
N / A for Pkg Type
-55 to 210
OPA2333S
HKJ
Samples
OPA2333SHKQ
ACTIVE
CFP
HKQ
8
25
RoHS & Green
AU
N / A for Pkg Type
-55 to 210
OPA2333S
HKQ
Samples
OPA2333SJD
ACTIVE
CDIP SB
JD
8
45
RoHS & Green
Call TI
N / A for Pkg Type
-55 to 210
OPA2333SJD
Samples
OPA2333SKGD1
ACTIVE
XCEPT
KGD
0
100
RoHS & Green
Call TI
N / A for Pkg Type
-55 to 210
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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