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OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
SBOS492F – JUNE 2009 – REVISED MAY 2018
OPAx354-Q1 250-MHz, Rail-to-Rail I/O, CMOS Operational Amplifiers
1 Features
3 Description
•
•
The design of the OPAx354-Q1 family of high-speed,
voltage-feedback CMOS operational amplifiers is for
video and other applications requiring wide
bandwidth. These devices are unity-gain stable and
can drive large output currents. Differential gain is
0.02% and differential phase is 0.09°. Quiescent
current is only 4.9 mA per channel.
1
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade: –40°C to +125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level:
– C6 for OPA354A-Q1 and OPA2354A-Q1
– C3 for OPA4354-Q1
Unity-Gain Bandwidth: 250 MHz
Wide Bandwidth: 100-MHz GBW Product
High Slew Rate: 150 V/μs
Low Noise: 6.5 nV/√Hz
Rail-to-Rail I/O
High Output Current: >100 mA
Excellent Video Performance
– Differential Gain Error: 0.02%
– Differential Phase Error: 0.09°
– 0.1-dB Gain Flatness: 40 MHz
Low Input Bias Current: 3 pA
Quiescent Current: 4.9 mA
Thermal Shutdown
Supply Range: 2.5 V to 5.5 V
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
Navigation and Radio System
Blind-Spot Detection
Short-to-Mid Range Radar
Video Processing
Ultrasound
Optical Networking, Tunable Lasers
Photodiode Transimpedance Amplifiers
Active Filters
High-Speed Integrators
Analog-to-Digital Converter (ADC) Input Buffers
Digital-to-Analog Converter (DAC) Output
Amplifiers
Barcode Scanners
Communications
The OPAx354-Q1 family of operational amplifiers (opamps) are optimized for operation on single or dual
supplies as low as 2.5 V (±1.25 V) and up to 5.5 V
(±2.75 V). Common-mode input range extends
beyond the supplies. The output swing is within 100
mV of the rails, supporting wide dynamic range.
The single-supply version (OPA354A-Q1) is available
in the tiny SOT–23-5 (DBV) package. The dualsupply version (OPA2354A-Q1) is available in the
miniature VSSOP-8 (DGK) package and features
completely independent circuitry for lowest crosstalk
and freedom from interaction. The quad-supply
version (OPA4354-Q1) is available in the TSSOP-14
(PW) package. The device specifications are for
operation over the automotive temperature range of
–40°C to +125°C.
Device Information(1)
PART NUMBER
PACKAGE (PIN)
BODY SIZE (NOM)
OPA354A-Q1
SOT-23 (5)
2.90 mm × 1.60 mm
OPA2354A-Q1
VSSOP (8)
3.00 mm × 3.00 mm
OPA4354-Q1
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
V+
-In
OPA354-Q1
VOUT
+In
V-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
SBOS492F – JUNE 2009 – REVISED MAY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
1
1
1
2
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information: OPA354A-Q1 ......................... 6
Thermal Information: OPA2354A-Q1 ....................... 7
Thermal Information: OPA4354A-Q1 ....................... 7
Electrical Characteristics........................................... 8
Typical Characteristics ............................................ 10
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 20
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Applications ................................................ 21
9
Power Supply Recommendations...................... 25
9.1 Power Dissipation ................................................... 26
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
29
29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2016) to Revision F
•
Page
Deleted table note about input terminals and input signals from Absolute Maximum Ratings table .................................... 6
Changes from Revision D (July 2016) to Revision E
•
Page
Changed the gain-bandwidth product typical value from 10 MHz back to 100 MHz in the Electrical Characteristics table .. 8
Changes from Revision C (June 2016) to Revision D
Page
•
Changed the gain-bandwidth product typical value from 100 MHz to 10 MHz in the Electrical Characteristics table........... 8
•
Added the Receiving Notification of Documentation Updates and Community Resources sections .................................. 28
Changes from Revision B (December 2014) to Revision C
Page
•
Added 3 additional applications to the Applications section .................................................................................................. 1
•
Updated ESD Ratings table to show CDM value for OPA354A-Q1 and OPA2354A-Q1 ...................................................... 6
Changes from Revision A (August 2009) to Revision B
Page
•
Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Added the OPA4354-Q1 device to the data sheet ................................................................................................................ 1
2
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Product Folder Links: OPA354A-Q1 OPA2354A-Q1 OPA4354-Q1
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
www.ti.com
SBOS492F – JUNE 2009 – REVISED MAY 2018
5 Pin Configuration and Functions
OPA354A-Q1 DBV Package
5-Pin SOT-23
Top View
OUT 1
5 V+
+
V± 2
+IN 3
4 ±IN
Pin Functions: OPA354A-Q1
PIN
NAME
NO.
I/O
DESCRIPTION
+IN
3
I
Noninverting input
–IN
4
I
Inverting input
OUT
1
O
Output
V+
5
—
Positive (highest) supply
V–
2
—
Negative (lowest) supply
Copyright © 2009–2018, Texas Instruments Incorporated
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3
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
SBOS492F – JUNE 2009 – REVISED MAY 2018
www.ti.com
OPA2354A-Q1 DGK Package
8-Pin VSSOP
Top View
OUT A 1
8 V+
±IN A 2
7 OUT B
A
+IN A 3
+
6 ±IN B
B
V± 4
+
5 +IN B
Pin Functions: OPA2354A-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V+
5
—
Positive (highest) supply
V–
2
—
Negative (lowest) supply
4
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Product Folder Links: OPA354A-Q1 OPA2354A-Q1 OPA4354-Q1
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
www.ti.com
SBOS492F – JUNE 2009 – REVISED MAY 2018
OPA4354-Q1 PW Package
14-Pin TSSOP
Top View
OUT A 1
±IN A 2
+IN A 3
14 OUT D
±
A
D
+
±
13 ±IN D
+
12 +IN D
V+ 4
11 V±
+IN B 5
10 +IN C
B
±IN B 6
C
±
OUT B 7
±
9 ±IN C
8 OUT C
Pin Functions: OPA4354-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
+IN C
10
I
Noninverting input, channel C
+IN D
12
I
Noninverting input, channel D
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
–IN C
9
I
Inverting input, channel C
–IN D
13
I
Inverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
1
O
Output, channel C
OUT D
7
O
Output, channel D
V+
5
—
Positive (highest) supply
V–
2
—
Negative (lowest) supply
Copyright © 2009–2018, Texas Instruments Incorporated
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5
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
SBOS492F – JUNE 2009 – REVISED MAY 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
7.5
V
(V+) + 0.5
V
Supply voltage, V+ to V–, VS
Signal input terminals voltage, VIN
(V–) – 0.5
Output short-circuit duration (2)
Continuous
Operating temperature, TA
–55
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
150
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short circuit to ground, one amplifier per package
6.2 ESD Ratings
VALUE
UNIT
OPA354A-Q1 IN DBV (SOT-23) PACKAGE AND OPA2354A-Q1 IN DGK (VSSOP) PACKAGE
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
±2000
Charged device model (CDM), per AEC Q100-011
±1000
Human body model (HBM), per AEC Q100-002 (1)
±2000
Charged device model (CDM), per AEC Q100-011
±250
V
OPA4354-Q1 IN PW (TSSOP) PACKAGE
V(ESD)
(1)
Electrostatic discharge
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VS
Supply voltage, V– to V+
2.5
5.5
UNIT
V
TA
Operating free-air temperature
–40
125
°C
6.4 Thermal Information: OPA354A-Q1
THERMAL METRIC (1)
OPA354A-Q1
OPA2354A-Q1
OPA4354-Q1
DBV (SOT-23)
DGK (VSSOP)
PW (TSSOP)
UNIT
5 PINS
8 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
216.3
175.9
92.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
84.3
67.8
27.5
°C/W
RθJB
Junction-to-board thermal resistance
43.1
97.1
33.6
°C/W
ψJT
Junction-to-top characterization parameter
3.8
9.3
1.9
°C/W
ψJB
Junction-to-board characterization parameter
42.3
95.5
33.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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www.ti.com
SBOS492F – JUNE 2009 – REVISED MAY 2018
6.5 Thermal Information: OPA2354A-Q1
OPA2354A-Q1
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
175.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
67.8
°C/W
RθJB
Junction-to-board thermal resistance
97.1
°C/W
ψJT
Junction-to-top characterization parameter
9.3
°C/W
ψJB
Junction-to-board characterization parameter
95.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4354A-Q1
OPA4354-Q1
THERMAL METRIC
(1)
PW (TSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
92.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
27.5
°C/W
RθJB
Junction-to-board thermal resistance
33.6
°C/W
ψJT
Junction-to-top characterization parameter
1.9
°C/W
ψJB
Junction-to-board characterization parameter
33.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2009–2018, Texas Instruments Incorporated
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SBOS492F – JUNE 2009 – REVISED MAY 2018
www.ti.com
6.7 Electrical Characteristics
VS = 2.5 V to 5.5 V, RF (feedback resistor) = 0 Ω, RL (load resistor) = 1 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±2
±8
TA = 25°C
UNIT
VOS
Input offset voltage
VS = 5 V
VCM = (V–) + 0.8 V
ΔVOS /
ΔT
Offset voltage drift over
temperature
TA = Full range
PSRR
Offset voltage drift vs power
supply
VS = 2.7 V to 5.5 V,
VCM = VS / 2 – 0.15 V
IB
Input bias current
TA = 25°C
3
±50
IOS
Input offset current
TA = 25°C
±1
±50
Vn
Input voltage noise density
f = 1 MHz, TA = 25°C
6.5
nV/√Hz
In
Input current noise density
f = 1 MHz, TA = 25°C
50
fA/√Hz
VCM
Input common-mode voltage
range
TA = 25°C
CMRR
Input common-mode rejection
ratio
ZID
Differential input impedance
ZICM
Common-mode input
impedance
AOL
TA = Full range
±10
±4
TA = 25°C
±200
TA = Full range
VS = 5.5 V
–0.1 V < VCM < 3.5 V
TA = 25°C
66
TA = Full range
64
VS = 5.5 V
–0.1 V < VCM < 5.6 V
TA = 25°C
56
TA = Full range
55
94
VS = 5 V, 0.4 V < VO < 4.6 V
TA = Full range
90
GBW
Gain-bandwidth product
G = 10
TA = 25°C
f0.1dB
Bandwidth for 0.1-dB gain
flatness
G = 2, VO = 100 mVp-p, TA = 25°C
SR
Slew rate
pA
pA
V
|| 2
dB
Ω || pF
Ω || pF
110
dB
G = 1, VO = 100 mVp-p, RF = 25 Ω, TA = 25°C
Small-signal bandwidth
68
10
VS = 5 V, 0.3 V < VO < 4.7 V
TA = 25°C
μV/V
80
13
TA = 25°C
f–3dB
±800
(V+) + 0.1
1013 || 2
TA = 25°C
Open-loop gain
μV/°C
±900
(V–) – 0.1
mV
250
G = 2, VO = 100 mVp-p, TA = 25°C
90
100
MHz
40
MHz
VS = 5 V, G = 1, 4-V step, TA = 25°C
150
VS = 5 V, G = 1, 2-V step
130
VS = 3 V, G = 1, 2-V step
110
G = 1, VO = 200 mVp-p, 10% to 90%, TA = 25°C
MHz
2
V/μs
trf
Rise-and-fall time
tsettle
Settling time
VS = 5 V, G = +1, 2-V output
step, TA = 25°C
Overload recovery time
VIN × Gain = VS
TA = 25°C
Second-order harmonic
distortion
G = 1, f = 1 MHz, VO = 2 Vp-p,
RL = 200 Ω, VCM = 1.5 V
TA = 25°C
–75
dBc
Third-order harmonic distortion
G = 1, f = 1 MHz, VO = 2 Vp-p
RL = 200 Ω, VCM = 1.5 V
TA = 25°C
–83
dBc
Differential gain error
NTSC, RL = 150 Ω, TA = 25°C
0.02%
Differential phase error
NTSC, RL = 150 Ω, TA = 25°C
0.09
8
G = 1, VO = 2 Vp-p, 10% to 90%, TA = 25°C
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11
0.1%
30
0.01%
60
5
ns
ns
ns
°
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SBOS492F – JUNE 2009 – REVISED MAY 2018
Electrical Characteristics (continued)
VS = 2.5 V to 5.5 V, RF (feedback resistor) = 0 Ω, RL (load resistor) = 1 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Channel-to-channel crosstalk
(OPA2354A-Q1) (OPA4354Q1)
f = 5 MHz, TA = 25°C
IQ
dB
0.3
100
VS = 3 V
mA
50
f < 100 kHz
0.05
Ω
35
VS = 5 V, IO = 0, enabled
UNIT
V
Open-loop output resistance
Quiescent current
(per amplifier)
MAX
0.4
VS = 5 V
Output current (1) (2)
Thermal shutdown junction
temperature
(1)
(2)
0.1
VS = 5 V, RL = 1 kΩ
AOL > 90 dB, TA = Full range
Closed-loop output impedance
RO
TYP
–100
VS = 5 V, RL = 1 kΩ, AOL > 94 dB
TA = 25°C
Voltage output swing from rail
IO
MIN
TA = 25°C
4.9
TA = Full range
Ω
6
7.5
Shutdown
160
Reset from shutdown
140
mA
°C
See typical characteristic graph Output Voltage Swing vs Output Current (Figure 20).
Not production tested
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6.8 Typical Characteristics
TA = 25°C, VS = 5 V, RF = 0 Ω, RL = 1 kΩ connected to VS / 2 (unless otherwise noted)
3
3
G = 1,
RF = 25W
VO = 0.1VPP
VO = 0.1VPP, RF = 604W
0
Normalized Gain (dB)
Normalized Gain (dB)
0
G = +2, RF = 604W
-3
G = +5, RF = 604W
-6
G = +10, RF = 604W
-9
-12
-3
G = -1
-6
G = -5
G = -10
-12
-15
100k
1M
10M
Frequency (Hz)
100M
-15
100k
1G
1M
100M
1G
Figure 2. Inverting Small-Signal Frequency Response
Output Voltage (40mV/div)
Time (20ns/div)
Time (20ns/div)
Figure 3. Noninverting Small-Signal Step Response
0.4
Figure 4. Noninverting Large-Signal Step Response
-50
VO = 0.1VPP
Harmonic Distortion (dBc)
0.5
Normalized Gain (dB)
10M
Frequency (Hz)
Output Voltage (500mV/div)
Figure 1. Noninverting Small-Signal Frequency Response
0.3
G = +1
RF = 25W
0.2
0.1
0
-0.1
-0.2
G = +2
RF = 604W
-0.3
G = -1
f = 1MHz
RL = 200W
-60
-70
2nd−Harmonic
-80
-90
-0.4
-0.5
100k
3rd−Harmonic
-100
1M
10M
Frequency (Hz)
100M
Figure 5. 0.1-dB Gain Flatness
10
G = -2
-9
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1G
0
1
2
Output Voltage (VPP)
3
4
Figure 6. Harmonic Distortion vs Output Voltage
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SBOS492F – JUNE 2009 – REVISED MAY 2018
Typical Characteristics (continued)
TA = 25°C, VS = 5 V, RF = 0 Ω, RL = 1 kΩ connected to VS / 2 (unless otherwise noted)
-50
VO = 2VPP
f = 1MHz
RL = 200W
-60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
-70
2nd−Harmonic
-80
-90
VO = 2VPP
f = 1MHz
RL = 200W
-60
-70
2nd−Harmonic
-80
3rd−Harmonic
-90
3rd−Harmonic
-100
-100
1
10
1
10
Gain (V/V)
Gain (V/V)
Figure 7. Harmonic Distortion vs Noninverting Gain
Figure 8. Harmonic Distortion vs Inverting Gain
-50
-60
G = +1
VO = 2VPP
RL = 200W
VCM = 1.5V
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
-70
2nd−Harmonic
-80
3rd−Harmonic
-90
G = +1
VO = 2VPP
f = 1MHz
VCM = 1.5V
-60
-70
2nd−Harmonic
-80
3rd−Harmonic
-90
-100
-100
100k
1M
Frequency (Hz)
100
10M
1k
RL (W)
Figure 9. Harmonic Distortion vs Frequency
Figure 10. Harmonic Distortion vs Load Resistance
3
10k
RL = 10kW
Normalized Gain (dB)
Voltage Noise (nV/√Hz),
Current Noise (fA/√Hz)
0
1k
Current Noise
Voltage Noise
100
10
-3
-6
G = +1
R F = 0W
VO = 0.1VPP
C L = 0pF
RL = 1kW
RL = 100W
-9
RL = 50W
-12
1
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 11. Input Voltage and Current Noise Spectral Density
vs Frequency
Copyright © 2009–2018, Texas Instruments Incorporated
-15
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 12. Frequency Response for Various RL Values
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, RF = 0 Ω, RL = 1 kΩ connected to VS / 2 (unless otherwise noted)
160
9
G = +1
VO = 0.1VPP
R S = 0W
Normalized Gain (dB)
6
3
120
100
-3
RS (W)
0
CL = 47pF
80
-6
60
-9
40
VO
CL
1kW
0
1M
10M
Frequency (Hz)
100M
1
1G
Figure 13. Frequency Response for Various CL Values
1k
10
100
Capacitive Load (pF)
Figure 14. Recommended RS vs Capacitive Load
3
100
G = +1
VO = 0.1VPP
0
CL = 5.6pF, RS = 0W
CMRR
CMRR, PSRR (dB)
80
CL = 47pF, RS = 140W
-3
CL = 100pF, RS = 120W
-6
VIN
-9
RS
VO
OPA354-Q1
CL
-12
PSRR+
60
PSRR40
20
1kW
0
-15
100k
1M
10M
Frequency (Hz)
1G
100M
10k
Figure 15. Frequency Response vs Capacitive Load
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 16. Common-Mode Rejection Ratio and PowerSupply Rejection Ratio vs Frequency
0.8
180
160
0.7
140
dG/dP (%/degree)
0.6
120
Phase
100
80
60
40
Gain
20
0.5
dP
0.4
0.3
0.2
0
0.1
dG
-20
0
-40
10
100
1k
10k 100k
1M
Frequency (Hz)
10M
100M
Figure 17. Open-Loop Gain and Phase
12
RS
OPA354-Q1
20
-15
100k
Normalized Gain (dB)
VIN
CL = 5.6pF
-12
Open−Loop Phase (degrees)
Open−Loop Gain (dB)
For 0.1dB
Flatness
140
CL = 100pF
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1G
1
2
3
4
Number of 150W Loads
Figure 18. Composite Video Differential Gain and Phase
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, RF = 0 Ω, RL = 1 kΩ connected to VS / 2 (unless otherwise noted)
3
1k
Output Voltage (V)
Input Bias Current (pA)
10k
100
2
125°C
–55°C
25°C
1
10
0
1
-55
-35
-15
5
25
45
65
Temperature (°C)
85
0
105 125 135
20
40
60
80
100
120
Output Current (mA)
VS = 3 V
Figure 19. Input Bias Current vs Temperature
Figure 20. Output Voltage Swing vs Output Current
5
7
4
VS = 5V
Output Voltage (V)
Supply Current (mA)
6
5
4
VS = 2.5V
3
2
3
25°C
125°C
-55°C
2
1
1
0
0
-55
-35
-15
5
25
45
65
Temperature (°C)
85
0
105 125 135
25
50
75
100
125
150
175
200
Output Current (mA)
VS = 5 V
Figure 21. Supply Current vs Temperature
Figure 22. Output Voltage Swing vs Output Current
6
100
VS = 5.5V
10
Output Voltage (VPP)
Output Impedance (W)
5
1
0.1
OPA354-Q1
4
3
VS = 2.7V
2
1
ZO
0.01
100k
Maximum Output
Voltage Without
Slew−Rate
Induced Distortion
0
1M
10M
Frequency (Hz)
100M
1G
Figure 23. Closed-Loop Output Impedance vs Frequency
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1
10
100
Frequency (MHz)
Figure 24. Maximum Output Voltage vs Frequency
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Typical Characteristics (continued)
TA = 25°C, VS = 5 V, RF = 0 Ω, RL = 1 kΩ connected to VS / 2 (unless otherwise noted)
0.5
120
0.4
Open−Loop Gain (dB)
Output Error (%)
RL = 1kW
VO = 2VPP
0.3
0.2
0.1
0
-0.1
-0.2
110
100
90
80
-0.3
-0.4
70
-0.5
0
10
20
30
40
50
60
70
80
90
100
-55
-35
-15
5
Time (ns)
Figure 25. Output Settling Time to 0.1%
25
45
65
Temperature (°C)
85
105 125 135
Figure 26. Open-Loop Gain vs Temperature
100
Population
CMRR, PSRR (dB)
90
Common−Mode Rejection Ratio
80
Power−Supply Rejection Ratio
70
60
50
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3
Offset Voltage (mV)
4 5 6
7 8
-55
-35
-15
5
25
45
65
85
105 125 135
Temperature (°C)
Figure 27. Offset Voltage Production Distribution
Figure 28. Common-Mode Rejection Ratio and PowerSupply Rejection Ratio vs Temperature
Crosstalk, Input−Referred (dB)
0
-20
-40
-60
OPA2354-Q1
-80
-100
-120
100k
1M
10M
100M
1G
Frequency (Hz)
Figure 29. Channel-to-Channel Crosstalk (OPAx354-Q1)
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7 Detailed Description
7.1 Overview
The OPAx354-Q1 operational amplifiers are high-speed,150-V/μs, amplifiers making them excellent choices for
transimpedance applications. The devices are unity-gain stable and can operate on a single-supply voltage (2.5
V to 5.5 V), or a split-supply voltage (±1.25 V to ±2.75 V), making them highly versatile and easy to use. The
OPAx354A-Q1 amplifiers are specified from 2.5 V to 5.5 V and over the automotive temperature range of –40°C
to +125°C.
Table 1. OPAx354-Q1 Related Products
FEATURES
PRODUCT
Shutdown Version of OPA354 Family
OPAx357
200-MHz GBW, Rail-to-Rail Output, CMOS, Shutdown
OPAx355
200-MHz GBW, Rail-to-Rail Output, CMOS
OPAx356
38-MHz GBW, Rail-to-Rail Input/Output, CMOS
OPAx350/3
75-MHz BW, G = 2, Rail-to-Rail Output
OPAx631
150-MHz BW, G = 2, Rail-to-Rail Output
OPAx634
100-MHz BW, Differential Input/Output, 3.3-V Supply
THS412x
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VIN±
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V±
(Ground)
7.3 Feature Description
7.3.1 Operating Voltage
The specifications of the OPAx354-Q1 family of devices apply over a power-supply range of 2.5 V to 5.5 V
(±1.25 V to ±2.75 V). Supply voltages higher than 7.5 V (absolute maximum) can permanently damage the
amplifier.
The Typical Characteristics section of this data sheet shows the parameters that vary over supply voltage or
temperature.
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Feature Description (continued)
7.3.2 Rail-to-Rail Input
The specified input common-mode voltage range of the OPAx354-Q1 family of devices extends 100 mV beyond
the supply rails. A complementary input stage (an N-channel input differential pair in parallel with a P-channel
differential pair) achieves this extension. The N-channel pair is active for input voltages close to the positive rail,
typically (V+) – 1.2 V to 100 mV above the positive supply, while the P-channel pair is on for inputs from 100 mV
below the negative supply to approximately (V+) – 1.2 V. A small transition region exists, typically (V+) – 1.5 V to
(V+) – 0.9 V, in which both pairs are on. This 600-mV transition region can vary ±500 mV with process variation.
As a result, the transition region (both input stages on) range from (V+) – 2 V to (V+) – 1.5 V on the low end, up
to (V+) – 0.9 V to (V+) – 0.4 V on the high end.
A double-folded cascode adds the signal from the two input pairs and presents a differential signal to the classAB output stage.
7.3.3 Rail-to-Rail Output
The device uses a class-AB output stage with common-source transistors to achieve rail-to-rail output. For highimpedance loads (> 200 Ω), the output voltage swing is typically 100 mV from the supply rails. With 10-Ω loads,
a user can achieve a useful output swing while maintaining high open-loop gain; see Figure 20 (Output Voltage
Swing vs Output Current).
7.3.4 Output Drive
The OPAx354-Q1 output stage supplies a continuous output current of ±100 mA and still provide approximately
2.7-V output swing on a 5-V supply, as shown in Figure 30.
R2
1 NŸ
+
V1
5V
C1
50 pF
1 µF
R1
10 NŸ
V+
OPA354-Q1
R3
VIN 10 NŸ
+
1 V In = 100 mA
Out as shown
V
RSHUNT
R4
1Ÿ
1 NŸ
Laser Diode
Figure 30. Laser Diode Driver
For maximum reliability, TI does not recommend running a continuous DC current greater than ±100 mA; see
Figure 20 (Output Voltage Swing vs Output Current). Operate the OPAx354-Q1 family of devices in parallel to
supply continuous output currents greater than ±100 mA, as shown in Figure 31.
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Feature Description (continued)
R2
10kW
C1
200pF
+5V
1mF
R1
100kW
R5
1W
OPA2354-Q1
R3
100kW
+
-
R6
1W
2V In = 200mA
Out, as Shown
RSHUNT
1W
OPA2354-Q1
R4
10kW
Laser Diode
Figure 31. Parallel Operation
The OPAx354-Q1 family of devices provides peak currents up to 200 mA, which correspond to the typical shortcircuit current. Therefore, an on-chip thermal shutdown circuit protects the OPAx354-Q1 family of devices from
dangerously high junction temperatures. At 160°C, the protection circuit shuts down the amplifier. Normal
operation resumes when the junction temperature cools below 140°C.
7.3.5 Video
The OPAx354-Q1 output stage is capable of driving standard back-terminated 75-Ω video cables (see
Figure 32). A back-terminated transmission line does not exhibit a capacitive load to the driver. A properly backterminated 75-Ω cable does not appear as capacitance; the cable presents a 150-Ω resistive load to the
OPAx354-Q1 output.
5V
Video
In
75 Ÿ
75 Ÿ
OPA354-Q1
Video
Output
2.5 V
604 Ÿ
604 Ÿ
2.5 V
Figure 32. Single-Supply Video Line Driver
This series of amplifiers can be used as an amplifier for RGB graphic signals, which have a voltage of zero at the
video black level by offsetting and AC-coupling the signal (see Figure 33).
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Feature Description (continued)
604 Ÿ
3V
+
1 µF
V+
10 nF
604 Ÿ
75 Ÿ
1/2
OPA2354-Q1
R1
Red(1)
Red
75 Ÿ
R2
V+
R1
Green(1)
604 Ÿ
R2
75 Ÿ
1/2
OPA2354-Q1
Green
75 Ÿ
604 Ÿ
604 Ÿ
3V
V+
+
1 µF
604 Ÿ
10 nF
75 Ÿ
Blue(1)
R1
Blue
OPA354-Q1
75 Ÿ
R2
(1)
Source video signal offset 300 mV above ground to accommodate op amp swing to ground capability.
Figure 33. RGB Cable Driver
7.3.6 Driving Analog-to-Digital Converters
The OPAx354-Q1 family of op-amps offers a 60-ns settling time to 0.01%, which makes the devices a viable
option for driving high- and medium-speed sampling ADCs and reference circuits. The OPAx354-Q1 family of
devices provides an effective means of buffering the input capacitance and resulting charge injection of the ADC
while providing signal gain. The OPAx354-Q1 family of devices is designed for applications requiring high DC
accuracy.
Figure 34 shows the OPAx354-Q1 family of devices driving an ADC. With the OPAx354-Q1 family of devices in
an inverting configuration, using a capacitor across the feedback resistor can filter high-frequency noise in the
signal.
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Feature Description (continued)
+5V
330pF
5kW
5kW
VIN
VREF
V+
ADS7816, ADS7861,
or ADS7864
12−Bit A/D Converter
+In
OPA354-Q1
+2.5V
-In
GND
VIN = 0V to -5V for 0V to 5V output.
NOTE: A/D Converter Input = 0V to VREF
Figure 34. OPA354A-Q1 Inverting Configuration Driving the ADS7816
7.3.7 Capacitive Load and Stability
The OPAx354-Q1 family op amps can drive a wide range of capacitive loads. However, all op-amps under
certain conditions can become unstable. Op amp configuration, gain, and load value are a few of the factors to
consider when determining stability. An op amp in unity-gain configuration is most susceptible to the effects of
capacitive loading. The capacitive load reacts with the output resistance of the op amp, along with any additional
load resistance, to create a pole in the small-signal response that degrades the phase margin. For details, see
Figure 15 (Frequency Response vs Capacitive Load.)
The OPAx354-Q1 topology enhances the ability of the device to drive capacitive loads. In unity gain, these opamps perform well with large capacitive loads. For details see Figure 14, Recommended RS vs Capacitive Load,
and Figure 15, Frequency Response vs Capacitive Load.
Insert a 10-Ω to 20-Ω resistor in series with the output to improve capacitive laod drive in the unity-gain
configuration, as shown in Figure 35. This configuration significantly reduces ringing with large capacitive loads;
see Figure 15 (Frequency Response vs Capacitive Load.) However, if a resistive load is in parallel with the
capacitive load, RS creates a voltage divider. This configuration introduces a DC error at the output and slightly
reduces output swing. This error may be insignificant. For example, if RL = 10 kΩ and RS = 20 Ω, the error at the
output is approximately 0.2%.
V+
RS
VOUT
OPA354-Q1
VIN
RL
CL
Figure 35. Series Resistor in Unity-Gain Configuration Improves Capacitive Load Drive
7.3.8 Wideband Transimpedance Amplifier
Wide bandwidth, low-input bias current, and low input voltage and current noise make the OPAx354-Q1 family of
devices is designed as a wideband photodiode transimpedance amplifier for low-voltage single-supply
applications. Low-voltage noise is important because photodiode capacitance causes the effective noise gain of
the circuit to increase at high frequency.
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Feature Description (continued)
The key elements to a transimpedance design, as shown in Figure 36, are the expected diode capacitance
[including the parasitic input common-mode and differential-mode input capacitance (2 + 2) pF for the OPAx354Q1], the desired transimpedance gain (RF), and the gain-bandwidth product (GBW) for the OPAx354-Q1 family of
devices (100 MHz). With these three variables set, the feedback capacitor value (CF) is set to control the
frequency response.
CF
< 1 pF
(prevents gain peaking)
RF
10 0Ÿ
+V
O
CD
OPA354-Q1
VOUT
Figure 36. Transimpedance Amplifier
To achieve a maximally flat second-order Butterworth frequency response, set the feedback pole as shown in
Equation 1.
1
+
2pR FCF
GBP
Ǹ4pR
C
F
D
(1)
Typical surface-mount resistors have a parasitic capacitance of approximately 0.2 pF that required deduction
from the calculated feedback capacitance value.
Use Equation 2 to calculate the bandwidth.
f *3dB +
GBP Hz
Ǹ2pR
C
F
D
(2)
For even higher transimpedance bandwidth, use the high-speed CMOS OPA355-Q1 (200-MHz GBW) or the
OPA655-Q1 (400-MHz GBW).
7.4 Device Functional Modes
The OPAx354-Q1 family of devices is powered on when the supply is connected. The devices operates as a
single-supply operational amplifier or dual-supply amplifier depending on the application. The devices are used
with asymmetrical supplies as long as the differential voltage (V– to V+) is at least 1.8 V and no greater than 5.5
V (example: V– set to –3.5 V and V+ set to 1.5 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx354-Q1 family of devices is a CMOS, rail-to-rail I/O, high-speed, voltage-feedback operational amplifier
designed for video, high-speed, and other applications. The OPAx354-Q1 family of devices is available as a
single, dual, or quad op-amp.
The amplifier features a 100-MHz gain bandwidth, and 150 V/μs slew rate, but the device is unity-gain stable and
operates as a 1-V/V voltage follower.
8.2 Typical Applications
8.2.1 Transimpedance Amplifier
Wide gain bandwidth, low input bias current, low input voltage, and current noise make the OPAx354-Q1 family
of devices a preferred wideband photodiode transimpedance amplifier. Low-voltage noise is important because
photodiode capacitance causes the effective noise gain of the circuit to increase at high frequency.
The key elements to a transimpedance design, as shown in Figure 37, are the expected diode capacitance
(C(D)), which must include the parasitic input common-mode and differential-mode input capacitance (4 pF + 5
pF); the desired transimpedance gain (R(FB)); and the gain-bandwidth (GBW) for the OPAx354-Q1 family of
devices (20 MHz). With these three variables set, the feedback capacitor value (C(FB)) is set to control the
frequency response. C(FB) includes the stray capacitance of R(FB), which is 0.2 pF for a typical surface-mount
resistor.
(1)
C(F)
< 1 pF
R(F)
10 MΩ
V(V+)
l
C(D)
OPA354-Q1
VO
V(V–)
(1) C(FB) is optional to prevent gain peaking. C(FB) includes the stray capacitance of R(FB).
Figure 37. Dual-Supply Transimpedance Amplifier
8.2.1.1 Design Requirements
PARAMETER
VALUE
Supply voltage V(V+)
2.5 V
Supply voltage V(V–)
–2.5 V
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8.2.1.2 Detailed Design Procedure
To achieve a maximally-flat, second-order Butterworth frequency response, the feedback pole must be set to:
1
=
2 ´ p ´ R(FB) ´ C(FB)
GBW
4 ´ p ´ R(FB) ´ C(D)
(3)
Use Equation 4 to calculate the bandwidth.
ƒ(–3 dB) =
GBW
2 ´ p ´ R(FB) ´ C(D)
(4)
For other transimpedance bandwidths, consider the high-speed CMOS OPA380 (90-MHz GBW), OPA354 (100MHz GBW), OPA300 (180-MHz GBW), OPA355 (200-MHz GBW), or OPA656 and OPA657 (400-MHz GBW).
For single-supply applications, the +INx input can be biased with a positive DC voltage to allow the output to
reach true zero when the photodiode is not exposed to any light, and respond without the added delay that
results from coming out of the negative rail; this configuration is shown in Figure 38. This bias voltage appears
across the photodiode, providing a reverse bias for faster operation.
0.5 pF
100 k
±
OPAx354-Q1
VOUT
+
13.7 k
SFH213
1 F
280
5V
Figure 38. Single-Supply Transimpedance Amplifier
For additional information, see the Compensate Transimpedance Amplifiers Intuitively application bulletin.
8.2.1.2.1 Optimizing The Transimpedance Circuit
To achieve the best performance, components must be selected according to the following guidelines:
1. For lowest noise, select R(FB) to create the total required gain. Using a lower value for R(FB) and adding gain
after the transimpedance amplifier generally produces poorer noise performance. The noise produced by
R(FB) increases with the square-root of R(FB), whereas the signal increases linearly. Therefore, signal-to-noise
ratio improves when all the required gain is placed in the transimpedance stage.
2. Minimize photodiode capacitance and stray capacitance at the summing junction (inverting input). This
capacitance causes the voltage noise of the op amp to be amplified (increasing amplification at high
frequency). Using a low-noise voltage source to reverse-bias a photodiode can significantly reduce the
capacitance. Smaller photodiodes have lower capacitance. Use optics to concentrate light on a small
photodiode.
3. Noise increases with increased bandwidth. Limit the circuit bandwidth to only that required. Use a capacitor
across the R(FB) to limit bandwidth, even if not required for stability.
4. Circuit board leakage can degrade the performance of an otherwise well-designed amplifier. Clean the circuit
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board carefully. A circuit board guard trace that encircles the summing junction and is driven at the same
voltage can help control leakage.
For additional information, see the Noise Analysis of FET Transimpedance Amplifiers, and Noise Analysis for
High-Speed Op Amps) application bulletins.
8.2.1.3 Application Curve
105
100
Gain (dB, V/A)
95
90
85
80
75
70
65
60
1000
10000
100000
1000000
Frequency (Hz)
1E+7
5E+7
D001
–3 dB bandwidth is 4.56 MHz
Figure 39. AC Transfer Function
8.2.2 High-Impedance Sensor Interface
Many sensors have high source impedances that may range up to 10 MΩ, or even higher. The output signal of
sensors often must be amplified or otherwise conditioned by an amplifier. The input bias current of this amplifier
can load the sensor output and cause a voltage drop across the source resistance, as shown in Figure 40, where
(V(+INx) = VS – I(BIAS) × R(S)). The last term, I(BIAS) × R(S), shows the voltage drop across R(S). To prevent errors
introduced to the system as a result of this voltage, use an op amp with low input bias current and highimpedance sensors. This low current keeps the error contribution by I(BIAS) × R(S) less than the input voltage
noise of the amplifier, so that the amplifier does not become the dominant noise factor. The OPAx354-Q1 family
of devices series of op amps feature low input bias current (typically 200 fA), and are therefore designed for such
applications.
R(S)
100 kΩ
IIB
V(+INx)
V(V+)
Device
V(V–)
VO
R(F)
R(G)
Figure 40. Noise as a Result of I(BIAS)
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8.2.3 Driving ADCs
The OPAx354-Q1 op amps are designed for driving sampling analog-to-digital converters (ADCs) with sampling
speeds up to 1 MSPS. The zero-crossover distortion input stage topology allows the OPAx354-Q1 family of
devices to drive ADCs without degradation of differential linearity and THD.
The OPAx354-Q1 family of devices can be used to buffer the ADC switched input capacitance and resulting
charge injection while providing signal gain. Figure 41 shows the OPAx354-Q1 family of devices configured to
drive the ADS8326.
5V
C1
100 nF
5V
(1)
R1
100 Ω
V(V+)
+INx
OPAx354-Q1
(1)
C3
1 nF
V(V–)
VI
0 to 4.096 V
–INx
ADS8326
16-Bit
250kSPS
REF IN
Optional
(2)
R2
50 kΩ
5V
SD1
BAS40
–5 V
C2
100 nF
REF3240
4.096 V
C4
100 nF
(1) Suggested value; may require adjustment based on specific application.
(2) Single-supply applications lose a small number of ADC codes near ground as a result of op amp output swing limitation. If a negative
power supply is available, this simple circuit creates a –0.3-V supply to allow output swing to true ground potential.
Figure 41. Driving the ADS8326
8.2.4 Active Filter
The OPAx354-Q1 family of devices is designed for active filter applications that require a wide bandwidth, fast
slew rate, low-noise, single-supply operational amplifier. Figure 42 shows a 500 kHz, second-order, low-pass
filter using the multiple-feedback (MFB) topology. The components are selected to provide a maximally-flat
Butterworth
response.
Beyond
the
cutoff
frequency,
roll-off
is
–40 dB/dec. The Butterworth response is designed for applications requiring predictable gain characteristics,
such as the anti-aliasing filter used in front of an ADC.
One point to observe when considering the MFB filter is that the output is inverted relative to the input. If this
inversion is not required, or not desired, a noninverting output can be achieved through one of the following
options:
1. Adding an inverting amplifier
2. Adding an additional second-order MFB stage
3. Using a noninverting filter topology, such as the Sallen-Key (see Figure 43).
MFB and Sallen-Key, low-pass and high-pass filter synthesis is accomplished using TI’s FilterPro™ program.
This software is available as a free download on www.ti.com.
24
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www.ti.com
SBOS492F – JUNE 2009 – REVISED MAY 2018
R3
549 Ω
C2
150 pF
R1
549 Ω
R2
1.24 kΩ
V(V+)
VI
VO
Device
C1
1 nF
V(V–)
Figure 42. Second-Order Butterworth 500-kHz Low-Pass Filter
220 pF
1.8 kΩ
19.5 kΩ
V(V+)
150 kΩ
VI = 1 VRMS
3.3 nF
47 pF
VO
Device
V(V–)
Figure 43. OPAx354-Q1 Configured as a Three-Pole, 20-kHz, Sallen-Key Filter
9 Power Supply Recommendations
The OPAx354-Q1 family of devices is specified for operation from 2.5 to 5.5 V (±1.25 to ±2.75 V); many
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are shown in the Typical Characteristics section.
CAUTION
Supply voltages larger than 7.5 V can permanently damage the device (see the
Absolute Maximum Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
Copyright © 2009–2018, Texas Instruments Incorporated
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SBOS492F – JUNE 2009 – REVISED MAY 2018
www.ti.com
9.1 Power Dissipation
Power dissipation depends on power-supply voltage, signal and load conditions. With dc signals, power
dissipation is equal to the product of output current times the voltage across the conducting output transistor
(VS – VO). Minimize power dissipation by using the lowest possible power-supply voltage required to ensure the
required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a DC output voltage of one-half the power-supply
voltage. Dissipation with AC signals is lower. The Power Amplifier Stress and Power Handling Limitations
application bulletin from www.ti.com explains how to calculate or measure power dissipation with unusual signals
and loads.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, limit junction temperature to 150°C, maximum. To estimate the margin of safety
in a complete design, increase the ambient temperature to trigger the thermal protection at 160°C. The thermal
protection must trigger more than 35°C above the maximum expected ambient condition of the application.
10 Layout
10.1 Layout Guidelines
Use good high-frequency printed circuit board (PCB) layout techniques for the OPAx354-Q1 family of devices.
Generous use of ground planes, short and direct signal traces, and a suitable bypass capacitor located at the V+
pin ensure clean, stable operation. Large areas of copper provide a means of dissipating heat that is generated
in normal operation. Sockets are not recommended for use with any high-speed amplifier. A 10-nF ceramic
bypass capacitor is the minimum recommended value; adding a 1-μF or larger tantalum capacitor in parallel can
be beneficial when driving a low-resistance load. Providing adequate bypass capacitance is essential to
achieving very low harmonic and intermodulation distortion.
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing lowimpedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, see Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the
inverting input minimizes parasitic capacitance, as shown in Figure 44.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
26
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www.ti.com
SBOS492F – JUNE 2009 – REVISED MAY 2018
10.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
GND
VS±
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 44. Operational Amplifier Board Layout for Noninverting Configuration
Copyright © 2009–2018, Texas Instruments Incorporated
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Product Folder Links: OPA354A-Q1 OPA2354A-Q1 OPA4354-Q1
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OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
SBOS492F – JUNE 2009 – REVISED MAY 2018
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, ADS8326 16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling Analog-to-Digital
Converter
• Texas Instruments,Circuit Board Layout Techniques
• Texas Instruments,Compensate Transimpedance Amplifiers Intuitively
• Texas Instruments,FilterPro™ User's Guide
• Texas Instruments,Noise Analysis of FET Transimpedance Amplifiers
• Texas Instruments,Noise Analysis for High-Speed Op Amps
• Texas Instruments,OPA380 and OPA2380 Precision, High-Speed Transimpedance Amplifier
• Texas Instruments,OPA354, OPA2354, and OPA4354 250MHz, Rail-to-Rail I/O, CMOS Operational
Amplifiers
• Texas Instruments,OPA355, OPA2355, and OPA3355 200MHz, CMOS Operational Amplifier With Shutdown
• Texas Instruments,OPA656 Wideband, Unity-Gain Stable, FET-Input Operational Amplifier
• Texas Instruments,Power Amplifier Stress and Power Handling Limitations
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA354A-Q1
Click here
Click here
Click here
Click here
Click here
OPA2354A-Q1
Click here
Click here
Click here
Click here
Click here
OPA4354-Q1
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
FilterPro is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
28
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Product Folder Links: OPA354A-Q1 OPA2354A-Q1 OPA4354-Q1
OPA354A-Q1, OPA2354A-Q1, OPA4354-Q1
www.ti.com
SBOS492F – JUNE 2009 – REVISED MAY 2018
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2009–2018, Texas Instruments Incorporated
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29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2354AQDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OSLQ
OPA354AQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OSFQ
OPA4354AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
4354Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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