OPA376-Q1, OPA2376-Q1, OPA4376-Q1
SBOS549C – APRIL 2011 – REVISED MARCH 2021
OPAx376-Q1 Low-Noise, Low Quiescent Current,
Precision e-trim™ Operational Amplifiers
1 Features
3 Description
•
The OPAx376-Q1 family represents a new generation
of low-noise e-trim™ operational amplifiers, offering
outstanding dc precision and ac performance. Rail-torail output, low offset (25 μV maximum), low noise
(7.5 nV/√Hz), quiescent current of 950 μA (maximum),
and a 5.5-MHz bandwidth make this device very
attractive for a variety of precision and portable
applications. In addition, this device has a reasonably
wide supply range with excellent PSRR, making the
OPA376-Q1 an excellent choice for applications that
run directly from batteries without regulation.
•
•
•
•
•
•
•
•
•
2 Applications
Device Information
Onboard (OBC) and wireless charger
Inverter and motor control
DC/DC converter
Battery management system (BMS)
PART NUMBER
OPA376-Q1
OPA2376-Q1
OPA4376-Q1
(1)
PACKAGE(1)
BODY SIZE (NOM)
SC70 (5)
2.00 mm × 1.25 mm
SOT-23 (5)
2.90 mm × 1.60 mm
SOIC (8)
4.90 mm × 3.91 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
TSSOP (14)
5.00 mm × 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Population
100
Voltage Noise (nV/ÖHz)
•
•
•
•
The OPA376-Q1 (single version) is available in
MicroSIZE SC70-5, SOT23-5, and SOIC-8 packages.
The OPA2376-Q1 (dual) is offered in the SOIC-8
and VSSOP-8 package. The OPA4376-Q1 (quad) is
offered in a TSSOP-14 package. All versions are
specified for operation from –40°C to +125°C.
10
1
1
10
100
1k
10k
Frequency (Hz)
Input Voltage Noise Spectral Density
100k
-25.0
-22.5
-20.0
-17.5
-15.0
-12.5
-10.0
-7.5
-5.0
-2.5
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Functional-Safety Capable
– Documentation available to aid functional safety
system design (OPA376-Q1 and OPA2376-Q1)
Low noise: 7.5 nV/√Hz at 1 kHz
0.1-Hz to 10-Hz noise: 0.8 μVPP
Quiescent current: 760 μA (typical)
Low offset voltage: 5 μV (typical)
Gain bandwidth product: 5.5 MHz
Rail-to-rail input and output
Single-supply operation
Supply voltage: 2.2 V to 5.5 V
Space-saving packages:
– SC70, SOT-23, VSSOP, TSSOP
Offset Voltage (mV)
Offset Voltage Production Distribution
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA376-Q1, OPA2376-Q1, OPA4376-Q1
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SBOS549C – APRIL 2011 – REVISED MARCH 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information: OPA376-Q1.............................. 7
6.5 Thermal Information: OPA2376-Q1............................ 7
6.6 Thermal Information: OPA4376-Q1............................ 7
6.7 Electrical Characteristics.............................................8
6.8 Typical Characteristics................................................ 9
7 Detailed Description......................................................13
7.1 Overview................................................................... 13
7.2 Functional Block Diagram......................................... 13
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................15
8 Application and Implementation.................................. 16
8.1 Application Information............................................. 16
8.2 Typical Application.................................................... 19
9 Power Supply Recommendations................................20
10 Layout...........................................................................21
10.1 Layout Guidelines................................................... 21
10.2 Layout Example...................................................... 21
11 Device and Documentation Support..........................22
11.1 Device Support........................................................22
11.2 Documentation Support.......................................... 22
11.3 Receiving Notification of Documentation Updates.. 22
11.4 Support Resources................................................. 22
11.6 Electrostatic Discharge Caution.............................. 23
11.7 Glossary.................................................................. 23
12 Mechanical, Packaging, and Orderable
Information.................................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2016) to Revision C (March 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Deleted HBM and CDM classification levels from Features and moved to ESD Ratings ..................................1
• Added functional safety links to Features .......................................................................................................... 1
• Changed Applications bullets............................................................................................................................. 1
• Changed ESD Ratings to show HBM and CDM classification levels................................................................. 6
• Added Figure 6-8, Common-Mode Voltage vs Temperature ............................................................................. 9
• Added Figure 6-9, Offset Voltage vs Common-Mode Voltage ...........................................................................9
Changes from Revision A (January 2016) to Revision B (May 2016)
Page
• Updated Applications examples......................................................................................................................... 1
• Updated the Pin Functions Table for OPA4376-Q1............................................................................................ 3
• Updated HBM ESD Rating ................................................................................................................................ 6
• Changed units on Channel Separation ..............................................................................................................8
• Deleted the temperature range parameters from the Electrical Characteristics table........................................ 8
• Removed section regarding WCSP photosensitivity ....................................................................................... 21
Changes from Revision * (April 2011) to Revision A (January 2016)
Page
• Added Pin Functions table, ESD Ratings table, Recommended Operating Conditions table, Thermal
Information tables, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support
section, and Mechanical, Packaging, and Orderable Information section.......................................................... 1
• Released the OPA2376-Q1 device as Production Data .................................................................................... 1
• Added the Input Offset Voltage and Input Offset Voltage Drift section to the Feature Description ..................13
2
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SBOS549C – APRIL 2011 – REVISED MARCH 2021
5 Pin Configuration and Functions
OUT
1
V-
2
+IN
3
V+
5
4
-IN
Figure 5-1. OPA376-Q1: DBV (5-Pin SOT-23)
Package, Top View
NC
(1)
+IN
1
V-
2
-IN
3
5
V+
4
OUT
Figure 5-2. OPA376-Q1: DCK (5-Pin SC70) Package,
Top View
1
8
NC
7
V+
(1)
-IN
2
+IN
3
6
OUT
V-
4
5
NC
+
(1)
(1) NC denotes no internal connection.
Figure 5-3. OPA376-Q1: D (8-Pin SOIC) Package, Top View
Table 5-1. Pin Functions: OPA376-Q1
PIN
NAME
NO.
I/O
DESCRIPTION
SOT-23
SC70
SOIC
+IN
3
1
3
I
Noninverting input+
–IN
4
3
2
I
Inverting input–
NC
—
—
1, 5, 8
—
No internal connection
OUT
1
4
6
O
Output
V+
5
5
7
—
Positive (highest) power supply+
V–
2
2
4
—
Negative (lowest) power supply–
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OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
Figure 5-4. OPA2376-Q1: D (8-Pin SOIC) and DGK (8-Pin VSSOP) Packages, Top View
Table 5-2. Pin Functions: OPA2376-Q1
PIN
NAME
4
NO.
I/O
DESCRIPTION
+IN A
3
I
Noninverting input, channel A+
–IN A
2
I
Inverting input, channel A–
+IN B
5
I
Noninverting input, channel B+
–IN B
6
I
Inverting input, channel B–
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) power supply
V+
8
—
Positive (highest) power supply
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SBOS549C – APRIL 2011 – REVISED MARCH 2021
OUT A
1
14
OUT D
-IN A
2
13
-IN D
+IN A
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
Figure 5-5. OPA4376-Q1: PW (14-Pin TSSOP) Package, Top View
Table 5-3. Pin Functions: OPA4376-Q1
PIN
NAME
NO.
I/O
DESCRIPTION
+IN A
3
I
Noninverting input, channel A+
–IN A
2
I
Inverting input, channel A–
+IN B
5
I
Noninverting input, channel B+
–IN B
6
I
Inverting input, channel B–
+IN C
10
I
Noninverting input, channel C+
–IN C
9
I
Inverting input, channel C–
+IN D
12
I
Noninverting input, channel D+
–IN D
13
I
Inverting input, channel D–
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V+
4
—
Positive (highest) power supply
V–
11
—
Negative (lowest) power supply
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SBOS549C – APRIL 2011 – REVISED MARCH 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VS = (V+) – (V–)
7
UNIT
V
voltage(2)
(V–) – 0.5
(V+) + 0.5
Signal input pin current(2)
–10
10
mA
–40
125
°C
150
°C
–65
150
°C
Signal input pin
Output short-circuit current(3)
TA
MAX
Supply voltage
Continuous
Operating temperature
TJ
Junction temperature
Tstg
Storage temperature
V
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2)
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must
be current limited to 10 mA or less.
(3)
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC
HBM ESD classification level 3A
Q100-002(1)
UNIT
±4000
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD classification level C6
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
6
VS = (V+) – (V–)
Supply voltage
TA
Operating temperature
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MIN
MAX
UNIT
2.2 (±1.1)
5.5 (±2.75)
V
–40
150
°C
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SBOS549C – APRIL 2011 – REVISED MARCH 2021
6.4 Thermal Information: OPA376-Q1
OPA376-Q1
THERMAL
METRIC(1)
DCK (SC70)
DBV (SOT-23)
D (SOIC)
5 PINS
5 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
267
273.8
100.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
80.9
126.8
42.4
°C/W
RθJB
Junction-to-board thermal resistance
54.8
85.9
41
°C/W
ψJT
Junction-to-top characterization parameter
1.2
10.9
4.8
°C/W
ψJB
Junction-to-board characterization parameter
54.1
84.9
40.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2376-Q1
OPA2376-Q1
THERMAL METRIC(1)
D (SOIC)
DGK (VSSOP)
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
111.1
171.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
54.7
63.9
°C/W
RθJB
Junction-to-board thermal resistance
51.7
92.8
°C/W
ψJT
Junction-to-top characterization parameter
10.5
9.2
°C/W
ψJB
Junction-to-board characterization parameter
51.2
91.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4376-Q1
OPA4376-Q1
THERMAL
METRIC(1)
PW (TSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
107.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.6
°C/W
RθJB
Junction-to-board thermal resistance
52.6
°C/W
ψJT
Junction-to-top characterization parameter
1.5
°C/W
ψJB
Junction-to-board characterization parameter
51.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.7 Electrical Characteristics
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5
25
μV
0.26
1
μV/°C
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage versus
temperature
TA = –40°C to +85°C
PSRR
Input offset voltage versus
power supply
VS = 2.2 V to 5.5 V,
VCM < (V+) – 1.3 V
TA = –40°C to +125°C
0.32
2
μV/°C
TA = 25°C
5
20
μV/V
TA = –40°C to +125°C
5
μV/V
0.5
µV/V
Channel separation, dc (dual,
quad)
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
TA = 25°C
0.2
TA = –40°C to +125°C
10
See Section 6.8
0.2
pA
pA
10
pA
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
0.8
μVPP
en
Input voltage noise density
f = 1 kHz
7.5
nV/√ Hz
in
Input current noise
f = 1 kHz
2
fA/√ Hz
INPUT VOLTAGE
VCM
Common-mode voltage
See Figure 6-8
CMRR
Common-mode rejection ratio
(V–) < VCM < (V+) – 1.3 V
(V–) – 0.1
76
(V+) + 0.1
V
90
dB
Differential
6.5
pF
Common-mode
13
pF
INPUT CAPACITANCE
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
50 mV < VO < (V+) – 50 mV, RL = 10 kΩ
120
134
dB
100 mV < VO < (V+) – 100 mV, RL = 2 kΩ
120
126
dB
5.5
MHz
2
V/μs
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
CL = 100 pF, VS = 5.5 V
SR
Slew rate
G = 1, CL = 100 pF, VS = 5.5 V
0.1%, 2-V Step , G = 1, CL = 100 pF, VS = 5.5 V
tS
Settling time
Overload recovery time
VIN × Gain > VS
THD+N
THD + noise
VO = 1 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ
0.01%, 2-V Step , G = 1, CL = 100 pF, VS = 5.5 V
1.6
μs
2
μs
0.33
μs
0.00027%
OUTPUT
RL = 10 kΩ
Voltage output swing from rail
RL = 2 kΩ
ISC
Short-circuit current
CLOAD
Capacitive load drive
RO
Open-loop output impedance
TA = 25°C
10
TA = –40°C to +125°C
TA = 25°C
40
TA = –40°C to +125°C
20
mV
40
mV
50
mV
80
mV
30 / –50
mA
See Section 6.8
150
Ω
POWER SUPPLY
VS
Specified voltage
2.2
Operating voltage
IQ
8
Quiescent current per amplifier IO = 0, VS = 5.5 V, VCM < (V+) – 1.3 V
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5.5
V
950
μA
1
mA
2 to 5.5
TA = 25°C
760
TA = –40°C to +125°C
V
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SBOS549C – APRIL 2011 – REVISED MARCH 2021
6.8 Typical Characteristics
0
140
-20
120
120
-40
Gain
100
-60
Phase
80
-80
60
-100
40
-120
20
-140
0
-160
-20
0.1
1
10
100
1k
10k
100k
V(+) Power-Supply Rejection Ratio
Power-Supply Rejection Ratio (dB)
160
Phase Margin (°)
Open-Loop Gain (dB)
at TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
100
80
40
V(-) Power-Supply Rejection Ratio
20
-180
10M
1M
Common-Mode
Rejection Ratio
60
0
10
100
1k
Frequency (Hz)
10k
100k
1M
10M
Frequency (Hz)
Figure 6-1. Open-Loop Gain and Phase vs Frequency
Figure 6-2. Power-Supply and Common-Mode Rejection Ratio
vs Frequency
Open-Loop Gain (RL = 2kW)
140
120
500nV/div
Open-Loop Gain and PSRR (dB)
160
Power-Supply Rejection Ratio
(VS = 2.1V to 5.5V)
100
80
-50
0
-25
25
50
75
100
125
150
Temperature (°C)
1s/div
Figure 6-4. 0.1-Hz to 10-Hz Input Voltage Noise
Figure 6-3. Open-Loop Gain and Power-Supply Rejection Ratio
vs Temperature
1
Total Harmonic Distortion + Noise (%)
Voltage Noise (nV/ÖHz)
100
10
1
VS = 5V, VCM = 2V, VOUT = 1VRMS
0.1
0.01
Gain = 10V/V
0.001
Gain = 1V/V
0.0001
1
10
100
1k
10k
100k
10
100
Frequency (Hz)
Figure 6-5. Input Voltage Noise Spectral Density
1k
10k
100k
Frequency (Hz)
Figure 6-6. Total Harmonic Distortion + Noise vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
Common-Mode Rejection Ratio (dB)
110
100
90
80
70
60
50
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
VCM range for typical CMRR = 90 dB
Figure 6-8. Common-Mode Voltage vs Temperature
Figure 6-7. Common-Mode Rejection Ratio vs Temperature
Quiescent Current (mA)
1000
900
800
700
600
500
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
(V–) = 0 V
TA = 125°C
Figure 6-10. Quiescent Current vs Temperature
Figure 6-9. Offset Voltage vs Common-Mode Voltage
75
50
1000
VS = ±2.75V
Quiescent Current (mA)
ISC+
30
800
IQ
700
20
10
600
Short-Circuit Current (mA)
40
900
Short-Circuit Current (mA)
50
ISC+
25
0
-25
ISC-
-50
-75
0
500
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-100
-50
-25
0
25
Supply Voltage (V)
Figure 6-11. Quiescent and Short-Circuit Current vs Supply
Voltage
10
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50
75
100
125
150
Temperature (°C)
Figure 6-12. Short-Circuit Current vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
3
1000
VS = ±2.75
2
800
Output Voltage (V)
Input Bias Current (pA)
900
700
600
500
400
300
200
1
+150°C
+125°C
+25°C
-40°C
0
-1
-2
100
0
-3
-50
-25
0
25
50
75
100
125
0
150
10
30
40
50
60
70
80
Figure 6-14. Output Voltage vs Output Current
-25.0
-22.5
-20.0
-17.5
-15.0
-12.5
-10.0
-7.5
-5.0
-2.5
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
Population
Population
Figure 6-13. Input Bias Current vs Temperature
½Offset Voltage Drift½ (mV/°C)
Offset Voltage (mV)
Figure 6-15. Offset Voltage Production Distribution
6
Small-Signal Overshoot (%)
G = +1V/V
4
3
VS = 2.5V
2
1
0
1k
Figure 6-16. Offset Voltage Drift Production Distribution
(–40°C to +125°C)
50
VS = 5.5V
VS = 5V
5
Output Voltage (VPP)
20
Output Current (mA)
Temperature (°C)
10k
100k
1M
10M
Frequency (Hz)
Figure 6-17. Maximum Output Voltage vs Frequency
40
30
20
10
0
10
100
1k
Load Capacitance (pF)
Figure 6-18. Small-Signal Overshoot vs Load Capacitance
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
G = +1
RL = 2kW
CL = 50pF
1V/div
50mV/div
G = +1
RL = 10kW
CL = 50pF
Time (2ms/div)
Time (400ns/div)
Figure 6-19. Small-Signal Pulse Response
Figure 6-20. Large-Signal Pulse Response
140
100
Channel Separation (dB)
Settling Time (ms)
120
10
0.01%
1
0.1%
100
80
60
40
20
0
0.1
10
1
10
100
100
10k
1k
100k
1M
10M
100M
Frequency (Hz)
Closed-Loop Gain (V/V)
Figure 6-22. Channel Separation vs Frequency
Figure 6-21. Settling Time vs Closed-Loop Gain
Open-Loop Output Resistance (W)
1k
100
10
400mA Load
2mA Load
1
0.1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 6-23. Open-Loop Output Resistance vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx376-Q1 family belongs to a new generation of low-noise e-trim operational amplifiers, giving
customers outstanding dc precision and ac performance. Low noise, rail-to-rail input and output, low offset,
and drawing a low quiescent current, make these devices an excellent choice for a variety of precision and
portable applications. In addition, these devices have a wide supply range with excellent PSRR, making the
OPAx376-Q1 a great option for applications that are battery powered without regulation.
7.2 Functional Block Diagram
V+
OPAx376
-IN
OUT
+IN
POR
e-trim
V-
7.3 Feature Description
The OPAx376-Q1 family of precision amplifiers offers excellent dc performance as well as excellent ac
performance. Operating from a single power-supply the OPAx376-Q1 is capable of driving large capacitive
loads, has a wide input common-mode voltage range, and is well-suited to drive the inputs of successiveapproximation response (SAR) analog-to-digital converters (ADCs) as well as 24-bit and higher resolution
converters. Including internal ESD protection, the OPAx376-Q1 family is offered in a variety of industry-standard
packages, including a wafer chip-scale package for applications that require space savings.
7.3.1 Operating Voltage
The OPAx376-Q1 family of amplifiers operate over a power-supply range of 2.2 V to 5.5 V (±1.1 V to ±2.75 V).
Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with
regard to operating voltage or temperature are presented in Section 6.8.
7.3.2 Input Offset Voltage and Input Offset Voltage Drift
The OPAx376-Q1 family of e-trim operational amplifiers is manufactured using TI's proprietary trim technology,
a method of trimming internal device parameters during either wafer probing or final testing. Each amplifier is
trimmed in production, thereby minimizing errors associated with input offset voltage and input offset voltage
drift.
7.3.3 Capacitive Load and Stability
The OPAx376-Q1 series of amplifiers may be used in applications where driving a capacitive load is required.
As with all op amps, there may be specific instances where the OPAx376-Q1 can become unstable, leading to
oscillation. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors
to consider when establishing whether an amplifier is be stable in operation. An op amp in the unity-gain (1 V/V)
buffer configuration and driving a capacitive load exhibits a greater tendency to be unstable than an amplifier
operated at a higher noise gain. The capacitive load, in conjunction with the op amp output resistance, creates a
pole within the feedback loop that degrades the phase margin. The degradation of the phase margin increases
as the capacitive loading increases.
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The OPAx376 in a unity-gain configuration can directly drive up to 250 pF of pure capacitive load. Increasing
the gain enhances the ability of the amplifier to drive greater capacitive loads; see the typical characteristic plot
Figure 6-18, Small-Signal Overshoot vs Load Capacitance. In unity-gain configurations, capacitive load drive can
be improved by inserting a small (10-Ω to 20-Ω) resistor, RS, in series with the output, as shown in Figure 7-1.
This resistor significantly reduces ringing while maintaining dc performance for purely capacitive loads. However,
if there is a resistive load in parallel with the capacitive load, a voltage divider is created, introducing a gain error
at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RS / RL, and
is generally negligible at low output current levels.
V+
RS
VOUT
OPA376
10W to
20W
VIN
RL
CL
Figure 7-1. Improving Capacitive Load Drive
7.3.4 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx376-Q1 series extends 100 mV beyond the supply rails. The
offset voltage of the amplifier is very low, from approximately (V–) to (V+) – 1 V, as shown in Figure 7-2. The
offset voltage increases as common-mode voltage exceeds (V+) –1 V. Common-mode rejection is specified from
(V–) to (V+) – 1.3 V.
Input Offset Voltage (mV)
3
2
1
0
-1
-2
-V
+V
-3
-0.5 0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common-Mode Voltage (V)
Figure 7-2. Offset and Common-Mode Voltage
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7.3.5 Input and ESD Protection
The OPAx376-Q1 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the
case of input and output pins, this protection primarily consists of current steering diodes connected between the
input and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as
long as the current is limited to 10 mA as stated in Section 6.1.
Figure 7-3 shows how a series input resistor may be added to the driven input to limit the input current. The
added resistor contributes thermal noise at the amplifier input and its value must be kept to a minimum in
noise-sensitive applications.
V+
IOVERLOAD
10mA max
OPA376
VOUT
VIN
5kW
Figure 7-3. Input Current Protection
7.4 Device Functional Modes
The OPAx376-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
2.2 V (±1.1 V). The maximum power supply voltage for the OPAx376-Q1 is 5.5 V (±2.75 V).
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The OPAx376-Q1 family of e-trim operational amplifiers is built using a proprietary technique in which offset
voltage is adjusted during the final steps of manufacturing. This technique compensates for performance shifts
that can occur during the molding process. Through e-trim operational amplifier technology, the OPAx376-Q1
family delivers excellent offset voltage (5 μV, typical). Additionally, the amplifier boasts a fast slew rate, low drift,
low noise, and excellent PSRR and AOL. These 5.5-MHz CMOS op amps operate on 760 μA (typical) quiescent
current.
8.1.1 Basic Amplifier Configurations
The OPAx376-Q1 family is unity-gain stable. It does not exhibit output phase inversion when the input is
overdriven. A typical single-supply connection is shown in Figure 8-1. The OPA376-Q1 is configured as a
basic inverting amplifier with a gain of –10 V/V. This single-supply connection has an output centered on the
common-mode voltage, VCM. For the circuit shown in Figure 8-1, this voltage is 2.5 V, but may be any value
within the common-mode input voltage range.
R2
10kW
+5V
C1
100nF
R1
1kW
OPA376
VOUT
VIN
VCM = 2.5V
Figure 8-1. Basic Single-Supply Connection
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8.1.2 Active Filtering
The OPA376-Q1 series is well-suited for filter applications requiring a wide bandwidth, fast slew rate, low-noise,
single-supply operational amplifier. Figure 8-2 shows a 50-kHz, second-order, low-pass filter. The components
have been selected to provide a maximally-flat Butterworth response. Beyond the cutoff frequency, roll-off is
–40 dB/dec. The Butterworth response is ideal for applications requiring predictable gain characteristics such as
the anti-aliasing filter used ahead of an ADC.
R3
5.49kW
C2
150pF
V+
R1
5.49kW
R2
12.4kW
OPA376
VOUT
C1
1nF
VIN
(V+)/2
Figure 8-2. Second-Order Butterworth, 50-kHz Low-Pass Filter
8.1.3 Driving an Analog-to-Digital Converter
The low noise and wide gain bandwidth of the OPA376-Q1 family make it an ideal driver for ADCs. Figure 8-3
illustrates the OPA376-Q1 driving an ADS8327, 16-bit, 250-kSPS converter. The amplifier is connected as a
unity-gain, noninverting buffer.
+5V
C1
0.1mF
+5V
(1)
R1
100W
+IN
OPA376
(1)
C3
1.2nF
VIN
ADS8327
Low Power
16-Bit
500kSPS
-IN
REF IN
+5V
REF5040
4.096V
C4
100nF
(1) Suggested value; may require adjustment based on specific application.
Figure 8-3. Driving an ADS8327
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8.1.4 Phantom-Powered Microphone
The circuit shown in Figure 8-4 depicts how a remote microphone amplifier can be powered by a phantom
source on the output side of the signal cable. The cable serves double duty, carrying both the differential output
signal from and dc power to the microphone amplifier stage.
An OPA2376-Q1 serves as a single-ended input to a differential output amplifier with a 6-dB gain. Commonmode bias for the two op amps is provided by the dc voltage developed across the electret microphone element.
A 48-V phantom supply is reduced to 5.1 V by the series 6.8-kΩ resistors on the output side of the cable, and the
4.7-kΩ resistors and zener diode on the input side of the cable. AC coupling blocks the different dc voltage levels
from each other on each end of the cable.
An INA163 instrumentation amplifier provides differential inputs and receives the balanced audio signals from
the cable.
The INA163 gain may be set from 0 dB to 80 dB by selecting the RG value. The INA163 circuit is typical of the
input circuitry used in mixing consoles.
Phantom Power
(Provides power source for microphone)
48V
Microphone
100W
+
1mF
D1
5.1V
+
33mF
R1
2.7kW
C2
33mF
R6
100W
R8
4.7kW
R9
4.7kW
R10
6.8kW
+
1/2
OPA2376
R11
6.8kW
+15V
10mF
+
2
2
3
3
1kW
RG
INA163
10mF
+
Panasonic
WM-034CY
1kW
1
10kW
+
+
1/2
OPA2376
C3
33mF
1
R7
100W
3.3kW
Low-level differential audio signal
is transmitted differentially on the
same cable as power to the microphone.
3.3kW
-15V
10mF
Typical microphone input circuit used in mixing consoles.
Figure 8-4. Phantom-Powered Electret Microphone
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8.1.5 Speech Bandpass-Filtered Data Acquisition System
Figure 8-5 illustrates the OPA2376-Q1 driving a speech bandpass-filtered data acquisition system.
V+ = +2.7V to 5V
Passband 300Hz to 3kHz
R9
510kW
R1
1.5kW
R4
20kW
R2
1MW
C3
33pF
C1
1000pF
R7
51kW
1/2
OPA2376
Electret
(1)
Microphone
R3
1MW
R8
150kW
VREF 1
8 V+
7
1/2
OPA2376
R6
100kW
C2
1000pF
+IN
ADS7822 6
12-Bit A/D
5
2
-IN
DCLOCK
DOUT
CS/SHDN
Serial
Interface
3
4
G = 100
R5
20kW
GND
(1) Electret microphone powered by R1.
Figure 8-5. OPA2376-Q1 as a Speech Bandpass-Filtered Data Acquisition System
8.2 Typical Application
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPA376-Q1 is ideally suited to construct high-speed, high-precision active filters. Figure 8-6 shows a
second-order, low-pass filter commonly encountered in signal processing applications.
R4
2.94 k
C5
1 nF
R1
590
R3
499
Input
C2
39 nF
±
Output
+
OPA376
Figure 8-6. Typical Application Schematic
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8.2.1 Design Requirements
Use the following parameters for this design example:
• Gain = 5 V/V (inverting gain)
• Low-pass cutoff frequency = 25 kHz
• Second-order Chebyshev filter response with 3-dB gain peaking in the passband
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 8-6. Use Equation 1
to calculate the voltage transfer function.
Output
s
Input
1 R1R3C2C5
s
2
s C2 1 R1 1 R3 1 R4
1 R3R4C2C5
(1)
This circuit produces a signal inversion. For this circuit, the gain at dc and the low-pass cutoff frequency are
calculated by Equation 2:
Gain
fC
1
2S
R4
R1
1 R3R 4 C2C5
(2)
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter
designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multi-stage active filter solutions within minutes.
8.2.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 8-7. Low-Pass Filter Transfer Function
9 Power Supply Recommendations
The OPAx376-Q1 family of devices is specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V); many
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in Section 6.8.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
the Circuit Board Layout Techniques application report.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 10-1, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Place components
close to device and to
Run the input
each other to reduce
traces as far away
parasitic errors
from the supply
lines as possible
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 10-1. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ Simulation Software (Free Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™
simulation software is a free, fully-functional version of the TINA software, preloaded with a library of macro
models in addition to a range of both passive and active models. TINA-TI simulation software provides all the
conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer
the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials,
and measured performance of many useful circuits. TI Precision Designs are available online at http://
www.ti.com/ww/en/analog/precision-designs/.
11.1.1.3 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The
WEBENCH® Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers
and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, INA163 Low-Noise, Low-Distortion Instrumentation Amplifier data sheet
• Texas Instruments, Operational Amplifier Gain stability, Part 3: AC Gain-Error Analysis
• Texas Instruments, Operational Amplifier Gain Stability, Part 2: DC Gain-Error Analysis
• Texas Instruments, Op Amp Performance Analysis
• Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes
• Texas Instruments, Single-Supply Operation of Operational Amplifiers
• Texas Instruments, Tuning in Amplifiers
• Texas Instruments, Using Infinite-Gain, MFB Filter Topology in Fully Differential Active Filters
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
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Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
e-trim™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2376AQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2376Q1
OPA2376QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2376
OPA376AQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OUHQ
OPA4376AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4376Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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