OPA607, OPA2607
SBOS981J – OCTOBER 2019 OPA607,
– REVISED OPA2607
APRIL 2021
SBOS981J – OCTOBER 2019 – REVISED APRIL 2021
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OPAx607 50-MHz, Low-Power, Rail-to-Rail Output CMOS Operational Amplifier for
Cost Sensitive Systems
1 Features
3 Description
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The
OPA607
and
OPA2607
devices
are
decompensated, minimum gain of 6 V/V stable,
general-purpose CMOS operational amplifier with low
noise of 3.8 nV/√ Hz and a GBW of 50 MHz.
The low noise and wide bandwidth of the OPAx607
devices make them attractive for general-purpose
applications which require a good balance between
cost and performance. The high-impedance CMOS
inputs make the OPAx607 devices an ideal amplifier
to interface with sensors with high output impedance
(for example, piezoelectric transducers).
Gain Bandwidth Product (GBW): 50 MHz
Quiescent Current: 900 µA (Typical)
Broadband Noise: 3.8 nV/√Hz
Input Offset Drift: 1.5 μV/°C (Maximum)
Offset Voltage: 120 µV (Typical)
Input Bias Current: 10 pA (Maximum)
Rail-to-Rail Output (RRO)
Decompensated, Gain ≥ 6 V/V (Stable)
Power Down Current: 1 µA (Maximum)
Supply Range: 2.2 V to 5.5 V
2 Applications
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The OPAx607 devices feature a Power Down mode
with a maximum quiescent current of less than 1 µA,
making the device suitable for use in portable batterypowered applications. The rail-to-rail output (RRO) of
the OPAx607 devices can swing up to 8 mV from the
supply rails, maximizing dynamic range.
Current-Sensing
Fish Finders and Sonar
Ultrasonic Flow Meters
Garden and Power Tools
Printers
Light Curtains and Safety Guards
Optical Modules
Handheld Test Equipment
PM2.5 and PM10 Particle Sensors
The OPAx607 is optimized for low supply voltage
operation as low as 2.2 V (±1.1 V) and up to 5.5 V
(±2.75 V), and is specified over the temperature range
of –40°C to +125°C.
Device Information(1)
PART NUMBER
OPA607
OPA2607
(1)
VTH
LOAD
±
RF
SOT23 (5)
2.90 mm × 1.60 mm
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
X2QFN (10)
1.50 mm × 2.00 mm
See the orderable addendum at the end of the data sheet for
all available packages.
VREF
TLV3201
LED driver
ADS7042
VS+
RF
±
RSH
Transimpedance
stage
+
OPA607
í
RG
ISH
BODY SIZE (NOM)
2.00 mm × 1.25 mm
Short Circuit
Detection
+
VS+
PACKAGE
SC70 (6)
REXT
ADS7042
OPA607
RG
+
CEXT
Photodiode
CF
RF
VREF
OPAx607 for Current-Sensing Application
OPAx607 for Transimpedance Application
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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SBOS981J – OCTOBER 2019 – REVISED APRIL 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 4
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings ....................................... 7
7.2 ESD Ratings .............................................................. 7
7.3 Recommended Operating Conditions ........................7
7.4 Thermal Information ...................................................8
7.5 Electrical Characteristics ............................................9
7.6 Typical Characteristics.............................................. 11
8 Detailed Description......................................................17
8.1 Overview................................................................... 17
8.2 Functional Block Diagram......................................... 17
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................21
9 Application and Implementation.................................. 22
9.1 Application Information............................................. 22
9.2 Typical Applications.................................................. 22
10 Power Supply Recommendations..............................29
11 Layout........................................................................... 30
11.1 Layout Guidelines................................................... 30
11.2 Layout Examples.....................................................30
12 Device and Documentation Support..........................31
12.1 Device Support....................................................... 31
12.2 Documentation Support.......................................... 31
12.3 Related Links.......................................................... 31
12.4 Receiving Notification of Documentation Updates..31
12.5 Support Resources................................................. 31
12.6 Trademarks............................................................. 31
12.7 Electrostatic Discharge Caution..............................31
12.8 Glossary..................................................................31
13 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (February 2021) to Revision J (April 2021)
Page
• Removed the preview statement from the VSSOP (8) and X2QFN (10) package in the Device Information
table.................................................................................................................................................................... 1
• Removed the preview statement from the OPA2607 X2QFN (RUG) package and VSSOP (DGK) in the
Device Comparison section................................................................................................................................ 4
• Removed the preview statement from the OPA2607 D, DGK and OPA2607 RUG package in the Pin
Configuration and Functions section.................................................................................................................. 5
Changes from Revision H (December 2020) to Revision I (February 2021)
Page
• Updated the title of the data sheet......................................................................................................................1
Changes from Revision G (October 2020) to Revision H (December 2020)
Page
• Updated the I/O and Descriptions in the Pin Functions—Single Channel table................................................. 5
Changes from Revision F (September 2020) to Revision G (October 2020)
Page
• Removed the RUG Package 8-Pin X2QFN pinout to the Pin Configuration and Functions section...................5
• Removed the N/C pin decription from the Pin Functions – Single Channel table...............................................5
• Changed Overdrive Recovery Time from 0.25µs to 0.3µs ...............................................................................9
• Updated the Turn-On and Turn-Off Time figure in the Typical Characteristics section..................................... 11
• Updated the Power Down Pin Bias Current vs Power Down Pin Voltage figure in the Typical Characteristics
section...............................................................................................................................................................11
• Updated the Input Offset Voltage vs Temperature figure in the Typical Characteristics section....................... 11
• Updated the Common Mode Rejection Ratio vs Temperature figure in the Typical Characteristics section.....11
• Updated the Short-Circuit Current vs Temperature figure in the Typical Characteristics section......................11
• Updated the Input Bias and Offset Current vs Temperature figure in the Typical Characteristics section........ 11
• Updated the Output Voltage vs Output Current Sourcing and Sinking figure in the Typical Characteristics
section...............................................................................................................................................................11
• Added the Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs
Frequency figure to the Typical Characteristics section....................................................................................11
• Added the Crosstalk vs Frequency figure to the Typical Characteristics section..............................................11
2
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•
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SBOS981J – OCTOBER 2019 – REVISED APRIL 2021
Added the Quiescent Current vs Temperature figure to the Typical Characteristics section............................ 11
Updated the Simulated Closed-Loop Bandwidth of TIA figure in the Application Curves section.................... 23
Updated the Simulated Time Domain Response figures in the Application Curves section.............................23
Updated the Small-Signal Frequency Response in Gains of 3V/V (a) and 6V/V (b) figure in the Noninverting
Gain of 3 V/V section........................................................................................................................................ 24
Updated the Small-Signal Frequency Response of Difference Amplifier (c) With and Without Noise Gain
Shaping figures in the Noninverting Gain of 3 V/V section............................................................................... 24
Changes from Revision E (August 2020) to Revision F (September 2020)
Page
• Deleted blank CMRR specifications from Electrical Characteristics table.......................................................... 9
Changes from Revision D (May 2020) to Revision E (August 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed status of OPA2607 SOIC (8) package From: Preview To: Active .......................................................1
Changes from Revision C (April 2020) to Revision D (May 2020)
Page
• Changed status From: Advanced Information To: Production Data ...................................................................1
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SBOS981J – OCTOBER 2019 – REVISED APRIL 2021
5 Device Comparison
DEVICE
NO. OF
CHANNELS
OPA607
1
OPA2607
(1)
4
PACKAGE LEADS
2
SOIC
(D)
X2QFN
(RUG)(1)
VSSOP (DGK)
SC-70
(DCK)(1)
SOT-23 (DBV)
—
—
—
6(1)
5
8
10(1)
8
—
—
Package with Power Down mode.
DEVICE
INPUT
OFFSET
DRIFT
(µV/°C, TYP)
MINIMUM
STABLE GAIN
(V/V)
IQ / CHANNEL
(mA, TYP)
GBW
(MHz)
SLEW RATE
(V/µs)
VOLTAGE
NOISE
(nV/√Hz)
OPAx365
CMOS
1
1
4.6
50
25
4.5
OPAx607
CMOS
0.3
6
0.9
50
24
3.8
OPAx837
Bipolar
0.4
1
0.6
50
105
4.7
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6 Pin Configuration and Functions
5
OUT
VS+
VS±
VS±
6
VS+
5
PD
IN-
IN+
OUT
Figure 6-1. DBV Package
5-Pin SOT-23
Top View
Figure 6-2. DCK Package
6-Pin SC70
Top View
Pin Functions – Single Channel
PIN
NAME
I/O
DESCRIPTION
DBV
DCK
IN–
4
3
I
Inverting input
IN+
3
1
I
Non inverting input
OUT
1
4
O
Output
PD
—
5
I
Power down (can be left floating)
VS–
2
2
—
Negative supply or ground (for single-supply operation)
VS+
5
6
—
Positive supply
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VS+
OUT1
1
IN1-
2
IN1+
3
8
7
±
A
+
±
B
VS-
4
+
6
5
10
VS+
OUT1 1
9 OUT2
OUT2
IN1- 2
IN2-
8 IN2-
B
A
IN2+
IN1+ 3
Figure 6-3. OPA2607 D, DGK Package
8-Pin SOIC, VSSOP
Top View
7 IN2+
PD1 4
6
5
PD2
VS-
Figure 6-4. OPA2607 RUG Package
10-Pin X2QFN
Top View
Pin Functions – Dual Channel
PIN
NAME
6
I/O
DESCRIPTION
D, DGK
RUG
IN1–
2
2
I
Inverting input, channel 1
IN1+
3
3
I
Noninverting input, channel 1
IN2–
6
8
I
Inverting input, channel 2
IN2+
5
7
I
Noninverting input, channel 2
OUT1
1
1
O
Output, channel 1
OUT2
7
9
O
Output, channel 2
VS–
4
5
—
Negative (lowest) supply or ground (for single-supply operation)
VS+
8
10
—
Positive (highest) supply
PD1
—
4
I
Low = amplifier 1 disabled, high = amplifier 1 enabled; see the Power Down
Mode section for more information.
PD2
—
6
I
Low = amplifier 2 disabled, high = amplifier 2 enabled; see the Power Down
Mode section for more information.
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
(VS+) – (VS–)
Supply voltage, Vs
VIN+, VIN–
Input voltage
VPD
PD voltage
VID
MAX
UNIT
6
V
(VS–) – 0.5
(VS+) + 0.5
V
(VS–) – 0.5
6
V
Differential input voltage(4)
±5
V
II
Continuous input current(2)
±10
mA
IO
Continuous output current(3)
±20
mA
Continuous power dissipation
See Thermal Information
TJ
Maximum junction temperature
150
°C
TA
Operating free-air temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
(4)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails
should be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
Long term drift of offset voltage (> 1mV) if a differential input in excess of ≈ 2V is applied continuously between the IN+ and IN- pins at
elevated temperatures.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
D Package , Charged-device model (CDM), per JEDEC specification JESD22C101(2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Supply voltage (VS+) – (VS–)
TA
Ambient operating temperature
NOM
MAX
2.2
5.5
±1.1
±2.75
–40
25
125
UNIT
V
°C
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7.4 Thermal Information
OPAx607
THERMAL METRIC(1)
DBV
(SOT23)
DCK (SC70)
RUG
(X2QFN)
8 PINS
8 PINS
5 PINS
6 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
131.1
179
196.5
219.7
152
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
73.2
71
118.7
182.6
58
°C/W
RθJB
Junction-to-board thermal resistance
74.5
101
64.5
105.7
77
°C/W
ψJT
Junction-to-top characterization parameter
24.5
13
41.1
87
1.2
°C/W
ψJB
Junction-to-board characterization parameter
73.3
100
64.2
105.4
77
°C/W
(1)
8
D (SOIC)
DGK
(VSSOP)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
At TA = 25°C, VS = 2.2 V to 5.5 V, G = 6 V/V(5), RF = 5 kΩ, CF = 2.5 pF, VCM = (VS / 2) – 0.5 V, CL = 10 pF,
connected to (VS / 2) – 0.5 V, and, PD connected to (VS+) (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
RL = 10 kΩ
TYP
MAX
–0.6
0.12
0.6
–0.7
0.12
0.7
±0.3
±1.5
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
Input offset voltage
TA = –40°C to +125°C
dVOS/dT
Input offset voltage drift
TA = –40°C to +125°C
PSRR
Power-supply rejection ratio
VS = 2.2 V to 5.5 V
95
120
mV
µV/°C
dB
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio(3)
(VS–)
(VS–) < VCM < (VS+) – 1.1 V
90
(VS+)–1.1
100
V
dB
INPUT BIAS CURRENT
IB
IOS
Input bias current(2)
Input offset
±3
TA = –40℃ to 125℃
±10
See Fig. 29
current(2)
±3
pA
±10
NOISE
Input voltage noise (peak-to-peak)
f = 0.1 Hz to 10 Hz
1.6
µVPP
eN
Input voltage noise density
f = 10 kHz, 1/f corner at 1 kHz
3.8
nV/√Hz
iN
Input current noise density
f = 1 kHz
46
fA/√Hz
INPUT IMPEDANCE
CIN
Differential
11.5
Common-mode
5.5
pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain(3)
(VS–) + 400 mV < VOUT < (VS+) – 400 mV
Phase margin
110
130
dB
65
°
AC Characteristics (VS = 5 V)
SSBW
Small-signal bandwidth
VOUT = 20 mVpp
GBW
Gain-bandwidth product
G = 20 V/V
50
SR
Slew rate
3-V output step (10-90%), VOCM = mid-supply
24
To 0.1%, 3-V step, G = 40, VOCM = mid-supply
1
tS
Settling time
Overdrive recovery time
To 0.01%, 3-V step, G = 40, VOCM = mid-supply
VIN+ × Gain > VS
9
1.8
0.3
VOUT = 2 VPP, f = 1 kHz , RL = 10 kΩ
-103
VOUT = 2 VPP, f = 20 kHz , RL = 10 kΩ
-91.5
THD + N
Total Harmonic Distortion + Noise(6)
VOUT = 2 VPP, f = 20 kHz , RL = 1 kΩ
-72.8
HD2
Second-order harmonic distortion
VOUT = 2 VPP f = 20 kHz
-105
HD3
Third-order harmonic distortion
VOUT = 2 VPP f = 20 kHz
-95
Channel-to-channel crosstalk
VOUT = 2 VPP, f = 100 kHz
-114
VOUT = 2 VPP, f = 1 kHz , RL = 1 kΩ
-96
MHz
V/µs
µs
µs
dB
dBc
dBc
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7.5 Electrical Characteristics (continued)
At TA = 25°C, VS = 2.2 V to 5.5 V, G = 6 V/V(5), RF = 5 kΩ, CF = 2.5 pF, VCM = (VS / 2) – 0.5 V, CL = 10 pF,
connected to (VS / 2) – 0.5 V, and, PD connected to (VS+) (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
RL = 10 kΩ
MAX
UNIT
OUTPUT
8
Output voltage swing from supply rails
ISC
Output Short-circuit current
ZO
Open-loop output impedance
TA = – 40℃ to +125℃
12
12
mV
60
mA
f = 1 MHz
500
Ω
IO = 0 mA
900
POWER SUPPLY
IQ
Quiescent current per amplifier
IO = 0 mA, TA = –40°C to +125°C
1100
1200
µA
POWER DOWN (Device Enabled When Floating)
Power Down quiescent current per amplifier(4)
PD = VS–
750
1000
Power Down pin bias current per amplifier(7)
PD = VS–
–750
–1000
Enable voltage threshold
Logic-High threshold
Disable voltage threshold
Logic-Low threshold
0.7 x VS
0.2 x VS
tON
Turn-on time delay(2)
10
tOFF
Turn-off time delay
0.5
(1)
(2)
(3)
(4)
(5)
(6)
(7)
10
nA
15
V
µs
Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted. Over
temperature limits are based on characterization and statistical analysis.
Specified by design and characterization or both ; not production tested.
Production Tested at VS = 5.5V
In Power Down mode current drawn by the opamp is equal to the bias current sourced on the PD pin
All Gains (G) mentioned are in V/V unless otherwise noted.
Lowpass-filter bandwidth is 92kHz for f = 20 kHz and 20 kHz for f = 1 kHz.
Negative value of the Power Down bias current indicates current being sourced from the opamp's PD pin towards external circuit.
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7.6 Typical Characteristics
180
120
150
100
120
80
90
60
60
40
30
20
0
0
-20
10
100
1k
10k
100k
Frequency (Hz)
.
1M
-60
100M
10M
1
10
.
1k
Frequency (Hz)
.
.
10k
100k
D010
.
.
Figure 7-2. Input Voltage Noise Density vs Frequency
3
100
0
10
Normalized Gain (dB)
Input Current Noise (pA/—Hz)
100
D002
Figure 7-1. Open Loop Gain and Phase vs Frequency
1
0.1
-3
-6
-9
-12
0.01
10
100
1k
10k
100k
Frequency (Hz)
.
1M
10M
.
.
.
Normalized Gain (dB)
0
-6
D003
VOUT = 20 mVPP
.
-3
-6
-9
CL = 10 pF
CL = 5 pF
CL = 22 pF
RL = 10 k:
RL = 2 k:
1M
10M
Frequency (Hz)
.
100M
Figure 7-4. Small-Signal Frequency Response vs Gain
0
-3
10M
Frequency (Hz)
3
-12
100k
1M
D101
3
-9
Gain = 6 V/V
Gain = 5 V/V
Gain = 10 V/V
Gain = 20 V/V
-15
100k
100M
Figure 7-3. Input Current Noise Density vs Frequency
Normalized Gain (dB)
10
-30
Magnitude (dB)
Phase (q)
1
100
Input Voltage Noise (nV/—Hz)
140
Open-Loop Phase (q)
Open-Loop Gain Magnitude (dB)
At TA = +25°C, VS = 5.5 V, RL = 10 kΩ, RF= 5 kΩ, CF= 2.5 pF, VCM = midsupply – 0.5 V, G = 6 V/V (unless otherwise noted).
VOUT = 20 mVPP
100M
-12
100k
1M
.
Figure 7-5. Small-Signal Frequency Response vs Capacitive
Load
10M
Frequency (Hz)
D005
.
VOUT = 20 mVPP
100M
D004
.
Figure 7-6. Small-Signal Frequency Response vs Output Load
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7.6 Typical Characteristics (continued)
At TA = +25°C, VS = 5.5 V, RL = 10 kΩ, RF= 5 kΩ, CF= 2.5 pF, VCM = midsupply – 0.5 V, G = 6 V/V (unless otherwise noted).
3
1
0.8
0.6
Normalized Gain (dB)
Normalized Gain (dB)
0
-3
-6
VO = 200 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
-9
-12
100k
0
-0.2
-0.4
VO = 200 mVPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
-0.8
1M
10M
.
-1
100k
100M
1M
Frequency (Hz)
D006
.
.
Figure 7-7. Large-Signal Frequency Response vs Output
Voltage
.
10M
D007
.
.
Figure 7-8. Large-Signal Response Flatness vs Frequency
-40
-40
HD2, RL = 10k:
HD3, RL = 10k:
HD2, RL = 2k:
HD3, RL = 2k:
-60
HD2
HD3
-50
Harmonic Distortion (dBc)
-50
Harmonic Distortion (dBc)
0.2
-0.6
Frequency (Hz)
-70
-80
-90
-100
-110
-120
-60
-70
-80
-90
-100
-110
-130
-120
-140
10
100
.
1k
10k
Freuency (Hz)
100k
1
1M
1.5
2
D008
VOUT = 2 VPP
.
.
2.5
3
3.5
Output Voltage (VPP)
4
4.5
5
DPLO
Frequency = 20 kHz
.
Figure 7-10. Harmonic Distortion vs Output Voltage
Figure 7-9. Harmonic Distortion vs Frequency
140
1000
CMRR
PSRR PSRR +
900
800
Output Impedance (:)
120
Rejection Ratio (dB)
0.4
100
80
60
40
700
600
500
400
300
200
20
100
0
1
10
100
.
1k
10k
100k
Frequency (Hz)
1M
10M
0
100
1k
D019
.
.
Figure 7-11. Rejection Ratio vs frequency
12
100M
.
10k
100k
1M
Frequency (Hz)
.
10M
100M
D011
.
Figure 7-12. Open Loop Output Impedance vs Frequency
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7.6 Typical Characteristics (continued)
4
2
3
1.5
Input and Output Voltage (V)
Input and Output Voltage (V)
At TA = +25°C, VS = 5.5 V, RL = 10 kΩ, RF= 5 kΩ, CF= 2.5 pF, VCM = midsupply – 0.5 V, G = 6 V/V (unless otherwise noted).
2
1
0
-1
-2
-3
0.5
0
-0.5
-1
-2
0
500
1000
1500
2000
Time (nsec)
.
2500
3000
0
500
1000
Time (nsec)
D012
.
.
.
1500
2000
D013
TRISE = 1 µsec , TFALL = 0.7 µsec
Figure 7-13. Output Overdrive Recovery
.
Figure 7-14. Large-Signal Transient Response
0.15
80
VIN u 6
VOUT
0.1
VS = 2.2V
VS = 5.5V
70
60
0.05
Phase (q)
Input and Output Voltage (V)
1
-1.5
VOUT
VIN x 6 V/V
-4
0
-0.05
50
40
30
20
-0.1
10
-0.15
0
0
.
500
1000
Time (nsec)
1500
2000
10p
TRISE = TFALL = 40 nsec
.
.
3
90
RISO for 45q Phase Margin (:)
100
2.7
2.4
2.1
1.8
1.5
1.2
VIN
VOUT Gain = 6 V/V
VOUT Gain = 10 V/V
VOUT Gain = 20 V/V
VOUT Gain = 40 V/V
0.6
0.3
80
Gain = 6 V/V
Gain = 10 V/V
Gain = 20 V/V
Gain = 40 V/V
70
60
50
40
30
20
0
10p
Time (100 nsec/div)
100p
.
Figure 7-17. Step Settling Time
1n
CLOAD (F)
D026
Simulated
.
10
0
.
.
D020
Figure 7-16. Phase Margin vs Capacitive Load
3.3
0.9
100p
Capacitive Load (F)
D014
Figure 7-15. Small-Signal Transient Response
Amplitude (V)
VOUT
VIN u 6
.
10n
D025
.
.
Figure 7-18. Recommended Isolation Resistor vs Capacitive
Load
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7.6 Typical Characteristics (continued)
At TA = +25°C, VS = 5.5 V, RL = 10 kΩ, RF= 5 kΩ, CF= 2.5 pF, VCM = midsupply – 0.5 V, G = 6 V/V (unless otherwise noted).
27
6
VS = 5 V, Overshoot
VS = 5 V, Undershoot
VS = 2.2 V, Overshoot
VS = 2.2 V, Undershoot
21
5
4
18
Voltage (V)
Overshoot/Undershoot (%)
24
15
12
9
3
2
1
6
0
3
0
10
VOUT
PD
-1
20
30
.
40
50
60
70
Capacitive Load (pF)
80
90
100
0
VOUT = 200 mVPP
.
10
Time (Psec)
.
Figure 7-19. Overshoot vs Capacitive Load
15
20
D016
.
.
Figure 7-20. Turn-On and Turn-Off Time
0
4000
VS = 5.5V
VS = 2.2V
3500
No. of Units in Each Bin
0.5
PD Pin Bias Current (PA)
5
D015
1
1.5
2
2.5
2500
2000
1500
1000
500
PD Sweep from V S- to VS+
PD Sweep from V S+ to VS-
3
3000
.
.
.
0.7
9000 units
.
Figure 7-22. Input Offset Voltage Distribution
100
12
80
11
10
60
No. of Units in Each Bin
40
20
0
-20
-40
-60
9
8
7
6
5
4
3
2
-80
1
.
32 Units, Normalized to
VOS = 0V at 25°C
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
125
-0.4
100
-0.6
0
25
50
75
Ambient Temperature (qC)
-0.8
-25
-1
0
-100
-50
-1.2
Normalized Input Offset Voltage (PV)
0.6
Input Offset Voltage (mV)
Figure 7-21. Power Down Pin Bias Current vs Power Down Pin
Voltage
D024
D023
Offset Voltage Drift (PV/qC)
.
.
Figure 7-23. Input Offset Voltage vs Temperature
14
0.5
D022
D033
PD Pin Voltage (V)
.
0.4
6
0.3
5.5
0.2
5
0
4.5
0.1
4
-0.1
3.5
-0.2
3
-0.3
2.5
-0.4
2
-0.5
1.5
-0.6
1
-0.7
0
0.5
32 Units, –40°C to
+125°C
.
Figure 7-24. Input Offset Drift Distribution
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7.6 Typical Characteristics (continued)
At TA = +25°C, VS = 5.5 V, RL = 10 kΩ, RF= 5 kΩ, CF= 2.5 pF, VCM = midsupply – 0.5 V, G = 6 V/V (unless otherwise noted).
8
350
300
250
4
200
Offset Voltage (PV)
Offset Voltage (mV)
6
2
2
4
150
100
50
0
-50
-100
-150
6
-200
8
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5
Input Common Mode Voltage (V)
.
-250
2
2.5
3
2
VS = ±2.75 V
.
3.5
4
VS (V)
4.5
5
5.5
6
D029
32 Units
.
Figure 7-26. Input Offset vs Supply
120
100
117
Short Circuit Current Limit (mA)
Common-Mode Rejection Ratio ( dB, typ.)
3
.
Figure 7-25. Input Offset vs Common Mode Voltage
114
111
108
105
102
99
96
93
90
-50
VCM = (VS-) to (VS+ 1.1)
VCM = (VS- + 0.25) to (VS+ 1.1)
VCM = (VS- 0.1) to (VS+ 1.1)
-25
0
.
25
50
Temperature (qC)
75
100
.
60
50
-50
-25
0
25
50
Temperature (°C)
.
75
100
125
D021
.
.
Figure 7-28. Short-Circuit Current vs Temperature
1000
IB+
IBIOS
VS = 2.2 V
VS = 5.5 V
950
900
250
200
150
100
50
850
800
750
700
650
600
0
-50
-50
70
.
Quiescent Current (PA)
300
80
D100
400
350
90
40
-75
125
Figure 7-27. Common Mode Rejection Ratio vs Temperature
IB and IOS (pA)
2.5
D028
550
-25
.
0
25
50
Temperature (qC)
.
75
100
125
500
-50
-25
D030
.
Figure 7-29. Input Bias and Offset Current vs Temperature
.
0
25
50
Temperature (qC)
75
100
.
125
D031
.
Figure 7-30. Quiescent Current vs Temperature
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7.6 Typical Characteristics (continued)
2.75
120
2.25
110
1.75
100
1.25
EMIRR IN + (dB)
Output Voltage (V)
At TA = +25°C, VS = 5.5 V, RL = 10 kΩ, RF= 5 kΩ, CF= 2.5 pF, VCM = midsupply – 0.5 V, G = 6 V/V (unless otherwise noted).
0.75
-40qC
+25qC
+125qC
0.25
-0.25
-0.75
-1.25
90
80
70
60
50
-1.75
40
-2.25
30
-2.75
0
10
20
30
40
Output Current (mA)
.
50
20
1M
60
10M
100M
Frequency (Hz)
D032
.
.
.
Figure 7-31. Output Voltage vs Output Current Sourcing and
Sinking
.
1G
10G
D001
.
Figure 7-32. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
-70
-75
Crosstalk (dBc)
-80
-85
-90
-95
-100
-105
-110
Ch B to Ch A
Ch A to Ch B
-115
-120
100k
.
1M
10M
Frequency (MHz)
.
100M
D001
.
Figure 7-33. Crosstalk vs Frequency
16
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8 Detailed Description
8.1 Overview
The OPAx607 devices are low-noise, rail-to-rail output (RRO) operational amplifiers (op amp). The devices
operate from a supply voltage of 2.2 V to 5.5 V. The input common-mode voltage range also extends
down to the negative rail allowing the OPAx607 to be used in most single-supply applications. Rail-to-rail
output swing significantly increases dynamic range, especially in low-supply, voltage-range applications, which
results in complete usage of the full-scale range of the consecutive analog-to-digital converters (ADCs).
The decompensated architecture allows for a favorable tradeoff of low-quiescent current for a very-high gainbandwidth product (GBW) and low-distortion performance in high-gain applications.
8.2 Functional Block Diagram
V+
7.5M
Reference
SW
PD
PD block
Current
V
IN+
V
INÛ
NMOS input pair
for phase reversal
protection only
V
BIAS1
Class AB
Control
Circuitry
V
O
V
BIAS2
SW
VÛ
(Ground)
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8.3 Feature Description
8.3.1 Operating Voltage
The OPAx607 operational amplifiers are fully specified and assured for operation from 2.2 V to 5.5 V, applicable
from –40°C to +125°C. The OPAx607 devices are completely operational with asymmetric, symmetric and single
supply voltages applied across the supply pins. The total voltage (that is, (VS+) – (VS–)) must be less than the
supply voltage mentioned in Section 7.1.
8.3.2 Rail-to-Rail Output and Driving Capacitive Loads
Designed as a low-power, low-voltage operational amplifier, the OPAx607 devices are capable of delivering a
robust output drive. For resistive loads of 10 kΩ, the output swings to within a few millivolts of either supply rail,
regardless of the applied power-supply voltage. Different load conditions change the ability of the amplifier to
swing close to the rails. The OPAx607 devices drive up to a nominal capacitive load of 47 pF on the output with
no special consideration and without the need of a series isolation resistor RISO while still being able to achieve
45° of phase margin. When driving capacitive loads greater than 47 pF, TI recommends using RISO as shown
in Figure 8-1 in series with the output as close to the device as possible. Refer to Figure 7-18 for looking up
different values of RISO required for CL to achieve 45° phase margin. Without RISO, the external capacitance (CL)
interacts with the output impedance (ZO) of the amplifier, resulting in stability issues. Inserting RISO isolates CL
from ZO and restores the phase margin. Figure 8-1 shows the test circuit.
IOVERLOAD
10mA max
RISO
OPAx607
+
VIN
VOUT
±
Rf
Rg
CL
10 k
Cf
Figure 8-1. Input Current Protection and Driving Capacitive Loads
100
100
90
90
80
80
70
70
Phase Margin (q)
Phase Margin (q)
Figure 8-2 and Figure 8-3 show the phase margin achieved with varying RISO with different values of CL.
60
50
40
10pF
22pF
47pF
0.1nF
1nF
10nF
30
20
10
50
40
10pF
22pF
47pF
0.1nF
1nF
10nF
30
20
10
0
0
0
50
100
Gain = 10 V/V,
150
200
250 300
RISO (:)
Cf = 2.5 pF,
350
400
450
500
0
50
100
D018
RL = 10 kΩ
Figure 8-2. Phase Margin vs. Series Isolation
Resistor
18
60
Gain = 20 V/V,
150
200
250 300
RISO (:)
Cf = 2.5 pF,
350
400
450
500
D017
RL = 10 kΩ
Figure 8-3. Phase Margin vs. Series Isolation
Resistor
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8.3.3 Input and ESD Protection
When the primary design goal is a linear amplifier with high CMRR, do not exceed the op amp input commonmode voltage range (VCM). This CMRR is used to set the common-mode input range specifications in Section
7.5. The typical VCM specifications for the OPAx607 devices are from the negative rail to 1.1 V below the positive
rail. Assuming the op amp is in linear operation, the voltage difference between the input pins is small (ideally
0 V) and the input common-mode voltage can be analyzed at either input pin; the other input pin is assumed to
be at the same potential. The voltage at VIN+ is easy to evaluate. In a noninverting configuration (Figure 8-1) the
input signal, VIN+, must not exceed the VCM rating. However, in an inverting amplifier configuration, VIN+ must be
connected to the voltage within VCM. The input signal applied at VIN- can be any voltage, such that the output
voltage swings with a headroom of 10 mV from either of the supply rails.
The input voltage limits have fixed headroom to the power rails and track the power-supply voltages. For single
5-V supply, the linear input voltage range is 0 V to 3.9 V and with a 2.2-V supply this range is 0 V to 1.1 V. The
headroom to each power-supply rail is the same in either case: 0 V and 1.1 V. A weak NMOS input pair from
VIN+ to VIN+ – 1.1 V ensures that an output phase reversal issue does not occur when the VCM is violated.
VS+
TVS
VDD
OPAx607
PD
IN+
±
OUT
IN-
+
Power-Supply
ESD Cell
VSS
V6¤
Figure 8-4. Internal ESD Structure
The OPAx607 devices also incorporate internal electrostatic discharge (ESD) protection circuits on all pins. For
the input and output pins, this protection primarily consists of current-steering diodes connected between the
input and power-supply pins. These ESD protection diodes provides input overdrive protection, as long as the
current is limited with a series resistor to 10 mA, as stated in Section 7.1. Figure 8-1 shows a series input
resistor can be added to the driven input to limit the input current.
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8.3.4 Decompensated Architecture with Wide Gain-Bandwidth Product
Amplifiers such as the OPAx607 devices are not unity-gain stable are referred to as decompensated amplifiers.
The decompensated architecture typically allows for higher GBW, higher slew rate, and lower noise compared to
a unity-gain stable amplifier with similar quiescent currents. The increased available bandwidth reduces the rise
time and the settling time of the op amp, allowing for sampling at faster rates in an ADC-based signal chain.
As shown in Figure 8-5, the dominant pole fd is moved to the frequency f1 in the case of a decompensated
op amp. The solid AOL plot is the open-loop gain plot of a traditional unity-gain stable op amp. The change
in internal compensation in a decompensated amp such as the OPAx607, increase the bandwidth for the
same amount of power. That is, the decompensated op amp has an increased bandwidth to power ratio when
compared to a unity-gain stable op amp of equivalent architecture. Besides the advantages in the above
mentioned parameters, an increased slew rate and a better distortion (HD2 and HD3) value is achieved because
of the higher available loop-gain, compared to its unity-gain counterpart. The most important factor to consider
is ensuring that the op amp is in a noise gain (NG) greater than Gmin. A value of NG lower than Gmin results in
instability, as shown in Figure 8-5, because the 1/ß curve intersects the AOL curve at 40 dB/decade. This method
of analyzing stability is called the rate of closure method. See the precision lab training videos from TI for a
better understanding on device stability and for different techniques of ensuring stability.
Unity Gain Stable Op Amp
Decompensated Op Amp
AOL
Gmin
´
¶GBP
´
¶d
´
¶1
´
¶u
´
¶2 ´ c
¶u
Figure 8-5. Gain vs Frequency Characteristics for a Unity-Gain Stable Op Amp and a Decompensated Op
Amp
The OPAx607 devices are stable in a noise gain of 6 V/V (15.56 dB) or higher in conventional gain circuits;
see Figure 8-6. The device has 9 MHz of small-signal bandwidth (SSBW) in this gain configuration with
approximately 65° of phase margin. The high GBW and low voltage noise of the OPAx607 devices make them
suitable for general-purpose, high-gain applications.
20
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8.4 Device Functional Modes
The OPAx607 devices have two functional modes: normal operating mode and Power Down ( PD) mode.
8.4.1 Normal Operating Mode
The OPAx607 devices are operational when the power-supply voltage is between 2.2 V (±1.1 V) and 5.5 V
(±2.75 V). Most newer systems use a single power supply to improve efficiency and simplify the power tree
design. The OPAx607 devices can be used with a single-supply power (VS– connected to GND) with no change
in performance from split supply, as long as the input and output pins are biased within the linear operating
region of the device. The valid input and output voltage ranges are given in Section 7.5. The outputs nominally
swing rail-to-rail with approximately 10-mV headroom required for linear operation. The inputs can typically
swing up to the negative rail (typically ground) and to within 1.1 V from the positive supply. Figure 8-6 shows
changing from a ±2.5-V split supply to a 5-V single-supply.
VSIG
VSIG
Bias
Bias
5V
Signal and bias from
previous stage
Signal and bias from
previous stage
OPA607
+
2.5 V
OPA607
+
VOUT
±
VOUT
±
Gain × VSIG
-2.5 V
Gain × Bias
RG
RF
Signal and bias to
next stage
Gain × VSIG
Gain × Bias
RG
RF
Signal and bias to
next stage
Figure 8-6. Single-Supply and Dual-Supply Operation
8.4.2 Power Down Mode
The OPAx607 devices feature a Power Down mode for power critical applications. Under logic control, the
amplifier can be switched from normal operation (consuming ≤ 1 mA) to a Power Down current of less than 1
µA. When the PD pin is connected high, the amplifier is active. Connecting the PD pin to logic low disables the
amplifier and places the output in a high-impedance state. The output of an op amp is high impedance similar
to a tri-state high-impedance gate under a Power Down condition; however, the feedback network behaves as a
parallel load.
If the Power Down mode is not used, connect PD to the positive supply pin or leave floating. See the Power
Down (Device Enabled When Floating) section in Section 7.5 table for the enable and disable threshold
voltages. The PD pin can be left floating to keep the op amp always enabled, which is primarily possible because
of the presence of an internal pullup resistor within the op amp that, by default, always keeps the PD pin weakly
tied to VS+. However it is also acceptable to strengthen the pull up from the PD pin by connecting a low value
resistance from the PD pin to VS+. This helps make the part less susceptible to noise and transient pick up on
the PD pin. Looking at the PD pin bias current in Figure 7-21 can help us get an accurate understanding of the
voltage required to be applied on the PD pin for enabling and powering down. Note: the hysteresis present in
Figure 7-21 help with single shot power up and power down of OPAx607 devices.
The PD pin exhibits a special type of ESD protection which allows users to apply any voltage between VS– to 6 V
irrespective of the voltage at the VS+. Special ESD structure at the PD pin helps in relaxing the requirements on
power sequencing during power up and power down condition. Refer to Figure 8-4 for details of the internal ESD
structure. The absolute voltage limits applicable on PD pin can be found in Section 7.1 table. Another key care
about in PD condition is to ensure the IN+ and IN– are not exposed to a high differential voltage continuously. In
a power up condition the op-amp's loop gain ensure the IN+ pin and the IN– track each other closely. However in
PD condition the op-amp is inactive and IN– will be usually weakly tied to GND through the R G resistor. Exposing
the IN+ pin continuously to a high voltage in such a condition will result in irreversible offset voltage (VOS) shift.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The OPAx607 devices feature a 50-MHz GBW with 900 µA of supply current, providing good AC performance at
low-power consumption. The low input noise voltage of 3.8 nV/√ Hz, the approximate pA of bias current, and a
typical input offset voltage of 0.1 mV make the device very suitable for both AC and DC applications.
9.2 Typical Applications
9.2.1 100-kΩ Gain Transimpedance Design
The high GBW and low input voltage and current noise for the OPAx607 devices make it an excellent wideband
transimpedance amplifier for moderate to high transimpedance gains.
Supply decoupling
not shown
+5 V
OPAx607
+
+0.5 V
VOUT
±
GND
CD
3 pF
RF
100 k
IPD
CCM
5.5 pF
CDIFF
11.5 pF
CF
1.1 pF
VOUT = IPD X RF
OPA607's input differential and
common-mode capacitance
Figure 9-1. Wideband, High-Sensitivity, Transimpedance Amplifier
9.2.1.1 Design Requirements
Design a high-bandwidth, high-transimpedance-gain amplifier with the design requirements shown in Table 9-1.
Table 9-1. Design Requirements
22
TARGET BANDWIDTH (MHz)
TRANSIMPEDANCE-GAIN (kΩ)
PHOTODIODE CAPACITANCE
(pF)
2
100
3
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9.2.1.2 Detailed Design Procedure
Designs that require high bandwidth from a large area detector with relatively high transimpedance-gain benefit
from the low input voltage noise of the OPAx607 devices. Use the Excel™ calculator available at What You Need
To Know About Transimpedance Amplifiers – Part 1 to help with the component selection based on total input
capacitance and CTOT. CTOT is referred as CIN in the calculator. CTOT is the sum of CD, CDIFF, and CCM which is
20 pF. Using this value of CTOT, and the targeted closed-loop bandwidth (f–3dB) of 2 MHz and transimpedance
gain of 100 kΩ results in amplifier GBW of approximately 50 MHz and a feedback capacitance (CF) of 1.1 pF
as shown in Figure 9-2. These results are for a Butterworth response with a Q = 0.707 and a phase margin of
approximately 65° which corresponds to 4.3% overshoot.
Calculator II
Closed-loop TIA Bandwidth (f -3dB)
2.00
MHz
Feedback Resistance (R F)
100.00
kOhm
Input Capacitance (C IN)
20.00
pF
Opamp Gain Bandwidth Product (GBP)
50.27
MHz
Feedback Capacitance (C F)
1.110
pF
Figure 9-2. Results of Inputting Design Parameters in the TIA Calculator
The OPA607's 50 MHz GBW, is suitable for the above design requirements. If the required feedback capacitance
CF comes out to be a very low value capacitor to be practically achievable, a T-Network capacitor circuit as
shown below can be used. A very low capacitor value (CEQ) can be achieved between Port1 and Port2 using
standard value capacitors in a T-Network circuit as shown in Figure 9-3.
CEQ
C1 u C2
C1 C2 CT
(1)
Port1
Port2
C1
C2
CT
GND
Figure 9-3. T-Network
40
100
0
90
-40
80
-80
70
-120
60
-160
50
-200
40
-240
30
-280
20
10
0
10k
VOUT
IPD
5
4
-320
Gain (dB)
Phase (q)
100k
6
3
2
1
PhotoDiode Current (20PA/Div)
80
110
VOUT (V)
120
Phase (qC)
Transimpedance Gain (dB)
9.2.1.3 Application Curves
-360
1M
Frequency (Hz)
10M
-400
100M
0
Time (50 Psec/Div)
OPA6
TIA_
Figure 9-4. Simulated Closed-Loop Bandwidth of
TIA
Figure 9-5. Simulated Time Domain Response
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9.2.2 Noninverting Gain of 3 V/V
The OPAx607 devices are normally stable in noise gain configurations (see SBOA066) of greater than 6 V/V
when conventional feedback networks are used, which is discussed in Section 8.3.4. The OPAx607 devices can
be configured in noise gains of less than 6 V/V by using capacitors in the feedback path and between the inputs
to maintain the desired gain at lower frequencies and increase the gain greater that 6 V/V at higher frequencies
such that the amplifier is stable. Configuration (a) in Figure 9-6 shows OPAx607 devices configured in a gain of 3
V/V by using capacitors and resistors to shape the noise gain and achieve a phase margin of approximately 56°
that is very close to the phase margin achieved for the conventional 6 V/V configuration (b) in Figure 9-6.
The key benefit of using a decompensated amplifier (such as the OPAx607) below the minimum stable gain,
is that it takes advantage of the low noise and low distortion performance at quiescent powers smaller
than comparable unity-gain stable architectures. By reducing the 100-pF input capacitor, higher closed-loop
bandwidth can be achieved at the expense of increased peaking and reduced phase margin. Ensure that low
parasitic capacitance layout techniques on the IN– pin are as small as 1 pF to 2 pF of parasitic capacitance
on the inverting input, which will require tweaking the noise-shaping component values to get a flat frequency
response and the desired phase margin. Configurations in Figure 9-6 does not take into account this parasitic
capacitance but it must be considered for practical purposes. Details on the benefits of decompensated
architectures are discussed in Using a decompensated op amp for improved performance. The one-capacitor,
externally compensated type method is used for noise gain shaping in the below circuit.
In a difference amplifier circuit, typically used for low side current sensing applications, the (noise gain) = (signal
gain + 1).
2.5 pF
2 NŸ
LOAD
+5 V
+5 V
VIN
OPAx607
+
VIN
1NŸ
±
±
OPAx607
+
VO
VO
470
ISH
OPAx607
+
GND
+5 V
RSH
100 pF
±
470
100 pF
1k
0V
0V
2k
2.5 pF
(a) G = 3 V/V
1k
5k
1NŸ
0V
2 NŸ
GND
2.5 pF
(b) G = 6 V/V
2.5 pF
(c) G = 2 V/V
Figure 9-6. Noninverting Gain of 3 V/V, 6 V/V Configurations and Difference Amplifier in Signal Gain of 2
V/V
24
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30
18
24
18
6
12
0
6
Gain (dB)
Gain (dB)
12
-6
-12
-12
-18
-24
0
-6
-18
Gain = 3 V/V with Noise Gain Shaping
Gain = 3 V/V without Noise Gain Shaping
Gain = 6 V/V
-30
100k
1M
10M
Frequency (Hz)
Without Noise Gain Shaping
With Noise Gain Shaping
-24
-30
100k
100M
1M
10M
Frequency (Hz)
Freq
Figure 9-7. Small-Signal Frequency Response in
Gains of 3V/V (a) and 6V/V (b)
100M
OPA6
Figure 9-8. Small-Signal Frequency Response of
Difference Amplifier (c) With and Without Noise
Gain Shaping
9.2.3 High-Input Impedance (Hi-Z), High-Gain Signal Front-End
0.4 nF
9 NŸ
SW
300 Ÿ
40 NŸ
+2.5V
1.8 NŸ
±
0.1 F
2 NŸ
±
OPA607
+
100 NŸ
To ADC/FDA
OPA837
105 Ÿ
Ultrasonic Sensor
+2.5V
0.4 nF
+
-2.5V
-2.5V
Figure 9-9. Hi-Z, High-Gain Front-End Circuit
9.2.3.1 Design Requirements
The objective is to design a high-input impedance, high-dynamic range, signal-conditioning front-end. An
example application for such a front-end circuit is the receive signal chain in an ultrasonic-based end equipment
(EE) such as fish finders, printers and flow meters. Table 9-2 lists the design requirements for this application.
Table 9-2. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Amplifier supply
±2.5 V
Input signal frequency
200 kHz
Minimum voltage
300 µVrms
Minimum SNR at 300 µVrms
40 dB
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9.2.3.2 Detailed Design Procedure
To achieve a SNR of greater than 40 dB for signals from 300 uVrms to 30 mV the front-end stage has two
gain settings: 6 V/V and 31 V/V. The SW (switch, relay, or analog mux) can be dynamically toggled to ensure
maximum sensitively to the receiving signal. The OPAx607 devices prove to be an attractive solution for this
front-end signal chain because of the right balance of low noise and high input impedance. The ultrasonic
sensors (Ex. piezo crystal) have high output impedance. The OPAx607 devices have an input bias current of 20
pA (maximum). This small bias current results in reduced distortion and signal loss across the source impedance
when compared with a bipolar amplifier with input bias currents in the range of a few hundreds of nano-amperes.
The OPAx607's high-gain front-end is followed by a narrowband band-pass filter that is tuned to a 200-kHz
center frequency. The narrowband filter is designed using the OPA837. OPA837 can be used as a variable
gain mux / PGA as shown in TIDA-01565. In this application section the OPA837-based band-pass filter was
designed using the techniques mentioned in the Filter Design in Thirty Seconds application report.
Figure 9-11 shows the frequency response of circuit in Figure 9-9. As shown in Figure 9-11, the frequency
response is a high-Q factor band-pass filter centered around 200 kHz. Designing such a high-Q band-pass filter
helps eliminate white band noise along with other interferences present in the circuitry, resulting in a high SNR
signal chain. The OPAx607's front-end combined with the OPA837-based band-pass filter help to achieve a total
gain of 33 dB (44 V/V) or 50 dB (316 V/V) based on the SW (switch) position.
9.2.3.3 Application Curves
100
90
80
60
50 dB Gain
33 dB Gain
50
40
70
30
Gain (dB)
60
SNR (dB)
Gain setting = 33 dB
Gain setting = 50 dB
50
40
20
10
0
-10
-20
30
-30
-40
20
100P
1m
10m
Input RMS voltage (V)
100m
-50
100
1k
D001
10k
100k
Frequency (Hz)
1M
10M
D005
Figure 9-10. Hi-Z, High-Gain Front-End Circuit SNR Figure 9-11. Hi-Z, High-Gain Front-End Circuit Gain
vs Input
vs Frequency
26
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9.2.4 Low-Cost, Low Side, High-Speed Current Sensing
VREF =1.24V
LOAD
ISH
20 NŸ
CF
3.3V
+
1NŸ
5PŸ
RSH
3.3V
VOUT
688 Ÿ
VADC
OPA607
ADS7042
±
1NŸ
GND
240 pF
GND
20 NŸ
GND
GND
CF
Figure 9-12. Low Side Current Sensing
9.2.4.1 Design Requirements
The objective is to design a high-speed, high-gain bidirectional current-sensing circuit for power systems and
motor drive systems. Section 9.2.4.2 lists the design requirements of this application.
Table 9-3. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Amplifier and ADC supply
3.3 V
Peak current to be measured from load to ground
20 A
Peak current to be measured from ground to load
12 A
Required Accuracy of current measurement
0.1%
Signal-Setting time at ADC input
< 1 µs
Current sensing direction
Bidirectional
9.2.4.2 Detailed Design Procedure
The aim of this application section is to measure bidirectional current with relatively high accuracy in a low-sidesensing-based, high-frequency switching system.
As shown in Figure 9-12, a single op amp of high bandwidth is capable of sensing current in a high gain
configuration as well as have the required effective bandwidth to drive the consecutive SAR ADC input. The SAR
ADC can be a standalone ADC or integrated inside a Micro-controller.
VOUT = (20 kΩ / 1 kΩ × VDIFF) + VREF, where VDIFF = ISH X RSH
(2)
The reference voltage is 1.24 V. When the ISH flowing across RSH equals zero, the VOUT of the difference
amplifier sits ideal at 1.24 V.
When the current (ISH) flows from LOAD to GND, the output of the OPAx607 increase above 1.24 V with a value
equal to 20 × VSH and when the current flows from GND to LOAD (in the opposite direction) the output of the
OPAx607 decrease below 1.24 V with a value proportional to 20 × VSH.
One of the main challenges in a high speed current sensing design is to choose an op amp of with sufficient
GBW that can drive a SAR ADC, while still being able to gain the signal by the required amount. The 0.1% and
0.01% settling of OPAx607 can found in Section 7.5. Another key care about is to ensure the op amp output
rises in less than 1 µs so as to feed the output to a comparator for short-circuit protection. This comparator
based short circuit protection loop is extremely fast and enables to turn off the switching devices very quickly.
This requirement makes a low cost high speed part like the OPAx607 very desirable in a current-sensing circuit.
Equation of the rise time as a function of bandwidth is shown below.
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tR (10% to 90%) = 0.35 Hz / BW
(3)
For an ADC like ADS7042 running at a sampling rate of 500 kSPS of a clock of 12.5 MHz, the effective
bandwidth of the op amp required to drive such an ADC is approximately 2.7 MHz. See the TI precision lab
videos on driving SAR ADCs to understand the underlying calculation. The OPAx607 has a GBW of 50 MHz.
With a gain of 20 V/V, the closed loop bandwidth turns out to approximately 2.5 MHz, making this device the
most suitable, cost-optimized amplifier for this application. The RC charge bucket (240 Ω and 688 pF in Figure
9-12) designed at the input of the SAR ADC is derived from the calculations provided in the SAR ADC precision
lab videos. The fundamental concept behind the design of this charge bucket filter is to ensure that the sample
and hold capacitor is charged to the required final voltage within the acquisition window of the ADC.
As shown in Figure 9-14, a DC accuracy of higher than 0.05% is achieved with the OPAx607. The simulations
are captured with and without voltage offset calibration. Frequency response shown in Figure 9-13 indicate
different signal bandwidth at VOUT, VADC and with and without CF of 220 pF.
30
6
24
5.2
0.16
18
4.4
0.12
12
3.6
0.08
2.8
0.04
6
0
-6
-24
-30
100
0
1.2
-0.04
VADC
VOUT
VOUT , CF = 220 pF
1k
10k
100k
1M
Frequency (Hz)
-1.2
10M
100M
D010
-2
-20
-0.08
Measured Output
Ideal Output
% Error w/o callibration
% Error with callibration
-0.4
Figure 9-13. Frequency Response of Low Side
Current Sensing
28
2
0.4
-12
-18
0.2
-15
-10
-5
0
5
10
15
Current across RSH (A)
% Error
Voltage (V)
Gain (dB)
9.2.4.3 Application Curves
-0.12
-0.16
20
25
-0.2
30
D003
Figure 9-14. DC Current-Sense Transfer Function
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9.2.5 Ultrasonic Flow Meters
OPA607
OPA607
Figure 9-15. High-Gain Ultrasonic Front-End
9.2.5.1 Design Requirements
The OPAx607 devices have a wide operating voltage range of 2.2 V to 5.5 V with a maximum quiescent current
of 1 mA. The availability of the inbuilt shutdown function enables designers to power cycle the front-end signal
chain, reducing the net quiescent current even further. The minimum operating voltage range of 2.2 V proves to
be very suitable for battery-powered and power sensitive applications such as the ultrasonic-based flow meters.
The high GBW of the OPAx607 devices enable the gain stages and the ADC drive stages to be designed
and combined, thereby reducing component count. A schematic similar to that of Figure 9-12 can be used in
ultrasonic flow meters for the front-end signal chain.
The Ultrasonic sensing subsystem reference design for gas flow measurement design guide has a detailed
design procedure for ultrasonic-based sensing for gas flow measurement. The OPAx607 devices are very
suitable op amps for the discrete front-end design described in this design guide.
10 Power Supply Recommendations
The OPAx607 devices are specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V), applicable from –40°C
to +125°C. Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from
noisy or high-impedance power supplies.
CAUTION
Supply voltages larger than 6 V can permanently damage the device (see Section 7.1).
For more detailed information on bypass capacitor placement, see Section 11.1.
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
•
•
•
•
•
Noise can propagate into analog circuitry through the power-supply pins of the circuit as a whole and of the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-equivalent series resistance (ESR), 0.1-µF ceramic bypass capacitors between each supply
pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is
applicable for single-supply applications.
Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make
sure to physically separate digital and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.
If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better than
crossing in parallel with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance; see Figure 11-1 and Figure 11-2.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Examples
GND
V-
C3
U1
OPAx607 OUTPUT
V+
INPUT
INPUT
GND
1 +
3
OUTPUT
V-
±
2
R3
4
6
5 C4
C2
V+
R1
GND
R2
C1
Figure 11-1. Operational Amplifier Board Layout
for a Noninverting Configuration
30
Figure 11-2. Layout Example Schematic
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
Texas Instruments, precision lab videos
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPA2834 50-MHz, 170-μA, Negative-Rail In, Rail-to-Rail Out, Voltage-Feedback Amplifier
data sheet
• Texas Instruments, ADS7042 Ultra-Low Power, Ultra-Small Size, 12-Bit, 1-MSPS, SAR ADC data sheet
• Texas Instruments, Ultrasonic Sensing Subsystem Reference Design For Gas Flow Measurement design
guide
• Texas Instruments, OPAx836 Very-Low-Power, Rail-to-Rail Out, Negative Rail In, Voltage-Feedback
Operational Amplifiers data sheet
• Texas Instruments, Filter Design in Thirty Seconds application report
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.6 Trademarks
Excel™ is a trademark of Microsoft Coproration.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2607IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2FRT
OPA2607IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OP2607
OPA2607SIRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
KJF
OPA607IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O6BV
OPA607IDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
O6BV
OPA607IDCKR
ACTIVE
SC70
DCK
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1G4
OPA607IDCKT
ACTIVE
SC70
DCK
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1G4
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
