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OPA2626
SBOS690A – JULY 2016 – REVISED DECEMBER 2019
OPA2626 High-Speed, High-Precision, Low-Distortion, 16-Bit and 18-Bit
Analog-to-Digital Converter (ADC) Driver
1 Features
3 Description
•
The OPA2626 operational amplifier is a 16-bit and
18-bit,
high-precision,
successive-approximation
register (SAR) analog-to-digital converter (ADC)
driver with low total harmonic distortion (THD) and
noise. This op amp is fully characterized and
specified with a 16-bit settling time of 280 ns that
enables a true 16-bit effective number of bits (ENOB).
With a high DC precision of only 100-µV offset
voltage, a wide gain-bandwidth product of 120 MHz,
and a low wideband noise of 2.5 nV/√Hz, this device
is optimized for driving high-throughput, highresolution SAR ADCs in applications such as the
ADS88xx family of SAR ADCs.
1
•
•
•
•
Excellent dynamic performance:
– Low distortion: –122 dBc for HD2 and
–140 dBc for HD3 at 100 kHz
– Gain bandwidth (G = 100): 120 MHz
– Slew rate: 115 V/µs
– 16-bit settling at 4-V step: 280 ns
– Low voltage noise: 2.5 nV/√Hz at 10 kHz
– Low output impedance: 1 Ω at 1 MHz
Excellent DC precision:
– Offset voltage: ±100 µV (maximum)
– Offset voltage drift: ±3 µV/ºC (maximum)
– Low quiescent current: 2 mA (typical)
Input common-mode range includes negative rail
Rail-to-rail output
Wide temperature range: fully specified from
–40°C to +125°C
2 Applications
•
•
•
•
•
•
•
The OPA2626 is available in an 8-pin VSSOP
package and is specified for operation from –40°C to
+125°C.
Device Information(1)
PART NUMBER
OPA2626
PACKAGE
VSSOP (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Precision SAR ADC drivers
Precision voltage reference buffers
Programmable logic controllers
Test and measurement equipment
Scientific instrumentation
High throughput data acquisition systems
High density, multiplexed data acquisition systems
spacer
SAR ADC Driver
1k
High Fidelity Topology
Improves Dynamic Performance
(fIN = 10-kHz, 1-MSPS FFT)
1k
0
5V
RFLT
4.7
VREF / 4
+
VREF
THD = -110.8 dBc
SNR = 91.88 dB
SINAD = 91.86 dB
ENOB = 14.97
-25
3.3 V
-50
OPA626
CFLT
RFLT
4.7
10 nF
REF
AVDD
ADS8860
GND
Amplitude (dB)
Input
Voltage
-75
-115.91 dBc (Third Harmonic)
-100
-125
-150
-175
0
50
100
150
200 250 300 350
Frequency (kHz)
400
450
500
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2626
SBOS690A – JULY 2016 – REVISED DECEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
7
9
Parameter Measurement Information ................ 18
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: High-Supply ....................
Electrical Characteristics: Low-Supply......................
Typical Characteristics ..............................................
DC Parameter Measurements ................................
Transient Parameter Measurements ......................
AC Parameter Measurements ................................
Noise Parameter Measurements ............................
18
19
19
20
Detailed Description ............................................ 21
8.1 Overview ................................................................. 21
8.2 Functional Block Diagram ....................................... 21
8.3 Feature Description................................................. 22
8.4 Device Functional Modes........................................ 23
9
Application and Implementation ........................ 23
9.1 Application Information............................................ 23
9.2 Typical Applications ................................................ 23
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 29
12 Device and Documentation Support ................. 30
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
Changes from Original (July 2016) to Revision A
Page
•
Deleted OPA626 (5-pin SOT DBV package) from document ............................................................................................... 1
•
Added 18-bit SAR ADC to amplifier description in Overview section ................................................................................. 21
•
Added 18-bit level to device description in Application Information section ........................................................................ 23
•
Added (pins 3 and 4) to input terminals in Design Requirements section of first typical application for clarity .................. 24
•
Changed description of slew and settle time in Design Requirements section of second typical application for clarity ..... 26
2
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SBOS690A – JULY 2016 – REVISED DECEMBER 2019
5 Pin Configuration and Functions
OPA2626 DGK Package
8-Pin VSSOP
Top View
OUT A 1
8 V+
7 OUT B
+
+IN A 3
-
+
±IN A 2
V± 4
6 ±IN B
5 +IN B
Pin Functions: OPA2626
PIN
NAME
NO.
I/O
DESCRIPTION
+IN A
3
I
Noninverting input for channel A
–IN A
2
I
Inverting input for channel A
+IN B
5
I
Noninverting input for channel B
–IN B
6
I
Inverting input for channel B
OUT A
1
O
Output terminal for channel A
OUT B
7
O
Output terminal for channel B
V+
8
—
Positive supply voltage
V–
4
—
Negative supply voltage
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OPA2626
SBOS690A – JULY 2016 – REVISED DECEMBER 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, VS
Input voltage (2)
Output voltage
(V+) – (V–)
Source current
Temperature
(1)
(2)
UNIT
6
V
+IN
(V–) – 0.3
(V+) + 0.3
–IN
(V–) – 0.3
(V+) + 0.3
OUT
(V–)
(V+)
+IN
Sink current
MAX
V
V
10
–IN
10
OUT
150
+IN
10
–IN
10
OUT
150
Operating junction
–40
150
Operating free-air, TA
–55
150
Storage, Tstg
–65
150
mA
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For input voltages beyond the power-supply rails, voltage or current must be limited.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Supply input voltage, (V+) – (V–)
NOM
MAX
2.7
5.5
+IN
(V–)
(V+) – 1.15
–IN
(V–)
(V+) – 1.15
UNIT
V
VI
Input voltage
VO
Output voltage
(V–)
(V+)
V
IO
Output current
–120
120
mA
TA
Operating free-air temperature
–40
125
°C
TJ
Operating junction temperature
–40
125
°C
4
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V
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SBOS690A – JULY 2016 – REVISED DECEMBER 2019
6.4 Thermal Information
OPA2626
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
171.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
68.4
°C/W
RθJB
Junction-to-board thermal resistance
91.9
°C/W
ψJT
Junction-to-top characterization parameter
9.4
°C/W
ψJB
Junction-to-board characterization parameter
90.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
6.5 Electrical Characteristics: High-Supply
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
Unity gain frequency
φm
Phase margin
GBW
Gain-bandwidth product
SR
Slew rate
VO = 10 mVPP
G = 100, VO = 10 mVPP
HD2
HD3
Settling time
120
MHz
VO = 4-V step, G = 2
115
VO = 4-V step, G = 2
VO = 4-V step, G = 2
Undershoot
VO = 4-V step, G = 2
Third-order harmonic
distortion
Degrees
45
Overshoot
Second-order harmonic
distortion
MHz
50
VO = 1-V step, G = 1
Settling time to 0.1%
(10-bit accuracy)
tsettle
80
V/µs
80
to 0.005%
(14-bit accuracy)
110
to 0.00153%
(16-bit accuracy)
280
ns
2.5%
3%
VO = 2 VPP, G = 2
VO = 2 VPP, G = 2
f = 10 kHz
144
f = 100 kHz
122
f = 1 MHz
80
f = 10 kHz
155
f = 100 kHz
140
f = 1 MHz
dBc
dBc
80
Second-order
VO = 2 VPP, f = 1 MHz, 200-kHz tone spacing
intermodulation distortion
90
dBc
Third-order
VO = 2 VPP, f = 1 MHz, 200-kHz tone spacing
intermodulation distortion
100
dBc
f = 0.1 Hz to 10 Hz, peak-to-peak
0.8
µVPP
f = 0.1 Hz to 10 Hz, rms
120
nVRMS
Input voltage noise
density
f = 1 kHz
3.2
f = 10 kHz
2.5
In
Input current noise
density
f = 1 kHz
6.6
f = 10 kHz
3.5
tOR
Overload recovery time
G=5
50
ns
Zo
Open-loop output
impedance
f = 1 MHz
1
Ω
VN
Input noise voltage
Vn
Crosstalk
At DC
150
f = 1 MHz
127
nV/√Hz
pA/√Hz
dB
DC PERFORMANCE
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Electrical Characteristics: High-Supply (continued)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
TA = –40°C to 125°C
PSRR
Power-supply rejection
ratio
2.7 V ≤ (V+) ≤ 5 V
IB
Input bias current
MIN
TYP
MAX
15
±100
TA = –40°C to 125°C
±300
0.5
±3
0.6
±4
100
TA = –40°C to 125°C
90
Input bias current drift
Input offset current
dIOS/dT
Input offset current drift
µV/°C
4
5.7
TA = –40°C to 125°C
µA
6.5
TA = –40°C to 125°C
15
nA/°C
20
IOS
µV
dB
120
2
dIB/dT
UNIT
120
150
TA = –40°C to 125°C
nA
350
TA = –40°C to 125°C
0.6
nA/°C
dB
OPEN LOOP GAIN
AOL
(V–) + 0.2 V < VO < (V+) – 0.2 V, RLOAD = 600 Ω
110
(V–) + 0.15 V < VO < (V+) – 0.15 V, RLOAD = 10 kΩ
114
Open-loop gain
TA = –40°C to 125°C
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
106
128
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
110
132
INPUT VOLTAGE
VCM
Common-mode voltage
range
TA = –40°C to 125°C
CMRR
Common-mode rejection
ratio
(V–) < VCOM < (V+) – 1.15 V
(V+) –
1.15
(V–)
TA = –40°C to 125°C
100
117
90
115
V
dB
INPUT IMPEDANCE
ZID
Differential input
impedance
27 || 1.2
KΩ || pF
ZIC
Common-mode input
impedance
47 || 1.5
MΩ || pF
OUTPUT
RLOAD = 600 Ω
Output voltage swing to
the rail
RLOAD = 10 kΩ
Isc
Short-circuit current
CLOAD
Capacitive load drive
60
TA = –40°C to 125°C
80
100
20
TA = –40°C to 125°C
35
mV
40
130
mA
See Typical Characteristics
POWER SUPPLY
IQ
6
Quiescent current per
amplifier
IO = 0 mA
2
TA = –40°C to 125°C
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2.2
3.1
mA
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SBOS690A – JULY 2016 – REVISED DECEMBER 2019
6.6 Electrical Characteristics: Low-Supply
at TA = 25°C, V+ = 2.7 V, V– = 0 V, VCOM = VO = 1.35 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF, and RLOAD =
1 kΩ connected to 1.35 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
Unity gain frequency
VO = 10 mVPP
φm
Phase margin
GBW
Gain-bandwidth product
G = 100, VO = 10 mVPP
SR
Slew rate
VO = 1-V step, G = 2
tsettle
HD2
HD3
Settling time
VO = 1-V step, G = 2
Overshoot
VO = 1-V step, G = 2
Undershoot
VO = 1-V step, G = 2
Second-order harmonic
distortion
Third-order harmonic
distortion
76
MHz
50
Degrees
110
MHz
45
V/µs
to 0.1%
80
to 0.01%
170
to 0.000763% (17-bit accuracy)
250
ns
6%
5%
(V+) = 3.3 V, (V–) = 0 V,
VCOM = 1.1 V,
VO = 2 VPP
(V+) = 3.3 V, (V–) = 0 V,
VCOM = 1.1 V,
VO = 2 VPP
f = 10 kHz
136
f = 100 kHz
118
f = 1 MHz
80
f = 10 kHz
143
f = 10 kHz
143
f = 100 kHz
130
f = 100 kHz
125
f = 1 MHz
85
f = 1 MHz
74
dBc
dBc
(V+) = 3.3 V, (V–) = 0 V, VCOM = 1.1 V, VO = 2 VPP,
Second-order
intermodulation distortion f = 1 MHz, 200-kHz tone spacing
95
dBc
(V+) = 3.3 V, (V–) = 0 V, VCOM = 1.1V, VO = 1 VPP,
Third-order
intermodulation distortion f = 1 MHz, 200-kHz tone spacing
104
dBc
f = 0.1 Hz to 10 Hz, peak-to-peak
0.8
µVPP
f = 0.1 Hz to 10 Hz, rms
120
nVRMS
Input voltage noise
density
f = 10 kHz
2.5
nV/√Hz
In
Input current noise
density
f = 10 kHz
3.5
pA/√Hz
tOR
Overload recovery time
G=5
35
ns
Zo
Open-loop output
impedance
f = 1 MHz
1.3
Ω
At DC
150
f = 1 MHz
127
VN
Input noise voltage
Vn
Crosstalk
dB
DC PERFORMANCE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
IB
Input bias current
15
TA = –40°C to 125°C
±300
TA = –40°C to 125°C
0.5
±3.1
0.6
±4
2
dIB/dT
Input bias current drift
TA = –40°C to 125°C
dIOS/dT
Input offset current
Input offset current drift
µV
µV/°C
4
5.7
µA
6.5
TA = –40°C to 125°C
15
20
IOS
±100
nA/°C
120
150
TA = –40°C to 125°C
nA
200
TA = –40°C to 125°C
80
pA/°C
OPEN-LOOP GAIN
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Electrical Characteristics: Low-Supply (continued)
at TA = 25°C, V+ = 2.7 V, V– = 0 V, VCOM = VO = 1.35 V, gain (G) = 1, RF = 1 kΩ, CF = 2.7 pF, CLOAD = 20 pF, and RLOAD =
1 kΩ connected to 1.35 V (unless otherwise noted)
PARAMETER
AOL
Open-loop gain
TEST CONDITIONS
MIN
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
110
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
114
TA = –40°C to 125°C
TYP
MAX
UNIT
dB
(V–) + 0.2 V < VO < (V+) – 0.2 V,
RLOAD = 600 Ω
100
128
(V–) + 0.15 V < VO < (V+) – 0.15 V,
RLOAD = 10 kΩ
104
132
INPUT VOLTAGE
VCM
Common-mode voltage
range
TA = –40°C to 125°C
CMRR
Common-mode rejection
ratio
(V–) < VCOM < (V+) – 1.15 V
(V+) –
1.15
(V–)
TA = –40°C to 125°C
100
117
90
115
V
dB
INPUT IMPEDANCE
ZID
Differential input
impedance
27 || 0.8
KΩ || pF
ZIC
Common-mode input
impedance
47 || 1.2
MΩ || pF
OUTPUT
R LOAD = 600 Ω
Output voltage swing to
the rail
R LOAD = 10 kΩ
ISC
Short-circuit current
CLOAD
Capacitive load drive
60
TA = –40°C to 125°C
80
100
20
TA = –40°C to 125°C
35
mV
40
80
mA
See Typical Characteristics
POWER SUPPLY
IQ
8
Quiescent current per
amplifier
IO = 0 mA
2
TA = –40°C to 125°C
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2.1
2.8
mA
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6.7 Typical Characteristics
25
25
20
20
15
15
10
10
5
5
Gain (dB)
Gain (dB)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
0
Gain = 1
±5
Gain = -1
±10
Gain = 2
±15
Gain = 1
±10
Gain = -1
Gain = 2
±15
Gain = 5
±20
0
±5
Gain = 5
±20
Gain = 10
±25
Gain = 10
±25
10k
100k
1M
10M
Frequency (Hz)
10k
100M
100k
VO = 10 mVPP
100M
C005
Figure 2. Large-Signal Frequency Response for Various
Gains
2.5
10
5.5 V
8
2.7 V
6
2.0
1.5
4
Gain (dB)
Gain (dB)
10M
VO = 2 VPP
Figure 1. Small-Signal Frequency Response for Various
Gains
1.0
0.5
0.0
2
0
±2
0 pF
±4
8.2 pF
22 pF
±6
-0.5
33 pF
±8
-1.0
100k
47 pF
±10
1M
10M
100M
Frequency (Hz)
1M
10M
100M
Frequency (Hz)
C006
VO = 10 mVPP, G = 1
1G
C007
VO = 10 mVPP , G = 1
Figure 3. Small-Signal Frequency Response for Various
Power Supply Voltages
Figure 4. Small-Signal Frequency Response for Various
Capacitive Loads
2.5
2
1
2k
2.0
0
±1
1k
1.5
Gain (dB)
Gain (dB)
1M
Frequency (Hz)
C004
±2
±3
±4
0 pF
±5
8.2 pF
1.0
0.5
22 pF
±6
0.0
33 pF
±7
47 pF
-0.5
±8
10k
100k
1M
Frequency (Hz)
10M
100M
1M
C007
VO = 2 VPP, G = 1
10M
100M
Frequency (Hz)
C007
VO = 10 mVPP , G = 1
Figure 5. Large-Signal Frequency Response for Various
Capacitive Loads
Figure 6. Small-Signal Frequency Response for Various
Resistive Loads
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Typical Characteristics (continued)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
180
80
135
40
90
0
45
Gain
1000
100
Impedance (:)
120
Gain (dB)
225
Phase (ƒ)
160
10
Phase
-40
±40
0.01
0.01 0.10
0.1
11
10
10 100
100
1k
1k
0
0
10k
10k 100k 1000k
1M 10000k
10M 100000k
100M
Frequency (Hz)
1
10
100
1k
10k
100k
Frequency (Hz)
C024
1M
10M
100M
VO = 10 mVPP
Figure 8. Open-Loop Output Impedance vs Frequency
Figure 7. Open-Loop Gain and Phase vs Frequency
140
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (db)
140
120
100
80
60
40
20
0
10
120
100
80
60
40
PSRR+
20
PSRR-
0
100
1k
10k
100k
Frequency (Hz)
1M
10M
1
100M
Riso = 0
Riso = 25
50
Overshoot (%)
0
Gain (dB)
10k
100k
1M
10M
100M
C025
60
55
±5
Riso = 0
45
Riso = 25
V
Riso = 10
V
V
V
V
Riso = 50
V
Riso = 10
2.7 V
Riso = 50
V
40
35
30
Riso = 10
25
Riso = 25
20
Riso = 50
15
10
1M
10M
Frequency (Hz)
100M
10
100
1000
10000
Load Capacitance (pF)
C024
G = 1, CLOAD = 1.2 nF
C027
G = 1, VO = 10 mVPP
Figure 11. Series Resistance for Capacitive Load Stability
10
1k
Figure 10. Power-Supply Rejection Ratio vs Frequency
5
±15
100k
100
Frequency (Hz)
Figure 9. Common-Mode Rejection Ratio vs Frequency
±10
10
Figure 12. Overshoot vs Capacitive Load, G = 1
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Typical Characteristics (continued)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
0
50
45
Riso = 25
40
Overshoot (%)
V
Riso = 0
35
V
Riso = 25
30
V
V
Riso = 10
V
Riso = 50
5.5 V
Riso = 10
V
Riso = 50
V
HD2, Gain = 1
±20
HD3, Gain = 1
±40
Distortion (dBc)
Riso = 0
25
20
15
HD3, Gain = 2
±80
±100
±120
10
±140
5
±160
0
HD2, Gain = 2
±60
±180
10
100
1000
Load Capacitance (pF)
1k
10000
1M
C010
VS = 5.5 V, VO = 2 VPP, RLOAD = 600 Ω
Figure 13. Overshoot vs Capacitive Load, G = –1
Figure 14. Distortion vs Frequency for Various Gains
0
0
HD2, Vs = 5.5 V
±20
HD3, Vs = 5.5 V
±40
HD2, Vs = 3.3 V
±60
HD3, Vs = 3.3 V
Distortion (dBc)
Distortion (dBc)
100k
Input Frequency (Hz)
G = –1, VO = 10 mVPP
±80
±100
±120
±20
HD2, Vs = 5.5 V
±40
HD3, Vs = 5.5 V
HD2, Vs = 3.3 V
±60
HD3, Vs = 3.3 V
±80
±100
±120
±140
±140
±160
±180
±160
1k
10k
100k
Input Frequency (Hz)
1k
1M
10k
100k
Input Frequency (Hz)
C010
G = 1, VO = 2 VPP, RLOAD = 600 Ω
1M
C010
G = 2, VO = 2 VPP, RLOAD = 600 Ω
Figure 15. Distortion vs Frequency for Various Power
Supplies
Figure 16. Distortion vs Frequency for Various Power
Supplies
0
0
f = 1 kHz
2k
±20
f = 10 kHz
±40
f = 100 kHz
Total Harmonic Distortion (dB)
Total Harmonic Distortion (dB)
10k
C027
f = 1 MHz
±60
±80
±100
±120
±140
±20
1k
±40
±60
±80
±100
±120
±140
±160
±160
1
2
3
Output Voltage (VPP)
4
1k
10k
100k
Input Frequency (Hz)
C013
G = 1, RLOAD = 600 Ω
1M
C010
G = 1, VO = 2 VPP , RLOAD = 600 Ω
Figure 17. Total Harmonic Distortion vs Output Voltage for
Various Frequencies
Figure 18. Total Harmonic Distortion vs Frequency for
Various Loads
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Typical Characteristics (continued)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
1000
Current Noise Density (pA/rtHz)
Voltage Noise Density (nV/rtHz)
1000
100
10
100
10
1
1
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
C015
Figure 19. Voltage Noise Density vs Frequency
C015
Figure 20. Current Noise Density vs Frequency
-80
Voltage Noise (200 nV/div)
Crosstalk (db)
-100
-120
-140
-160
-180
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
Time (1 s/div)
C020
Figure 22. 0.1-Hz to 10-Hz Voltage Noise
Figure 21. Crosstalk vs Frequency
6
180
Maximum Output Voltage (VPP)
Falling, Gain = 1
Slew Rate (V/ s)
140
Rising, Gain = 2
120
Falling, Gain = 2
100
80
60
40
20
0
0
1
2
3
4
Output Voltage Step (V)
5
4
3
2
1
0
1k
C018
Figure 23. Slew Rate vs Output Step Size
12
VS = 5 V
VS = 3.3 V
Rising, Gain = 1
160
10k
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 24. Maximum Output Voltage vs Frequency
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Typical Characteristics (continued)
Output Voltage (1 V/div)
Output Voltage (1 V/div)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
Time (200 ns/div)
Time (200 ns/div)
C020
C019
G = 1, VO = 4-V step
G = –1, VO = 4-V step
Output Voltage (2 mV/div)
Figure 26. Large-Signal Pulse Response
Output Voltage (2 mV/div)
Figure 25. Large-Signal Pulse Response
Time (200 ns/div)
Time (200 ns/div)
C029
C029
G = 1, VO = 10-mV step
G = –1, VO = 10-mV step
Figure 27. Small-Signal Pulse Response
Figure 28. Small-Signal Pulse Response
200
150
Output Delta from Final Value (µV)
Output Delta from Final Value (µV)
200
16-bit settling
100
50
0
±50
±100
16-bit settling
±150
±200
150
16-bit settling
100
50
0
±50
±100
16-bit settling
±150
±200
0
200
400
600
800
Time (ns)
1000
0
C032
VO = 3.6-V step at t = 0 s
200
400
600
800
Time (ns)
1000
C032
VO = 3.6-V step at t = 0 s
Figure 29. 16-Bit Negative Settling Time
Figure 30. 16-Bit Positive Settling Time
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Typical Characteristics (continued)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
4
0.8
4
0.6
3
0.4
2
0.2
1
3
Input Voltage (V)
1
0
±1
±2
Input
0.0
Input
Output
±3
±4
Output Voltage (V)
Voltage (1 V/div)
2
0
Output
-0.2
Time (200 µs/div)
-1
Time (100 ns/div)
C021
C031
VS = ±2.75 V, G = 1
VS = ±2.75 V, G = 5
Figure 31. No Phase Reversal
Figure 32. Positive Overload Recovery
20
1
0.2
Input
C021
100
75
50
0
-4
Time (100 ns/div)
-100
-0.8
5
25
-3
0
-0.6
-25
-2
10
-50
-0.4
Amplifiers (%)
-1
-0.2
15
Output Voltage (V)
Input Voltage (V)
0
-75
Output
0.0
Offset Voltage (µV)
VS = ±2.75 V, G = 5
C013
Distribution taken from 3139 amplifiers, TA = 25°C
Figure 34. Input Offset Voltage Distribution
20
15
15
Offset Voltage (µV)
300
250
200
150
50
100
0
-50
-100
Offset Voltage (µV)
C013
Figure 35. Input Offset Voltage Distribution
-150
-300
300
250
200
150
50
100
0
-50
-100
0
-150
0
-200
5
-250
5
Distribution taken from 80 amplifiers, TA = 125°C
14
10
-200
10
-250
Amplifiers (%)
20
-300
Amplifiers (%)
Figure 33. Negative Overload Recovery
C013
Distribution taken from 80 amplifiers, TA = –40°C
Figure 36. Input Offset Voltage Distribution
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Typical Characteristics (continued)
30
35
25
30
25
Amplifiers (%)
20
15
10
20
15
5
4
3
2
0
3
2
2.5
1.5
1
0.5
0
-1
-0.5
-1.5
0
-2
0
-2.5
5
1
10
5
-3
Amplifiers (%)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
Input Bias Current (µA)
Offset Voltage Drift (µV/ƒC)
C013
C013
Distribution taken from 75 amplifiers, TA = –40°C to +125°C
Distribution taken from 3139 amplifiers
Figure 37. Input Offset Voltage Drift Distribution
Figure 38. Input Bias Current Distribution
5
30
25
4
Amplifiers (%)
3
2
1
20
15
10
5
0
75
100
125
Temperature (ƒC)
150
C001
300
50
200
25
100
0
0
±25
-100
±50
-300
0
±75
-200
Input Bias Current (µA)
IB IB+
Input Offset Current (nA)
C013
Distribution taken from 3139 amplifiers
Figure 40. Input Offset Current Distribution
Figure 39. Input Bias Current vs Temperature
Common-Mode Rejection Ratio (µV/V)
Input Offset Current (nA)
1000
100
10
1
30
20
VS = ±2.75 V, (V±) ” 9CM ” 9
10
± 1.15
0
VS = ±1.35 V, (V±) ” 9CM ” 9
± 1.15 V
±10
±20
±30
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±75
Figure 41. Input Offset Current vs Temperature
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
150
C001
Figure 42. Common-Mode Rejection Ratio vs Temperature
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Typical Characteristics (continued)
30
3.0
20
2.0
10
1.0
AOL (µV/V)
Power-Supply Rejection Ratio (µV/V)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
0
0.0
VS = ±2.5 V
-10
±1.0
-20
±2.0
-30
VS = ±1.35 V
±3.0
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±75
±50
±25
0
25
50
75
100
Temperature (ƒC)
C001
2.7 V ≤ VS ≤ 5.5 V
125
150
C001
RLOAD = 10 kΩ
Figure 43. Power-Supply Rejection Ratio vs Temperature
Figure 44. Open-Loop Gain vs Temperature With 10-kΩ
Load
5.0
1
4.0
0
Input Bias Current (µA)
3.0
AOL (µV/V)
2.0
VS = ±1.35 V
1.0
0.0
±1.0
VS = ±2.5 V
±2.0
±3.0
±1
±2
±3
±4
±4.0
±5.0
±5
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±4
0
±2
2
4
VCM (V)
C001
RLOAD = 600 Ω
C001
VS = ±2.5 V
Figure 45. Open-Loop Gain vs Temperature With 600-Ω
Load
Figure 46. Input Bias Current vs Input Common-Mode
Voltage
50
50
40
30
25
10
VOS ( V)
VOS ( V)
20
0
±10
±20
±30
VCM = 1.35 V
±25
VS = ±2.75 V
VS = ±1.35 V
VCM = ±2.5 V
0
±40
±50
±50
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
VSUPPLY (V)
2.8
±3
6 typical units shown, VS = ±1.35 V to ±2.75 V
Figure 47. Input Offset Voltage vs Power-Supply Voltage
16
±2
0
±1
VCM (V)
C001
1
2
C001
6 typical units shown, VS = ±2.5 V
Figure 48. Input Offset Voltage vs Common-Mode Voltage
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Typical Characteristics (continued)
at TA = 25°C, V+ = 5 V, V– = 0 V, VCOM = VO = 2.5 V, gain (G) = 2, RF = 1 kΩ, CF= 2.7 pF, CLOAD= 20 pF, and RLOAD = 2 kΩ
connected to 2.5 V (unless otherwise noted)
200
3
180
25°C
2
±40°C
0
-1
ISC, Sink
160
125°C
140
ISC (mA)
VO (V)
1
ISC, Source
120
125°C
100
-2
80
±40°C
25°C
60
-3
0
20
40
60
80
100
120
140
160
180
IO (mA)
±75
200
0
±25
25
50
75
100
125
150
Temperature (ƒC)
C001
Figure 50. Short-Circuit Current vs Temperature
Figure 49. Output Voltage vs Output Current
3
3
2.5
2.5
2
2
IQ (mA)
IQ (mA)
±50
C001
1.5
VS = ±1.35 V
1.5
1
1
0.5
0.5
0
VS = ±2.5 V
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
6
±75
±50
0
±25
25
50
75
100
125
Temperature (ƒC)
C001
Figure 51. Quiescent Current vs Power-Supply Voltage
150
C001
Figure 52. Quiescent Current vs Temperature
Change in Input Offset Voltage (PV)
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
0
0.2
0.4
0.6
Time (s)
0.8
1
1.2
D001
Powered on at t = 0 s, PCB dimensions: 4 in2, 2 layer, FR4
Figure 53. Warm-Up Time
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7 Parameter Measurement Information
7.1 DC Parameter Measurements
The circuit shown in Figure 54 measures the dc input offset related parameters of the OPA2626. Input offset
voltage, power-supply rejection ratio, common-mode rejection ratio, and open-loop gain can be measured with
this circuit. The basic test procedure requires setting the inputs (the power-supply voltage, VS, and the commonmode voltage, VCM), to the desired values. VO is set to the desired value by adjusting the loop-drive voltage while
measuring VO. After all inputs are configured, measure the input offset at the VX measurement point. Calculate
the input offset voltage by dividing the measured result by 101. Changing the voltages on the various inputs
changes the input offset voltage. The input parameters can be measured according to the relationships illustrated
in Equation 1 through Equation 5.
RCOMP = 1 k
RB = 1.26 k
Loop
Drive
V+
CCOMP = 0.1 PF
+
±
30 V
VX
VOS
+
RA = 12.6
+
RIN = 12.6
V-
VCM
VO
-30 V
RLOAD
+
±
Figure 54. DC-Parameters Measurement Circuit
VOS
VX
101
VOSDrift
PSRR
CMRR
AOL
18
(1)
'VOS
'Temperature
'VOS
'VSUPPLY
(2)
(3)
'VOS
'VCM
(4)
'VO
'VOS
(5)
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7.2 Transient Parameter Measurements
The circuit shown in Figure 55 measures the transient response of the OPA2626. Configure V+, V–, RISO, RLOAD,
and CLOAD as desired. Monitor the input and output voltages on an oscilloscope or other signal analyzer. Use this
circuit to measure large-signal and small-signal transient response, slew rate, overshoot, and capacitive-load
stability.
V+
RISO
+
V-
O-Scope
CLOAD
RLOAD
+
Input
±
Figure 55. Pulse-Response Measurement Circuit
7.3 AC Parameter Measurements
The circuit shown in Figure 56 measures the ac parameters of the OPA2626. Configure V+, V–, and CLOAD as
desired. The THS4271 family is used to buffer the input and output of the OPA2626 to prevent loading by the
gain phase analyzer. Monitor the input and output voltages on a gain phase analyzer. Use this circuit to measure
the gain bandwidth product, and open-loop gain versus frequency versus capacitive load.
249
249
50
+
249
Gain/Phase
Analyzer
249
50
1k
1k
+
+
CLOAD
Figure 56. AC-Parameters Measurement Circuit
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7.4 Noise Parameter Measurements
The circuit shown in Figure 57 measures the voltage noise of the OPA2626. Configure V+, V–, and CLOAD as
desired.
10
1k
Spectrum
Analyzer
+
CLOAD
Figure 57. Voltage Noise Measurement Circuit
The circuit shown in Figure 58 measures the current noise of the OPA2626. Configure V+, V– and CLOAD as
desired.
Spectrum
Analyzer
+
CLOAD
100 k
Figure 58. Current Noise Measurement Circuit
The circuit shown in Figure 59 measures the 0.1-Hz to 10-Hz voltage noise of the OPA2626. Configure V+, V–,
and CLOAD as desired.
10
0.1 Hz to 10 Hz
Active Bandpass Filter
1k
O-Scope
+
40 db/dec
-80 db/dec
CLOAD
Figure 59. 0.1-Hz to 10-Hz Voltage-Noise Measurement Circuit
20
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8 Detailed Description
8.1 Overview
The OPA2626 is a fast-settling, high slew rate, high-bandwidth, voltage-feedback operational amplifier. Low
offset and low offset drift combine with the superior dynamic performance and low output impedance of this
device, resulting in an amplifier suited for driving 16-bit and 18-bit SAR ADCs, and buffering precision voltage
references in industrial applications. The OPA2626 includes low-noise input, slew boost, and rail-to-rail output
stages.
8.2 Functional Block Diagram
V+
Bias
+IN
Low Noise Input
Stage
Common
Mode
Feedback
Slew
Boost
Rail-to-Rail
Output Stage
OUT
-IN
Frequency
Compensation
Network
V-
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8.3 Feature Description
8.3.1 SAR ADC Driver
The OPA2626 is designed to drive precision (16-bit and 18-bit) SAR ADCs at sample rates up to 1 MSPS. The
combination of low output impedance, low THD, low noise, and fast settling time make the OPA2626 the ideal
choice for driving both the SAR ADC inputs, as well as the reference input to the ADC. Internal slew boost
circuitry increases the slew rate as a function of the input signal magnitude, resulting in settling from a 4-V step
input to 16-bit levels within 280 ns. Low output impedance (1 Ω at 1 MHz) ensures capacitive load stability with
minimal overshoot.
8.3.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly. A good understanding of this basic ESD
circuitry and how the ESD circuitry relates to an electrical overstress event is helpful. Figure 60 provides a
diagram of the ESD circuits contained in the OPA2626. The ESD protection circuitry involves several currentsteering diodes connected from the input and output pins and routed back to the internal power-supply lines,
where the diodes meet at an absorption device or the power-supply ESD cell, internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
V+
Power Supply
ESD Cell
30 O
+IN
+
30 O
–
OUT
– IN
V–
Figure 60. Simplified ESD Circuit
22
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8.4 Device Functional Modes
The OPA2626 has a single functional mode and is operational when the power supply voltage, VS, is between
2.7 V (±1.35 V) and 5.5 V (±2.75 V).
8.4.1 High-Drive Mode
The OPA2626 has a 120-MHz gain bandwidth, 2.5-nV/√Hz input-referred noise, and consumes 2 mA of
quiescent current. Additionally, the OPA2626 has an offset voltage of 100 µV (maximum) and an offset voltage
drift of 1 µV/°C (typical). This combination of high precision, high speed, and low noise makes this device
suitable for use as an input driver for high-precision, high-throughput SAR ADCs such as the ADS88xx family of
SAR ADCs, as illustrated in Figure 61.
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPA2626 consists of precision, high-speed, voltage-feedback operational amplifiers. Fast settling to 16-bit
and 18-bit levels, low THD, and low noise make the OPA2626 suitable for driving SAR ADC inputs and buffering
precision voltage references. With a wide power-supply voltage range from 2.7 V to 5.5 V, and operating from
–40°C to +125°C, the OPA2626 is suitable for a variety of high-speed, industrial applications. The following
sections show application information for the OPA2626. For simplicity, power-supply decoupling capacitors are
not shown in these diagrams.
9.2 Typical Applications
9.2.1 Single-Supply, 16-Bit, 1-MSPS SAR ADC Driver
1 kO
1 kO
5V
RFLT
4.7 O
VREF / 4
+
VREF
OPA626
10 nF
CFLT
3.3 V
REF
AVDD
ADS8860
GND
4.7 O
RFLT
Figure 61. Single-Supply, 16-Bit, 1-MSPS SAR ADC Driver
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Typical Applications (continued)
9.2.1.1 Design Requirements
A SAR ADC, such as the ADS8860 device, uses sampling capacitors on the data converter input. During the
signal acquisition phase, these sampling capacitors are connected to the ADC analog input terminals AINP and
AINN (pins 3 and 4), through a set of switches. After the acquisition period has elapsed, the internal sampling
capacitors are disconnected from the input terminals (pins 3 and 4) and connected to the ADC input through a
second set of switches, during this period the ADC is performing the analog-to-digital conversion. Figure 62
shows this architecture.
SAR ADC
RSW
AINP
CS/H
RSW
CS/H
AINN
Figure 62. Simplified SAR ADC Input
The SAR ADC inputs and sampling capacitors must be driven by the OPA2626 to 16-bit levels within the
acquisition time of the ADC. For the example illustrated in Figure 61, the OPA2626 is used to drive the ADS8860
at a sample rate of 1 MSPS.
9.2.1.2 Detailed Design Procedure
The circuit illustrated in Figure 61 consists of the SAR ADC driver, a low-pass filter, and the SAR ADC. The SAR
ADC driver circuit consists of an OPA2626 configured in an inverting gain of 1. The filter consists of RFLT and
CFLT, connected between the OPA2626 output and the ADS8860 input. Selecting the proper values for each of
these passive components is critical to obtain the best performance from the ADC. Capacitor CFLT serves as a
charge reservoir, providing the necessary charge to the ADC sampling capacitors. The dynamic load presented
by the ADC creates a glitch on the filter capacitor, CFLT. To minimize the magnitude of this glitch, choose a value
for CFLT large enough to maintain a glitch amplitude of less than 100 mV. Maintaining such a low glitch amplitude
at the amplifier output makes sure that the amplifier remains in the linear operating region, and results in a
minimum settling time. Using Equation 6, a 10-nF capacitor is selected for CFLT.
CFLT t 15 u CSH
(6)
Connecting a 10-nF capacitor directly to the OPA2626 output degrades the OPA2626 phase margin and results
in stability and settling-time problems. To properly drive the 10-nF capacitor, use a series resistor (RFLT) to
isolate the capacitor, CFLT, from the OPA2626. RFLT must be sized based upon several constraints. To
determination a suitable value for RFLT, consider the impact upon the THD resulting from the voltage divider
effect from RFLT reacting with the switch resistance (RSW) of the ADC input circuit, as well as the impact of the
output impedance upon amplifier stability. In this example, 4.7-Ω resistors are selected. In this design example,
Figure 13 can be used to estimate a suitable value for RISO. RISO represents the total resistance in series with
CFLT, and in this example is equivalent to 2 × RFLT.
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results,
refer to the Power-optimized 16-bit 1MSPS Data Acquisition Block for Lowest Distortion and Noise Reference Design reference guide.
24
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9.2.1.3 Application Curve
Figure 63 shows the performance of the circuit in Figure 61.
0
THD = -110.8 dBc
SNR = 91.88 dB
SINAD = 91.86 dB
ENOB = 14.97
-25
Amplitude (dB)
-50
-75
-115.91 dBc (Third Harmonic)
-100
-125
-150
-175
0
50
100
150
200 250 300 350
Frequency (kHz)
400
450
500
4096-point FFT at 1 MSPS, fIN = 10 kHz , VIN = 1.5 VRMS
Figure 63. ADC Output FFT for Figure 61
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9.2.2 Single-Supply, 16-Bit, 1-MSPS, Multiplexed, SAR ADC Driver
In order to operate a high-resolution, 16-bit ADC at its maximum throughput, the full-scale voltage step must
settle to better than 16-bit accuracy at the ADC inputs within the minimum specified acquisition time (tACQ). This
settling imposes very stringent requirements on the driver amplifier in terms of large-signal bandwidth, slew rate,
and settling time. Figure 64 shows a typical multiplexed ADC driver application using the OPA2626.
1.5 pF
8k
2k
5V
5V
Mux
10
VREF
4.5 V
RFLT
12.4
+
OPA320
+
1 nF
TS5A3159
100 pF
22 µF
Input
Voltage
3.3 V
10
CFLT
REF
AVDD
ADS8860
GND
12.4
RFLT
Figure 64. Single-Supply, 16-Bit, 1-MSPS, Multiplexed, SAR ADC Driver
9.2.2.1 Design Requirements
To optimize this circuit for performance, this design does not allow any large signal input transients at the driver
circuit inputs for a small quiet-time period (tQT) towards the end of the previous conversion. The input step
voltage can appear anytime from the beginning of conversion (CONVST rising edge) until the elapse of a half
cycle time (0.5 × tCYC). This timing constraint on the input step allows a minimum settling time of (tQT + tACQ) for
the ADC input to settle within the required accuracy, in the worst-case scenario. tQT + tACQ is the total time in
which the output of the amplifier has to slew and settle within the required accuracy before the next conversion
starts. Figure 65 shows this timing sequence.
No Transients Allowed
Transients Allowed
CONVST
0.5 x tCYC_MIN = 500 ns
tQT
Slewing
tACQ
Settling
VIN
tCYC_MIN = 1 µs
Conversion
Sampling
Figure 65. Timing Diagram for Input Signals
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9.2.2.2 Detailed Design Procedure
An ADC input driver circuit consists of two parts: a driving amplifier and a fly-wheel RC filter. The amplifier is
used for signal conditioning of the input voltage and the low output impedance provides a buffer between the
signal source and the ADC input. The RC filter helps attenuate the sampling charge-injection from the switchedcapacitor input stage of the ADC and acts as an antialiasing filter to band-limit the wideband noise contributed by
the front-end circuit. The design of the ADC input driver involves optimizing the bandwidth of the circuit, driven by
the following requirements:
• The RFLT and CFLT filter bandwidth must be low to band-limit the noise fed into the input of the ADC, thereby
increasing the signal-to-noise ratio (SNR) of the system
• The overall system bandwidth must be large enough to accommodate optimal settling of the input signal at
the ADC input before the conversion starts
CFLT is chosen based upon Equation 7. CFLT is chosen to be 1 nF.
CFLT t 15 u CSH
(7)
Connecting a 1-nF capacitor directly to the output of the OPA2626 degrades the OPA2626 phase margin and
results in stability and settling time problems. To properly drive the 1-nF capacitor, a series resistor, RFLT, is used
to isolate the capacitor, CFLT, from the OPA2626. RFLT must be sized based upon several constraints. To
determination a suitable value for RFLT, the system designer must consider the impact upon the THD resulting
from the voltage divider effect from RFLT reacting with the switch resistance, RSW, of the ADC input circuit as well
as the impact of the output impedance upon amplifier stability. In this example 12.4-Ω resistors are selected. In
this design example, Figure 12 can be used to estimate a suitable value for RISO. RISO represents the total
resistance in series with CFLT, which in this example is equivalent to 2 × RFLT.
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test
results, refer to the 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step Response reference guide.
9.2.2.3 Application Curves
2
2
1.5
1.5
1
1
0.5
0.5
Error (LSB)
Error (LSB)
Figure 66 and Figure 67 show the performance of the circuit in Figure 64.
0
-0.5
0
-0.5
-1
-1
-1.5
-1.5
-2
-2
0
500
1000
Time (ns)
1500
2000
Figure 66. Positive Transient Response for Figure 64
0
500
1000
Time (ns)
1500
2000
Figure 67. Negative Transient Response for Figure 64
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10 Power Supply Recommendations
The OPA2626 is specified for operation from 2.7 V to 5.5 V (±1.35 V to ±2.75 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section. Place bypass capacitors close to the powersupply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed
information on bypass capacitor placement, see the Layout section.
CAUTION
Supply voltages larger than 6 V can cause permanent damage to the device. See the
Absolute Maximum Ratings section.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Use bypass capacitors to reduce the noise coupled from the power supply. Connect low ESR, ceramic,
bypass capacitors between the power-supply pins (V+ and V–) and the ground plane. Place the bypass
capacitors as close to the device as possible with the 100-nF capacitor closest to the device, as indicated in
Figure 68. For single-supply applications, bypass capacitors on the V– pin are not required.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make sure
to physically separate digital and analog grounds paying attention to the flow of the ground current. (For more
details, see the Circuit Board Layout Techniques chapter extract.)
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If the traces cannot be kept separate, crossing the sensitive trace perpendicular is better as
opposed to in parallel with the noisy trace.
• Minimize parasitic coupling between +IN and OUT for best ac performance.
• Place the external components as close to the device as possible. As illustrated in Figure 68, keeping RF,
CF, and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at
85°C for 30 minutes is sufficient for most circumstances.
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11.2 Layout Example
Place components
close to device and to
each other to reduce
parasitic errors .
OUT 1
VS+
OUT1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
V+
RF
OUT 2
GND
IN1 ±
OUT2
IN1 +
IN2 ±
RF
RG
VIN 1
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
IN2 +
VS±
Ground (GND) plane on another layer
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible .
Figure 68. PCB Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
12.1.1.2 TI Precision Designs
TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision
Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of
operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured
performance of many useful circuits.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Fast Settling 16-bit 1MSPS Multiplexed Data Acquisition Reference Design design guide
• Texas Instruments, Power-optimized 16-bit 1MSPS Data Acquisition Block for Lowest Distortion and Noise
Reference Design reference guide
• Texas Instruments, 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step Response
reference guide
• Texas Instruments, Circuit Board Layout Techniques chapter extract
• Texas Instruments, THS427x Low Noise, High Slew Rate, Unity Gain Stable Voltage Feedback Amplifier data
sheet
• Texas Instruments, ADS8860 16-bit, 1-MSPS, serial interface, micropower, miniature, single-ended input,
SAR analog-to-digital converter data sheet
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA is a trademark of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
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12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2626IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
16R6
OPA2626IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
16R6
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
