OPA2652E3K

Burr Brown Products from Texas Instruments OP A2 652 OPA2652 SBOS125A – JUNE 2000 – REVISED MAY 2006 Dual, 700MHz, Voltage-Feedback OPERATIONAL AMPLIFIER FEATURES • • • • • • • • • • • • • WIDEBAND BUFFER: 700MHz, G = +1 WIDEBAND LINE DRIVER: 200MHz, G = +2 HIGH OUTPUT CURRENT: 140mA LOW SUPPLY CURRENT: 5.5mA/Ch ULTRA-SMALL PACKAGE: SOT23-8 LOW dG/dφ: 0.05%/0.03° HIGH SLEW RATE: 335V/µsec SUPPLY VOLTAGE: ±3V to ±6V TM DESCRIPTION The OPA2652 is a dual, low-cost, wideband voltage feedback amplifier intended for price-sensitive applications. It features a high gain bandwidth product of 200MHz on only 5.5mA/channel quiescent current. Intended for operation on ±5V supplies, it also supports applications on a single supply from +6V to +12V with 140mA output current. Its classical differential input, voltage-feedback design allows wide application in active filters, integrators, transimpedance amplifiers, and differential receivers. The OPA2652 is internally compensated for unity gain stability. It has exceptional bandwidth (700MHz) as a unity gain buffer, with little peaking (0dB typ). Excellent DC accuracy is achieved with a low 1.5mV input offset voltage and 300nA input offset current. RELATED PRODUCTS SINGLES OPA650 OPA680 OPA631 OPA634 DUALS OPA2650 OPA2680 OPA2631 OPA2634 TRIPLES — OPA3680 — — QUADS OPA4650 — — — NOTES ±5V Spec +5V Capable +3V Capable +3V Capable APPLICATIONS A/D DRIVERS CONSUMER VIDEO ACTIVE FILTERS PULSE DELAY CIRCUITS LOW COST UPGRADE TO THE AD8056 OR EL2210 200W - 402W 24.9W 0.1mF 22pF 1.00kW +5V +5V 1/2 OPA2652 +In 0.1mF CM ADS807 12-Bit -In 1.00kW 53MHz VIN 133W 200W + 402W 24.9W 0.1mF 22pF 1/2 OPA2652 133W -5V Differential ADC Driver Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2006, Texas Instruments Incorporated OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PACKAGELEAD SO-8 SOT23-8 PACKAGE DESIGNATOR D DCN SPECIFIED TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C PACKAGE MARKING OPA2652U C52 ORDERING NUMBER OPA2652U OPA2652U/2K5 OPA2652E/250 OPA2652E/3K TRANSPORT MEDIA, QUANTITY Rails Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 3000 PRODUCT OPA2652U OPA2652E (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) OPA2652 Supply voltage Internal power dissipation Differential input voltage Input voltage range Storage temperature range Lead temperature (SO-8) Junction temperature, TJ ESD rating: Human body model Machine model (1) 2000 200 V V ±6.5 See Thermal Characteristics ±1.2 ±VS –40 to +125 +260 +175 V V °C °C °C UNIT V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. PIN CONFIGURATION Top View SO-8 SOT23-8 SOT23-8 Marking / Pin Orientation OPA2652 Out A -In A +In A -VS 1 2 3 4 8 7 6 5 +VS Out B -In B +In B C52 Pin 1 2 Submit Documentation Feedback OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 ELECTRICAL CHARACTERISTICS: VS = ±5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 28 and Figure 29 for AC performance only. OPA2652U, E TYP PARAMETER AC PERFORMANCE Small-Signal Bandwidth CONDITIONS (Figure 28 and Figure 29) G = +1, RF = 25Ω, VO = 200mVPP G = +2,VO = 200mVPP G = +5,VO = 200mVPP Gain Bandwidth Product Bandwidth for 0.1dB Flatness Peaking at a Gain of +1 Slew Rate Rise-and-Fall Time G ≥ +10 VO = 200mVPP G = +1, RF = 25Ω, VO = 200mVPP 4V step 200mV step 4V step Large-Signal Bandwidth SFDR Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Channel-to-Channel Crosstalk DC PERFORMANCE (4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT (4) Common-Mode Input Range Common-Mode Rejection Ratio Input Impedance Differential Common-Mode VCM = 0V 35 || 1 18 || 1 kΩ || pF MΩ || pF typ typ C C ±4.0 95 ±3.0 75 ±2.8 ±2.7 V dB min min A A ±0.3 ±1.0 ±1.4 ±2.0 4 15 VO = 4VPP VO = 2VPP, 5MHz f > 1MHz f > 1MHz NTSC, RL = 150Ω NTSC, RL = 150Ω f = 5MHz VCM = 0V 63 ±1.5 56 ±7 5 20 7 25 55 54 dB mV µV/°C µA µA/°C µA µA/°C min max max max max max max A A B A B A B 700 200 45 200 50 0 335 2.0 10 50 66 8 1.4 0.05 0.03 –100 MHz MHz MHz MHz MHz dB V/µs ns ns MHz dB nV/√Hz pA/√Hz % degrees dBc typ typ typ typ typ typ typ typ typ typ typ typ typ typ typ typ C C C C C C C C C C C C C C C C +25°C MIN/MAX OVER TEMPERATURE +25°C (2) 0°C to 70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX TEST LEVEL (1) (1) (2) (3) (4) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Junction temperature = ambient for +25°C tested specifications. Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature specifications. Current is considered positive-out-of node. VCM is the input common-mode voltage. Submit Documentation Feedback 3 OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 ELECTRICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 28 and Figure 29 for AC performance only. OPA2652U, E TYP PARAMETER OUTPUT Voltage Output Swing 1kΩ load 100Ω load Output Current, Sourcing Output Current, Sinking Closed-Loop Output Impedance POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio THERMAL CHARACTERISTICS Specified Operating Temperature Range Thermal Resistance, θJA U E SO-8 SOT23-8 U, E Packages Junction-to-Ambient 125 150 °C/W °C/W typ typ C C –40 to +85 °C typ C (–PSRR) Total both channels Total both channels Input-referred 11 11 58 ±5 ±6 13.2 8.8 54 ±6 14 8 ±6 15.5 7.5 V V mA mA dB typ max max min min C A A A A VO = 0V VO = 0V f < 100kHz ±3.0 ±2.5 140 140 0.06 ±2.4 ±2.2 100 100 85 85 75 75 V V mA mA Ω min min min min typ A A A A C CONDITIONS +25°C MIN/MAX OVER TEMPERATURE +25°C (2) 0°C to 70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX TEST LEVEL (1) 4 Submit Documentation Feedback OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 TYPICAL CHARACTERISTICS: VS = ±5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 28 and Figure 29. NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE 6 3 VO = 0.2VPP G = +1 RF = 25W 6 3 VO = 0.2VPP G = -1 G = -2 INVERTING SMALL-SIGNAL FREQUENCY RESPONSE Normalized Gain (dB) -3 -6 -9 -12 -15 -18 -21 -24 1M 10M 100M Frequency (Hz) G = +10 G = +5 Normalized Gain (dB) 0 G = +2 0 -3 -6 -9 -12 -15 -18 -21 -24 G = -5 G = -10 1G 1M 10M 100M Frequency (Hz) 1G Figure 1. NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE 6 3 G = +2 VO < 1VPP 6 3 G = -1 Figure 2. INVERTING LARGE-SIGNAL FREQUENCY RESPONSE Normalized Gain (dB) -3 -6 -9 -12 -15 -18 -21 -24 1M 10M 100M Frequency (Hz) 1G VO = 2VPP Normalized Gain (dB) 0 0 -3 -6 -9 -12 -15 -18 -21 -24 1M 10M 100M Frequency (Hz) VO = 1.0VPP VO = 0.5VPP VO = 4VPP VO = 2.0VPP 1G Figure 3. NONINVERTING PULSE RESPONSE G = +2 Figure 4. INVERTING PULSE RESPONSE G = -1 Output Voltage (800mV/div) Output Voltage (800mV/div) Output Voltage (50mV/div) 200mVPP 200mVPP Time (5ns/div) Time (5ns/div) Figure 5. Figure 6. Output Voltage (50mV/div) 4VPP 4VPP Submit Documentation Feedback 5 OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 28 and Figure 29. HARMONIC DISTORTION vs NONINVERTING GAIN -50 VO = 2VPP f = 5MHz -50 3rd Harmonic HARMONIC DISTORTION vs INVERTING GAIN VO = 2VPP f = 5MHz 3rd Harmonic Harmonic Distortion (dBc) -60 2nd Harmonic -70 Harmonic Distortion (dBc) -60 2nd Harmonic -70 -80 -80 -90 1 Gain Magnitude (V/V) 10 -90 1 Gain Magnitude (V/V) 10 Figure 7. HARMONIC DISTORTION vs OUTPUT VOLTAGE -50 f = 5MHz -50 VO = 2VPP Figure 8. HARMONIC DISTORTION vs FREQUENCY Harmonic Distortion (dBc) Harmonic Distortion (dBc) -60 3rd Harmonic -70 2nd Harmonic -80 -60 3rd Harmonic -70 -80 2nd Harmonic -90 0.1 1 Output Voltage (VPP) 4 -90 0.1 1 Frequency (MHz) 10 20 Figure 9. HARMONIC DISTORTION vs LOAD RESISTANCE -50 VO = 2VPP f = 5MHz -60 3rd Harmonic -70 2nd Harmonic -80 -50 Figure 10. HARMONIC DISTORTION vs SUPPLY VOLTAGE VO = 2VPP f = 5MHz Harmonic Distortion (dBc) Harmonic Distortion (dBc) -60 3rd Harmonic -70 2nd Harmonic -80 -90 100 RL (W) 1000 -90 ±3 ±4 ±5 ±6 Supply Voltage (V) Figure 11. Figure 12. 6 Submit Documentation Feedback OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 28 and Figure 29. TWO-TONE, 3rd-ORDER SPURIOUS LEVEL -50 0.30 df, Positive Video 0.25 -60 10MHz -70 5MHz 2MHz -80 1MHz Load Power at matched 50W load -8 -6 -4 -2 0 2 4 20MHz 0.20 df, Negative Video 0.15 0.10 0.05 0.00 1 2 dG, Positive Video dG, Negative Video 3 4 COMPOSITE VIDEO dG/dφ 3rd-Order Spurious Level (dBc) -90 Single-Tone Load Power (dBm) dG/df (%/°) Number of 150W Loads Figure 13. INPUT VOLTAGE AND CURRENT NOISE DENSITY 100 -30 Figure 14. CHANNEL-TO-CHANNEL CROSSTALK Crosstalk, Input-Referred (dB) 10M -40 -50 -60 -70 -80 -90 Voltage Noise (nV/ÖHz) Current Noise (pA/ÖHz) Voltage Noise = 8.0nV/ÖHz 10 Current Noise = 1.4pA/ÖHz 1 100 1k 10k 100k 1M Frequency (Hz) 10 100 Frequency (MHz) 1000 Figure 15. RECOMMENDED RS vs CAPACITIVE LOAD Normalized Gain to Capacitive Load (dB) 70 60 50 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 0 10M 1/2 OPA2652 Figure 16. FREQUENCY RESPONSE vs CAPACITIVE LOAD G = +2 CL = 10pF CL = 22pF CL = 100pF RS (W) 40 30 20 10 0 1 10 100 1000 Capacitive Load (pF) RS VO CL = 47pF CL 1kW 100M Frequency (Hz) 1G Figure 17. Figure 18. Submit Documentation Feedback 7 OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 28 and Figure 29. CMRR AND PSRR vs FREQUENCY 100 70 OPEN-LOOP GAIN AND PHASE 0 -30 Open-Loop Phase Power Supply Rejection Ratio (dB) Common-Mode Rejection Ratio (dB) 90 80 70 60 50 40 30 20 10 0 CMRR Open-Loop Gain (dB) 60 50 40 30 20 10 0 -10 Open-Loop Gain +PSRR -PSRR -90 -120 -150 -180 -210 -240 10k 100k 1M 10M 100M 1G Frequency (Hz) 1k 10k 100k 1M 10M 100M Frequency (Hz) Figure 19. CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 100 200W Figure 20. OUTPUT VOLTAGE AND CURRENT LIMITATIONS 5 4 1W Internal Power Limit Output Current Limited 1/2 OPA2652 Output Impedance (W) 10 402W ZO 3 2 VO (V) 1 0 -1 100W Load Line 50W Load Line 20W Load Line 10W Load Line Output Current Limit 1W Internal Power Limit 1 402W 0.1 -2 -3 -4 0.01 10k 100k 1M 10M 100M 400M -5 -200 -150 -100 -50 0 IO (mA) 50 100 150 200 Frequency (Hz) Figure 21. NONINVERTING OVERDRIVE RECOVERY 5 4 VIN VOUT G = +2 2.5 2.0 5 4 Figure 22. INVERTING OVERDRIVE RECOVERY G = -1 VIN Input and Output Voltage (V) Output Voltage (V) 3 2 1 0 -1 -2 -3 -4 -5 1.5 3 2 1 0 -1 -2 -3 -4 -5 VOUT 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 Time (20ns/div) Input Voltage (V) Time (20ns/div) Figure 23. Figure 24. 8 Submit Documentation Feedback Open-Loop Phase (°) -60 OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 28 and Figure 29. TYPICAL DC DRIFT OVER TEMPERATURE 6 250 Sourcing Output Current 200 20 Sinking Output Current 150 15 SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 25 Input Offset Voltage (mV) Input Bias and Offset Current (A) 5 4 2 1 0 -1 -2 -3 -4 -5 -6 -40 -20 0 20 40 60 80 100 0 -40 IB IOS VOS 100 Quiescent Supply Current (Both Channels) 50 10 5 0 -20 0 20 40 60 80 100 Ambient Temperature (°C) Ambient Temperature (°C) Figure 25. COMMON-MODE INPUT VOLTAGE RANGE AND OUTPUT SWING vs SUPPLY VOLTAGE 6 Positive Common-Mode Input Range Figure 26. 5 Negative Common-Mode Input Range Voltage Range (V) 4 3 2 Negative Output Voltage Range 1 Positive Output Voltage Range 0 ±3 ±4 ±5 ±6 Supply Voltage (V) Figure 27. Supply Current (mA) Output Current (mA) 3 Submit Documentation Feedback 9 OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 APPLICATIONS INFORMATION Wideband Voltage Feedback Operation The OPA2652 is a dual, low-power, wideband voltage feedback operational amplifier. Each channel is internally compensated to provide unity gain stability. The OPA2652 voltage feedback architecture features true differential and fully symmetrical inputs. This architecture minimizes offset errors, making the OPA2652 well-suited for implementing filter and instrumentation designs. As a dual operational amplifier, OPA2652 is an ideal choice for designs that require multiple channels where reduction of board space, power dissipation and cost are critical. Its AC performance is optimized to provide a gain bandwidth product of 200MHz and a fast rise time of 2.0ns, which is an important consideration in high-speed data conversion applications. The low DC input offset of ±1.5mV and drift of ±5µV/°C support high accuracy requirements. In applications requiring a higher slew rate and wider bandwidth, such as video and high bit rate digital communications, consider the dual current feedback OPA2694, or the OPA2691. Figure 28 shows the DC-coupled, gain of +2, dual power-supply circuit configuration used as the basis of the ±5V specifications and typical characteristics. This configuration is for one channel. The other channel is connected similarly. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. +5V + 0.1mF 6.8mF + 0.1mF 50W Source 174W VI 49.9W 1/2 OPA2652 VO 49.9W 50W Load RB 205W 1/2 OPA2652 RO VO 49.9W 50W Load 0.1mF 6.8mF Voltage swings reported in the specifications are taken directly at the input and output pins, while output powers (dBm) are at the matched 50Ω load. For the circuit of Figure 28, the total effective load will be 100Ω || 804Ω. Two optional components are included in Figure 28. An additional resistor (174Ω) is included in series with the noninverting input. Combined with the 25Ω DC source resistance looking back towards the signal generator, this additional resistor gives an input bias current cancelling resistance that matches the 201Ω source resistance seen at the inverting input (see the DC Accuracy and Offset Control section). In addition to the usual power-supply decoupling capacitors to ground, a 0.1µF capacitor is included between the two power-supply pins. In practical printed circuit board (PCB) layouts, this optional-added capacitor typically improves the 2nd-harmonic distortion performance by 3dB to 6dB. Figure 29 shows the DC-coupled, gain of –1, bipolar supply circuit configuration that is the basis of the specifications and typical characteristics at G = –1. The input impedance matching resistor (57.6Ω) used for testing gives a 50Ω input load. A resistor (205Ω) connects the noninverting input to ground. This configuration provides the DC source resistance matching to cancel outputs errors arising from input bias current. +5V 0.1mF 50W RF 402W Source VI RG 402W RF 402W VO = -1 VI RG 402W + -5V 6.8mF 0.1mF RM 57.6W 0.1mF + 6.8mF -5V Figure 28. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit Figure 29. DC-Coupled, G = –1, Bipolar Supply, Specification and Test Circuit 10 Submit Documentation Feedback OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 Differential ADC Driver The circuit on the front page shows an OPA2652 driving the ADS807 analog-to-digital converter (ADC) differentially, at a gain of +2V/V. The outputs are AC-coupled to the converter to adjust for the difference in supply voltages. The 133Ω resistors at the noninverting inputs minimize DC offset errors. The differential topology minimizes even-order distortion products, such as second-harmonic distortion. 0 -5 -10 Gain (dB) -15 -20 -25 -30 -35 -40 10k Bandpass Filter Figure 31 shows a single OPA2652 implementing a sixth-order bandpass filter. This filter cascades two second-order Sallen-Key sections with transmission zeros, and a double real pole section. It has 0.3dB of ripple, –3dB frequencies of 450kHz and 11MHz, and –23dB frequencies of 315kHz and 16MHz. The 20.0Ω resistor isolates the first OPA2652 output from capacitive loading. This configuration improves stability with minimal impact on the filter response. Figure 30 shows the nominal response simulated by SPICE. 2.2nF 100k 1M Frequency (Hz) 10M 100M Figure 30. Nominal Filter Response 1% Resistors 5% Capacitors +5V 140W 2.10kW 1/2 OPA2652 VIN 1.0nF 1.0nF 1.30kW -5V 24.9W 143W 180pF +5V 225W 200W VOUT 100pF 100W -5V 24.9W 107W 2.7nF 1/2 OPA2652 158W 18pF 20.0W 12pF 150pF Figure 31. Bandpass Filter Submit Documentation Feedback 11 OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 Video Line Driver Figure 32 shows the OPA2652 used as a video line driver. Its outstanding differential gain and phase allow it to be used in studio equipment, while its low cost and SOT23-8 package option also support consumer applications. +5V Video Input 75.0W 1/2 OPA2652 C1 VIN +5V 402W C2 402W VOUT 1/2 OPA2652 75.0W Video Output 402W -5V -5V 402W 402W Figure 34. Inverting Bandpass Filter DESIGN-IN TOOLS Figure 32. Video Line Driver Demonstration Fixtures Pulse Delay Circuit Figure 33 shows the OPA2652 used in a pulse delay circuit. This circuit cascades the two op amps in the OPA2652, each forming a single pole, active allpass filter. The overall gain is +1, and the overall delay through the filter is: tGD = n(2RC), overall group delay n = 2, the number of cascaded stages +5V C VIN R 1/2 OPA2652 R 1/2 OPA2652 VO C +5V Two printed circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the OPA2652 in its two package options. Both of these are offered free of charge as unpopulated PCBs, delivered with a user's guide. The summary information for these fixtures is shown in Table 1. Table 1. Demonstration Fixtures for the OPA2652 PRODUCT OPA2652U OPA2652E PACKAGE SO-8 SOT23-8 ORDERING NUMBER DEM-OPA-SO-2A DEM-OPA-SOT-2A LITERATURE NUMBER SBOU003 SBOU001 The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the OPA2652 product folder. Macromodels and Applications Support Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This method is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. Check the Texas Instruments web site (www.ti.com) for available SPICE products (note that not all parts have models). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dφ characteristics. These models do not attempt to distinguish between the package types in small-signal AC performance. RG 402W -5V RF 402W -5V 402W 402W Figure 33. Pulse Delay Circuit RF and RG need to be equal to maintain a constant gain magnitude. The rise and fall times of the input pulses, tr(IN), should be slow enough to prevent pre-shoot artifacts in the response. tr(IN) ≥ 5RC, minimal pre-shoot Simple Bandpass Filter Figure 34 shows the OPA2652 used as simple bandpass filter. The OPA2652 is well-suited for this type of circuit because it is very stable at a noise gain of +1. 12 Submit Documentation Feedback OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 OPERATING SUGGESTIONS Optimizing Resistor Values Because the OPA2652 is a unity gain stable voltage feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a noninverting unity gain follower application, the feedback connection should be made with a 25Ω resistor, not a direct short. This configuration isolates the inverting input capacitance from the output pin and improves the frequency response flatness. Usually, the feedback resistor value should be between 200Ω and 1.5kΩ. Below 200Ω, the feedback network presents additional output loading that can degrade the harmonic distortion performance of the OPA2652. Above 1.5kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional bandlimiting in the amplifier response. A good rule of thumb is to target the parallel combination of RF and RG (see Figure 28) to be less than approximately 300Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network, and thus a zero in the forward response. Assuming a 2pF total parasitic on the inverting node, holding RF || RG < 300Ω keeps this pole above 250MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This increase is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest. Bandwidth vs Gain: Noninverting Operation Voltage feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the specifications. Ideally, dividing GBP by the noninverting signal gain (also called the Noise Gain, or NG) predicts the closed-loop bandwidth. In practice, this prediction only holds true when the phase margin approaches 90°, as it does in high gain configurations. At low gains (increased feedback factor), most amplifiers exhibit a wider bandwidth and lower phase margin. The OPA2652 is compensated to give a flat response in a noninverting gain of 1 (see Figure 28). This configuration results in a typical gain of +1 bandwidth of 700MHz, far exceeding that predicted by dividing the 200MHz GBP by NG = 1. Increasing the gain causes the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +5, the 45MHz bandwidth shown in the Electrical Characteristics is close to that predicted using this simple formula. Inverting Amplifier Operation Because the OPA2652 is a general-purpose, wideband voltage feedback op amp, all of the familiar op amp application circuits are available to the designer. Inverting operation is one of the more common requirements and offers several performance benefits. Figure 29 shows a typical inverting configuration. In the inverting configuration, three key design consideration must be noted. First, the gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PCB trace or other transmission line conductor), RG may be set equal to the required termination value and RF adjusted to give the desired gain. This approach is the simplest, and results in optimum bandwidth and noise performance. However, at low inverting gains, the resulting feedback resistor value can present a significant load to the amplifier output. For an inverting gain of –1, setting RG to 50Ω for input matching eliminates the need for RM but requires a 50W feedback resistor. This configuration has the interesting advantage that the noise gain becomes equal to 2 for a 50Ω source impedance—the same as the noninverting circuits considered above. However, the amplifier output now sees the 50Ω feedback resistor in parallel with the external load. In general, the feedback resistor should be limited to the 200Ω to 1.5kΩ range. In this case, it is preferable to increase both the RF and RG values as shown in Figure 29, and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of RG and RM. The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and influences the bandwidth. For the example in Figure 29, the RM value combines in parallel with the external 50Ω source impedance, yielding an effective driving impedance of 50Ω || 57.6Ω = 26.8Ω. This impedance is added in series with RG for calculating the noise gain (NG). The resulting NG is 1.94 for Figure 29 (an ideal source would cause NG = 2.00). The third important consideration in inverting amplifier design is setting the bias current cancellation resistor on the noninverting input (RB). If this resistor is set equal to the total DC resistance looking out of the inverting node, the output DC 13 Submit Documentation Feedback OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 error, as a result of the input bias currents, is reduced to (Input Offset Current) • RF. If the 50Ω source impedance is DC-coupled in Figure 29, the total resistance to ground on the inverting input will be 429Ω. Combining this in parallel with the feedback resistor gives 208Ω, which is close to the RB = 205Ω used in Figure 29. To reduce the additional high-frequency noise introduced by this resistor, it is sometimes bypassed with a capacitor. As long as RB 1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. The 402Ω feedback used in the typical performance specifications is a good starting point for design. Note that a 25Ω feedback resistor, rather than a direct short, is suggested for the unity gain follower application. This effectively isolates the inverting input capacitance from the output pin that would otherwise cause additional peaking in the gain of +1 frequency response. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load (Figure 17). Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA2652 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin) If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the OPA2652 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA2652 allows multiple destination devices to be handled as separate transmission lines, each with respective series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Recommended RS vs Capacitive Load (Figure 17). This configuration will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA2652 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network that can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2652 directly onto the board. Input and ESD Protection The OPA2652 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies as shown in Figure 37. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the OPA2652), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. +VCC External Pin Internal Circuitry -VCC Figure 37. Internal ESD Protection Submit Documentation Feedback 17 OPA2652 www.ti.com SBOS125A – JUNE 2000 – REVISED MAY 2006 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (June 2000) to A Revision ........................................................................................................ Page • • • • Changed format of data sheet. Updated to XML from PageMaker. ..................................................................................... 1 Changed input voltage axis values to correct units. ............................................................................................................ 8 Changed reference to alternate part numbers. ................................................................................................................... 10 Changed information regarding available demonstration fixtures....................................................................................... 12 18 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 26-Mar-2007 PACKAGING INFORMATION Orderable Device OPA2652E/250 OPA2652E/250G4 OPA2652E/3K OPA2652E/3KG4 OPA2652U OPA2652U-1/2K5 OPA2652U-1/2K5G4 OPA2652U/2K5 OPA2652U/2K5G4 OPA2652UG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type SOT-23 SOT-23 SOT-23 SOT-23 SOIC SOIC SOIC SOIC SOIC SOIC Package Drawing DCN DCN DCN DCN D D D D D D Pins Package Eco Plan (2) Qty 8 8 8 8 8 8 8 8 8 8 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR 3000 Green (RoHS & no Sb/Br) 3000 Green (RoHS & no Sb/Br) 100 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 100 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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