OPA2674
SBOS270 − AUGUST 2003
Dual Wideband, High Output Current Operational Amplifier with Current Limit
FEATURES
D D D D D D D D D D D D D D D
WIDEBAND +12V OPERATION: 220MHz (G = +4) UNITY-GAIN STABLE: 250MHz (G = +1) HIGH OUTPUT CURRENT: 500mA OUTPUT VOLTAGE SWING: 10VPP HIGH SLEW RATE: 2000V/µs LOW SUPPLY CURRENT: 18mA FLEXIBLE POWER CONTROL: SO-14 Only OUTPUT CURRENT LIMIT (±800mA)
DESCRIPTION
The OPA2674 provides the high output current and low distortion required in emerging xDSL and Power Line Modem driver applications. Operating on a single +12V supply, the OPA2674 consumes a low 9mA/ch quiescent current to deliver a very high 500mA output current. This output current supports even the most demanding ADSL CPE requirements with > 380mA minimum output current (+25°C minimum value) with low harmonic distortion. Differential driver applications deliver < −85dBc distortion at the peak upstream power levels of full rate ADSL. The high 200MHz bandwidth also supports the most demanding VDSL line driver requirements. Power control features are included in the SO-14 package version to allow system power to be minimized. Two logic control lines allow four quiescent power settings. These include full power, power cutback for short loops, idle state for no signal transmission but line match maintenance, and shutdown for power off with a high impedance output. Specified on ±6V supplies (to support +12V operation), the OPA2674 will also support a single +5V or dual ±5V supply. Video applications will benefit from a very high output current to drive up to 10 parallel video loads (15Ω) with < 0.1%/0.1° dG/dP nonlinearity.
APPLICATIONS
POWER LINE MODEM xDSL LINE DRIVERS CABLE MODEM DRIVERS MATCHED I/Q CHANNEL AMPLIFIERS BROADBAND VIDEO LINE DRIVERS ARB LINE DRIVERS HIGH CAP LOAD DRIVER
OPA2674 RELATED PRODUCTS
SINGLES OPA691 DUALS OPA2691 THS6042 OPA2677 TRIPLES OPA3691 NOTES Single +12V Capable ±15V Capable Single +12V Capable
+12V 20Ω
1 /2 O P A 26 74
324Ω 2kΩ 2kΩ 1µ F 82.5Ω 324Ω
17.4Ω 1:1.7
AFE Output
+6.0V 2VPP
17.7VPP 17.4Ω
15VPP
Twisted Pair
100Ω
20Ω
1 /2 O P A 26 74
Single− Supply CPE Upstream Driver
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
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OPA2674
SBOS270 − AUGUST 2003
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ORDERING INFORMATION
PRODUCT OPA2674 PACKAGE−LEAD SO-8 PACKAGE DESIGNATOR(1) D SPECIFIED TEMPERATURE RANGE −40°C to +85°C −40°C to +85°C PACKAGE MARKING OPA2674ID ORDERING NUMBER OPA2674ID OPA2674IDR OPA2674I-14D OPA2674I-14DR TRANSPORT MEDIA, QUANTITY Rails, 100 Tape and Reel, 2500 Rails, 58 Tape and Reel, 2500
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OPA2674
SO-14
D
OPA2674I-14D
(1) For the most current specification and package information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6.5VDC Internal Power Dissipation . . . . . . . . . . . . . . See Thermal Analysis Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2V Input Common-Mode Voltage Range . . . . . . . . . . . . . . . . . . . . ±VS Storage Temperature Range: D, -14D . . . . . . . . . . . −40°C to +125°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . +300°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C ESD Rating Human Body Model (HBM)(2) . . . . . . . . . . . . . . . . . . . . . . 2000V Charge Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . 1000V Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Pins 2 and 6 on SO-8 package, and pins 1 and 7 on SO-14 package > 500V HBM.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PIN CONFIGURATIONS
Top View SO-8 Top View OPA2674I− 14D − In A OPA2674ID Out A − In A +In A − VS 1 2 3 4 8 7 6 5 +VS Out B − In B +In B − VS A1 +In B − In B 4 5 6 7 +In A A0 1 2 3 Power Control 14 Out A 13 NC 12 NC 11 +VS 10 NC 9 8 NC = No Connection NC Out B SO-14
2
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OPA2674
SBOS270 − AUGUST 2003
ELECTRICAL CHARACTERISTICS: VS = ±6V
Boldface limits are tested at +25°C.
At TA = +25°C, A1 = A0 = 1 (full power: for SO-14 only), G = +4, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1 for AC performance only.
OPA2674ID, OPA2674I-14D TYP PARAMETER AC Performance (see Figure 1) Small-Signal Bandwidth (VO = 0.5VPP) 0.5V TEST CONDITIONS G = +1, RF = 511Ω G = +2, RF = 475Ω G = +4, RF = 402Ω G = +8, RF = 250Ω G = +1, RF = 511Ω G = +4, VO = 0.5VPP G = +4, VO = 5VPP G = +4, 5V step G = +4, VO = 2V step G = +4, f = 5MHz, VO = 2VPP RL = 100Ω RL ≥ 500Ω RL = 100Ω RL ≥ 500Ω f > 1MHz f > 1MHz f > 1MHz NTSC, G = +2, RL = 150Ω NTSC, G = +2, RL = 37.5Ω NTSC, G = +2, RL = 150Ω NTSC, G = +2, RL = 37.5Ω f = 5MHz, Input Referred VO = 0V, RL = 100Ω VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V +25°C 250 225 220 260 0.2 100 220 2000 1.6 −72 −82 −81 −93 2 16 24 0.03 0.05 0.01 0.04 −92 135 ±1 ±4 ±10 ±5 ±10 ±10 ±4.5 55 250 2 22 22 ±5.1 ±5.0 ±4.8 ±500 ±800 0.01 ±500 ±450 ±100 +25°C(1) MIN/MAX OVER TEMPERATURE 0°C to +70°C(2) −40°C to +85°C(2) UNITS MHz MHz MHz MHz dB MHz MHz V/µs ns dBc dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz % % deg deg dB kΩ mV µV/°C µA nA/°C µA nA/°C V dB kΩ pF Ω Ω V V V mA mA Ω mA mA mA MIN/ MAX typ min min min typ min typ min typ max max max max max max max typ typ typ typ typ min max max max max max max min min typ min max min min typ min typ typ min min min TEST LEVEL (3) C B B B C B C B C B B B B B B B C C C C C A A B A B A B A A C B B A A C A C C A A A
170 170 200 40 160 1500
165 165 195 35 155 1450
160 160 190 30 150 1400
Peaking at a Gain of +1 Bandwidth for 0.1dB Gain Flatness Large-Signal Bandwidth Slew Rate Rise Time and Fall Time Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Noninverting Input Current Noise Inverting Input Current Noise NTSC Differential Gain NTCS Differential Phase Channel-to-Channel Crosstalk DC Performance(4) Open-Loop Transimpedance Gain Input Offset Voltage Offset Voltage Drift Noninverting Input Bias Current Noninverting Input Bias Current Drift Inverting Input Bias Current Inverting Input Bias Current Drift Input(4) Common-Mode Input Range (CMIR)(5) Common-Mode Rejection Ratio (CMRR) Noninverting Input Impedance Minimum Inverting Input Resistance Maximum Inverting Input Resistance Output (4) Output Voltage Swing
−68 −80 −79 −91 2.6 20 29
−67 −79 −78 −90 2.9 21 30
−66 −78 −77 −89 3.1 22 31
80 ±4.5 ±10 ±30 ±50 ±35 ±100 ±4.1 51 12 35 ±4.9 ±4.8 ±380
76 ±5 ±10 ±32 ±50 ±40 ±100 ±4.0 50
75 ±5.3 ±12 ±35 ±75 ±45 ±150 ±4.0 50
VCM = 0V, Input Referred Open-Loop Open-Loop No Load RL = 100Ω RL = 25Ω VO = 0 VO = 0 G = +4, f ≤ 100kHz A1 = 1, A0 = 1, VO = 0 A1 = 1, A0 = 0, VO = 0 A1 = 0, A0 = 1, VO = 0
±4.8 ±4.7 ±350
±4.7 ±4.5 ±320
Current Output Short-Circuit Current Closed-Loop Output Impedance Output (4) (SO-14 Only) Current Output at Full Power Current Output at Power Cutback Current Output at Idle Power
±380 ±350 ±60
±350 ±320 ±55
±320 ±300 ±50
(1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ± CMIR limits.
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OPA2674
SBOS270 − AUGUST 2003
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ELECTRICAL CHARACTERISTICS: VS = ±6V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, A1 = A0 = 1 (full power: for SO-14 only), G = +4, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1 for AC performance only.
OPA2674ID, OPA2674I-14D TYP PARAMETER Power Supply Specified Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (PSRR) Power Supply (SO-14 Only) Maximum Logic 0 Minimum Logic 1 Logic Input Current Supply Current at Full Power Supply Current at Power Cutback Supply Current at Idle Power Supply Current at Shutdown Output Impedance in Idle Power Output Impedance in Shutdown Supply Current Step Time Output Switching Glitch Shutdown Isolation Thermal Characteristics Specification: ID, I-14D Thermal Resistance, qJA ID SO-8 I-14D SO-14 Junction-to-Ambient −40 to +85 125 100 °C °C/W °C/W typ typ C C A1, A0, +VS = +6V A1, A0, +VS = +6V A1 = 0V, A0 = 0V, Each Line A1 = 1, A0 = 1 (logic levels) A1 = 1, A0 = 0 (logic levels) A1 = 0, A0 = 1 (logic levels) A1 = 0, A0 = 0 (logic levels) G = +4, f < 1MHz 10% to 90% Change Inputs at GND G = +4, 1MHz, A1 = 0, A0 = 0 2.5 3.3 60 18.0 13.3 4.0 1.0 0.1 100 4 200 ±20 85 2.0 3.6 90 18.6 14.2 4.8 1.3 1.8 4.0 100 18.8 14.4 5.1 1.4 1.5 4.2 105 19.2 14.8 5.3 1.5 V V µA mA mA mA mA Ω kΩ pF ns mV dB max min max max max max max typ typ typ typ typ A A A A A A A C C C C C ±6 VS = ±6V VS = ±6V f = 100kHz, Input Referred 18 18 56 ±6.3 18.6 17.4 51 ±6.3 18.8 16.5 49 ±6.3 19.2 16.0 48 V V mA mA dB typ max max min min C A A A A TEST CONDITIONS +25°C +25°C(1) MIN/MAX OVER TEMPERATURE 0°C to +70°C(2) −40°C to +85°C(2) UNITS MIN/ MAX TEST LEVEL (3)
(1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ± CMIR limits.
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OPA2674
SBOS270 − AUGUST 2003
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
At TA = +25°C, A1 = 1, A0 = 1 (Full Power: for SO-14 only), G = +4, RF = 453Ω, and RL = 100Ω, unless otherwise noted. See Figure 3 for AC performance only.
OPA2674ID, OPA2674I-14D TYP PARAMETER AC Performance (see Figure 3) Small-Signal Bandwidth (VO = 0.5VPP) 0.5V G = +1, RF = 536Ω G = +2, RF = 511Ω G = +4, RF = 453Ω G = +8, RF = 332Ω G = +1, RF = 511Ω G = +4, VO = 0.5VPP G = +4, VO = 5VPP G = +4, 2V Step G = +4, VO = 2V Step G = +4, f = 5MHz, VO = 2VPP RL = 100Ω RL ≥ 500Ω RL = 100Ω RL ≥ 500Ω f > 1MHz f > 1MHz f > 1MHz f = 5MHz, Input Referred VO = 0V, RL = 100Ω VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V 220 175 168 175 0.6 34 190 900 2 −65 −72 −72 −74 2 16 24 −92 140 130 140 24 140 650 130 126 130 22 135 625 120 120 125 20 130 600 MHz MHz MHz MHz dB MHz MHz V/µs ns dBc dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz dB kΩ mV µV/°C µA nA/°C µA nA/°C V V dB kΩ pF 15 40 Ω Ω 3.8 3.7 1.1 1.2 ±180 3.6 3.5 1.3 1.5 ±160 V V V V mA Ω mA mA mA typ min min min typ min typ min typ max max max max max max max typ C B B B C B C B C B B B B B B B C TEST CONDITIONS +25°C +25°C(1) MIN/MAX OVER TEMPERATURE 0°C to +70°C(2) −40°C to +85°C(2) UNITS MIN/ MAX TEST LEVEL (3)
Peaking at a Gain of +1 Bandwidth for 0.1dB Gain Flatness Large-Signal Bandwidth Slew Rate Rise Time and Fall Time Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Noninverting Input Current Noise Inverting Input Current Noise Channel-to-Channel Crosstalk DC Performance(4) Open-Loop Transimpedance Gain Input Offset Voltage Offset Voltage Drift Noninverting Input Bias Current Noninverting Input Bias Current Drift Inverting Input Bias Current Inverting Input Bias Current Drift Input Most Positive Input Voltage(5) Most Negative Input Voltage(5) Common-Mode Rejection Ratio (CMRR) Noninverting Input Impedance Minimum Inverting Input Resistance Maximum Inverting Input Resistance Output Most Positive Output Voltage Most Negative Output Voltage Current Output Closed-Loop Output Impedance Output (SO-14 Only) Current Output at Full Power Current Output at Power Cutback Current Output at Idle Power
−63 −70 −70 −71 2.6 20 29
−62 −69 −69 −70 2.9 21 30
−61 −68 −68 −69 3.1 22 31
110 ±0.8 ±4 ±10 ±5 ±10 ±10 3.7 1.3
72 ±3.5 ±10 ±30 ±50 ±35 ±100 3.3 1.7 49
70 ±4.0 ±10 ±32 ±50 ±40 ±100 3.2 1.8 48
68 ±4.3 ±12 ±35 ±75 ±45 ±150 3.1 1.9 47
min max max max max max max min min min typ min max
A A B A B A B A A A C B B
VCM = 2.5V, Input Referred Open-Loop Open-Loop No Load RL = 100Ω No Load RL = 100Ω VO = 0 G = +4, f ≤ 100kHz A1 = 1, A0 = 1, VO = 0 A1 = 1, A0 = 0, VO = 0 A1 = 0, A0 = 1, VO = 0
53 250 2 25 25
4.1 3.9 0.8 1.0 ±260 0.02 ±260 ±200 ±80
3.9 3.8 1.0 1.1 ±200
min min max max min typ min min min
A A A A A C A A A
±200 ±160 ±50
±180 ±140 ±45
±160 ±120 ±40
(1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current considered positive out of node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR at min/max input ranges.
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OPA2674
SBOS270 − AUGUST 2003
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ELECTRICAL CHARACTERISTICS: VS = +5V(continued)
Boldface limits are tested at +25°C.
At TA = +25°C, A1 = 1, A0 = 1 (Full Power: for SO-14 only), G = +4, RF = 453Ω, and RL = 100Ω, unless otherwise noted. See Figure 3 for AC performance only.
OPA2674ID, OPA2674I-14D TYP PARAMETER Power Supply (Single−Supply Mode) Specified Operating Voltage Maximum Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (PSRR) Power Control (SO-14 Only) Maximum Logic 0 Minimum Logic 1 Logic Input Current Supply Current at Full Power Supply Current at Power Cutback Supply Current at Idle Power Supply Current at Shutdown Output Impedance in Idle Power Output Impedance in Shutdown Supply Current Step Time Output Switching Glitch Shutdown Isolation Thermal Characteristics Specification: ID, I-14D Thermal Resistance, qJA ID SO-8 I-14D SO-14 Junction-to-Ambient −40 to +85 125 100 °C °C/W °C/W typ typ C C 10% to 90% Change Inputs at GND G = +4, 1MHz, A1 = 0, A0 = 0 A1, A0, +VS = +5V A1, A0, +VS = +5V A1 = 0V, A0 = 0V, Each Line A1 = 1, A0 = 1 (logic levels) A1 = 1, A0 = 0 (logic levels) A1 = 1, A0 = 1 (logic levels) A1 = 0, A0 = 0 (logic levels) G = +4, f = 1MHz 100 4 200 ±20 85 1.5 2.4 50 13.8 10.2 3.0 0.6 1.0 2.7 80 14.8 10.8 3.2 0.9 0.9 3.1 90 15.2 11.1 3.5 1.0 0.8 3.3 95 15.6 11.4 3.8 1.1 V V µA mA mA mA mA Ω kΩ pF ns mV dB max min max max max max max typ typ typ typ typ A A A A A A A C C C C C +5 VS = +5V VS = +5V f = 100kHz, Input Referred 13.6 13.6 52 12.6 14.8 12 12.6 15.2 11.7 12.6 15.6 11.4 V V mA mA dB typ max max min typ C A A A C TEST CONDITIONS +25°C +25°C(1) MIN/MAX OVER TEMPERATURE 0°C to +70°C(2) −40°C to +85°C(2) UNITS MIN/ MAX TEST LEVEL (3)
(1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current considered positive out of node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR at min/max input ranges.
6
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OPA2674
SBOS270 − AUGUST 2003
TYPICAL CHARACTERISTICS: VS = ±6V
At TA = +25°C, G = +4, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
NONINVERTING SMALL− SIGNAL FREQUENCY RESPONSE OVER GAIN 3 VO = 0.5VPP 0 Normalized Gain (dB) −3 −6 −9 − 12 See Figure 1 − 15 0 100 200 G = +4, RF = 402Ω 300 400 500 G = +1, RF = 511Ω G = +2, RF = 475Ω Normalized Gain (dB) G = +8, RF = 250Ω 0 −3 3
INVERTING SMALL− SIGNAL FREQUENCY RESPONSE OVER GAIN VO = 0.5VPP
G = − 1, RF = 475Ω −6 −9 − 12 See Figure 2 − 15 0 100 200 300 400 500 Frequency (MHz) G = − 8, RF = 402Ω G = − 2, RF = 422Ω G = − 4, RF = 402Ω
Frequency (MHz)
NONINVERTING SMALL− SIGNAL FREQUENCY RESPONSE OVER POWER SETTINGS 15 12 9 Gain (dB) 6 Full Power 3 0 −3 −6 0 See Figure 1 100 Idle Power −6 200 300 400 500 0 Power Cutback Gain (dB) G = +4 VO = 0.5VPP 15 12 9 6
INVERTING SMALL− SIGNAL FREQUENCY RESPONSE OVER POWER SETTINGS G = −4 VO = 0.5VPP
Full Power 3 0 −3 See Figure 2 100 Idle Power 200 300 400 500
Power Cutback
Frequency (MHz)
Frequency (MHz)
NONINVERTING LARGE− SIGNAL FREQUENCY RESPONSE 15 G = +4 12 9 Gain (dB) 6 3 VO = 10VPP 0 −3 −6 0 See Figure 1 100 200 300 400 500 VO = 8VPP VO = 2VPP VO ≤ 1VPP 12 9 Gain (dB) 6 3 0 −3 −6 0 Frequency (MHz) See Figure 2 100 15
INVERTING LARGE− SIGNAL FREQUENCY RESPONSE VO ≤ 1VPP G = −4
VO = 5VPP VO = 10VPP VO = 8VPP
200
300
400
500
Frequency (MHz)
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OPA2674
SBOS270 − AUGUST 2003
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TYPICAL CHARACTERISTICS: VS = ±6V (continued)
At TA = +25°C, G = +4, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
NONINVERTING PULSE RESPONSE G = +4 RL = 100Ω 4VPP Large Signal 200mVPP Small Signal Right Scale
NONINVERTING PULSE RESPONSE G = +4 RL = 100Ω 4VPP Large Signal 200mVPP Small Signal Right Scale
Output Voltage (100mV/div)
See Figure 1 Time (5ns/div)
See Figure 1 Time (5ns/div)
− 60 − 65 Harmonic Distortion (dBc) − 70 − 75 − 80 − 85 − 90 − 95 − 100 − 105 0.1
HARMONIC DISTORTION vs FREQUENCY G = +4 VO = 2VPP RL = 100Ω
− 50 − 60 − 70 − 80
HARMONIC DISTORTION vs OUTPUT VOLTAGE f = 5MHz RL = 100Ω 2nd− Harmonic
Harmonic Distortion (dBc)
2nd− Harmonic
3rd− Harmonic − 90 Single Channel, See Figure 1 − 100
3rd− Harmonic Single Channel, See Figure 1 1 Frequency (MHz) 10 20
0.1
1 Output Voltage (VPP)
10
− 60 − 65 − 70 − 75 − 80
HARMONIC DISTORTION vs NONINVERTING GAIN VO = 2VPP f = 5MHz RL = 100Ω
− 60 − 65 − 70 − 75 − 80 − 85
HARMONIC DISTORTION vs INVERTING GAIN VO = 2VPP f = 5MHz RL = 100Ω
Harmonic Distortion (dBc)
2nd− Harmonic
Harmonic Distortion (dBc)
2nd− Harmonic
3rd− Harmonic
3rd− Harmonic − 85 Single Channel, See Figure 1 − 90 1 Gain Magnitude (V/V) 10
Single Channel, See Figure 2 − 90 1 Gain Magnitude (− V/V) 10
8
Output Voltage (100mV/div)
Left Scale Output Voltage (1V/div)
Left Scale Output Voltage (1V/div)
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OPA2674
SBOS270 − AUGUST 2003
TYPICAL CHARACTERISTICS: VS = ±6V (continued)
At TA = +25°C, G = +4, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE − 50 − 55 Harmonic Distortion (dBc) − 60 − 65 − 70 − 75 − 80 − 85 − 90 − 95 − 100 Single Channel, See Figure 1 10 100 Load Resistance (Ω) 1k 3rd− Harmonic 2nd− Harmonic VO = 2VPP f = 5MHz − 60 3rd− Order Spurious Level (dBc) − 65 − 70 − 75 − 80 − 85 − 90 − 95
2− TONE, 3rd− ORDER SPURIOUS LEVEL dBc = dB Below Carriers 20MHz 10MHz
5MHz
1MHz
Power at Matched 50Ω Load, See Figure 1 − 100 − 10 −5 0 5 Single− Tone Load Power (dBm)
10
MAXIMUM OUTPUT SWING vs LOAD RESISTANCE 6 5 4 Output Voltage (V) 3 2 VO (V) 1 0 −1 −2 −3 −4 −5 −6 10 100 Load Resistance (Ω) 1k 6 5 4 3 2 1 0 −1 −2 −3 −4 −5 −6 − 600
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
R L = 100 Ω R L = 50 Ω R L = 10Ω 1 W In terna l P ower S ingle Cha nnel R L = 25 Ω
1 W In ternal P ower Single Ch ann el
− 400
− 200
0 IO (mA)
200
400
600
INPUT VOLTAGE AND CURRENT NOISE DENSITY 100 Inverting Current N oise Voltage Noise (nV/√ Hz) Current Noise (pA/√ Hz) 24pA/ √ Hz Noninverting Current Noise 16pA/ √ H z Crosstalk, Input Referred (dB)
− 60 − 65 − 70 − 75 − 80 − 85 − 90 − 95 − 100 − 105 − 110 10M
CHANNEL− CHANNEL CROSSTALK TO− Input Referred
10
Voltage Noise 1 100 1k 10k 100k
2.0nV/ √ Hz 1M
1M
10M Frequency (Hz)
100M
Frequency (Hz)
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OPA2674
SBOS270 − AUGUST 2003
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TYPICAL CHARACTERISTICS: VS = ±6V (continued)
At TA = +25°C, G = +4, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
RECOMMENDED RS vs CAPACITIVE LOAD 90 Normalized Gain to Capacitive Load (dB) 80 70 60 RS (Ω) 50 40 30 20 10 0 1 10 100 1k Capacitive Load (pF)
FREQUENCY RESPONSE vs CAPACITIVE LOAD 2 CL = 10pF 0 −2 −4 −6 −8 − 10 1M 10M 100M 1G Frequency (Hz)
RS
CL = 100pF
CL = 22pF
1/2 OPA2674
CL = 47pF
1kΩ(1)
402Ω 133Ω
CL
NOTE: (1) 1kΩ is optional.
CMRR AND PSRR vs FREQUENCY 70 Power− Supply Rejection Ratio (dB) Common− Mode Rejection Ratio (dB) CMRR Transimpedance Gain (dBΩ) 60 50 40 30 +PSRR 20 10 0 1k 10k 100k 1M 10M 100M Frequency (Hz) − PSRR 100 80 60 40 20 0 10k 120
OPEN− LOOP TRANSIMPEDANCE GAIN AND PHASE 0 Gain Phase Transimpedance Phase (_ ) − 45 − 90 − 135 − 180 − 225 − 270 100k 1M 10M 100M 1G Frequency (Hz)
CLOSED− LOOP OUTPUT IMPEDANCE vs FREQUENCY 100 0.10 0.09 Output Resistance (Ω) 10 dG/dP (%/_ ) 0.08 0.07 1 Idle Power 0.06 0.05 0.04 0.03 0.01 Full Power Power Cutback 0.001 100k 1M 10M Frequency (Hz) 100M 0.02 0.01 0 1 2 3 G = +2 R F = 475Ω VS = ± 5V
COMPOSITE VIDEO dG/dP dP, Positive Video dP, Negative Video
dG , Negative Video
0.1
dG, Positive Video
4
5
6
7
8
9
10
Number of 150Ω Loads
10
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OPA2674
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TYPICAL CHARACTERISTICS: VS = ±6V (continued)
At TA = +25°C, G = +4, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
NONINVERTING OVERDRIVE RECOVERY 16 Input 12 Output Voltage (V) 8 4 0 −4 −8 − 12 − 16 G = +4 R L = 100Ω See Figure 1 Time (25ns/div) TYPICAL DC DRIFT OVER TEMPERATURE 14 12 10 8 6 4 2 0 −2 −4 −6 −8 −10 −12 −14 − 50 Inverting Bias Current Noninverting Bias Current Output Current (mA) 750 700 650 600 550 500 450 400 350 300 250 − 25 0 25 50 75 100 125 − 50 Output 3 Output Voltage (V) 2 Input Voltage (V) 1 0 −1 −2 −3 −4 12 8 4 0 −4 −8 − 12 − 16 4 16
INVERTING OVERDRIVE RECOVERY Input G = −4 R L = 100Ω 4 3 2 1 0 −1 Output See Figure 2 Time (25ns/div) SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 18 16 Supply Current, Power Cutback 14 12 Sinking Output Current Sourcing Output Current 10 8 6 4 Supply Current, Idle Power 2 0 − 25 0 25 50 75 100 125 Temperature (_ C) Supply Current, Both Channels (mA) Supply Current, Full Power 20 −2 −3 −4 Input Voltage (V)
Input Offset Voltage (mV) Input Bias Current (µA)
Input Offset Voltage
Ambient Temperature (_ C) COMMON− MODE INPUT VOLTAGE RANGE AND OUTPUT SWING vs SUPPLY VOLTAGE 6 5 Voltage Range (± V) 4 Negative Output Swing 3 2
Positive Output Swing
Negative Common− Mode Input Voltage 1 Positive Common− Mode Input Voltage 0 2 3 4 Supply Voltage (± V) 5 6
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TYPICAL CHARACTERISTICS: VS = ±6V
At TA = +25°C, Differential Gain = +9, RF = 300Ω, and RL = 70Ω, unless otherwise noted. See Figure 5 for AC performance only.
DIFFERENTIAL SMALL− SIGNAL FREQUENCY RESPONSE 3 0 Normalized Gain (dB) −3 −6 −9 − 12 − 15 0 See Figure 5 1 50 100 150 200 250 300 0 Frequency (MHz) RL = 70Ω VO = 1VPP Gain (dB) 22
DIFFERENTIAL LARGE− SIGNAL FREQUENCY RESPONSE 1VPP 19 16 13 16VPP 10 7 4 See Figure 5 50 100 150 200 250 300 RL = 70Ω GD = +9 4VPP 8VPP
GD = +2, RF = 442Ω
GD = +5, RF = 383Ω
GD = +9, RF = 300Ω
Frequency (MHz)
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE − 60 − 65 Harmonic Distortion (dB) − 70 − 75 − 80 − 85 − 90 − 95 − 100 − 105 − 110 3rd− Harmonic 2nd− Harmonic f = 500kHz G = +9 RL = 70Ω VO = 4VPP
− 50 − 65 − 70
DIFFERENTIAL DISTORTION vs FREQUENCY G = +9 RL = 70Ω
Harmonic Distortion (dB)
2nd− Harmonic − 80 − 90 − 100 − 110 See Figure 5 0.1 1 Frequency (MHz) 10 100 3rd− Harmonic
See Figure 5 10 100 Load Resistance (Ω) 1k
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE − 60 − 70 − 80 − 90 3rd− Harmonic −100 See Figure 5 −110 0.1 1 Differential Output Voltage (VPP) 10 20 f = 500kHz G = +9 RL = 70Ω Power (dBm) 2nd− Harmonic 0 − 10 − 20 − 30 − 40 − 50 − 60 − 70 − 80 − 90 − 100
ADSL MULTITONE POWER RATIO (Upstream) VS = ± 6V
Harmonic Distortion (dBc)
See Figure 5 0 20 40 60 80 100 120 140 160
Frequency (kHz)
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OPA2674
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TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, G = +4, RF = 453Ω, and RL = 100Ω, unless otherwise noted.
NONINVERTING SMALL− SIGNAL FREQUENCY RESPONSE 3 0 Normalized Gain (dB) −3 −6 −9 − 12 − 15 − 18 0 See Figure 3 100 G = +8 RF = 332Ω G = +4 RF = 453Ω 200 300 400 500 Normalized Gain (dB) G = +1 RF = 549Ω G = +2 RF = 511Ω 3 0 −3 −6 −9 − 12 − 15 − 18 0 See Figure 4 100
INVERTING SMALL− SIGNAL FREQUENCY RESPONSE
G = −2 RF = 511Ω
G = −8 RF = 402Ω
G = −1 RF = 549Ω
G = −4 R F = 453Ω
200
300
400
500
Frequency (MHz)
Frequency (MHz)
NONINVERTING LARGE− SIGNAL FREQUENCY RESPONSE 15 12 9 Gain (dB) Gain (dB) 6 VO = 3VPP 3 0 −3 −6 0 See Figure 3 100 200 300 400 500 VO = 1VPP VO = 2VPP G = +4 RL = 100Ω to VS/2 15 12 9 6 3
INVERTING LARGE− SIGNAL FREQUENCY RESPONSE G = −4 RL = 100Ω to VS/2
VO = 3VPP VO = 2VPP
0 −3 −6 0 See Figure 4 100
VO = 1VPP
200
300
400
500
Frequency (MHz)
Frequency (MHz)
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
Left Scale Input Voltage (100mV/div) Output Voltage (0.5V/div) Output Voltage (0.5V/div) 2VPP Large Signal Right Scale 200mVPP Small Signal
Left Scale Input Voltage (100mV/div) 2VPP Large Signal Right Scale 200mVPP Small Signal
G = +4 RL = 100Ω to VS/2 Time (5ns/div)
See Figure 3
G = −4 RL = 100Ω to VS/2 Time (5ns/div)
See Figure 4
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TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, G = +4, RF = 453Ω, and RL = 100Ω, unless otherwise noted.
− 50 − 55 Harmonic Distortion (dBc) − 60 − 65 − 70 − 75 − 80 − 85 − 90
HARMONIC DISTORTION vs FREQUENCY VO = 2VPP G = +4 RL = 100Ω to VS/2 2nd− Harmonic
− 60 − 65 − 70
HARMONIC DISTORTION vs OUTPUT VOLTAGE f = 5MHz RL = 100Ω to VS/2
Harmonic Distortion (dBc)
2nd− Harmonic − 75 3rd− Harmonic − 80 − 85 Single Channel, See Figure 3 − 90 0.1 1 Output Voltage (VPP) 5
3rd− Harmonic Single Channel, See Figure 3 0.1 1 Frequency (MHz) 10 20
− 55 − 60 − 65 − 70 − 75 − 80
HARMONIC DISTORTION vs NONINVERTING GAIN VO = 2VPP f = 5MHz R L = 100Ω to VS/2
− 55 − 60 − 65 − 70 − 75 − 80
HARMONIC DISTORTION vs INVERTING GAIN VO = 2VPP f = 5MHz RL = 100Ω to VS/2 2nd− Harmonic
Harmonic Distortion (dBc)
2nd− Harmonic
Harmonic Distortion (dBc)
3rd− Harmonic
3rd− Harmonic
Single Channel, See Figure 3 − 85 1 Gain Magnitude (V/V) 10
Single Channel, See Figure 4 − 85 1 Gain (− V/V) 10
− 40 − 45 Harmonic Distortion (dBc) − 50 − 55 − 60 − 65 − 70 − 75 − 80 − 85 − 90
HARMONIC DISTORTION vs LOAD RESISTANCE VO = 2VPP f = 5MHz RL = 100Ω to VS/2
2− TONE, 3rd− ORDER SPURIOUS LEVEL − 55 3rd− Order Spurious Level (dBc) − 60 − 65 − 70 − 75 − 80 − 85 − 90 Single Channel. See Figure 3. Power at matched 50Ω load. − 12 − 10 −8 −6 −4 10MHz 5MHz 20MHz
2nd− Harmonic
3rd− Harmonic
1MHz
Single Channel, See Figure 3 10 100 Load Resistance (Ω) 1k
− 95 − 14
−2
0
2
Single− Tone Load Power (dBm)
14
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OPA2674
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TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, Differential Gain = +9, RF = 316Ω, and RL = 70Ω, unless otherwise noted.
DIFFERENTIAL PERFORMANCE TEST CIRCUIT
DIFFERENTIAL SMALL− SIGNAL FREQUENCY RESPONSE 3 R L = 70Ω 0 Normalized Gain (dB) −3 −6 −9 −12 −15
+V 5
RF 316Ω VI RG RL VO
RF CG 316Ω
GD = +9 RF = 316Ω GD = +2 RF = 511Ω G D = +5 R F = 422Ω 0 50 100 150 200 250 300
FO GD=1+ 2×R = V VI R G
Frequency (MHz)
DIFFERENTIAL LARGE− SIGNAL FREQUENCY RESPONSE 22 19 Harmonic Distortion (dBc) 16 Gain (dB) 13 10 7 4 1 0 50 100 150 200 250 300 Frequency (MHz) RL = 70Ω GD = +9 1VPP 2VPP 4VPP 5VPP
− 60 − 65 − 70 − 75 − 80 − 85 − 90 − 95 − 100 10
HARMONIC DISTORTION vs LOAD RESISTANCE GD = +9 RL = 70Ω f = 500kHz VO = 4VPP
2nd− Harmonic
3rd− Harmonic
100 Load Resistance (Ω)
1k
DIFFERENTIAL DISTORTION vs FREQUENCY − 50 − 60 − 70 − 80 3rd− Harmonic − 90 − 100 0.1 1 Frequency (MHz) 10 100 GD = +9 R L = 70Ω Harmonic Distortion (dB)
− 60
HARMONIC DISTORTION vs OUTPUT VOLTAGE GD = +9 RL = 70Ω f = 500kHz
Harmonic Distortion (dBc)
− 70
2nd− Harmonic
2nd− Harmonic − 80
− 90 3rd− Harmonic − 100 1 Output Voltage (VPP) 10
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APPLICATION INFORMATION
WIDEBAND CURRENT-FEEDBACK OPERATION
The OPA2674 gives the exceptional AC performance of a wideband current-feedback op amp with a highly linear, high-power output stage. Requiring only 9mA/ch quiescent current, the OPA2674 swings to within 1V of either supply rail and delivers in excess of 380mA at room temperature. This low output headroom requirement, along with supply voltage independent biasing, gives remarkable single (+5V) supply operation. The OPA2674 delivers greater than 150MHz bandwidth driving a 2VPP output into 100Ω on a single +5V supply. Previous boosted output stage amplifiers typically suffer from very poor crossover distortion as the output current goes through zero. The OPA2674 achieves a comparable power gain with much better linearity. The primary advantage of a current-feedback op amp over a voltage-feedback op amp is that AC performance (bandwidth and distortion) is relatively independent of signal gain. Figure 1 shows the DC-coupled, gain of +4, dual power-supply circuit configuration used as the basis of the ±6V Electrical and Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the electrical characteristics are taken directly at the input and output pins whereas load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 1, the total effective load is 100Ω || 535Ω = 84Ω.
Figure 2 shows the DC-coupled, bipolar supply circuit inverting gain configuration used as the basis for the ±6V Electrical and Typical Characteristics. Key design considerations of the inverting configuration are developed in the Inverting Amplifier Operation discussion.
+6V
Power− supply decoupling not shown. VO 50Ω
50Ω Load
1/2 OPA2674
50Ω Source VI
RG 100Ω RM 100Ω
− 6V
RF 402Ω
Figure 2. DC-Coupled, G = −4, Bipolar Supply, Specification and Test Circuit
Figure 3 shows the AC coupled, gain of +4, single-supply circuit configuration used as the basis of the +5V Electrical and Typical Characteristics. Though not a rail-to-rail design, the OPA2674 requires minimal input and output voltage headroom compared to other wideband current-feedback op amps. It will deliver a 3VPP output swing on a single +5V supply with greater than 100MHz bandwidth. The key requirement of broadband singlesupply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 3 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 806Ω resistors). The input signal is then AC-coupled into this midpoint voltage bias. The input voltage can swing to within 1.3V of either supply pin, giving a 2.4VPP input signal range centered between the supply pins. The input impedance matching resistor (57.6Ω) used for testing is adjusted to give a 50Ω input match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1which puts the input DC bias voltage (2.5V) on the output as well. The feedback resistor value is adjusted from the bipolar supply condition to re-optimize for a flat frequency response in +5V, gain of +4, operation. Again, on a single +5V supply, the output voltage can swing to within 1V of either supply pin while delivering more than 200mA output current. A demanding 100Ω load to a midpoint bias is used in this characterization circuit. The new output stage used in the OPA2674 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown by the +5V supply, harmonic distortion plots in the Typical Characteristics charts.
0.1µ F
+6V +VS
6.8µF +
50Ω Source VI 50Ω 50Ω Load
50Ω
1/2 OPA2674
VO
RF 402Ω RG 133Ω 6.8µ F − VS − 6V + 0.1µ F
Figure 1. DC-Coupled, G = +4, Bipolar Supply, Specification and Test Circuit
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OPA2674
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+5V +VS
reduction of even-order harmonic distortion products. Another important advantage for ADSL is that each amplifier needs only half of the total output swing required to drive the load.
0.1µ F + 6.8µF 20Ω VO 100Ω VS/2 0.1µF
1/2 OP A2674
806Ω 0.1µF VI 57.6Ω 806Ω 1/2 OPA2674 RF 453Ω
+12V
IP = 128mA 17.4Ω RM
RF 324Ω 2kΩ 2kΩ RG 82.5Ω 1µF RF 324Ω
1:1.7
RG 150Ω 0.1µF
AFE 2VPP Max Assumed
+6V 0.1µF
17.7VPP 17.4Ω RM
ZLine 100Ω
IP = 128mA 20Ω
1/2 OP A2674
Figure 3. AC-Coupled, G = +4, Single-Supply, Specification and Test Circuit Figure 5. Single-Supply ADSL Upstream Driver
The last configuration used as the basis of the +5V Electrical and Typical Characteristics is shown in Figure 4. Design considerations for this inverting, bipolar supply configuration are covered either in single-supply configuration (as shown in Figure 3) or in the Inverting Amplifier Operation discussion.
+5V +
The analog front-end (AFE) signal is AC-coupled to the driver and the noninverting input of each amplifier is biased to the mid-supply voltage (in this case, +6V). Furthermore, by providing the proper biasing to the amplifier, this scheme also provides high-pass filtering with a corner frequency set here at 5kHz. As the upstream signal bandwidth starts at 26kHz, this high-pass filter does not generate any problems and has the advantage of filtering out unwanted lower frequencies. The input signal is amplified with a gain set by the following equation:
806Ω
0.1µ F VO
6.8µF
806Ω
1/2 OPA2674 RF 453Ω
100Ω VS/2
GD + 1 )
2
RF RG
(1)
RG 0.1µF 113Ω VI RM 88.7Ω
With RF = 324Ω and RG = 82.5Ω, the gain for this differential amplifier is 8.85. This gain boosts the AFE signal, assumed to be a maximum of 2VPP, to a maximum of 17.7VPP. Refer to the Setting Resistor Values to Optimize Bandwidth section for a discussion on which feedback resistor value to choose. The two back-termination resistors (17.4Ω each) added at each input of the transformer make the impedance of the modem match the impedance of the phone line, and also provide a means of detecting the received signal for the receiver. The value of these resistors (RM) is a function of the line impedance and the transformer turns ratio (n), given by the following equation:
Figure 4. AC-Coupled, G = −4, Single-Supply, Specification and Test Circuit
SINGLE-SUPPLY ADSL UPSTREAM DRIVER
Figure 5 shows a single-supply ADSL upstream driver. The dual OPA2674 is configured as a differential gain stage to provide signal drive to the primary of the transformer (here, a step-up transformer with a turns ratio of 1:1.7). The main advantage of this configuration is the
RM +
Z LINE 2n2
(2)
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OPA2674 HDSL2 UPSTREAM DRIVER
Figure 6 shows an HDSL2 implementation of a singlesupply driver.
Consolidating Equations 3 through 6 allows the required peak-to-peak voltage at the load function of the crest factor, the load impedance, and the power in the load to be expressed. Thus:
+12V 20Ω
1/2 OPA2674
V LPP + 2
CF
(1mW)
RL
10 10 (7)
PL
This VLPP is usually computed for a nominal line impedance and may be taken as a fixed design target.
IP = 185mA 11.5Ω 1:2.4
0.1µF AFE 2VPP Max Assumed 2kΩ 2kΩ
324Ω
+6V 0.1µF
82.5Ω 1µF 324Ω
17.7VPP 11.5Ω
ZLine 135Ω
The next step for the driver is to compute the individual amplifier output voltage and currents as a function of VPP on the line and transformer turns ratio. As the turns ratio changes, the minimum allowed supply voltage also changes. The peak current in the amplifier is given by:
" IP + 1 2
2
V LPP n
1 4R M
(8)
IP = 185mA 20Ω
1/2 OPA2674
With VLPP defined in Equation 7 and RM defined in Equation 2. The peak current is computed in Figure 7 by noting that the total load is 4RM and that the peak current is half of the peak-to-peak calculated using VLPP.
Figure 6. HDSL2 Upstream Driver
The two designs differ by the values of the matching impedance, the load impedance, and the ratio turns of the transformers. All of these differences are reflected in the higher peak current and thus, the higher maximum power dissipation in the output of the driver.
± IP RM 1:n 2VLPP n VLPP n RM ± IP
RL
VLPP
LINE DRIVER HEADROOM MODEL
The first step in a driver design is to compute the peak-to-peak output voltage from the target specifications. This is done using the following equations:
Figure 7. Driver Peak Output Model
With the required output voltage and current versus turns ratio set, an output stage headroom model will allow the required supply voltage versus turns ratio to be developed. The headroom model (see Figure 8) can be described with the following set of equations: First, as available output voltage for each amplifier:
P L + 10
VRMS log (1mW) RL
2
(3)
With PL power and VRMS voltage at the load, and RL load impedance, this gives:
V RMS +
(1mW)
RL
10 10
PL
(4) V RMS (5)
V P + CrestFactor
V RMS + CF
V OPP + VCC * (V1 ) V2) * I P
(R 1 ) R 2) (9) (R 1 ) R 2) (10)
Or, second, as required single-supply voltage:
with VP peak voltage at the load and CF Crest Factor;
V LPP + 2
V CC + VOPP ) (V1 ) V2) ) I P
CF
VRMS
(6)
with VLPP: peak-to-peak voltage at the load.
The minimum supply voltage for a power and load requirement is given by Equation 10.
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OPA2674
SBOS270 − AUGUST 2003 +VCC
R1 V1
VO IP
V2 R2
The two output stages used to drive the load of Figure 7 can be seen as an H-Bridge in Figure 9. The average current drawn from the supply into this H-Bridge and load will be the peak current in the load given by Equation 8 divided by the crest factor (CF) for the xDSL modulation. This total power from the supply is then reduced by the power in RT to leave the power dissipated internal to the drivers in the four output stage transistors. That power is simply the target line power used in Equation 2 plus the power lost in the matching elements (RM). In the examples here, a perfect match is targeted giving the same power in the matching elements as in the load. The output stage power is then set by Equation 11.
P OUT +
IP CF
VCC * 2PL
(11)
The total amplifier power is then:
Figure 8. Line Driver Headroom Model
Table 1 gives V1, V2, R1, and R2 for both +12V and +5V operation of the OPA2674.
P TOT + I q
VCC )
IP CF
V CC * 2P L
(12)
Table 1. Line Driver Headroom Model Values
V1 +5V +12V 0.9V 0.9V R1 5Ω 2Ω V2 0.8V 0.9V R2 5Ω 2Ω
For the ADSL CPE upstream driver design of Figure 5, the peak current is 128mA for a signal that requires a crest factor of 5.33 with a target line power of 13dBm into 100Ω (20mW). With a typical quiescent current of 18mA and a nominal supply voltage of +12V, the total internal power dissipation for the solution of Figure 5 will be:
(13)
PTOT + 18mA(12V) ) 128mA (12V) * 2(20mW) + 464mW 5.33
TOTAL DRIVER POWER FOR xDSL APPLICATIONS
The total internal power dissipation for the OPA2674 in an xDSL line driver application will be the sum of the quiescent power and the output stage power. The OPA2674 holds a relatively constant quiescent current versus supply voltage—giving a power contribution that is simply the quiescent current times the supply voltage used (the supply voltage will be greater than the solution given in Equation 10). The total output stage power may be computed with reference to Figure 9.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Several PC boards are available to assist in the initial evaluation of circuit performance using the OPA2674 in the two package styles. These are available, free, as unpopulated PC boards delivered with descriptive documentation. Table 2 shows the summary information for these boards.
Table 2. Demo Board Availability
PRODUCT PACKAGE SO-8 SO-14 DEMO BOARD NUMBER DEM-OPA268XU DEM-OPA268XN ORDERING NUMBER SBOU003 SBOU002
+VCC IAVG =
IP CF
OPA2674ID OPA2674I-14D
RT
Go to the TI web site (www.ti.com) to request either of these boards.
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and
19
Figure 9. Output Stage Power Model
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inductance can have a major effect on circuit performance. A SPICE model for the OPA2674 is available through the TI web site (www.ti.com). This model does a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions, but does not do as well in predicting the harmonic distortion or dG/dP characteristics. This model does not attempt to distinguish between the package types in small-signal AC performance, nor does it attempt to simulate channel-tochannel coupling.
IERR = feedback error current signal Z(s) = frequency dependent open-loop transimpedance gain from IERR to VO NG + NoiseGain + 1 ) RF RG
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH
A current-feedback op amp such as the OPA2674 can hold an almost constant bandwidth over signal gain settings with the proper adjustment of the external resistor values, which are shown in the Typical Characteristics; the small-signal bandwidth decreases only slightly with increasing gain. These characteristic curves also show that the feedback resistor is changed for each gain setting. The resistor values on the inverting side of the circuit for a current-feedback op amp can be treated as frequency response compensation elements, whereas the ratios set the signal gain. Figure 10 shows the small-signal frequency response analysis circuit for the OPA2674.
The buffer gain is typically very close to 1.00 and is normally neglected from signal gain considerations. This gain, however, sets the CMRR for a single op amp differential amplifier configuration. For a buffer gain of α < 1.0, the CMRR = −20 • log(1 − α)dB. RI, the buffer output impedance, is a critical portion of the bandwidth control equation. The OPA2674 inverting output impedance is typically 22Ω. A current-feedback op amp senses an error current in the inverting node (as opposed to a differential input error voltage for a voltage-feedback op amp) and passes this on to the output through an internal frequency dependent transimpedance gain. The Typical Characteristics show this open-loop transimpedance response, which is analogous to the open-loop voltage gain curve for a voltage-feedback op amp. Developing the transfer function for the circuit of Figure 10 gives Equation 14:
VO + VI
a 1 ) RF 1)
R
G RF G
+
a 1)
NG
R F)R I Z(s) NG
R )R 1) F I R Z(s)
(14)
VI α VO RI Z(S) IERR
IERR
This is written in a loop-gain analysis format, where the errors arising from a non-infinite open-loop gain are shown in the denominator. If Z(s) were infinite over all frequencies, the denominator of Equation 14 reduces to 1 and the ideal desired signal gain shown in the numerator is achieved. The fraction in the denominator of Equation 14 determines the frequency response. Equation 15 shows this as the loop-gain equation:
RF
Z(s) + LoopGain R F ) R I NG
(15)
RG
Figure 10. Current-Feedback Transfer Function Analysis Circuit
The key elements of this current-feedback op amp model are:
α = buffer gain from the noninverting input to the inverting input RI = buffer output impedance
20
If 20 log(RF + NG × RI) is drawn on top of the open-loop transimpedance plot, the difference between the two would be the loop gain at a given frequency. Eventually, Z(s) rolls off to equal the denominator of Equation 15, at which point the loop gain has reduced to 1 (and the curves have intersected). This point of equality is where the amplifier closed-loop frequency response given by Equation 14 starts to roll off, and is exactly analogous to the frequency at which the noise gain equals the open-loop voltage gain for a voltage-feedback op amp. The difference here is that the total impedance in the denominator of Equation 15 may be controlled somewhat separately from the desired signal gain (or NG). The OPA2674 is internally compensated to give a maximally flat frequency response for RF = 402Ω at NG = 4 on ±6V
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OPA2674
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supplies. Evaluating the denominator of Equation 15 (which is the feedback transimpedance) gives an optimal target of 490Ω. As the signal gain changes, the contribution of the NG × RI term in the feedback transimpedance changes, but the total can be held constant by adjusting RF. Equation 16 gives an approximate equation for optimum RF over signal gain:
INVERTING AMPLIFIER OPERATION
As the OPA2674 is a general-purpose, wideband current-feedback op amp, most of the familiar op amp application circuits are available to the designer. Those dual op amp applications that require considerable flexibility in the feedback element (for example, integrators, transimpedance, and some filters) should consider a unity-gain stable, voltage-feedback amplifier such as the OPA2822, because the feedback resistor is the compensation element for a current-feedback op amp. Wideband inverting operation (and especially summing) is particularly suited to the OPA2674. Figure 12 shows a typical inverting configuration where the I/O impedances and signal gain from Figure 1 are retained in an inverting circuit configuration.
+6V Power− supply decoupling not shown. 50Ω Load
1 /2
R F + 490 * NG
RI
(16)
As the desired signal gain increases, this equation eventually suggests a negative RF. A somewhat subjective limit to this adjustment can also be set by holding RG to a minimum value of 20Ω. Lower values load both the buffer stage at the input and the output stage if RF gets too lowactually decreasing the bandwidth. Figure 11 shows the recommended RF versus NG for both ±6V and a single +5V operation. The values for RF versus gain shown here are approximately equal to the values used to generate the Typical Characteristics. They differ in that the optimized values used in the Typical Characteristics are also correcting for board parasitic not considered in the simplified analysis leading to Equation 16. The values shown in Figure 11 give a good starting point for designs where bandwidth optimization is desired.
600
VO
50Ω
50Ω Source VI
O PA 267 4
RG 97.6 Ω RM 102Ω − 6V
RF 392Ω
Feedback Resistor (Ω)
500
400
+5V
Figure 12. Inverting Gain of −4 with Impedance Matching
RG = 20Ω
300
± 6V
200 0 5 10 15 20 25 Noise Gain
Figure 11. Feedback Resistor vs Noise Gain
The total impedance going into the inverting input may be used to adjust the closed-loop signal bandwidth. Inserting a series resistor between the inverting input and the summing junction increases the feedback impedance (the denominator of Equation 15), decreasing the bandwidth. The internal buffer output impedance for the OPA2674 is slightly influenced by the source impedance coming from of the noninverting input terminal. High-source resistors also have the effect of increasing RI, decreasing the bandwidth. For those single-supply applications that develop a midpoint bias at the noninverting input through high valued resistors, the decoupling capacitor is essential for power-supply ripple rejection, noninverting input noise current shunting, and to minimize the high-frequency value for RI in Figure 10.
In the inverting configuration, two key design considerations must be noted. First, the gain resistor (RG) becomes part of the signal source input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PC board trace, or other transmission line conductor), it is normally necessary to add an additional matching resistor to ground. RG, by itself, normally is not set to the required input impedance since its value, along with the desired gain, will determine an RF, which may be nonoptimal from a frequency response standpoint. The total input impedance for the source becomes the parallel combination of RG and RM. The second major consideration is that the signal source impedance becomes part of the noise gain equation and has a slight effect on the bandwidth through Equation 15. The values shown in Figure 12 have accounted for this by slightly decreasing RF (from the optimum values) to reoptimize the bandwidth for the noise gain of Figure 12 (NG = 3.98). In the example of Figure 12, the RM value combines in parallel with the external 50Ω source impedance, yielding an effective driving impedance of 50Ω || 102Ω = 33.5Ω. This impedance is added in series
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with RG for calculating the noise gainwhich gives NG = 3.98. This value, and the inverting input impedance of 22Ω, are inserted into Equation 16 to get the RF that appears in Figure 12. Note that the noninverting input in this bipolar supply inverting application is connected directly to ground. It is often suggested that an additional resistor be connected to ground on the noninverting input to achieve bias current error cancellation at the output. The input bias currents for a current-feedback op amp are not generally matched in either magnitude or polarity. Connecting a resistor to ground on the noninverting input of the OPA2674 in the circuit of Figure 12 actually provides additional gain for that input bias and noise currents, but does not decrease the output DC error because the input bias currents are not matched.
specifications since the output stage junction temperatures will be higher than the minimum specified operating ambient.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an analog-to-digital (A/D) converterincluding additional external capacitance that may be recommended to improve the A/D converter linearity. A high-speed, high open-loop gain amplifier like the OPA2674 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the Recommended RS vs Capacitive Load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA2674. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA2674 output pin (see the Board Layout Guidelines section).
OUTPUT CURRENT AND VOLTAGE
The OPA2674 provides output voltage and current capabilities that are unsurpassed in a low-cost dual monolithic op amp. Under no-load conditions at 25°C, the output voltage typically swings closer than 1V to either supply rail; the tested (+25°C) swing limit is within 1.1V of either rail. Into a 6Ω load (the minimum tested load), it delivers more than ±380mA. The specifications described previously, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage times current (or V−I product) that is more relevant to circuit operation. Refer to the Output Voltage and Current Limitations plot in the Typical Characteristics (see page 9). The X and Y axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA2674 output drive capabilities, noting that the graph is bounded by a safe operating area of 1W maximum internal power dissipation (in this case, for one channel only). Superimposing resistor load lines onto the plot shows that the OPA2674 can drive ±4V into 10Ω or ±4.5V into 25Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±5.0V output swing capability, as stated in the Electrical Characteristics tables. The minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the Electrical Characteristics tables. As the output transistors deliver power, the junction temperatures increase, decreasing the VBE’s (increasing the available output voltage swing), and increasing the current gains (increasing the available output current). In steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature
DISTORTION PERFORMANCE
The OPA2674 provides good distortion performance into a 100Ω load on ±6V supplies. It also provides exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic dominates the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback networkin the noninverting configuration (see Figure 1), this is the sum of RF + RG; in the inverting configuration, it is RF. Also, providing an additional supply decoupling capacitor (0.01µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB).
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In most op amps, increasing the output voltage swing directly increases harmonic distortion. The Typical Characteristics show the 2nd-harmonic increasing at a little less than the expected 2x rate, whereas the 3rd-harmonic increases at a little less than the expected 3x rate. Where the test power doubles, the difference between it and the 2nd-harmonic decreases less than the expected 6dB, whereas the difference between it and the 3rd-harmonic decreases by less than the expected 12dB. This factor also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low-output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 20MHz, with 10dBm/tone into a matched 50Ω load (i.e., 2VPP for each tone at the load, which requires 8VPP for the overall 2-tone envelope at the output pin), the Typical Characteristics show 67dBc difference between the test-tone power and the 3rd-order intermodulation spurious levels. This exceptional performance improves further when operating at lower frequencies.
The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 17 shows the general form for the output noise voltage using the terms given in Figure 13.
EO + E NI ) I BN
2 2
RS
) 4kTRS ) I BI
RF
2
) 4kTRFNG
(17)
ENI 1/2 OPA2674 IBN EO
RS
ERS √4kTRS RG IBI
RF √4kTRF 4kT = 1.6E −20J at 290_K
4kT RG
Figure 13. Op Amp Noise Analysis Model
Dividing this expression by the noise gain (NG = (1 + RF/RG)) gives the equivalent input referred spot noise voltage at the noninverting input, as shown in Equation 18.
EN + E NI 2 ) I BN 2 R S ) 4kTR ) S I BI RF NG 2 ) 4kTR F NG
NOISE PERFORMANCE
Wideband current-feedback op amps generally have a higher output noise than comparable voltage-feedback op amps. The OPA2674 offers an excellent balance between voltage and current noise terms to achieve low output noise. The inverting current noise (24pA/√Hz) is lower than earlier solutions whereas the input voltage noise (2.0nV/√Hz) is lower than most unity-gain stable, wideband voltage-feedback op amps. This low input voltage noise is achieved at the price of higher noninverting input current noise (16pA/√Hz). As long as the AC source impedance from the noninverting node is less than 100Ω, this current noise does not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. Figure 13 shows the op amp noise analysis model with all noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz.
(18)
Evaluating these two equations for the OPA2674 circuit and component values of Figure 1 gives a total output spot noise voltage of 14.3nV/√Hz and a total equivalent input spot noise voltage of 3.6nV/√Hz. This total input referred spot noise voltage is higher than the 2.0nV/√Hz specification for the op amp voltage noise alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. If the feedback resistor is reduced in high-gain configurations (as suggested previously), the total input referred voltage noise given by Equation 18 approaches just the 2.0nV/√Hz of the op amp. For example, going to a gain of +10 using RF = 298Ω gives a total input referred noise of 2.3nV/√Hz.
DIFFERENTIAL NOISE PERFORMANCE
As the OPA2674 is used as a differential driver in xDSL applications, it is important to analyze the noise in such a configuration. See Figure 14 for the op amp noise model for the differential configuration.
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IN Driver EN
In order to minimize the noise contributed by IN, it is recommended to keep the noninverting source impedance as low as possible.
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp such as the OPA2674 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate DC accuracy. The Electrical Characteristics show an input offset voltage comparable to high-speed, voltage-feedback amplifiers; however, the two input bias currents are somewhat higher and are unmatched. While bias current cancellation techniques are very effective with most voltage-feedback op amps, they do not generally reduce the output DC offset for wideband current-feedback op amps. Because the two input bias currents are unrelated in both magnitude and polarity, matching the input source impedance to reduce error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to:
RS ERS √4 kTRS II RG EO2 √ 4kTRG RF IN √ 4kTRF √ 4kTRF
RF
RS ERS √4 kTRS
EN II
VOS = ± (NG × VIO(MAX)) ± (IBN × RS/2 × NG) ± (IBI × RF)
where NG = noninverting signal gain
= ± (4 × 4.5mV) ± (30µA × 25Ω × 4) ± (402Ω × 35µA) = ±18mV ± 3mV ± 14mV VOS = ±35.0mV (max at 25°C)
Figure 14. Differential Op Amp Noise Analysis Model
As a reminder, the differential gain is expressed as:
POWER CONTROL OPERATION (SO-14 ONLY)
The OPA2674I-14D provides a power control feature that may be used to reduce system power. The four modes of operation for this power control feature are full-power, power cutback, idle state, and power shutdown. These four operating modes are set through two logic lines A0 and A1. Table 3 shows the different modes of operation.
GD + 1 )
2
RF RG
(19)
The output noise voltage can be expressed as shown below:
(20)
e 2+ O 2 G 2 D e 2) i N N 2 R S ) 4kTR S )2 i R IF 2 ) 2 4kTR G FD
Table 3. Power Control Mode of Operation
MODE OF OPERATION Full-Power A1 1 1 0 0 A0 1 0 1 0
D ividing this expression by the differential noise gain G D = (1 + 2R F /R G ) gives the equivalent input referred spot noise voltage at the noninverting input, as shown in Equation 21.
Power Cutback Idle State Shutdown
(21)
eN + 2 eN2 ) i N RS
2
) 4kTR S ) 2 iI
RF GD
2
)2
4kTR F GD
Evaluating this equation for the OPA2674 circuit and component values of Figure 5 gives a total output spot noise voltage of 31.0nV/√Hz and a total equivalent input spot noise voltage of 3.5nV/√Hz.
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The full-power mode is used for normal operating condition. The power cutback mode brings the quiescent power to 13.5mA. The idle state mode keeps a low output impedance but reduces output power and bandwidth. The shutdown mode has a high output impedance as well as the lowest quiescent power (1.0mA). If the A0 and A1 pins are left unconnected, the OPA2674I-14D operates normally (full-power).
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To change the power mode, the control pins (either A0 or A1) must be asserted low. This logic control is referenced to the positive supply, as shown in the simplified circuit of Figure 15.
TJ MAX = 70°C + ((12V × 18.8mA) + 12V × 128mA/(5.33) − 40mW) × 125°C/W = 129°C This maximum junction temperature is well below the maximum of 150°C but may exceed system design targets. Lower junction temperature would be possible using the SO-14 package and the power cutback feature. Repeating this calculation for that solution gives: TJ MAX = 70°C + ((12V × 14.2mA) + 12V × 128mA/(5.33) − 40mW) × 100°C/W = 112°C
+VS
120kΩ Q2 Q1
1.2V
For extremely high internal power applications, where improved thermal performance is required, consider the PSO-8 package of the OPA2677—a similar part with no output stage current limit and a thermal impedance of less than 50°C/W.
60kΩ 46kΩ A0 or A1 − VS Control − VS
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency amplifier like the OPA2674 requires careful attention to board layout parasitic and external component types. Recommendations that optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25″) from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections (on pins 4 and 8 for an SO-8 package) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) improves 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at a lower frequency, should also be used on the main supply pins. These can be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components preserve the high-frequency performance of the OPA2674. Resistors should be of a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition axially leaded resistors can also provide good high-frequency performance. Again, keep the leads and PC board trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Although the output pin and inverting input pin are the most
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Figure 15. Supply Power Control Circuit
The shutdown feature for the OPA2674 is a positive-supply referenced, current-controlled interface. Open-collector (or drain) interfaces are most effective, as long as the controlling logic can sustain the resulting voltage (in open mode) that appears at the A0 or A1 pins. The A0/A1 pin voltage is one diode below the positive supply voltage applied to the OPA2674 if the logic interface is open. For voltage output logic interfaces, the on/off voltage levels described in the Electrical Characteristics apply only for either the +6V used for the ±6V specifications or the +5V for the single-supply specifications. An open-drain interface is recommended to operate the A1 and A0 pins using a higher positive supply and/or logic families with inadequate high-level voltage swings.
THERMAL ANALYSIS
Due to the high output power capability of the OPA2674, heat-sinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature sets the maximum allowed internal power dissipation, described below. In no case should the maximum junction temperature be allowed to exceed 150°C. Operating junction temperature (TJ) is given by TA + PD × qJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipation in the output stage (PDL) to deliver load power. Quiescent power is the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load. Using the example power calculation for the ADSL CPE line driver concluded in Equation 13, and a worst-case analysis at +70°C ambient, the maximum internal junction temperature for the SO-8 package will be: TJ MAX = TAMBIENT + PMAX × 125°C/W
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sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. The frequency response is primarily determined by the feedback resistor value as described previously. Increasing the value reduces the bandwidth, whereas decreasing it gives a more peaked frequency response. The 402Ω feedback resistor used in the Typical Characteristics at a gain of +4 on ±6V supplies is a good starting point for design. Note that a 511Ω feedback resistor, rather than a direct short, is recommended for the unity-gain follower application. A current-feedback op amp requires a feedback resistor even in the unity-gain follower configuration to control stability. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load (see page 10). Low parasitic capacitive loads (< 5pF) may not need an RS because the OPA2674 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary onboard. In fact, a higher impedance environment improves distortion; see the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA2674 is used, as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device. This total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA2674 allows multiple destination
devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case, and set the series resistor value as shown in the plot of RS vs Capacitive Load. However, this does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA2674 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2674 onto the board.
INPUT AND ESD PROTECTION
The OPA2674 is built using a high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices and are reflected in the absolute maximum ratings table. All device pins have limited ESD protection using internal diodes to the power supplies, as shown in Figure 16. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the OPA2674), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible, because high values degrade both noise performance and frequency response.
+VCC
External Pin
Internal Circuitry
− VCC
Figure 16. ESD Steering Diodes
26
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device OPA2674I-14D OPA2674I-14DR OPA2674ID OPA2674IDR
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SOIC SOIC SOIC SOIC
Package Drawing D D D D
Pins Package Eco Plan (2) Qty 14 14 8 8 58 2500 100 2500 None None None None
Lead/Ball Finish CU SNPB CU SNPB CU SNPB CU SNPB
MSL Peak Temp (3) Level-3-220C-168 HR Level-3-220C-168 HR Level-3-235C-168 HR Level-3-235C-168 HR
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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