OPA
268
0
®
OPA
OPA2680
268
0
Dual Wideband, Voltage Feedback
OPERATIONAL AMPLIFIER With Disable
TM
FEATURES
APPLICATIONS
●
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●
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WIDEBAND +5V OPERATION: 220MHz (G = 2)
HIGH OUTPUT CURRENT: 150mA
OUTPUT VOLTAGE SWING: ±4.0V
HIGH SLEW RATE: 1800V/µs
LOW SUPPLY CURRENT: 6.4mA/Ch.
LOW DISABLED CURRENT: 300µA/Ch.
ENABLE/DISABLE TIME: 25ns/100ns
DESCRIPTION
VIDEO LINE DRIVING
xDSL LINE DRIVER/RECEIVER
HIGH SPEED IMAGING CHANNELS
ADC BUFFERS
PORTABLE INSTRUMENTS
TRANSIMPEDANCE AMPLIFIERS
ACTIVE FILTERS
The OPA2680’s low 6.4mA/ch. supply current is precisely trimmed at 25°C. This trim, along with low temperature drift, guarantees lower maximum supply current
than competing products. System power may be reduced
further using the optional disable control pin (SO-14
package only). Leaving this disable pin open, or holding
it high, will operate the OPA2680N normally. If pulled
low, the OPA2680N supply current drops to less than
600µA while the output goes into a high impedance state.
The OPA2680 represents a major step forward in unity
gain stable, voltage feedback op amps. A new internal
architecture provides slew rate and full power bandwidth previously found only in wideband current feedback op amps. A new output stage architecture delivers
high currents with a minimal headroom requirement.
These combine to give exceptional single supply operation. Using a single +5V supply, the OPA2680 can
deliver a 1V to 4V output swing with over 100mA drive
current and 150MHz bandwidth. This combination of
features makes the OPA2680 an ideal RGB line driver
or single supply ADC input driver.
OPA2680 RELATED PRODUCTS
SINGLES
DUALS
TRIPLES
Voltage Feedback
OPA680
OPA2680
OPA3680
Current Feedback
OPA681
OPA2681
OPA3681
Fixed Gain
OPA682
OPA2682
OPA3682
+5V
0.1µF
1.5kΩ
REFB
1.5kΩ
+3.5V
50Ω
200Ω
+1.5V
REFT
0.1µF
+2.5V
+5V
0.1µF
3.2kΩ
1/2
OPA2680
50Ω
ADS822
10pF
+1.5V
800Ω
IN
1/2
OPA2680
1.6kΩ
1.6kΩ
10-Bit
40MSPS
2.5VCM
±1VDIFF
Clock
400Ω
400Ω
50Ω
VIN
0V to +1V
IN
10pF
Single-Supply, DC-Coupled, Single-to-Differential ADC Driver
nternational Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
SBOS086
1997 Burr-Brown Corporation
PDS-1433C
Printed in U.S.A. October, 1999
SPECIFICATIONS: VS = ±5V
RF = 402Ω, RL = 100Ω, and G = +2, (Figure 1 for AC performance only), unless otherwise noted.
OPA2680U, N
TYP
PARAMETER
AC PERFORMANCE (Figure 1)
Small-Signal Bandwidth
Gain-Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large Signal Bandwidth
Slew Rate
Rise/Fall Time
Settling Time to 0.02%
0.1%
Harmonic Distortion
2nd Harmonic
3rd Harmonic
Input Voltage Noise
Input Current Noise
Differential Gain
Differential Phase
Channel-to-Channel Crosstalk
DC PERFORMANCE(4)
Open-Loop Voltage Gain (AOL)
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Average Bias Current Drift (magnitude)
Input Offset Current
Average Offset Current Drift
INPUT
Common-Mode Input Range (CMIR)(5)
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Voltage Output Swing
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
DISABLE (SO-14 Only)
Power Down Supply Current (+VS)
Disable Time
Enable Time
Off Isolation
Output Capacitance in Disable
Turn On Glitch
Turn Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (VDIS)
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage Range
Max Quiescent Current
Min Quiescent Current
Power Supply Rejection (+PSRR)
THERMAL CHARACTERISTICS
Specified Operating Range U, N Package
Thermal Resistance, θJA
U SO-8
N SO-14
CONDITIONS
+25°C
G = +1, VO = 0.5Vp-p, RF = 25Ω
G = +2, VO = 0.5Vp-p
G = +10, VO = 0.5Vp-p
G ≥ 10
G = +2, VO < 0.5Vp-p
VO < 0.5Vp-p
G = +2, VO = 5Vp-p
G = +2, 4V Step
G = +2, VO = 0.5V Step
G = +2, VO = 5V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
400
220
30
300
30
4
175
1800
1.4
2.8
12
8
G = +2, f = 5MHz, VO = 2Vp-p
RL = 100Ω
RL ≥ 500Ω
RL = 100Ω
RL ≥ 500Ω
f > 1MHz
f > 1MHz
G = +2, NTSC, VO = 1.4Vp, RL = 150
G = +2, NTSC, VO = 1.4Vp, RL = 150
f = 5MHz
–68
–80
–80
–88
4.8
2.5
0.05
0.03
–70
VO = 0V, RL = 100Ω
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
GUARANTEED
+25°C(2)
0°C to
70°C(3)
–40°C to
+85°C(3)
210
20
200
200
20
200
190
20
200
1400
1200
900
–63
–70
–75
–85
5.3
2.8
–62
–68
–73
–83
5.9
3.0
54
58
±1.0
±4.5
+8
+14
±0.1
±0.7
VCM = ±1V
±3.5
59
±3.4
VCM = 0
VCM = 0
190 || 0.6
3.2 || 0.9
No Load
100Ω Load
VO = 0
VO = 0
G = +2, f = 100kHz
±4.0
±3.9
+190
–150
0.03
Disabled Low
VDIS = 0, Both Channels
G = +2, RL = 150Ω, VIN = 0
G = +2, RL = 150Ω, VIN = 0
VDIS = 0, Each Channel
+160
–135
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
ns
ns
ns
ns
typ
min
min
min
typ
typ
typ
min
typ
typ
typ
typ
C
B
B
B
C
C
C
C
C
C
C
C
–60
–65
–70
–80
6.1
3.6
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
%
deg
dBc
max
max
max
max
max
max
typ
typ
typ
,
B
B
B
B
B
C
C
C
52
±5.2
±10
+19
–70
±1
±1
50
±6.0
±10
+32
–150
±1.2
±1.5
dB
mV
µV/°C
µA
nA/°C
µA
nA/°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
±3.3
53
±3.2
52
V
dB
min
min
A
A
kΩ || pF
MΩ || pF
typ
typ
C
C
V
V
mA
mA
Ω
min
min
min
min
typ
A
A
A
A
C
typ
typ
typ
typ
typ
typ
typ
min
max
max
C
C
C
C
C
C
C
A
A
A
±3.7
±3.6
+140
–130
±3.6
±3.3
+80
–80
3.5
1.7
160
3.6
1.6
160
3.7
1.5
160
±6
±6
14.0
12.0
58
±6
14.4
10.6
56
V
V
mA
mA
dB
typ
max
max
min
min
C
A
A
A
A
–40 to +85
°C
typ
C
125
100
°C/W
°C/W
typ
typ
C
C
±5
VS = ±5V
VS = ±5V
Input Referred
±3.8
±3.7
MIN/ TEST
MAX LEVEL(1)
µA
ns
ns
dB
pF
mV
mV
V
V
µA
–600
100
25
70
4
±50
±20
3.3
1.8
100
G = +2, 5MHz
56
UNITS
12.8
12.8
65
13.6
12.0
60
Junction-to-Ambient
NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction temperature = ambient for 25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature
limit: junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive-out-of node.
VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ±CMIR limits.
®
OPA2680
2
SPECIFICATIONS: VS = +5V
RF = 402Ω, RL = 100Ω to VS /2, G = +2, (Figure 2 for AC performance only), unless otherwise noted.
OPA2680U, N
TYP
CONDITIONS
+25°C
G = +1, VO < 0.5Vp-p, RF = ±25Ω
G = +2, VO < 0.5Vp-p
G = +10, VO < 0.5Vp-p
G ≥ 10
G = +2, VO < 0.5Vp-p
VO < 0.5Vp-p
G = +2, VO = 2Vp-p
G = +2, 2V Step
G = +2, VO = 0.5V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, f = 5MHz, VO = 2Vp-p
RL = 100Ω to VS /2
RL ≥ 500Ω to VS /2
RL = 100Ω to VS /2
RL ≥ 500Ω to VS /2
f > 1MHz
f > 1MHz
G = +2, NTSC, VO = 1.4Vp, RL = 150 to VS /2
G = +2, NTSC, VO = 1.4Vp, RL = 150 to VS /2
300
220
25
250
20
5
200
1000
1.6
2.0
12
8
PARAMETER
AC PERFORMANCE (Figure 2)
Small-Signal Bandwidth
Gain-Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large Signal Bandwidth
Slew Rate
Rise/Fall Time
Settling Time to 0.02%
0.1%
Harmonic Distortion
2nd Harmonic
3rd Harmonic
Input Voltage Noise
Input Current Noise
Differential Gain
Differential Phase
DC PERFORMANCE(4)
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Average Bias Current Drift (magnitude)
Input Offset Current
Average Offset Current Drift
INPUT
Least Positive Input Voltage(5)
Most Positive Input Voltage(5)
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Most Positive Output Voltage
Least Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
DISABLE (SO-14 Only)
Power Down Supply Current (+VS)
Disable Time
Enable Time
Off Isolation
Output Capacitance in Disable
Turn On Glitch
Turn Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (VDIS)
POWER SUPPLY
Specified Single Supply Operating Voltage
Maximum Single Supply Operating Voltage
Max Quiescent Current
Min Quiescent Current
Power Supply Rejection (+PSRR)
TEMPERATURE RANGE
Specification: U, N
Thermal Resistance, θJA
U SO-8
N SO-14
VO = 2.5V, RL = 100Ω to 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
GUARANTEED
+25°C(2)
0°C to
70°C(3)
–40°C to
+85°C(3)
120
20
200
160
19
190
140
18
180
700
670
550
–55
–66
–66
–76
5.3
2.8
–54
–63
–64
–74
6.0
3.0
54
typ
min
min
min
typ
typ
typ
min
typ
typ
typ
typ
C
B
B
B
C
C
C
B
C
C
C
C
–51
–59
–62
–71
6.2
3.4
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
%
deg
max
max
max
max
max
max
typ
typ
B
B
B
B
B
B
C
C
52
±7
–10
+18
–52
±1.0
±0.5
50
±8.5
–12
+32
–52
±1.2
±1.0
dB
mV
µV/°C
µA
nA/°C
µA
nA/°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
1.7
3.3
53
1.8
3.2
52
V
V
dB
max
min
min
A
A
A
kΩ || pF
MΩ || pF
typ
typ
C
C
V
V
V
V
mA
mA
Ω
min
min
max
max
min
min
typ
A
A
A
A
A
A
C
µA
ns
ns
dB
pF
mV
mV
V
V
µA
typ
typ
typ
typ
typ
typ
typ
min
max
typ
C
C
C
C
C
C
C
A
A
C
V
V
mA
mA
dB
typ
max
max
min
typ
C
B
A
A
C
–40 to +85
°C
typ
C
125
100
°C/W
°C/W
typ
typ
C
C
–60
–70
–72
–80
5
2.5
0.06
0.03
±6.0
+8
+15
±0.1
±0.6
VCM = 2.5V ±0.5V
1.5
3.5
59
1.6
3.4
56
VCM = 2.5V
VCM = 2.5V
92 || 1.4
2.2 || 1.5
No Load
RL = 100Ω to 2.5V
No Load
RL = 100Ω to 2.5V
4
3.9
1
1.1
+150
–110
0.03
G = +2, 5MHz
G = +2, RL = 150Ω, VIN = VS /2
G = +2, RL = 150Ω, VIN = VS /2
VDIS = 0, Each Channel
–500
100
25
65
4
±50
±20
3.3
1.8
100
3.8
3.7
1.2
1.3
+110
–75
3.6
3.5
1.4
1.5
+110
–70
3.5
3.4
1.5
1.7
+60
–50
3.5
1.7
3.6
1.6
3.7
1.5
12
12.0
8.0
12
12.0
8.0
12
12.0
7.6
5
VS = +5V
VS = +5V
Input Referred
MIN/ TEST
MAX LEVEL(1)
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
ns
ns
ns
ns
58
±2.0
G =+2, f = 100kHz
Disabled Low
VDIS = 0, Both Channels
UNITS
10.2
10.2
55
Junction-to-Ambient
NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction temperature = ambient for 25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature
limit: Junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive-out-of node.
VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ±CMIR limits.
®
3
OPA2680
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATIONS
Power Supply .............................................................................. ±6.5VDC
Internal Power Dissipation ..................................... See Thermal Analysis
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±VS
Storage Temperature Range: U, N ................................ –40°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (TJ ) ........................................................... +175°C
Top View
SO-8
Out A
–In A
ELECTROSTATIC
DISCHARGE SENSITIVITY
1
2
+In A
3
–VS
4
A
B
8
+VS
7
Out B
6
–In B
5
+In B
SO-14
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.
–In A
1
14 Out A
+In A
2
13 NC
DISA
3
12 NC
–VS
4
11 +VS
DISB
5
10 NC
+In B
6
9
NC
–In B
7
8
Out B
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
OPA2680U
SO-8 Surface Mount
182
–40°C to +85°C
OPA2680U
"
"
"
"
SO-14 Surface mount
235
–40°C to +85°C
OPA2680N
"
"
"
"
"
OPA2680N
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
OPA2680U
OPA2680U/2K5
OPA2680N
OPA2680N/2K5
Rails
Tape and Reel
Rails
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA2680U/2K5” will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product
for use in life support devices and/or systems.
®
OPA2680
4
TYPICAL PERFORMANCE CURVES: VS = ±5V
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1.
SMALL-SIGNAL FREQUENCY RESPONSE
6
VO = 0.5Vp-p
VO = 1Vp-p
VO = 2Vp-p
12
0
9
G = +2
–3
–6
–9
G = +5
–12
–15
6
Gain (3dB/div)
Normalized Gain (3dB/div)
3
LARGE-SIGNAL FREQUENCY RESPONSE
15
G = +1
RF = 25Ω
3
VO = 7Vp-p
0
–3
VO = 4Vp-p
–6
G = +10
–18
–9
–21
–12
–24
–15
0.5
10
100
500
0.5
Frequency (MHz)
SMALL-SIGNAL PULSE RESPONSE
G = +2
VO = 0.5Vp-p
300
G = +2
VO = 5Vp-p
+3
Output Voltage (1V/div)
Output Voltage (100mV/div)
500
LARGE-SIGNAL PULSE RESPONSE
200
100
0
–100
–200
+2
+1
0
–1
–2
–3
–300
–4
–400
Time (5ns/div)
Time (5ns/div)
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
4.0
2.0
0
0
–10
–20
Crosstalk (10dB/div)
VDIS
VDIS (2V/div)
CHANNEL-TO-CHANNEL CROSSTALK
5.0
Output Voltage
2.0
1.6
VO (0.4V/div)
100
+4
400
Each Channel
SO-14 Package
Only
1.2
0.8
0.4
10
Frequency (MHz)
G = +2
VIN = +1V
–30
–40
–50
–60
–70
–80
0
–90
–100
Time (50ns/div)
1
10
100
Frequency (MHz)
®
5
OPA2680
TYPICAL PERFORMANCE CURVES: VS = ±5V
(CONT)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1.
5MHz 2nd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
5MHz 3rd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–60
RL = 100Ω
–65
3rd Harmonic Distortion (dBc)
2nd Harmonic Distortion (dBc)
–60
RL = 200Ω
–70
–75
RL = 500Ω
–80
–85
–65
–70
RL = 100Ω
–75
RL = 200Ω
–80
–85
RL = 500Ω
–90
0.1
1
–90
10
0.1
10MHz 2nd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
10MHz 3rd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–60
3rd Harmonic Distortion (dBc)
–65
RL = 100Ω
–70
RL = 200Ω
–75
RL = 500Ω
–80
–85
RL = 200Ω
–65
RL = 100Ω
–70
–75
–80
RL = 500Ω
–85
–90
–90
0.1
1
0.1
10
1
10
Output Voltage Swing (Vp-p)
Output Voltage Swing (Vp-p)
20MHz 2nd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
20MHz 3rd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–50
–50
–55
3rd Harmonic Distortion (dBc)
RL = 100Ω
2nd Harmonic Distortion (dBc)
10
Output Voltage Swing (Vp-p)
–60
2nd Harmonic Distortion (dBc)
1
Output Voltage Swing (Vp-p)
RL = 200Ω
–60
RL = 500Ω
–65
–70
–75
–80
RL = 200Ω
–55
RL = 100Ω
–60
–65
–70
RL = 500Ω
–75
–80
0.1
1
10
0.1
Output Voltage Swing (Vp-p)
®
OPA2680
1
Output Voltage Swing (Vp-p)
6
10
TYPICAL PERFORMANCE CURVES: VS = ±5V
(CONT)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1.
2nd HARMONIC DISTORTION vs FREQUENCY
3rd HARMONIC DISTORTION vs FREQUENCY
–40
VO = 2Vp-p
RL = 100Ω
–45
–50
G = +10
–55
–60
VO = 2Vp-p
RL = 100Ω
–45
3rd Harmonic Distortion (dBc)
2nd Harmonic Distortion (dBc)
–40
G = +5
–65
–70
–75
–80
G = +2
–85
–50
G = +10
–55
–60
–65
G = +5
–70
–75
–80
G = +2
–85
–90
–90
0.1
1
10
20
0.1
1
Frequency (MHz)
10
20
Frequency (MHz)
INPUT VOLTAGE AND CURRENT NOISE DENSITY
TWO-TONE, 3rd-ORDER SPURIOUS LEVEL
100
–40
10
Voltage Noise
3rd-Order Spurious Level (dBc)
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
50MHz
4.8nV/√Hz
Current Noise
2.5pA/√Hz
–50
–60
20MHz
–70
10MHz
–80
Load Power at matched 50Ω load
1
–90
100
1k
10k
100k
1M
10M
–8
–6
–4
Frequency (Hz)
0
2
4
6
8
10
FREQUENCY RESPONSE vs CAPACITIVE LOAD
RECOMMENDED RS vs CAPACITIVE LOAD
12
70
9
Gain-to-Capacitive Load (3dB/div)
80
60
50
RS (Ω)
–2
Single-Tone Load Power (dBm)
40
30
20
10
CL = 10pF
G = +2
CL = 22pF
6
3
CL = 47pF
0
VIN
–3
–6
1/2
OPA2680
402Ω
–9
–12
RS
VO
CL
1kΩ
CL = 100pF
402Ω
–15
1kΩ is optional
–18
0
10
0
100
100MHz
200MHz
Frequency (20MHz/div)
Capacitive Load (pF)
®
7
OPA2680
TYPICAL PERFORMANCE CURVES: VS = ±5V
(CONT)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1.
OPEN-LOOP GAIN AND PHASE
90
60
0
–30
Open-Loop Phase
80
–PSRR
70
+PSRR
50
–60
Open-Loop Gain
40
–90
30
–120
20
–150
10
–180
0
–210
10
–10
–240
0
–20
60
CMRR
50
40
30
20
10k
100k
1M
10M
–270
10k
100M
100k
1M
COMPOSITE VIDEO dG/dP
75Ω
402Ω
Input Offset Voltage (mV)
Input Bias and Offset Current (µA)
With 1.3kΩ
Pulldown
Optional
1.3kΩ
Pulldown
dP
dG
0.1
402Ω
0.075
–5V
0.05
dG
dP
0.025
0
10
IB
5
VIO
0
IOS
–5
–10
–15
1
2
3
4
–40
–20
0
Number of 150Ω Loads
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
5
3
VO (Volts)
2
1
1W Internal
Power Limit
One Channel
Only
25Ω
Load Line
50Ω Load Line
–1
100Ω Load Line
–2
–3
–4
60
80
100
120
140
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Output Current Limited
0
40
200
Output Current (50mA/div)
4
20
Ambient Temperature (°C)
20.0
Sourcing Output Current
Sinking Output Current
150
15.0
Quiescent Supply Current
100
10.0
50
5.0
1W Internal
Power Limit
Output Current Limit
–5
0
–300
–200
–100
0
100
200
300
IO (mA)
–20
0
20
40
60
80
Ambient Temperature (°C)
®
OPA2680
0
–40
8
100
120
140
Supply Current (5.0mA/div)
dG/dP (%/degrees)
TYPICAL DC DRIFT OVER TEMPERATURE
Video
Loads
1/2
OPA2680
0.125
1G
No Pulldown
Video In
0.15
100M
15
+5V
0.175
10M
Frequency (Hz)
Frequency (Hz)
0.2
Open-Loop Phase (degrees)
70
Open-Loop Gain (dB)
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
CMRR AND PSRR vs FREQUENCY
100
TYPICAL PERFORMANCE CURVES: VS = +5V
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 2.
SMALL-SIGNAL FREQUENCY RESPONSE
6
VO = 0.5Vp-p
9
0
VO = 1Vp-p
6
G = +2
–3
Gain (3dB/div)
Normalized Gain (3dB/div)
G = +1
RF = 25Ω
VO = 0.5Vp-p
3
LARGE-SIGNAL FREQUENCY RESPONSE
12
–6
–9
G = +5
–12
–15
3
VO = 2Vp-p
0
–3
VO = 3Vp-p
–6
–9
G = +10
–18
–12
–21
–15
–24
–18
0.5
10
100
500
0.5
10
Frequency (MHz)
SMALL-SIGNAL PULSE RESPONSE
4.1
G = +2
VO = 0.5Vp-p
2.8
Output Voltage (400mV/div)
Output Voltage (100mV/div)
500
LARGE-SIGNAL PULSE RESPONSE
2.9
2.7
2.6
2.5
2.4
2.3
2.2
G = +2
VO = 2Vp-p
3.7
3.3
2.9
2.5
2.1
1.7
1.3
2.1
0.9
Time (5ns/div)
Time (5ns/div)
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
70
12
Gain-to-Capacitive Load (3dB/div)
Noise Gain = 2.6
60
50
RS (Ω)
100
Frequency (MHz)
40
30
20
10
0
CL = 47pF
Signal Gain = +2
Noise Gain = 2.6
9
CL = 10pF
CL = 22pF
6
CL = 100pF
3
+5V
0
–3
0.1µF
714Ω
VI
–6
58Ω
714Ω
714Ω
1/2
OPA2680
RS
VO
CL
–9
402Ω
–12
402Ω
–15
0.1µF
–18
1
10
100
0
Capacitive Load (pF)
100MHz
200MHz
Frequency (20MHz/div)
®
9
OPA2680
TYPICAL PERFORMANCE CURVES: VS = +5V
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 2.
2nd HARMONIC DISTORTION vs FREQUENCY
3rd HARMONIC DISTORTION vs FREQUENCY
–40
VO = 2Vp-p
RL = 100Ω to VS/2
–45
3rd Harmonic Distortion (dBc)
2nd Harmonic Distortion (dBc)
–40
G = +10
–50
–55
G = +5
–60
–65
G = +2
–70
VO = 2Vp-p
RL = 100Ω to VS/2
–45
–50
G = +10
–55
G = +5
–60
–65
–70
–75
G = +2
–75
–80
0.1
1
10
20
0.1
1
Frequency (MHz)
–40
VO = 2Vp-p
VO = 2Vp-p
–45
–50
3rd Harmonic Distortion (dBc)
2nd Harmonic Distortion (dBc)
20
3rd HARMONIC DISTORTION vs FREQUENCY
2nd HARMONIC DISTORTION vs FREQUENCY
–40
RL = 100Ω
–55
–60
RL = 200Ω
–65
–70
RL = 500Ω
–75
–45
–50
RL = 500
–55
–60
RL = 200
–65
RL = 100
–70
–75
–80
–80
0.1
1
10
0.1
20
1
10
20
Frequency (MHz)
Frequency (MHz)
TWO-TONE, 3RD-ORDER SPURIOUS LEVEL
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
10
–40
dBc = dB Below Carrier
–45
+5V
50MHz
Output Impedance (Ω)
3rd-Order Spurious Level (dBc)
10
Frequency (MHz)
–50
–55
20MHz
–60
–65
–70
200Ω
1/2
OPA2680
ZO
1
–5V
402Ω
402Ω
0.1
10MHz
–75
Load Power at Matched 50Ω Load
0.01
–80
–14
–12
–10
–8
–6
–4
–2
0
2
10k
Single-Tone Load Power (dBm)
1M
Frequency (Hz)
®
OPA2680
100k
10
10M
100M
200Ω source resistance seen at the inverting input (see the
DC Accuracy and Offset Control section). In addition to the
usual power supply decoupling capacitors to ground, a 0.1µF
capacitor is included between the two power supply pins. In
practical PC board layouts, this optional-added capacitor will
typically improve the 2nd harmonic distortion performance
by 3dB to 6dB.
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE FEEDBACK OPERATION
The OPA2680 provides an exceptional combination of high
output power capability in a dual, wideband, unity gain
stable voltage feedback op amp using a new high slew rate
input stage. Typical differential input stages used for voltage
feedback op amps are designed to steer a fixed-bias current
to the compensation capacitor, setting a limit to the achievable slew rate. The OPA2680 uses a new input stage which
places the transconductance element between two input
buffers, using their output currents as the forward signal. As
the error voltage increases across the two inputs, an increasing current is delivered to the compensation capacitor. This
provides very high slew rate (1800V/µs) while consuming
relatively low quiescent current (6.4mA/ch.). This exceptional full power performance comes at the price of a slightly
higher input noise voltage than alternative architectures. The
4.8nV/√Hz input voltage noise for the OPA2680 is exceptionally low for this type of input stage.
Figure 2 shows the AC-coupled, gain of +2, single supply
circuit configuration which is the basis of the +5V Specifications and Typical Performance Curves. Though not a “railto-rail” design, the OPA2680 requires minimal input and
output voltage headroom compared to other very wideband
voltage feedback op amps. It will deliver a 3Vp-p output
swing on a single +5V supply with >150MHz bandwidth.
The key requirement of broadband single-supply operation is
to maintain input and output signal swings within the useable
voltage ranges at both the input and the output. The circuit
of Figure 2 establishes an input midpoint bias using a simple
resistive divider from the +5V supply (two 698Ω resistors).
Separate networks would be required at each input. The
input signal is then AC-coupled into the midpoint voltage
bias. The input voltage can swing to within 1.5V of either
supply pin, giving a 2Vp-p input signal range centered
between the supply pins. The input impedance matching
resistor (59Ω) used for testing is adjusted to give a 50Ω input
load when the parallel combination of the biasing divider
network is included. Again, an additional resistor (50Ω in
this case) is included directly in series with the non-inverting
input. This minimum recommended value provides part of
the DC source resistance matching for the non-inverting
input bias current. It is also used to form a simple parasitic
pole to roll off the frequency response at very high frequencies (>500MHz) using the input parasitic capacitance. The
gain resistor (RG) is AC-coupled, giving the circuit a DC
gain of +1, which puts the input DC bias voltage (2.5V) on
the output as well. The output voltage can swing to within
1V of either supply pin while delivering >100mA output
Figure 1 shows the DC-coupled, gain of +2, dual power
supply circuit configuration used as the basis of the ±5V
Specifications and Typical Performance Curves. This is for
one channel. The other channel is connected similarly. For
test purposes, the input impedance is set to 50Ω with a
resistor to ground and the output impedance is set to 50Ω
with a series output resistor. Voltage swings reported in the
specifications are taken directly at the input and output pins,
while output powers (dBm) are at the matched 50Ω load. For
the circuit of Figure 1, the total effective load will be 100Ω
|| 804Ω. The disable control line (SO-14 package only) is
typically left open to guarantee normal amplifier operation.
Two optional components are included in Figure 1. An
additional resistor (175Ω) is included in series with the noninverting input. Combined with the 25Ω DC source resistance looking back towards the signal generator, this gives an
input bias current cancelling resistance that matches the
+5V
0.1µF
+5V
+VS
6.8µF
+
0.1µF
50Ω Source
175Ω
VI
50Ω
VO
1/2
OPA2680
50Ω
0.1µF
50Ω Load
50Ω
DIS
VD
VI
698Ω
59Ω
0.1µF
6.8µF
698Ω
DIS
VD
+
1/2
OPA2680
VO
100Ω
VS/2
RF
402Ω
RF
402Ω
RG
402Ω
RG
402Ω
+
6.8µF
0.1µF
0.1µF
–5V
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit.
FIGURE 2. AC-Coupled, G = +2, Single Supply Specification and Test Circuit.
®
11
OPA2680
current. A demanding 100Ω load to a midpoint bias is used
in this characterization circuit. The new output stage circuit
used in the OPA2680 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown in the +5V supply, 3rd harmonic distortion
plots.
73
VO = 2Vp-p, 10MHz
72
SFDR (dBc)
71
SINGLE SUPPLY A/D CONVERTER INTERFACE
Most modern, high performance analog-to-digital converters (such as the Burr-Brown ADS8xx and ADS9xx series)
operate on a single +5V (or lower) power supply. It has been
a considerable challenge for single supply op amps to
deliver a low distortion input signal at the ADC input for
signal frequencies exceeding 5MHz. The high slew rate,
exceptional output swing and high linearity of the OPA2680
make it an ideal single supply ADC driver. The circuit on the
front page shows one possible interface particularly suited to
DC-coupled pulse digitization requirements. Figure 3 shows
the AC-coupled test circuit of Figure 2 modified for a
capacitive (A/D) load and with an optional output pull-down
resistor (RB).
70
69
68
67
66
65
0
1
2
3
4
5
6
7
High frequency DDS DACs require a low distortion output
amplifier to retain their SFDR performance into real-world
loads. A differential output drive implementation is shown
in Figure 5. The diagram shows the signal output current(s)
connected into the virtual ground summing junction(s) of
the OPA2680, which is set up as a transimpedance stage or
“I-V converter”. If the DAC requires its outputs terminated
to a compliance voltage other than ground for operation,
the appropriate voltage level may be applied to the noninverting inputs of the OPA2680. The DC gain for this
circuit is equal to RF. At high frequencies, the DAC output
capacitance (CD in Figure 5) will produce a zero in the
noise gain for the OPA2680 that may cause peaking in the
closed-loop frequency response. CF is added across RF to
compensate for this noise gain peaking. To achieve a flat
Power supply decoupling not shown
698Ω
50Ω
RS
30Ω
1/2
OPA2680
1Vp-p
59Ω
698Ω
2.5V DC
±1V AC
50pF
402Ω
402Ω
RB
0.1µF
FIGURE 3. Single-Supply ADC Input Driver. One of Two Channels.
®
OPA2680
10
HIGH PERFORMANCE DAC TRANSIMPEDANCE
AMPLIFIER
+5V
0.1µF
9
FIGURE 4. SFDR vs IB.
The OPA2680 in the circuit of Figure 3 provides >200MHz
bandwidth for a 2Vp-p output swing. Minimal 3rd harmonic
distortion or two-tone, 3rd-order intermodulation distortion
will be observed due to the very low crossover distortion in
the OPA2680 output stage. The limit of output Spurious
Free Dynamic Range (SFDR) will be set by the 2nd harmonic distortion. Without RB, the circuit of Figure 3 measured at 10MHz shows an SFDR of 65dBc. This may be
improved by pulling additional DC bias current (IB) out of
the output stage through the optional RB resistor to ground
(the output midpoint is at 2.5V for Figure 3). Adjusting IB
gives the improvement in SFDR shown in Figure 4. SFDR
improvement is achieved for IB values up to 6mA, with
worse performance for higher values. Using the dual
OPA2680 in an IQ receiver channel will give matched AC
performance through high frequencies.
VI
8
Output Pull-Down Current (mA)
12
IB
ADC Input
WIDEBAND VIDEO MULTIPLEXING
transimpedance frequency response, the pole in each feedback network should be set to:
One common application for video speed amplifiers which
include a disable pin is to wire multiple amplifier outputs
together, then select which one of several possible video
inputs to source onto a single line. This simple “Wired-OR
Video Multiplexer” can be easily implemented using the
OP2680N (SO-14 package only) as shown in Figure 6.
1/2πRFCF = √GBP/4πRFCD
which will give a corner frequency f–3dB of approximately:
f–3dB = √GBP/(2πRFCD)
Typically, channel switching is performed either on sync or
retrace time in the video signal. The two inputs are approximately equal at this time. The “make-before-break” disable
characteristic of the OPA2680N ensures that there is always
one amplifier controlling the line when using a wired-OR
circuit like that shown in Figure 6. Since both inputs may be
on for a short period during the transition between channels,
the outputs are combined through the output impedance
matching resistors (82.5Ω in this case). When one channel is
disabled, its feedback network forms part of the output
impedance and slightly attenuates the signal in getting out
onto the cable. The gain and output matching resistor have
been slightly increased to get a signal gain of +1 at the
matched load and provide a 75Ω output impedance to the
cable. The video multiplexer connection (Figure 6) also
insures that the maximum differential voltage across the
inputs of the unselected channel does not exceed the rated
±1.2V maximum for standard video signal levels.
50Ω
1/2
OPA2680
High Speed
DAC
VO = IO RF
RF1
CF1
IO
CD1
RF2
CD2
IO
CF2
1/2
OPA2680
50Ω
VO = IO RF
GBP → Gain Bandwidth
Product (Hz) for the OPA2680
The section on Disable Operation shows the turn-on and
turn-off switching glitches using a 0V input for a single
channel is typically less than ±50mV. Where two outputs are
switched (as shown in Figure 6), the output line is always
under the control of one amplifier or the other due to the
“make-before-break” disable timing. In this case, the switching glitches for two 0V inputs drop to
